445 lines
16 KiB
C
445 lines
16 KiB
C
//*****************************************************************************
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//
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//! @file am_util_faultisr.c
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//!
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//! @brief An extended hard-fault handler.
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//
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// This module is intended to be completely portable with no HAL or BSP
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// dependencies.
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//
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// Further, it is intended to be compiler/platform independent enabling it to
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// run on GCC, Keil, IAR, etc.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Macros
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//
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//*****************************************************************************
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//
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// Macros used by am_util_faultisr_collect_data().
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//
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#define AM_REG_SYSCTRL_CFSR_O 0xE000ED28
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#define AM_REG_SYSCTRL_BFAR_O 0xE000ED38
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#define AM_REGVAL(x) (*((volatile uint32_t *)(x)))
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//*****************************************************************************
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//
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// Data structures
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//
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//*****************************************************************************
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//
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// Define a structure for local storage in am_util_faultisr_collect_data().
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// Set structure alignment to 1 byte to minimize storage requirements.
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//
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#pragma pack(1)
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typedef struct
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{
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//
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// Stacked registers
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//
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volatile uint32_t u32R0;
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volatile uint32_t u32R1;
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volatile uint32_t u32R2;
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volatile uint32_t u32R3;
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volatile uint32_t u32R12;
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volatile uint32_t u32LR;
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volatile uint32_t u32PC;
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volatile uint32_t u32PSR;
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//
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// Other data
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//
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volatile uint32_t u32FaultAddr;
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volatile uint32_t u32BFAR;
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volatile uint32_t u32CFSR;
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volatile uint8_t u8MMSR;
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volatile uint8_t u8BFSR;
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volatile uint16_t u16UFSR;
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} am_fault_t;
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//
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// Restore the default structure alignment
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//
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#pragma pack()
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//*****************************************************************************
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//
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// Prototypes
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//
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//*****************************************************************************
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void am_util_faultisr_collect_data(uint32_t u32IsrSP);
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//
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// Prototype for printf, if used.
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//
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extern uint32_t am_util_stdio_printf(char *pui8Fmt, ...);
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//*****************************************************************************
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//
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// getStackedReg() will retrieve a specified register value, as it was stacked
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// by the processor after the fault, from the stack.
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//
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// The registers are stacked in the following order:
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// R0, R1, R2, R3, R12, LR, PC, PSR.
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// To get R0 from the stack, call getStackedReg(0), r1 is getStackedReg(1)...
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//
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//*****************************************************************************
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#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
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__asm uint32_t
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#if AM_CMSIS_REGS
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HardFault_Handler(void)
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#else // AM_CMSIS_REGS
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am_fault_isr(void)
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#endif // AM_CMSIS_REGS
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{
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import am_util_faultisr_collect_data
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push {r0, lr} // Always pushes to MSP stack
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tst lr, #4 // Check if we should use MSP or PSP
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itet eq // Instrs executed when: eq,ne,eq
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mrseq r0, msp // bit2=0 indicating MSP stack
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mrsne r0, psp // e: bit2=1 indicating PSP stack
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addseq r0, r0, #8 // t: bit2=0, adjust for pushes to MSP stack
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bl am_util_faultisr_collect_data
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pop {r0, pc} // Restore from MSP stack
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}
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__asm uint32_t
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getStackedReg(uint32_t regnum, uint32_t u32SP)
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{
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lsls r0, r0, #2
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adds r0, r0, r1
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ldr r0, [r0]
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bx lr
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}
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#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION > 6000000)
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uint32_t __attribute__((naked))
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#if AM_CMSIS_REGS
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HardFault_Handler(void)
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#else // AM_CMSIS_REGS
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am_fault_isr(void)
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#endif // AM_CMSIS_REGS
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{
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__asm(" push {r0,lr}"); // Always pushes to MSP stack
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__asm(" tst lr, #4\n" // Check if we should use MSP or PSP
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" itet eq\n" // Instrs executed when: eq,ne,eq
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" mrseq r0, msp\n" // bit2=0 indicating MSP stack
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" mrsne r0, psp\n" // e: bit2=1 indicating PSP stack
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" addseq r0, r0, #8\n"); // t: bit2=0, adjust for pushes to MSP stack
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__asm(" bl am_util_faultisr_collect_data");
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__asm(" pop {r0,pc}"); // Restore from MSP stack
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}
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uint32_t __attribute__((naked))
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getStackedReg(uint32_t regnum, uint32_t u32SP)
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{
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__asm(" lsls r0, r0, #2");
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__asm(" adds r0, r1");
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__asm(" ldr r0, [r0]");
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__asm(" bx lr");
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}
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#elif defined(__GNUC_STDC_INLINE__)
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uint32_t __attribute__((naked))
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#if AM_CMSIS_REGS
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HardFault_Handler(void)
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#else // AM_CMSIS_REGS
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am_fault_isr(void)
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#endif // AM_CMSIS_REGS
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{
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__asm(" push {r0,lr}"); // Always pushes to MSP stack
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__asm(" tst lr, #4"); // Check if we should use MSP or PSP
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__asm(" itet eq"); // Instrs executed when: eq,ne,eq
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__asm(" mrseq r0, msp"); // bit2=0 indicating MSP stack
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__asm(" mrsne r0, psp"); // e: bit2=1 indicating PSP stack
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__asm(" addseq r0, r0, #8"); // t: bit2=0, adjust for pushes to MSP stack
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__asm(" bl am_util_faultisr_collect_data");
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__asm(" pop {r0,pc}"); // Restore from MSP stack
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}
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uint32_t __attribute__((naked))
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getStackedReg(uint32_t regnum, uint32_t u32SP)
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{
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__asm(" lsls r0, r0, #2");
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__asm(" adds r0, r1");
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__asm(" ldr r0, [r0]");
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__asm(" bx lr");
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing
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// return statement on a non-void function
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__stackless uint32_t
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#if AM_CMSIS_REGS
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HardFault_Handler(void)
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#else // AM_CMSIS_REGS
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am_fault_isr(void)
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#endif // AM_CMSIS_REGS
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{
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__asm("push {r0,lr}"); // Always pushes to MSP stack
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__asm("tst lr, #4\n" // Check if we should use MSP or PSP
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"itet eq\n" // Instrs executed when: eq,ne,eq
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"mrseq r0, msp\n" // bit2=0 indicating MSP stack
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"mrsne r0, psp\n" // e: bit2=1 indicating PSP stack
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"addseq r0, r0, #8\n"); // t: bit2=0, adjust for pushes to MSP stack
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__asm("bl am_util_faultisr_collect_data");
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__asm("pop {r0,pc}"); // Restore from MSP stack
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}
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__stackless uint32_t
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getStackedReg(uint32_t regnum, uint32_t u32SP)
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{
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__asm(" lsls r0, r0, #2");
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__asm(" adds r0, r0, r1");
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__asm(" ldr r0, [r0]");
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__asm(" bx lr");
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}
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#pragma diag_default = Pe940 // Restore IAR compiler warning
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#endif
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//*****************************************************************************
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//
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// am_util_faultisr_collect_data(uint32_t u32IsrSP);
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//
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// This function is intended to be called by HardFault_Handler(), called
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// when the processor receives a hard fault interrupt. This part of the
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// handler parses through the various fault codes and saves them into a data
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// structure so they can be readily examined by the user in the debugger.
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//
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// The input u32IsrSP is expected to be the value of the stack pointer when
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// HardFault_Handler() was called.
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//
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//*****************************************************************************
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void
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am_util_faultisr_collect_data(uint32_t u32IsrSP)
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{
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volatile am_fault_t sFaultData;
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am_hal_mcuctrl_fault_t sHalFaultData = {0};
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uint32_t u32Mask = 0;
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//
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// Following is a brief overview of fault information provided by the M4.
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// More details can be found in the Cortex M4 User Guide.
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//
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// CFSR (Configurable Fault Status Reg) contains MMSR, BFSR, and UFSR:
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// 7:0 MMSR (MemManage)
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// [0] IACCVIOL Instr fetch from a location that does not
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// permit execution.
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// [1] DACCVIOL Data access violation flag. MMAR contains
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// address of the attempted access.
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// [2] Reserved
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// [3] MUNSTKERR MemMange fault on unstacking for a return
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// from exception.
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// [4] MSTKERR MemMange fault on stacking for exception
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// entry.
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// [5] MLSPERR MemMange fault during FP lazy state
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// preservation.
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// [6] Reserved
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// [7] MMARVALID MemManage Fault Addr Reg (MMFAR) valid flag.
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// 15:8 BusFault
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// [0] IBUSERR If set, instruction bus error.
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// [1] PRECISERR Data bus error. Stacked PC points to instr
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// that caused the fault.
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// [2] IMPRECISERR Data bus error, but stacked return addr is not
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// related to the instr that caused the error and
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// BFAR is not valid.
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// [3] UNSTKERR Bus fault on unstacking for a return from
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// exception.
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// [4] STKERR Bus fault on stacking for exception entry.
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// [5] LSPERR Bus fault during FP lazy state preservation.
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// [6] Reserved
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// [7] BFARVALID BFAR valid.
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// 31:16 UFSR (UsageFault)
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// [0] UNDEFINSTR Undefined instruction.
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// [1] INVSTATE Invalid state.
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// [2] INVPC Invalid PC load.
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// [3] NOCP No coprocessor.
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// [7:4] Reserved
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// [8] UNALIGNED Unaligned access.
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// [9] DIVBYZERO Divide by zero.
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// [15:10] Reserved
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//
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//
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// u32Mask is used for 2 things: 1) in the print loop, 2) as a spot to set
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// a breakpoint at the end of the routine. If the printing is not used,
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// we'll get a compiler warning; so to avoid that warning, we'll use it
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// in a dummy assignment here.
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//
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sFaultData.u32CFSR = u32Mask; // Avoid compiler warning
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sFaultData.u32CFSR = AM_REGVAL(AM_REG_SYSCTRL_CFSR_O);
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sFaultData.u8MMSR = (sFaultData.u32CFSR >> 0) & 0xff;
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sFaultData.u8BFSR = (sFaultData.u32CFSR >> 8) & 0xff;
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sFaultData.u16UFSR = (sFaultData.u32CFSR >> 16) & 0xffff;
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//
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// The address of the location that caused the fault. e.g. if accessing an
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// invalid data location caused the fault, that address will appear here.
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//
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sFaultData.u32BFAR = AM_REGVAL(AM_REG_SYSCTRL_BFAR_O);
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//
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// The address of the instruction that caused the fault is the stacked PC
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// if BFSR bit1 is set.
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//
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sFaultData.u32FaultAddr = (sFaultData.u8BFSR & 0x02) ? getStackedReg(6, u32IsrSP) : 0xffffffff;
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//
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// Get the stacked registers.
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// Note - the address of the instruction that caused the fault is u32PC.
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//
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sFaultData.u32R0 = getStackedReg(0, u32IsrSP);
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sFaultData.u32R1 = getStackedReg(1, u32IsrSP);
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sFaultData.u32R2 = getStackedReg(2, u32IsrSP);
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sFaultData.u32R3 = getStackedReg(3, u32IsrSP);
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sFaultData.u32R12 = getStackedReg(4, u32IsrSP);
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sFaultData.u32LR = getStackedReg(5, u32IsrSP);
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sFaultData.u32PC = getStackedReg(6, u32IsrSP);
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sFaultData.u32PSR = getStackedReg(7, u32IsrSP);
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//
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// Use the HAL MCUCTRL functions to read the fault data.
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//
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#if AM_APOLLO3_MCUCTRL
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am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_FAULT_STATUS, &sHalFaultData);
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#else // AM_APOLLO3_MCUCTRL
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am_hal_mcuctrl_fault_status(&sHalFaultData);
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#endif // AM_APOLLO3_MCUCTRL
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#ifdef AM_UTIL_FAULTISR_PRINT
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//
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// If printf has previously been initialized in the application, we should
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// be able to print out the fault information.
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//
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am_util_stdio_printf("Hard Fault stacked data:\n");
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am_util_stdio_printf(" R0 = 0x%08X\n", sFaultData.u32R0);
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am_util_stdio_printf(" R1 = 0x%08X\n", sFaultData.u32R1);
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am_util_stdio_printf(" R2 = 0x%08X\n", sFaultData.u32R2);
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am_util_stdio_printf(" R3 = 0x%08X\n", sFaultData.u32R3);
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am_util_stdio_printf(" R12 = 0x%08X\n", sFaultData.u32R12);
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am_util_stdio_printf(" LR = 0x%08X\n", sFaultData.u32LR);
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am_util_stdio_printf(" PC = 0x%08X\n", sFaultData.u32PC);
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am_util_stdio_printf(" PSR = 0x%08X\n", sFaultData.u32PSR);
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am_util_stdio_printf("Other Hard Fault data:\n");
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am_util_stdio_printf(" Fault address = 0x%08X\n", sFaultData.u32FaultAddr);
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am_util_stdio_printf(" BFAR (Bus Fault Addr Reg) = 0x%08X\n", sFaultData.u32BFAR);
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am_util_stdio_printf(" MMSR (Mem Mgmt Fault Status Reg) = 0x%02X\n", sFaultData.u8MMSR);
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am_util_stdio_printf(" BFSR (Bus Fault Status Reg) = 0x%02X\n", sFaultData.u8BFSR);
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am_util_stdio_printf(" UFSR (Usage Fault Status Reg) = 0x%04X\n", sFaultData.u16UFSR);
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//
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// Print out any bits set in the BFSR.
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//
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u32Mask = 0x80;
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while (u32Mask)
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{
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switch (sFaultData.u8BFSR & u32Mask)
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{
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case 0x80:
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am_util_stdio_printf(" BFSR bit7: BFARVALID\n");
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break;
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case 0x40:
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am_util_stdio_printf(" BFSR bit6: RESERVED\n");
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break;
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case 0x20:
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am_util_stdio_printf(" BFSR bit5: LSPERR\n");
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break;
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case 0x10:
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am_util_stdio_printf(" BFSR bit4: STKERR\n");
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break;
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case 0x08:
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am_util_stdio_printf(" BFSR bit3: UNSTKERR\n");
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break;
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case 0x04:
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am_util_stdio_printf(" BFSR bit2: IMPRECISERR\n");
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break;
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case 0x02:
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am_util_stdio_printf(" BFSR bit1: PRECISEERR\n");
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break;
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case 0x01:
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am_util_stdio_printf(" BFSR bit0: IBUSERR\n");
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break;
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default:
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break;
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}
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u32Mask >>= 1;
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}
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//
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// Print out any Apollo* Internal fault information.
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//
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am_util_stdio_printf("MCU Fault data:\n");
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if (sHalFaultData.bICODE)
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{
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am_util_stdio_printf(" ICODE Fault Address: 0x%08X\n", sHalFaultData.ui32ICODE);
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}
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if (sHalFaultData.bDCODE)
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{
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am_util_stdio_printf(" DCODE Fault Address: 0x%08X\n", sHalFaultData.ui32DCODE);
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}
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if (sHalFaultData.bSYS)
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{
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am_util_stdio_printf(" SYS Fault Address: 0x%08X\n", sHalFaultData.ui32SYS);
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}
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#endif
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u32Mask = 0;
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//
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// Spin in an infinite loop.
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// We need to spin here inside the function so that we have access to
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// local data, i.e. sFaultData.
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//
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while(1)
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{
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}
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}
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