342 lines
21 KiB
C
342 lines
21 KiB
C
//*****************************************************************************
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//
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// am_hal_pwrctrl_internal.h
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//! @file
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//!
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//! @brief Internal definitions for Power Control
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//!
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//! @addtogroup pwrctrl3p Power Control
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//! @ingroup apollo3phal
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//! @{
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_HAL_PWRCTRL_INTERNAL_H
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#define AM_HAL_PWRCTRL_INTERNAL_H
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//*****************************************************************************
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//
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// Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable()
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_IOS (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN))
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#define AM_HAL_PWRCTRL_IOM0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN))
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#define AM_HAL_PWRCTRL_IOM1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN))
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#define AM_HAL_PWRCTRL_IOM2 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN))
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#define AM_HAL_PWRCTRL_IOM3 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN))
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#define AM_HAL_PWRCTRL_IOM4 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN))
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#define AM_HAL_PWRCTRL_IOM5 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN))
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#define AM_HAL_PWRCTRL_UART0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN))
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#define AM_HAL_PWRCTRL_UART1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN))
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#define AM_HAL_PWRCTRL_ADC (_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN))
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#define AM_HAL_PWRCTRL_SCARD (_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN))
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#define AM_HAL_PWRCTRL_MSPI0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI0, PWRCTRL_DEVPWREN_PWRMSPI_EN))
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#define AM_HAL_PWRCTRL_MSPI1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI1, PWRCTRL_DEVPWREN_PWRMSPI_EN))
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#define AM_HAL_PWRCTRL_MSPI2 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI2, PWRCTRL_DEVPWREN_PWRMSPI_EN))
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#define AM_HAL_PWRCTRL_PDM (_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN))
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#define AM_HAL_PWRCTRL_BLEL (_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN))
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#define AM_HAL_PWRCTRL_DEVPWREN_MASK 0x0000FFFF
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#define AM_HAL_PWRCTRL_DEVPWRSTATUS_MASK 0x000003FC
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//*****************************************************************************
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//
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// Memory enable values for all defined memory configurations.
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_128K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP0))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_192K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_128K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP1))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_256K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_192K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP2))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_320K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_256K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP3))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_384K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_320K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP4))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_448K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_384K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP5))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_512K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_448K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP6))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_576K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_512K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP7))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_672K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_576K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP8))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_768K \
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(AM_HAL_PWRCTRL_MEMEN_SRAM_672K | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP9))
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#define AM_HAL_PWRCTRL_MEMEN_SRAM_ALL (AM_HAL_PWRCTRL_MEMEN_SRAM_768K)
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#define AM_HAL_PWRCTRL_MEMEN_FLASH_1M PWRCTRL_MEMPWREN_FLASH0_Msk
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#define AM_HAL_PWRCTRL_MEMEN_FLASH_2M \
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(PWRCTRL_MEMPWREN_FLASH0_Msk | PWRCTRL_MEMPWREN_FLASH1_Msk)
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#define AM_HAL_PWRCTRL_MEMEN_CACHE \
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(PWRCTRL_MEMPWREN_CACHEB0_Msk | PWRCTRL_MEMPWREN_CACHEB2_Msk)
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#define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS (~AM_HAL_PWRCTRL_MEMEN_CACHE)
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//
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// Power up all available memory devices (this is the default power up state)
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//
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#define AM_HAL_PWRCTRL_MEMEN_ALL \
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(_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL) | \
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_VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_ALL) | \
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_VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN) | \
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_VAL2FLD(PWRCTRL_MEMPWREN_FLASH1, PWRCTRL_MEMPWREN_FLASH1_EN) | \
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_VAL2FLD(PWRCTRL_MEMPWREN_CACHEB0, PWRCTRL_MEMPWREN_CACHEB0_EN) | \
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_VAL2FLD(PWRCTRL_MEMPWREN_CACHEB2, PWRCTRL_MEMPWREN_CACHEB2_EN))
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//*****************************************************************************
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//
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// Memory deepsleep powerdown values for all defined memory configurations.
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_448K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_512K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_448K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_576K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_512K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_672K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_576K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_768K \
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(AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_672K | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9))
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_ALL (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_768K)
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_2M \
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(PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk | PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk)
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE (PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk)
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE_DIS (~AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE)
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//
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// Power down all available memory devices
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//
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#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL \
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(_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL) | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL) | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN) | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN) | \
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_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP, PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN))
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//*****************************************************************************
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//
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// Memory status values for all defined memory configurations
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM \
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(PWRCTRL_MEMPWRSTATUS_DTCM00_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM | \
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PWRCTRL_MEMPWRSTATUS_DTCM01_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM | \
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PWRCTRL_MEMPWRSTATUS_DTCM1_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM | \
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PWRCTRL_MEMPWRSTATUS_SRAM0_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K | \
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PWRCTRL_MEMPWRSTATUS_SRAM1_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K | \
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PWRCTRL_MEMPWRSTATUS_SRAM2_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K | \
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PWRCTRL_MEMPWRSTATUS_SRAM3_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K | \
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PWRCTRL_MEMPWRSTATUS_SRAM4_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_448K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K | \
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PWRCTRL_MEMPWRSTATUS_SRAM5_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_512K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_448K | \
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PWRCTRL_MEMPWRSTATUS_SRAM6_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_576K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_512K | \
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PWRCTRL_MEMPWRSTATUS_SRAM7_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_672K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_576K | \
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PWRCTRL_MEMPWRSTATUS_SRAM8_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_768K \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_672K | \
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PWRCTRL_MEMPWRSTATUS_SRAM9_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_768K)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M \
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(PWRCTRL_MEMPWRSTATUS_FLASH0_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_2M \
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(AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M | \
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PWRCTRL_MEMPWRSTATUS_FLASH1_Msk)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_ALL \
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(AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_768K | \
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AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_2M)
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//*****************************************************************************
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//
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// Memory event values for all defined memory configurations
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \
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PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \
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PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \
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PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K \
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((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \
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PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_448K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_512K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_448K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_576K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_512K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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|
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_672K \
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(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_576K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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|
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN)))
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#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_768K \
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|
(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_672K | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \
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|
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN)))
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|
#define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH0EN, \
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|
PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN))
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|
#define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_2M \
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|
(AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M | \
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(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH1EN, \
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|
PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN)))
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|
#define AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE \
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((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB0EN, \
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|
PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN)) | \
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|
(_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB2EN, \
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|
PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN)))
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|
#define AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL \
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|
(AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_768K | \
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|
AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_2M | \
|
|
AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE)
|
|
|
|
//*****************************************************************************
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|
//
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|
// Memory region mask values for all defined memory configurations
|
|
//
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|
//*****************************************************************************
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|
#define AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK AM_HAL_PWRCTRL_MEMEN_SRAM_ALL
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|
#define AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK AM_HAL_PWRCTRL_MEMEN_FLASH_2M
|
|
#define AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK AM_HAL_PWRCTRL_MEMEN_CACHE
|
|
#define AM_HAL_PWRCTRL_MEM_REGION_ALT_CACHE_MASK AM_HAL_PWRCTRL_PWRONSTATUS_CACHE
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|
#define AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK AM_HAL_PWRCTRL_MEMEN_ALL
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|
#define AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK AM_HAL_PWRCTRL_PWRONSTATUS_ALL
|
|
|
|
|
|
#endif // AM_HAL_PWRCTRL_INTERNAL_H
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
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|
//! @}
|
|
//
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|
//*****************************************************************************
|