859 lines
31 KiB
C
859 lines
31 KiB
C
//*****************************************************************************
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//
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// am_hal_mspi.h
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//! @file
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//!
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//! @brief Functions for accessing and configuring the MSPI.
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//!
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//! @addtogroup mspi3p Multi-bit SPI (MSPI)
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//! @ingroup apollo3phal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_HAL_MSPI_H
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#define AM_HAL_MSPI_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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//! CMSIS-Style macro for handling a variable MSPI module number.
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//
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//*****************************************************************************
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#define MSPIn(n) ((MSPI0_Type*)(MSPI0_BASE + (n * (MSPI1_BASE - MSPI0_BASE))))
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#define MSPI_IRQn(n) MSPI_IRQn_temp(n)
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#define MSPI_XIP_BASEADDRn(n) MSPI_XIP_BASEADDRn_temp(n)
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#define MSPI_XIPMM_BASEADDRn(n) MSPI_XIPMM_BASEADDRn_temp(n)
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#define AM_HAL_MSPI_MAX_TRANS_SIZE 16777215 // 2^24 - 1
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#define AM_HAL_MSPI_MAX_FIFO_SIZE 16
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#define AM_HAL_MSPI_DEFAULT_BURST_COUNT 32
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#define AM_HAL_MSPI_HIGH_SPEED_OFFSET 4
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// Size guideline for allocation of application supploed buffers
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#if 0
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#define AM_HAL_MSPI_CQ_ENTRY_SIZE (28 * sizeof(uint32_t))
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#else
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#define AM_HAL_MSPI_CQ_ENTRY_SIZE (22 * sizeof(uint32_t))
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#endif
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#define AM_HAL_MSPI_HIPRIO_ENTRY_SIZE (6 * sizeof(uint32_t))
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#define AM_HAL_MSPI_SC_CLEAR(flag) ((flag) << 16)
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#define AM_HAL_MSPI_SC_SET(flag) ((flag))
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// For MSPI - Need to Set the flag for unpausing
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#define AM_HAL_MSPI_SC_UNPAUSE(flag) AM_HAL_MSPI_SC_SET(flag)
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#define AM_HAL_MSPI_SC_PAUSE(flag) AM_HAL_MSPI_SC_CLEAR(flag)
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// Use this macro to directly control the flags
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#define AM_HAL_MSPI_SETCLR(module, scVal) \
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do { \
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MSPIn(module)->CQSETCLEAR = (scVal); \
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} while (0);
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// Flags 5, 7 & 6 are reserved by HAL
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#define AM_HAL_MSPI_PAUSE_FLAG_RESV (MSPI0_CQFLAGS_CQFLAGS_SWFLAG7 | MSPI0_CQFLAGS_CQFLAGS_SWFLAG6 | MSPI0_CQFLAGS_CQFLAGS_SWFLAG5)
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#define AM_HAL_MSPI_SC_RESV_MASK (AM_HAL_MSPI_PAUSE_FLAG_RESV | (AM_HAL_MSPI_PAUSE_FLAG_RESV << 8) | (AM_HAL_MSPI_PAUSE_FLAG_RESV << 16))
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// We use SWFLAGEN7 to control SW pausing Command Queue - default unPause
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// We use SWFLAGEN6 to pause on the sequece loopback - default Pause
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// We use SWFLAGEN5 to pause CQ while a block is building
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#define AM_HAL_MSPI_PAUSE_FLAG_IDX (_VAL2FLD(MSPI0_CQFLAGS_CQFLAGS, MSPI0_CQFLAGS_CQFLAGS_CQIDX))
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#define AM_HAL_MSPI_PAUSE_FLAG_CQ (_VAL2FLD(MSPI0_CQFLAGS_CQFLAGS, MSPI0_CQFLAGS_CQFLAGS_SWFLAG7))
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#define AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP (_VAL2FLD(MSPI0_CQFLAGS_CQFLAGS, MSPI0_CQFLAGS_CQFLAGS_SWFLAG6))
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#define AM_HAL_MSPI_PAUSE_FLAG_BLOCK (_VAL2FLD(MSPI0_CQFLAGS_CQFLAGS, MSPI0_CQFLAGS_CQFLAGS_SWFLAG5))
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// By default - we Pause CQ for no more entries, or force pause from SW
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#define AM_HAL_MSPI_PAUSE_DEFAULT (AM_HAL_MSPI_PAUSE_FLAG_IDX)
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#define AM_HAL_MSPI_CQP_PAUSE_DEFAULT (AM_HAL_MSPI_PAUSE_FLAG_IDX | AM_HAL_MSPI_PAUSE_FLAG_CQ)
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//*****************************************************************************
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//
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//! @name MSPI Interrupts
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//! @brief Macro definitions for MSPI interrupt status bits.
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//!
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//! These macros correspond to the bits in the MSPI interrupt status register.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_MSPI_INT_SCRERR MSPI0_INTEN_SCRERR_Msk
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#define AM_HAL_MSPI_INT_CQERR MSPI0_INTEN_CQERR_Msk
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#define AM_HAL_MSPI_INT_CQPAUSED MSPI0_INTEN_CQPAUSED_Msk
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#define AM_HAL_MSPI_INT_CQUPD MSPI0_INTEN_CQUPD_Msk
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#define AM_HAL_MSPI_INT_CQCMP MSPI0_INTEN_CQCMP_Msk
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#define AM_HAL_MSPI_INT_DMAERR MSPI0_INTEN_DERR_Msk
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#define AM_HAL_MSPI_INT_DMACMP MSPI0_INTEN_DCMP_Msk
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#define AM_HAL_MSPI_INT_RX_FIFO_FULL MSPI0_INTEN_RXF_Msk
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#define AM_HAL_MSPI_INT_RX_FIFO_OVFL MSPI0_INTEN_RXO_Msk
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#define AM_HAL_MSPI_INT_RX_FIFO_UNFL MSPI0_INTEN_RXU_Msk
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#define AM_HAL_MSPI_INT_TX_FIFO_OVFL MSPI0_INTEN_TXO_Msk
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#define AM_HAL_MSPI_INT_TX_FIFO_EMPTY MSPI0_INTEN_TXE_Msk
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#define AM_HAL_MSPI_INT_CMDCMP MSPI0_INTEN_CMDCMP_Msk
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#define AM_HAL_MSPI_INT_ALL 0xFFFFFFFF
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#define AM_HAL_MSPI_INT_ERR (AM_HAL_MSPI_INT_DMAERR | AM_HAL_MSPI_INT_CQERR | AM_HAL_MSPI_INT_SCRERR)
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#define AM_HAL_MSPI_LINK_NONE 0x7
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#define AM_HAL_MSPI_LINK_BASE 0x8
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//*****************************************************************************
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//
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//! Internal macros to support CMSIS-Style macros
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//! These should never be used from callers
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//
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//*****************************************************************************
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#define MSPI_IRQn_temp(n) (MSPI##n##_IRQn)
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#define MSPI_XIP_BASEADDRn_temp(n) (MSPI##n##_XIP_BASEADDR)
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#define MSPI_XIPMM_BASEADDRn_temp(n) (MSPI##n##_XIPMM_BASEADDR)
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//*****************************************************************************
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//
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//! @brief Configuration structure for the MSPI.
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//
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//*****************************************************************************
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//
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// Number of bytes in the address
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//
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typedef enum
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{
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AM_HAL_MSPI_ADDR_1_BYTE,
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AM_HAL_MSPI_ADDR_2_BYTE,
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AM_HAL_MSPI_ADDR_3_BYTE,
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AM_HAL_MSPI_ADDR_4_BYTE
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} am_hal_mspi_addr_e;
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//
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// Number of bytes in the instruction
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//
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typedef enum
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{
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AM_HAL_MSPI_INSTR_1_BYTE,
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AM_HAL_MSPI_INSTR_2_BYTE
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} am_hal_mspi_instr_e;
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//
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// Transmit or receive
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//
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typedef enum
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{
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AM_HAL_MSPI_RX = 0,
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AM_HAL_MSPI_TX = 1
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} am_hal_mspi_dir_e;
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//
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// Mode of Transfer.
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//
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typedef enum
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{
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AM_HAL_MSPI_TRANS_PIO,
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AM_HAL_MSPI_TRANS_DMA
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} am_hal_mspi_trans_e;
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//
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// MSPI interface mode and chip enable selection
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//
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typedef enum
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{
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AM_HAL_MSPI_FLASH_SERIAL_CE0,
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AM_HAL_MSPI_FLASH_SERIAL_CE1,
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AM_HAL_MSPI_FLASH_DUAL_CE0,
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AM_HAL_MSPI_FLASH_DUAL_CE1,
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AM_HAL_MSPI_FLASH_QUAD_CE0,
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AM_HAL_MSPI_FLASH_QUAD_CE1,
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AM_HAL_MSPI_FLASH_OCTAL_CE0,
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AM_HAL_MSPI_FLASH_OCTAL_CE1,
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AM_HAL_MSPI_FLASH_QUADPAIRED,
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AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL,
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AM_HAL_MSPI_FLASH_MAX = AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL
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} am_hal_mspi_device_e;
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//
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// Enumerate the SPI modes. Note that these are arranged per the ordering of
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// SPHA (bit1) and SPOL (bit0) in the IOM.MSPICFG register.
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//
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typedef enum
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{
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AM_HAL_MSPI_SPI_MODE_0, // CPOL = 0; CPHA = 0
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AM_HAL_MSPI_SPI_MODE_2, // CPOL = 1; CPHA = 0
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AM_HAL_MSPI_SPI_MODE_1, // CPOL = 0; CPHA = 1
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AM_HAL_MSPI_SPI_MODE_3, // CPOL = 1; CPHA = 1
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} am_hal_mspi_spi_mode_e;
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typedef enum
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{
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AM_HAL_MSPI_CLK_48MHZ = 1,
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AM_HAL_MSPI_CLK_24MHZ = 2,
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AM_HAL_MSPI_CLK_16MHZ = 3,
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AM_HAL_MSPI_CLK_12MHZ = 4,
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AM_HAL_MSPI_CLK_8MHZ = 6,
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AM_HAL_MSPI_CLK_6MHZ = 8,
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AM_HAL_MSPI_CLK_4P8MHZ = 10,
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AM_HAL_MSPI_CLK_4MHZ = 12,
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AM_HAL_MSPI_CLK_3P2MHZ = 15,
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AM_HAL_MSPI_CLK_3MHZ = 16,
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AM_HAL_MSPI_CLK_1P5MHZ = 32
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} am_hal_mspi_clock_e;
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//
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// Transfer callback function prototype
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//
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typedef void (*am_hal_mspi_callback_t)(void *pCallbackCtxt, uint32_t status);
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typedef struct
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{
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bool bDQSEnable;
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bool bOverrideRXDQSDelay;
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uint8_t ui8RxDQSDelay;
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bool bOverrideTXDQSDelay;
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uint8_t ui8TxDQSDelay;
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bool bDQSSyncNeg;
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uint8_t ui8DQSDelay;
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} am_hal_mspi_dqs_t;
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typedef struct
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{
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bool bLoop;
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//! Command Queue Transaction Gating
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uint32_t ui32PauseCondition;
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//! Command Queue Post-Transaction status setting
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uint32_t ui32StatusSetClr;
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} am_hal_mspi_seq_end_t;
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typedef struct
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{
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uint8_t *pBuf; // Buffer provided to store the high priority transaction context
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uint32_t size; // Size of buffer in bytes
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} am_hal_mspi_hiprio_cfg_t;
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typedef struct
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{
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//! Command Queue Advanced control on gating conditions for transaction to start
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uint32_t ui32PauseCondition;
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//! Command Queue Advanced Post-Transaction status setting
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uint32_t ui32StatusSetClr;
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am_hal_cmdq_entry_t *pCQEntry;
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uint32_t numEntries;
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am_hal_mspi_callback_t pfnCallback;
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void *pCallbackCtxt;
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uint32_t *pJmpAddr;
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} am_hal_mspi_cq_raw_t;
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typedef enum
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{
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// Pass uint32_t as pConfig
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AM_HAL_MSPI_REQ_APBCLK,
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// Used to set/clear 8 CQ Pause flags - reserved flags are defined as AM_HAL_MSPI_PAUSE_FLAG_RESV
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AM_HAL_MSPI_REQ_FLAG_SETCLR,
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// Pass uint32_t as pConfig indicating the IOM# to link to. AM_HAL_MSPI_LINK_NONE indicates no IOM linked
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AM_HAL_MSPI_REQ_LINK_IOM,
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// Pass uint32_t as pConfig indicating the MSPI# to link to. AM_HAL_MSPI_LINK_NONE indicates no MSPI linked
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AM_HAL_MSPI_REQ_LINK_MSPI,
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// pConfig N/A
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AM_HAL_MSPI_REQ_DCX_DIS,
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// pConfig N/A
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AM_HAL_MSPI_REQ_DCX_EN,
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// pConfig N/A
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AM_HAL_MSPI_REQ_SCRAMB_DIS,
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// pConfig N/A
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AM_HAL_MSPI_REQ_SCRAMB_EN,
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// Pass uint32_t as pConfig
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AM_HAL_MSPI_REQ_XIPACK,
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// pConfig N/A
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AM_HAL_MSPI_REQ_DDR_DIS,
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// pConfig N/A
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AM_HAL_MSPI_REQ_DDR_EN,
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// Pass am_hal_mspi_dqs_t as pConfig
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AM_HAL_MSPI_REQ_DQS,
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// pConfig N/A
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AM_HAL_MSPI_REQ_XIP_DIS,
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// pConfig N/A
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AM_HAL_MSPI_REQ_XIP_EN,
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// Pass mspi_device_info_t as pConfig
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AM_HAL_MSPI_REQ_DEVICE_CONFIG,
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// Pause the CQ gracefully
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AM_HAL_MSPI_REQ_PAUSE,
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// Unpause the CQ
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AM_HAL_MSPI_REQ_UNPAUSE,
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// Get in and out of Sequence Mode - which allows building a sequence, which either runs once, or repeats
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// Pass in bool as pConfig - true/false
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AM_HAL_MSPI_REQ_SET_SEQMODE,
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// Pass am_hal_mspi_seq_end_t * as pConfig
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AM_HAL_MSPI_REQ_SEQ_END,
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// Initialize configuration for high priority trasactions
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// These transactions take precedence over existing CQ transactions
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// Pass am_hal_mspi_hiprio_cfg_t * as pConfig
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AM_HAL_MSPI_REQ_INIT_HIPRIO,
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// Create a block of transactions which are not paused in between
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// pConfig N/A
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AM_HAL_MSPI_REQ_START_BLOCK,
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// pConfig N/A
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AM_HAL_MSPI_REQ_END_BLOCK,
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// Raw CQ transaction
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// Pass am_hal_mspi_cq_raw_t * as pConfig
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AM_HAL_MSPI_REQ_CQ_RAW,
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AM_HAL_MSPI_REQ_MAX
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} am_hal_mspi_request_e;
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typedef enum
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{
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AM_HAL_MSPI_XIPMIXED_NORMAL = 0,
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AM_HAL_MSPI_XIPMIXED_D2 = 1, //1:1:2 timing for Instr:Addr:Data
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AM_HAL_MSPI_XIPMIXED_AD2 = 3, //1:2:2 timing for Instr:Addr:Data
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AM_HAL_MSPI_XIPMIXED_D4 = 5, //1:1:4 timing for Instr:Addr:Data
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AM_HAL_MSPI_XIPMIXED_AD4 = 7 //1:4:4 timing for Instr:Addr:Data
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} am_hal_mspi_xipmixed_mode_e;
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typedef enum
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{
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AM_HAL_MSPI_BOUNDARY_NONE, // Disable DMA address boundary breaks
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AM_HAL_MSPI_BOUNDARY_BREAK32, //Break at 32 byte boundary (0x20 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK64, //Break at 64 byte boundary (0x40 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK128, //Break at 128 byte boundary (0x80 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK256, //Break at 256 byte boundary (0x100 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK512, //Break at 512 byte boundary (0x200 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK1K, //Break at 1KB boundary (0x400 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK2K, //Break at 2KB boundary (0x800 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK4K, //Break at 4KB boundary (0x1000 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK8K, //Break at 8KB boundary (0x2000 increments)
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AM_HAL_MSPI_BOUNDARY_BREAK16K, //Break at 16KB boundary (0x4000 increments)
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AM_HAL_MSPI_BOUNDARY_MAX
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} am_hal_mspi_dma_boundary_e;
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//
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// Device configuration structure
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//
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typedef struct
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{
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//
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// MSPI device configuration for Polling I/O (PIO) Operation.
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//
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//! Number of turn around cycles between an Address write and Data read.
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uint8_t ui8TurnAround;
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//! Address Configuration
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am_hal_mspi_addr_e eAddrCfg;
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//! Instruction Configuration
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am_hal_mspi_instr_e eInstrCfg;
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//! Read instruction sent to flash device
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uint8_t ui8ReadInstr;
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//! Write instruction sent to flash device
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uint8_t ui8WriteInstr;
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//! External Flash Device configuration
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am_hal_mspi_device_e eDeviceConfig;
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//! Write Latency
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uint8_t ui8WriteLatency;
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//
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// MSPI clock configuration.
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//
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//! SPI Mode.
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am_hal_mspi_spi_mode_e eSpiMode;
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//! Clock frequency
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am_hal_mspi_clock_e eClockFreq;
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//! XIPMIXED configure
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am_hal_mspi_xipmixed_mode_e eXipMixedMode;
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//! XIPENWLAT configure
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bool bEnWriteLatency;
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//
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// MSPI device configuration for XIP/DMA/Scrambling operations.
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//
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//! Send Device Address
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bool bSendAddr;
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//! Send Device Instruction
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bool bSendInstr;
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//! Separate MOSI/MISO
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bool bSeparateIO;
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//! Enable Turnaround between Address write and Data read.
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bool bTurnaround;
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//! Emulate DDR mode.
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bool bEmulateDDR;
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//
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// MSPI device DMA Boundary configuration.
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//
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//! Maximum time a DMA transaction is allowed before releasing CE.
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uint16_t ui16DMATimeLimit; // 100nsec units
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//! Maximum number of bytes DMA transaction is allowed before releasing CE.
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am_hal_mspi_dma_boundary_e eDMABoundary;
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//
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// MSPI DMA TCB/Command Queue memory allocation.
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|
//
|
|
|
|
//! DMA Transfer Control Buffer size in words.
|
|
uint32_t ui32TCBSize;
|
|
|
|
//! DMA Transfer Control Buffer
|
|
uint32_t *pTCB;
|
|
|
|
//
|
|
// MSPI Scrambling configuration.
|
|
//
|
|
|
|
//! Scrambling Start Address
|
|
uint32_t scramblingStartAddr;
|
|
|
|
//! Scrambling End Address
|
|
uint32_t scramblingEndAddr;
|
|
|
|
} am_hal_mspi_dev_config_t;
|
|
|
|
//
|
|
// MSPI configuration record for determining virtual device configuration.
|
|
//
|
|
typedef struct
|
|
{
|
|
//! External Flash Device configuration
|
|
am_hal_mspi_device_e eDeviceConfig;
|
|
|
|
//! XIPMIXED configure
|
|
am_hal_mspi_xipmixed_mode_e eXipMixedMode;
|
|
|
|
//! Separate MOSI/MISO
|
|
bool bSeparateIO;
|
|
|
|
} mspi_device_info_t;
|
|
//
|
|
// MSPI Capabilities structure
|
|
//
|
|
typedef struct
|
|
{
|
|
am_hal_mspi_device_e eDeviceConfig;
|
|
} am_hal_mspi_capabilities_t;
|
|
|
|
//
|
|
// Device PIO transfer structure
|
|
//
|
|
typedef struct
|
|
{
|
|
//! Number of bytes to transfer
|
|
uint32_t ui32NumBytes;
|
|
|
|
//! Enable scrambling.
|
|
bool bScrambling;
|
|
|
|
//! Enable DCX
|
|
bool bDCX;
|
|
|
|
//! Transfer Direction (Transmit/Receive)
|
|
am_hal_mspi_dir_e eDirection;
|
|
|
|
//! Send Device Address
|
|
bool bSendAddr;
|
|
|
|
//! Device Address
|
|
uint32_t ui32DeviceAddr;
|
|
|
|
//! Send Device Instruction
|
|
bool bSendInstr;
|
|
|
|
//! Device Instruction
|
|
uint16_t ui16DeviceInstr;
|
|
|
|
//! Enable Turnaround between Address write and Data read.
|
|
bool bTurnaround;
|
|
|
|
//! Enable Write Latency Counter
|
|
bool bEnWRLatency;
|
|
|
|
//! Paired-Quad
|
|
bool bQuadCmd;
|
|
|
|
//! Continuation
|
|
bool bContinue;
|
|
|
|
//! Buffer
|
|
uint32_t *pui32Buffer;
|
|
|
|
} am_hal_mspi_pio_transfer_t;
|
|
|
|
//
|
|
// DMA transfer structure
|
|
//
|
|
typedef struct
|
|
{
|
|
//! Priority 0 = Low (best effort); 1 = High (service immediately)
|
|
uint8_t ui8Priority;
|
|
|
|
//! Direction RX: 0 = Peripheral to Memory; TX: 1 = Memory to Peripheral
|
|
am_hal_mspi_dir_e eDirection;
|
|
|
|
//! Transfer Count
|
|
uint32_t ui32TransferCount;
|
|
|
|
//! External Flash Device Address
|
|
uint32_t ui32DeviceAddress;
|
|
|
|
//! Internal SRAM Address
|
|
uint32_t ui32SRAMAddress;
|
|
|
|
//! Command Queue Transaction Gating
|
|
uint32_t ui32PauseCondition;
|
|
//! Command Queue Post-Transaction status setting
|
|
uint32_t ui32StatusSetClr;
|
|
|
|
} am_hal_mspi_dma_transfer_t;
|
|
|
|
|
|
//
|
|
// MSPI status structure.
|
|
//
|
|
typedef struct
|
|
{
|
|
//
|
|
// DMA status.
|
|
//
|
|
bool bErr;
|
|
bool bCmp;
|
|
bool bTIP;
|
|
uint32_t ui32NumCQEntries;
|
|
} am_hal_mspi_status_t;
|
|
|
|
|
|
#define am_hal_mspi_buffer(A) \
|
|
union \
|
|
{ \
|
|
uint32_t words[(A + 3) >> 2]; \
|
|
uint8_t bytes[A]; \
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI initialization function
|
|
//!
|
|
//! @param ui32Module - module instance.
|
|
//! @param handle - returns the handle for the module instance.
|
|
//!
|
|
//! This function accepts a module instance, allocates the interface and then
|
|
//! returns a handle to be used by the remaining interface functions.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_initialize(uint32_t ui32Module,
|
|
void **ppHandle);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI deinitialization function
|
|
//!
|
|
//! @param handle - the handle for the module instance.
|
|
//!
|
|
//! This function accepts a handle to an instance and de-initializes the
|
|
//! interface.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_deinitialize(void *pHandle);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI device configuration function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param pConfig - pointer to the configuration structure.
|
|
//!
|
|
//! This function configures the MSPI settings for a particular external flash device.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_device_configure(void *pHandle,
|
|
am_hal_mspi_dev_config_t *pConfig);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI enable function
|
|
//!
|
|
//! @param handle - the handle for the module instance.
|
|
//!
|
|
//! This function accepts a handle to an instance and enables the
|
|
//! interface.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_enable(void *pHandle);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI disable function
|
|
//!
|
|
//! @param handle - the handle for the module instance.
|
|
//!
|
|
//! This function accepts a handle to an instance and disables the
|
|
//! interface.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_disable(void *pHandle);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI device specific control function.
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param request - device specific special request code.
|
|
//! @param pConfig - pointer to the request specific configuration.
|
|
//!
|
|
//! This function configures the MSPI settings for XIP or DMA operation.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_control(void *pHandle,
|
|
am_hal_mspi_request_e eRequest,
|
|
void *pConfig);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI capability interrogation function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param pCapabilities - pointer to an interface specific structure used to
|
|
//! return the capabilities of the interface.
|
|
//!
|
|
//! This function returns the specific capabilities of the MSPI. In some
|
|
//! cases the capabilities may be instance specific (e.g. maximum data rate).
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_capabilities_get(void *pHandle,
|
|
am_hal_mspi_capabilities_t **pCapabilities);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI blocking transfer function
|
|
//!
|
|
//! @param pHandle - handle for the interface.
|
|
//! @param pTransaction - pointer to the transaction control structure.
|
|
//! @param ui32Timeout - timeout in usecs.
|
|
//!
|
|
//! This function performs a transaction on the MSPI in PIO mode. It handles
|
|
//! half duplex transactions only (TX or RX).
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_blocking_transfer(void *pHandle,
|
|
am_hal_mspi_pio_transfer_t *pTransaction,
|
|
uint32_t ui32Timeout);
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI Non-Blocking transfer function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param pTransaction - pointer to the transaction control structure.
|
|
//! @param pfnCallback - pointer the callback function to be executed when
|
|
//! transaction is complete.
|
|
//!
|
|
//! This function performs a transaction on the MSPI using either DMA or the
|
|
//! Command Queue with DMA. It handles half duplex transactions.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle,
|
|
void *pTransfer,
|
|
am_hal_mspi_trans_e eMode,
|
|
am_hal_mspi_callback_t pfnCallback,
|
|
void *pCallbackCtxt);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI status function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//!
|
|
//! This function returns the current status of the DMA operation.
|
|
//!
|
|
//! @return status - DMA status flags.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_status_get(void *pHandle,
|
|
am_hal_mspi_status_t *pStatus );
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI enable interrupts function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param ui32IntMask - MSPI interrupt mask.
|
|
//!
|
|
//! This function enables the specific indicated interrupts.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_interrupt_enable(void *pHandle,
|
|
uint32_t ui32IntMask);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI disable interrupts function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param ui32IntMask - MSPI interrupt mask.
|
|
//!
|
|
//! This function disable the specific indicated interrupts.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_interrupt_disable(void *pHandle,
|
|
uint32_t ui32IntMask);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI interrupt status function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param pui32Status - returns the interrupt status value.
|
|
//! @param bEnabledOnly - TRUE: only report interrupt status for enalbed ints.
|
|
//! FALSE: report all interrupt status values.
|
|
//!
|
|
//! This function returns the specific indicated interrupt status.
|
|
//!
|
|
//! @return status - interrupt status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_interrupt_status_get(void *pHandle,
|
|
uint32_t *pui32Status,
|
|
bool bEnabledOnly);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI interrupt clear
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param ui32IntMask - uint32_t for interrupts to clear
|
|
//!
|
|
//! This function clears the interrupts for the given peripheral.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_interrupt_clear(void *pHandle,
|
|
uint32_t ui32IntMask);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI interrupt service routine
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param ui32IntStatus - interrupt status.
|
|
//!
|
|
//! This function is designed to be called from within the user defined ISR
|
|
//! in order to service the non-blocking, queued, or DMA processing for a given
|
|
//! module instance.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_interrupt_service(void *pHandle,
|
|
uint32_t ui32IntStatus);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief MSPI power control function
|
|
//!
|
|
//! @param handle - handle for the interface.
|
|
//! @param ePowerState - the desired power state to move the peripheral to.
|
|
//! @param bRetainState - flag (if true) to save/restore peripheral state upon
|
|
//! power state change.
|
|
//!
|
|
//! This function updates the peripheral to a given power state.
|
|
//!
|
|
//! @return status - generic or interface specific status.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint32_t am_hal_mspi_power_control(void *pHandle,
|
|
am_hal_sysctrl_power_state_e ePowerState,
|
|
bool bRetainState);
|
|
//
|
|
// MSPI High Priority transfer function
|
|
//
|
|
extern uint32_t am_hal_mspi_highprio_transfer(void *pHandle,
|
|
am_hal_mspi_dma_transfer_t *pTransfer,
|
|
am_hal_mspi_trans_e eMode,
|
|
am_hal_mspi_callback_t pfnCallback,
|
|
void *pCallbackCtxt);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // AM_HAL_MSPI_H
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|