370 lines
13 KiB
C
370 lines
13 KiB
C
//*****************************************************************************
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//
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// am_reg_jedec.h
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//! @file
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//!
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//! @brief Register macros for the ARM JEDEC module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_JEDEC_H
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#define AM_REG_JEDEC_H
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//*****************************************************************************
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//
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// JEDEC
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_JEDEC_NUM_MODULES 1
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#define AM_REG_JEDECn(n) \
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(REG_JEDEC_BASEADDR + 0x00000000 * n)
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/* ======================================== Start of section using anonymous unions ======================================== */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language = extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
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#pragma clang diagnostic ignored "-Wnested-anon-types"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/**
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\brief Structure type to access the Apollo CM4 JEDEC registers.
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*/
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typedef struct
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{
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uint32_t RESERVED0[52U]; /* 0xF00 - 0xFCF */
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union
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{
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__IM uint32_t PID4; /*!< 0xF0000FD0 (R/ ) PID4 Register */
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struct
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{
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__IM uint32_t JEPCONT : 4; /* [3..0] Contains the JEP Continuation bits. */
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} PID4_b;
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};
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union
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{
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__IM uint32_t PID5; /*!< 0xF0000FD4 (R/ ) PID5 Register */
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struct
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{
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__IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */
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} PID5_b;
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};
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union
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{
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__IM uint32_t PID6; /*!< 0xF0000FD8 (R/ ) PID6 Register */
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struct
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{
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__IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */
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} PID6_b;
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};
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union
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{
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__IM uint32_t PID7; /*!< 0xF0000FDC (R/ ) PID7 Register */
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struct
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{
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__IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */
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} PID7_b;
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};
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union
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{
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__IM uint32_t PID0; /*!< 0xF0000FE0 (R/ ) PID0 Register */
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struct
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{
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__IM uint32_t PNL8 : 8; /* [7..0] Contains the low 8 bits of the Ambiq Micro device part number. */
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} PID0_b;
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};
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union
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{
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__IM uint32_t PID1; /*!< 0xF0000FE4 (R/ ) PID1 Register */
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struct
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{
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__IM uint32_t PNH4 : 4; /* [3..0] Contains the high 4 bits of the Ambiq Micro device part number. */
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__IM uint32_t JEPIDL : 4; /* [7..4] Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID is therefore 0x9B. */
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} PID1_b;
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};
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union
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{
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__IM uint32_t PID2; /*!< 0xF0000FE8 (R/ ) PID2 Register */
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struct
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{
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__IM uint32_t JEPIDH : 4; /* [3..0] Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this field is hard-coded to 1. The full JEPID is therefore 0x9B. */
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__IM uint32_t CHIPREVH4 : 4; /* [7..4] Contains the high 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */
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} PID2_b;
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};
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union
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{
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__IM uint32_t PID3; /*!< 0xF0000FEC (R/ ) PID3 Register */
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struct
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{
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__IM uint32_t ZERO : 4; /* [3..0] This field is hard-coded to 0x0. */
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__IM uint32_t CHIPREVL4 : 4; /* [7..0] Contains the low 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */
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} PID3_b;
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};
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union
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{
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__IM uint32_t CID0; /*!< 0xF0000FE0 (R/ ) CID0 Register */
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struct
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{
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__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID0. */
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} CID0_b;
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};
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union
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{
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__IM uint32_t CID1; /*!< 0xF0000FE4 (R/ ) CID1 Register */
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struct
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{
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__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID1. */
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} CID1_b;
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};
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union
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{
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__IM uint32_t CID2; /*!< 0xF0000FE8 (R/ ) CID2 Register */
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struct
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{
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__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID2. */
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} CID2_b;
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};
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union
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{
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__IM uint32_t CID3; /*!< 0xF0000FEC (R/ ) CID3 Register */
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struct
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{
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__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID3. */
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} CID3_b;
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};
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} JEDEC_Type;
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//*****************************************************************************
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//
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// JEDEC_PID4 - JEP Continuation Register
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//
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//*****************************************************************************
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// Contains the JEP Continuation bits.
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#define JEDEC_PID4_JEPCONT_Pos 0U
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#define JEDEC_PID4_JEPCONT_Msk (0x0000000FUL)
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//*****************************************************************************
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//
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// JEDEC_PID5 - JEP reserved Register
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//
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//*****************************************************************************
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// Contains the value of 0x00000000.
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#define JEDEC_PID5_VALUE_Pos 0U
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#define JEDEC_PID5_VALUE_Msk (0xFFFFFFFFUL)
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//*****************************************************************************
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//
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// JEDEC_PID6 - JEP reserved Register
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//
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//*****************************************************************************
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// Contains the value of 0x00000000.
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#define JEDEC_PID6_VALUE_Pos 0U
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#define JEDEC_PID6_VALUE_Msk (0xFFFFFFFFUL)
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//*****************************************************************************
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//
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// JEDEC_PID7 - JEP reserved Register
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//
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//*****************************************************************************
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// Contains the value of 0x00000000.
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#define JEDEC_PID7_VALUE_Pos 0U
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#define JEDEC_PID7_VALUE_Msk (0xFFFFFFFFUL)
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//*****************************************************************************
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//
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// JEDEC_PID0 - Ambiq Partnum low byte
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//
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//*****************************************************************************
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// Contains the low 8 bits of the Ambiq Micro device part number.
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#define JEDEC_PID0_PNL8_Pos 0U
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#define JEDEC_PID0_PNL8_Msk (0x000000FFUL)
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//*****************************************************************************
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//
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// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble.
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//
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//*****************************************************************************
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// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID
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// is therefore 0x9B.
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#define JEDEC_PID1_JEPIDL_Pos 4U
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#define JEDEC_PID1_JEPIDL_Msk (0x000000F0UL)
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// Contains the high 4 bits of the Ambiq Micro device part number.
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#define JEDEC_PID1_PNH4_Pos 0U
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#define JEDEC_PID1_PNH4_Msk (0x0000000FUL)
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//*****************************************************************************
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//
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// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble
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//
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//*****************************************************************************
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// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also
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// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
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// chip.
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#define JEDEC_PID2_CHIPREVH4_Pos 4U
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#define JEDEC_PID2_CHIPREVH4_Msk (0x000000F0UL)
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// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this
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// field is hard-coded to 1. The full JEPID is therefore 0x9B.
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#define JEDEC_PID2_JEPIDH_Pos 0U
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#define JEDEC_PID2_JEPIDH_Msk (0x0000000FUL)
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//*****************************************************************************
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//
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// JEDEC_PID3 - Ambiq chip revision high-nibble.
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//
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//*****************************************************************************
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// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also
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// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
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// chip.
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#define JEDEC_PID3_CHIPREVL4_Pos 4U
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#define JEDEC_PID3_CHIPREVL4_Msk (0x000000F0UL)
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// This field is hard-coded to 0x0.
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#define JEDEC_PID3_ZERO_Pos 0U
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#define JEDEC_PID3_ZERO_Msk (0x0000000FUL)
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//*****************************************************************************
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//
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// JEDEC_CID0 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID0.
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#define JEDEC_CID0_CID_Pos 0U
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#define JEDEC_CID0_CID_Msk (0x000000FFUL)
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//*****************************************************************************
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//
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// JEDEC_CID1 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID1.
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#define JEDEC_CID1_CID_Pos 0U
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#define JEDEC_CID1_CID_Msk (0x000000FFUL)
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//*****************************************************************************
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//
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// JEDEC_CID2 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID2.
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#define JEDEC_CID2_CID_Pos 0U
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#define JEDEC_CID2_CID_Msk (0x000000FFUL)
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//*****************************************************************************
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//
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// JEDEC_CID3 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID3.
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#define JEDEC_CID3_CID_Pos 0U
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#define JEDEC_CID3_CID_Msk (0x000000FFUL)
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#define JEDEC_BASE (0xF0000F00UL) /*!< JEDEC Base Address */
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#define JEDEC ((JEDEC_Type *) JEDEC_BASE ) /*!< JEDEC configuration struct */
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/* ========================================= End of section using anonymous unions ========================================= */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#endif
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#endif // AM_REG_JEDEC_H
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