290 lines
10 KiB
C
290 lines
10 KiB
C
// ****************************************************************************
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//
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// am_hal_cachectrl.h
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//! @file
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//!
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//! @brief Functions for accessing and configuring the CACHE controller.
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//!
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//! @addtogroup cachectrl3 Cache Control (CACHE)
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//! @ingroup apollo3hal
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//! @{
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//
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// ****************************************************************************
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// ****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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// ****************************************************************************
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#ifndef AM_HAL_CACHECTRL_H
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#define AM_HAL_CACHECTRL_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//
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// Designate this peripheral.
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//
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#define AM_APOLLO3_CACHECTRL 1
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//
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// Cachectrl status.
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//
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typedef struct
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{
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bool bFlash0SleepMode;
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bool bFlash1SleepMode;
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bool bCacheReady;
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} am_hal_cachectrl_status_t;
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// ****************************************************************************
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//
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//! @name Cache Config
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//! @brief Configuration selection for the cache.
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//!
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//! These macros may be used in conjunction with the
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//! am_hal_cachectrl_cache_config() function to select the cache type.
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//!
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//! @{
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//
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// ****************************************************************************
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//
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// Cache description type, where:
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// nWay = number of ways (associativity)
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// 128B = 128 bits linesize
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// 512E = 512 entries, 1024E = 1024 entries
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//
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typedef enum
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{
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AM_HAL_CACHECTRL_DESCR_1WAY_128B_512E = CACHECTRL_CACHECFG_CONFIG_W1_128B_512E,
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AM_HAL_CACHECTRL_DESCR_2WAY_128B_512E = CACHECTRL_CACHECFG_CONFIG_W2_128B_512E,
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AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E = CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E
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} am_hal_cachectrl_descr_e;
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typedef enum
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{
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AM_HAL_CACHECTRL_NCR0 = 0,
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AM_HAL_CACHECTRL_NCR1 = 1
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} am_hal_cachectrl_nc_region_e;
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// Config struture for AM_HAL_CACHECTRL_CONTROL_NC_CFG
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typedef struct
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{
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am_hal_cachectrl_nc_region_e eNCRegion;
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bool bEnable;
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uint32_t ui32StartAddr;
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uint32_t ui32EndAddr;
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} am_hal_cachectrl_nc_cfg_t;
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//
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// Control operations.
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//
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typedef enum
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{
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AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE = 1,
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AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET,
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AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE,
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AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE,
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AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE,
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AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE,
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AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE,
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AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE,
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AM_HAL_CACHECTRL_CONTROL_MONITOR_ENABLE,
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AM_HAL_CACHECTRL_CONTROL_MONITOR_DISABLE,
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AM_HAL_CACHECTRL_CONTROL_LPMMODE_RESET,
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AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED,
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AM_HAL_CACHECTRL_CONTROL_LPMMODE_AGGRESSIVE,
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AM_HAL_CACHECTRL_CONTROL_LPMMODE_SET,
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AM_HAL_CACHECTRL_CONTROL_SEDELAY_SET,
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AM_HAL_CACHECTRL_CONTROL_RDWAIT_SET,
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// Configure up to two non-cacheable regions
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AM_HAL_CACHECTRL_CONTROL_NC_CFG,
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} am_hal_cachectrl_control_e;
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//
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// Cache config values used for ui8Mode.
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//
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typedef enum
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{
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// Note - this enum ordering is critical, do not modify.
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AM_HAL_CACHECTRL_CONFIG_MODE_DISABLE,
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AM_HAL_CACHECTRL_CONFIG_MODE_INSTR,
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AM_HAL_CACHECTRL_CONFIG_MODE_DATA,
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AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA
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} am_hal_cachectrl_config_mode_e;
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//
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// FLASHCFG LPMMODE.
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//
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typedef enum
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{
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AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_NEVER = CACHECTRL_FLASHCFG_LPMMODE_NEVER,
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AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY = CACHECTRL_FLASHCFG_LPMMODE_STANDBY,
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AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_ALWAYS = CACHECTRL_FLASHCFG_LPMMODE_ALWAYS
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} am_hal_cachectrl_flashcfg_lppmode_e;
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// ****************************************************************************
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//
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// Cache configuration structure
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// This structure used for am_hal_cachectrl_config().
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//
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// ****************************************************************************
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typedef struct
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{
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//
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//! Set to one of:
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//! AM_HAL_CACHECTRL_DESCR_1WAY_128B_512E
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//! Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active)
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//! AM_HAL_CACHECTRL_DESCR_2WAY_128B_512E
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//! Two way set associative, 128-bit linesize, 512 entries (8 SRAMs active)
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//! AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E
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//! Direct-mapped set associative, 128-bit linesize, 1024 entries (8 SRAMs active)
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am_hal_cachectrl_descr_e eDescript;
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//
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//! Set to one of the following:
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//! AM_HAL_CACHECTRL_CONFIG_MODE_DISABLE - Disable both instr and data caching
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//! AM_HAL_CACHECTRL_CONFIG_MODE_INSTR - Enable instr caching only
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//! AM_HAL_CACHECTRL_CONFIG_MODE_DATA - Enable data caching only
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//! AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA - Enable both instr and data caching
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am_hal_cachectrl_config_mode_e eMode;
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//
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//! Set to true to enable the LRU (least recently used) replacement policy.
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//! Set to false to enable the LRR (least recently replaced) replacement policy.
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//! Note - LRR minimizes writes to the TAG SRAM.
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//
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bool bLRU;
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} am_hal_cachectrl_config_t;
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extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults;
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// ****************************************************************************
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//
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// Function prototypes
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//
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// ****************************************************************************
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// ****************************************************************************
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//
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//! @brief Configure the cache using the supplied settings.
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//!
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//! @param psConfig - pointer to a config structure containing cache settings.
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//!
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//! This function takes in a structure of cache settings and uses them to
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//! configure the cache. This function will configures all of the settings in
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//! the structure as well as recommended settings for various other cache
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//! configuration parameters.
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//!
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//! This function does NOT enable the cache, which is handled in a separate
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//! function. In fact, if the cache is enabled prior to calling this function,
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//! it will return from the call disabled.
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//!
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//! For most applications, the default cache settings will be the most
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//! efficient choice. To use the default cache settings with this function, use
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//! the address of the global am_hal_cachectrl_defaults structure as the
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//! psConfig argument.
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//!
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//! @return Status.
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//
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// ****************************************************************************
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extern uint32_t am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig);
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// ****************************************************************************
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//
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//! @brief Enable the cache.
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//!
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//! Enable the cache for operation.
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//!
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//! @return Status.
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//
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// ****************************************************************************
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extern uint32_t am_hal_cachectrl_enable(void);
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// ****************************************************************************
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//
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//! @brief Disable the cache.
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//!
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//! Use this function to disable cache. Other configuration settings are not
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//! not required.
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//!
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//! @return Status.
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//
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// ****************************************************************************
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extern uint32_t am_hal_cachectrl_disable(void);
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// ****************************************************************************
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//
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//! @brief Assert various specific controls on the cache.
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//!
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//! This function is used to apply various controls on the cache.
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//!
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//! @param eControl - One of the following:
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//! AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE
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//! AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET
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//! AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE,
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//! AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE,
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//! AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE
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//! AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE
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//! AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE
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//! AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE
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//!
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//! @return status - generic or interface specific status.
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//
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// ****************************************************************************
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extern uint32_t am_hal_cachectrl_control(am_hal_cachectrl_control_e eControl,
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void *pArgs);
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// ****************************************************************************
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//
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//! @brief Cache controller status function
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//!
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//! This function returns the current status of the cache.
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//!
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//! @param psStatus - ptr to a status structure to receive the current statuses.
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//!
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//! @return status - generic or interface specific status.
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//
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// ****************************************************************************
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extern uint32_t am_hal_cachectrl_status_get(am_hal_cachectrl_status_t *psStatus);
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#ifdef __cplusplus
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}
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#endif
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#endif // AM_HAL_CACHECTRL_H
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