289 lines
9.4 KiB
C
289 lines
9.4 KiB
C
//*****************************************************************************
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//
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// am_hal_sysctrl.c
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//! @file
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//!
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//! @brief Functions for interfacing with the M4F system control registers
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//!
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//! @addtogroup sysctrl1 System Control (SYSCTRL)
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//! @ingroup apollo1hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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//! @brief Place the core into sleep or deepsleep.
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//!
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//! @param bSleepDeep - False for Normal or True Deep sleep.
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//!
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//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep.
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//!
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//! Valid values for bSleepDeep are:
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//!
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//! AM_HAL_SYSCTRL_SLEEP_NORMAL
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//! AM_HAL_SYSCTRL_SLEEP_DEEP
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_sleep(bool bSleepDeep)
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{
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//
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// If the user selected DEEPSLEEP and the TPIU is off, attempt to enter
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// DEEP SLEEP.
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//
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if ((bSleepDeep == AM_HAL_SYSCTRL_SLEEP_DEEP) &&
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(AM_BFM(MCUCTRL, TPIUCTRL, ENABLE) == AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS))
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{
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//
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// Prepare the core for deepsleep (write 1 to the DEEPSLEEP bit).
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//
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AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 1);
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}
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else
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{
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AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 0);
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}
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//
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// Before executing WFI, flush any buffered core and peripheral writes.
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//
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AM_ASM_DSB
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//
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// Go to sleep.
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//
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AM_ASM_WFI;
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//
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// Upon wake, execute the Instruction Sync Barrier instruction.
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//
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AM_ASM_ISB
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}
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//*****************************************************************************
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//
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//! @brief Place the core into the deepest sleep state possible
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//!
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//! This function puts the MCU to sleep or deepsleep depending on which
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//! peripherals are on. If the UART or either IOM module is enabled, the MCU
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//! will be placed into normal sleep. Otherwise, the MCU will go to deep sleep.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_sleep_auto(void)
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{
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//
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// If any of the HFRC peripherals are on, go to normal sleep. Otherwise go
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// to deep sleep.
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//
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if (AM_BFM(MCUCTRL, TPIUCTRL, ENABLE) || AM_BFMn(IOMSTR, 0, CFG, IFCEN) ||
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AM_BFMn(IOMSTR, 1, CFG, IFCEN) || AM_REG(CLKGEN, UARTEN))
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{
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AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 1);
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}
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else
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{
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AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 0);
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}
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//
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// Before executing WFI, flush any buffered core and peripheral writes.
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//
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AM_ASM_DSB
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//
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// Go to sleep.
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//
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AM_ASM_WFI;
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//
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// Upon wake, execute the Instruction Sync Barrier instruction.
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//
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AM_ASM_ISB
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}
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//*****************************************************************************
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//
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//! @brief Enable the floating point module.
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//!
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//! Call this function to enable the ARM hardware floating point module.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_enable(void)
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{
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//
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// Enable access to the FPU in both privileged and user modes.
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// NOTE: Write 0s to all reserved fields in this register.
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//
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AM_REG(SYSCTRL, CPACR) = (AM_REG_SYSCTRL_CPACR_CP11(0x3) |
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AM_REG_SYSCTRL_CPACR_CP10(0x3));
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}
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//*****************************************************************************
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//
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//! @brief Disable the floating point module.
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//!
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//! Call this function to disable the ARM hardware floating point module.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_disable(void)
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{
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//
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// Disable access to the FPU in both privileged and user modes.
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// NOTE: Write 0s to all reserved fields in this register.
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//
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AM_REG(SYSCTRL, CPACR) = 0x00000000 &
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~(AM_REG_SYSCTRL_CPACR_CP11(0x3) |
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AM_REG_SYSCTRL_CPACR_CP10(0x3));
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}
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//*****************************************************************************
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//
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//! @brief Enable stacking of FPU registers on exception entry.
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//!
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//! @param bLazy - Set to "true" to enable "lazy stacking".
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//!
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//! This function allows the core to save floating-point information to the
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//! stack on exception entry. Setting the bLazy option enables "lazy stacking"
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//! for interrupt handlers. Normally, mixing floating-point code and interrupt
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//! driven routines causes increased interrupt latency, because the core must
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//! save extra information to the stack upon exception entry. With the lazy
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//! stacking option enabled, the core will skip the saving of floating-point
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//! registers when possible, reducing average interrupt latency.
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//!
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//! @note At reset of the Cortex M4, the ASPEN and LSPEN bits are set to 1,
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//! enabling Lazy mode by default. Therefore this function will generally
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//! only have an affect when setting for full-context save (or when switching
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//! from full-context to lazy mode).
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//!
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//! @note See also:
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//! infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/DAFGGBJD.html
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//!
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//! @note Three valid FPU context saving modes are possible.
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//! 1. Lazy ASPEN=1 LSPEN=1 am_hal_sysctrl_fpu_stacking_enable(true)
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//! and default.
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//! 2. Full-context ASPEN=1 LSPEN=0 am_hal_sysctrl_fpu_stacking_enable(false)
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//! 3. No FPU state ASPEN=0 LSPEN=0 am_hal_sysctrl_fpu_stacking_disable()
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//! 4. Invalid ASPEN=0 LSPEN=1
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_stacking_enable(bool bLazy)
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{
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#define SYSCTRL_FPCCR_LAZY (AM_REG_SYSCTRL_FPCCR_ASPEN_M | AM_REG_SYSCTRL_FPCCR_LSPEN_M)
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uint32_t ui32fpccr;
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//
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// Set the requested FPU stacking mode in ISRs.
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//
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AM_CRITICAL_BEGIN
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ui32fpccr = AM_REG(SYSCTRL, FPCCR);
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ui32fpccr &= ~(SYSCTRL_FPCCR_LAZY);
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ui32fpccr |= (bLazy ? SYSCTRL_FPCCR_LAZY : AM_REG_SYSCTRL_FPCCR_ASPEN_M);
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AM_REG(SYSCTRL, FPCCR) = ui32fpccr;
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AM_CRITICAL_END
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}
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//*****************************************************************************
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//
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//! @brief Disable FPU register stacking on exception entry.
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//!
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//! This function disables all stacking of floating point registers for
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//! interrupt handlers. This mode should only be used when it is absolutely
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//! known that no FPU instructions will be executed in an ISR.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_stacking_disable(void)
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{
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//
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// Completely disable FPU context save on entry to ISRs.
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//
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AM_CRITICAL_BEGIN
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AM_REG(SYSCTRL, FPCCR) &= ~SYSCTRL_FPCCR_LAZY;
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AM_CRITICAL_END
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}
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//*****************************************************************************
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//
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//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl.
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//!
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//! This function issues a system wide reset (Apollo POR level reset).
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_reset(void)
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{
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//
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// Set the system reset bit in the AIRCR register
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//
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AM_REG(SYSCTRL, AIRCR) = AM_REG_SYSCTRL_AIRCR_VECTKEY(0x5FA) |
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AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(1);
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}
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//*****************************************************************************
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//
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// End Doxygen group.
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//! @}
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//
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//*****************************************************************************
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