2830 lines
121 KiB
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2830 lines
121 KiB
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<title>AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview</title>
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<img alt="Logo" src="../resources/am_logo.png" />
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</td>
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<td style="padding-left: 0.5em;">
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<div id="projectname">Apollo Register Documentation  <span id="projectnumber">v2.4.2</span></div>
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</td>
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<!-- window showing the filter options -->
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<div class="header">
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<div class="title">PDM - PDM Audio</div>
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</div>
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<!--header-->
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<body>
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<br>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 class="panel-title"> PDM Register Index</h3>
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</div>
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<div class="panel-body">
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<table>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000000:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#PCFG" target="_self">PCFG - PDM Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000004:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#VCFG" target="_self">VCFG - Voice Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000008:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#VOICESTAT" target="_self">VOICESTAT - Voice Status Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000000C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOREAD" target="_self">FIFOREAD - FIFO Read</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000010:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOFLUSH" target="_self">FIFOFLUSH - FIFO Flush</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000014:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOTHR" target="_self">FIFOTHR - FIFO Threshold</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000200:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTEN" target="_self">INTEN - IO Master Interrupts: Enable</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000204:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTSTAT" target="_self">INTSTAT - IO Master Interrupts: Status</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000208:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTCLR" target="_self">INTCLR - IO Master Interrupts: Clear</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000020C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTSET" target="_self">INTSET - IO Master Interrupts: Set</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000240:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DMATRIGEN" target="_self">DMATRIGEN - DMA Trigger Enable Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000244:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DMATRIGSTAT" target="_self">DMATRIGSTAT - DMA Trigger Status Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000280:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DMACFG" target="_self">DMACFG - DMA Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000288:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DMATOTCOUNT" target="_self">DMATOTCOUNT - DMA Total Transfer Count</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000028C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DMATARGADDR" target="_self">DMATARGADDR - DMA Target Address Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000290:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DMASTAT" target="_self">DMASTAT - DMA Status Register</a>
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</td>
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</tr>
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</table>
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</div>
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</div>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 id="PCFG" class="panel-title">PCFG - PDM Configuration Register</h3>
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</div>
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<div class="panel-body">
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<h3>Address:</h3>
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<table style="margin:10px">
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">Instance 0 Address:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x50011000</span>
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</td>
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</tr>
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</table>
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<h3>Description:</h3>
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<p>PDM Configuration Register</p>
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<h3>Example Macro Usage:</h3>
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<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
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// Register access is all performed through the standard CMSIS structure-based
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// interface. This includes module-level structure definitions with members and
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// bitfields corresponding to the physical registers and bitfields within each
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// module. In addition, Ambiq has provided instance-level macros for modules
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// that have more than one physical instance and a generic AM_REGVAL() macro
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// for directly accessing memory by address.
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//
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// The following examples show how to use these structures and macros:
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// Setting the ADC configuration register...</span>
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AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
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ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
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ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
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<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
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ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
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ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
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<h3>Register Fields:</h3>
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<table style="margin:10px" class="table table-bordered table-condensed">
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<thead>
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<tr>
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<th>31</th>
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<th>30</th>
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<th>29</th>
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<th>28</th>
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<th>27</th>
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<th>26</th>
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<th>25</th>
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<th>24</th>
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<th>23</th>
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<th>22</th>
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<th>21</th>
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<th>20</th>
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<th>19</th>
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<th>18</th>
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<th>17</th>
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<th>16</th>
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<th>15</th>
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<th>14</th>
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<th>13</th>
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<th>12</th>
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<th>11</th>
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<th>10</th>
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<th>9</th>
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<th>8</th>
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<th>7</th>
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<th>6</th>
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<th>5</th>
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<th>4</th>
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<th>3</th>
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<th>2</th>
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<th>1</th>
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<th>0</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td align="center" colspan="1">LRSWAP
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<br>0x0</td>
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<td align="center" colspan="5">PGARIGHT
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<br>0x0</td>
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<td align="center" colspan="5">PGALEFT
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<br>0x0</td>
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<td align="center" colspan="2">RSVD
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<br>0x0</td>
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<td align="center" colspan="2">MCLKDIV
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<br>0x0</td>
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<td align="center" colspan="7">SINCRATE
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<br>0x30</td>
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<td align="center" colspan="1">ADCHPD
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<br>0x1</td>
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<td align="center" colspan="4">HPCUTOFF
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<br>0xb</td>
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<td align="center" colspan="3">CYCLES
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<br>0x1</td>
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<td align="center" colspan="1">SOFTMUTE
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<br>0x0</td>
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<td align="center" colspan="1">PDMCOREEN
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<br>0x1</td>
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</tr>
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</tbody>
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</table>
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<br>
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<table style="margin:10px" class="table table-bordered table-condensed">
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<thead>
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<tr>
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<th>Bits</th>
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<th>Name</th>
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<th>RW</th>
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<th>Description</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>31</td>
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<td>LRSWAP</td>
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<td>RW</td>
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<td>Left/right channel swap.<br><br>
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EN = 0x1 - Swap left and right channels (FIFO Read RIGHT_LEFT).<br>
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NOSWAP = 0x0 - No channel swapping (IFO Read LEFT_RIGHT).</td>
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</tr>
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<tr>
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<td>30:26</td>
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<td>PGARIGHT</td>
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<td>RW</td>
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<td>Right channel PGA gain.<br><br>
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P405DB = 0x1F - 40.5 db gain.<br>
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P390DB = 0x1E - 39.0 db gain.<br>
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P375DB = 0x1D - 37.5 db gain.<br>
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P360DB = 0x1C - 36.0 db gain.<br>
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P345DB = 0x1B - 34.5 db gain.<br>
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P330DB = 0x1A - 33.0 db gain.<br>
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P315DB = 0x19 - 31.5 db gain.<br>
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P300DB = 0x18 - 30.0 db gain.<br>
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P285DB = 0x17 - 28.5 db gain.<br>
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P270DB = 0x16 - 27.0 db gain.<br>
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P255DB = 0x15 - 25.5 db gain.<br>
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P240DB = 0x14 - 24.0 db gain.<br>
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P225DB = 0x13 - 22.5 db gain.<br>
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P210DB = 0x12 - 21.0 db gain.<br>
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P195DB = 0x11 - 19.5 db gain.<br>
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P180DB = 0x10 - 18.0 db gain.<br>
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P165DB = 0xF - 16.5 db gain.<br>
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P150DB = 0xE - 15.0 db gain.<br>
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P135DB = 0xD - 13.5 db gain.<br>
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P120DB = 0xC - 12.0 db gain.<br>
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P105DB = 0xB - 10.5 db gain.<br>
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P90DB = 0xA - 9.0 db gain.<br>
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P75DB = 0x9 - 7.5 db gain.<br>
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P60DB = 0x8 - 6.0 db gain.<br>
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P45DB = 0x7 - 4.5 db gain.<br>
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P30DB = 0x6 - 3.0 db gain.<br>
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P15DB = 0x5 - 1.5 db gain.<br>
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|
0DB = 0x4 - 0.0 db gain.<br>
|
|
M15DB = 0x3 - -1.5 db gain.<br>
|
|
M300DB = 0x2 - -3.0 db gain.<br>
|
|
M45DB = 0x1 - -4.5 db gain.<br>
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M60DB = 0x0 - -6.0 db gain.</td>
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</tr>
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|
|
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<tr>
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|
<td>25:21</td>
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|
<td>PGALEFT</td>
|
|
<td>RW</td>
|
|
<td>Left channel PGA gain.<br><br>
|
|
P405DB = 0x1F - 40.5 db gain.<br>
|
|
P390DB = 0x1E - 39.0 db gain.<br>
|
|
P375DB = 0x1D - 37.5 db gain.<br>
|
|
P360DB = 0x1C - 36.0 db gain.<br>
|
|
P345DB = 0x1B - 34.5 db gain.<br>
|
|
P330DB = 0x1A - 33.0 db gain.<br>
|
|
P315DB = 0x19 - 31.5 db gain.<br>
|
|
P300DB = 0x18 - 30.0 db gain.<br>
|
|
P285DB = 0x17 - 28.5 db gain.<br>
|
|
P270DB = 0x16 - 27.0 db gain.<br>
|
|
P255DB = 0x15 - 25.5 db gain.<br>
|
|
P240DB = 0x14 - 24.0 db gain.<br>
|
|
P225DB = 0x13 - 22.5 db gain.<br>
|
|
P210DB = 0x12 - 21.0 db gain.<br>
|
|
P195DB = 0x11 - 19.5 db gain.<br>
|
|
P180DB = 0x10 - 18.0 db gain.<br>
|
|
P165DB = 0xF - 16.5 db gain.<br>
|
|
P150DB = 0xE - 15.0 db gain.<br>
|
|
P135DB = 0xD - 13.5 db gain.<br>
|
|
P120DB = 0xC - 12.0 db gain.<br>
|
|
P105DB = 0xB - 10.5 db gain.<br>
|
|
P90DB = 0xA - 9.0 db gain.<br>
|
|
P75DB = 0x9 - 7.5 db gain.<br>
|
|
P60DB = 0x8 - 6.0 db gain.<br>
|
|
P45DB = 0x7 - 4.5 db gain.<br>
|
|
P30DB = 0x6 - 3.0 db gain.<br>
|
|
P15DB = 0x5 - 1.5 db gain.<br>
|
|
0DB = 0x4 - 0.0 db gain.<br>
|
|
M15DB = 0x3 - -1.5 db gain.<br>
|
|
M300DB = 0x2 - -3.0 db gain.<br>
|
|
M45DB = 0x1 - -4.5 db gain.<br>
|
|
M60DB = 0x0 - -6.0 db gain.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>20:19</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>18:17</td>
|
|
<td>MCLKDIV</td>
|
|
<td>RW</td>
|
|
<td>PDM_CLK frequency divisor.<br><br>
|
|
MCKDIV4 = 0x3 - Divide input clock by 4<br>
|
|
MCKDIV3 = 0x2 - Divide input clock by 3<br>
|
|
MCKDIV2 = 0x1 - Divide input clock by 2<br>
|
|
MCKDIV1 = 0x0 - Divide input clock by 1</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>16:10</td>
|
|
<td>SINCRATE</td>
|
|
<td>RW</td>
|
|
<td>SINC decimation rate.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9</td>
|
|
<td>ADCHPD</td>
|
|
<td>RW</td>
|
|
<td>High pass filter control.<br><br>
|
|
EN = 0x1 - Enable high pass filter.<br>
|
|
DIS = 0x0 - Disable high pass filter.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8:5</td>
|
|
<td>HPCUTOFF</td>
|
|
<td>RW</td>
|
|
<td>High pass filter coefficients.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4:2</td>
|
|
<td>CYCLES</td>
|
|
<td>RW</td>
|
|
<td>Number of clocks during gain-setting changes.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>SOFTMUTE</td>
|
|
<td>RW</td>
|
|
<td>Soft mute control.<br><br>
|
|
EN = 0x1 - Enable Soft Mute.<br>
|
|
DIS = 0x0 - Disable Soft Mute.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>PDMCOREEN</td>
|
|
<td>RW</td>
|
|
<td>Data Streaming Control.<br><br>
|
|
EN = 0x1 - Enable Data Streaming.<br>
|
|
DIS = 0x0 - Disable Data Streaming.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="VCFG" class="panel-title">VCFG - Voice Configuration Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011004</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Voice Configuration Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="1">IOCLKEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">RSTB
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="3">PDMCLKSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">PDMCLKEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="5">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">I2SEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BCLKINV
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DMICKDEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SELAP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="7">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">PCMPACK
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="3">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">CHSET
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="3">RSVD
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31</td>
|
|
<td>IOCLKEN</td>
|
|
<td>RW</td>
|
|
<td>Enable the IO clock.<br><br>
|
|
DIS = 0x0 - Disable FIFO read.<br>
|
|
EN = 0x1 - Enable FIFO read.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>30</td>
|
|
<td>RSTB</td>
|
|
<td>RW</td>
|
|
<td>Reset the IP core.<br><br>
|
|
RESET = 0x0 - Reset the core.<br>
|
|
NORM = 0x1 - Enable the core.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>29:27</td>
|
|
<td>PDMCLKSEL</td>
|
|
<td>RW</td>
|
|
<td>Select the PDM input clock.<br><br>
|
|
DISABLE = 0x0 - Static value.<br>
|
|
12MHz = 0x1 - PDM clock is 12 MHz.<br>
|
|
6MHz = 0x2 - PDM clock is 6 MHz.<br>
|
|
3MHz = 0x3 - PDM clock is 3 MHz.<br>
|
|
1_5MHz = 0x4 - PDM clock is 1.5 MHz.<br>
|
|
750KHz = 0x5 - PDM clock is 750 KHz.<br>
|
|
375KHz = 0x6 - PDM clock is 375 KHz.<br>
|
|
187KHz = 0x7 - PDM clock is 187.5 KHz.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>26</td>
|
|
<td>PDMCLKEN</td>
|
|
<td>RW</td>
|
|
<td>Enable the serial clock.<br><br>
|
|
DIS = 0x0 - Disable serial clock.<br>
|
|
EN = 0x1 - Enable serial clock.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>25:21</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>20</td>
|
|
<td>I2SEN</td>
|
|
<td>RW</td>
|
|
<td>I2S interface enable.<br><br>
|
|
DIS = 0x0 - Disable I2S interface.<br>
|
|
EN = 0x1 - Enable I2S interface.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>19</td>
|
|
<td>BCLKINV</td>
|
|
<td>RW</td>
|
|
<td>I2S BCLK input inversion.<br><br>
|
|
INV = 0x0 - BCLK inverted.<br>
|
|
NORM = 0x1 - BCLK not inverted.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>18</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>17</td>
|
|
<td>DMICKDEL</td>
|
|
<td>RW</td>
|
|
<td>PDM clock sampling delay.<br><br>
|
|
0CYC = 0x0 - No delay.<br>
|
|
1CYC = 0x1 - 1 cycle delay.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>16</td>
|
|
<td>SELAP</td>
|
|
<td>RW</td>
|
|
<td>Select PDM input clock source.<br><br>
|
|
I2S = 0x1 - Clock source from I2S BCLK.<br>
|
|
INTERNAL = 0x0 - Clock source from internal clock generator.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:9</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8</td>
|
|
<td>PCMPACK</td>
|
|
<td>RW</td>
|
|
<td>PCM data packing enable.<br><br>
|
|
DIS = 0x0 - Disable PCM packing.<br>
|
|
EN = 0x1 - Enable PCM packing.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:5</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4:3</td>
|
|
<td>CHSET</td>
|
|
<td>RW</td>
|
|
<td>Set PCM channels.<br><br>
|
|
DIS = 0x0 - Channel disabled.<br>
|
|
LEFT = 0x1 - Mono left channel.<br>
|
|
RIGHT = 0x2 - Mono right channel.<br>
|
|
STEREO = 0x3 - Stereo channels.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2:0</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="VOICESTAT" class="panel-title">VOICESTAT - Voice Status Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011008</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Voice Status Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="26">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="6">FIFOCNT
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:6</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5:0</td>
|
|
<td>FIFOCNT</td>
|
|
<td>RO</td>
|
|
<td>Valid 32-bit entries currently in the FIFO.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FIFOREAD" class="panel-title">FIFOREAD - FIFO Read</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5001100C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>FIFO Read</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">FIFOREAD
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>FIFOREAD</td>
|
|
<td>RO</td>
|
|
<td>FIFO read data.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FIFOFLUSH" class="panel-title">FIFOFLUSH - FIFO Flush</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011010</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>FIFO Flush</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="31">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FIFOFLUSH
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>FIFOFLUSH</td>
|
|
<td>WO</td>
|
|
<td>FIFO FLUSH.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FIFOTHR" class="panel-title">FIFOTHR - FIFO Threshold</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011014</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>FIFO Threshold</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="27">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="5">FIFOTHR
|
|
<br>0x10</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:5</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>This bitfield is reserved for future use.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4:0</td>
|
|
<td>FIFOTHR</td>
|
|
<td>RW</td>
|
|
<td>FIFO Threshold value. When the FIFO count is equal to, or larger than this value (in words), a THR interrupt is generated (if enabled)<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTEN" class="panel-title">INTEN - IO Master Interrupts: Enable</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Set bits in this register to allow this module to generate the corresponding interrupt.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="27">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DERR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DCMP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">UNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">OVF
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:5</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>DERR</td>
|
|
<td>RW</td>
|
|
<td>DMA Error receieved<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>DCMP</td>
|
|
<td>RW</td>
|
|
<td>DMA completed a transfer<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>UNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>OVF</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTSTAT" class="panel-title">INTSTAT - IO Master Interrupts: Status</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Read bits from this register to discover the cause of a recent interrupt.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="27">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DERR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DCMP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">UNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">OVF
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:5</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>DERR</td>
|
|
<td>RW</td>
|
|
<td>DMA Error receieved<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>DCMP</td>
|
|
<td>RW</td>
|
|
<td>DMA completed a transfer<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>UNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>OVF</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTCLR" class="panel-title">INTCLR - IO Master Interrupts: Clear</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011208</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Write a 1 to a bit in this register to clear the interrupt status associated with that bit.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="27">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DERR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DCMP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">UNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">OVF
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:5</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>DERR</td>
|
|
<td>RW</td>
|
|
<td>DMA Error receieved<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>DCMP</td>
|
|
<td>RW</td>
|
|
<td>DMA completed a transfer<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>UNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>OVF</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTSET" class="panel-title">INTSET - IO Master Interrupts: Set</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5001120C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="27">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DERR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DCMP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">UNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">OVF
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:5</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>DERR</td>
|
|
<td>RW</td>
|
|
<td>DMA Error receieved<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>DCMP</td>
|
|
<td>RW</td>
|
|
<td>DMA completed a transfer<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>UNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>OVF</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMATRIGEN" class="panel-title">DMATRIGEN - DMA Trigger Enable Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011240</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DMA Trigger Enable Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="30">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DTHR90
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DTHR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:2</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>DTHR90</td>
|
|
<td>RW</td>
|
|
<td>Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>DTHR</td>
|
|
<td>RW</td>
|
|
<td>Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD,at granularity of 16 bytes only<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMATRIGSTAT" class="panel-title">DMATRIGSTAT - DMA Trigger Status Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011244</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DMA Trigger Status Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="30">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DTHR90STAT
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DTHRSTAT
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:2</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>DTHR90STAT</td>
|
|
<td>RO</td>
|
|
<td>Triggered DMA from FIFO reaching 90 percent full<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>DTHRSTAT</td>
|
|
<td>RO</td>
|
|
<td>Triggered DMA from FIFO reaching threshold<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMACFG" class="panel-title">DMACFG - DMA Configuration Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011280</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DMA Configuration Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="21">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DPWROFF
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DAUTOHIP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DMAPRI
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="5">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DMADIR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DMAEN
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:11</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10</td>
|
|
<td>DPWROFF</td>
|
|
<td>RW</td>
|
|
<td>Power Off the ADC System upon DMACPL.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9</td>
|
|
<td>DAUTOHIP</td>
|
|
<td>RW</td>
|
|
<td>Raise priority to high on fifo full, and DMAPRI set to low<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8</td>
|
|
<td>DMAPRI</td>
|
|
<td>RW</td>
|
|
<td>Sets the Priority of the DMA request<br><br>
|
|
LOW = 0x0 - Low Priority (service as best effort)<br>
|
|
HIGH = 0x1 - High Priority (service immediately)</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>DMADIR</td>
|
|
<td>RO</td>
|
|
<td>Direction<br><br>
|
|
P2M = 0x0 - Peripheral to Memory (SRAM) transaction. THe PDM module will only DMA to memory.<br>
|
|
M2P = 0x1 - Memory to Peripheral transaction. Not available for PDM module</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>DMAEN</td>
|
|
<td>RW</td>
|
|
<td>DMA Enable<br><br>
|
|
DIS = 0x0 - Disable DMA Function<br>
|
|
EN = 0x1 - Enable DMA Function</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMATOTCOUNT" class="panel-title">DMATOTCOUNT - DMA Total Transfer Count</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011288</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DMA Total Transfer Count</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="12">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="20">TOTCOUNT
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:20</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>19:0</td>
|
|
<td>TOTCOUNT</td>
|
|
<td>RW</td>
|
|
<td>Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMATARGADDR" class="panel-title">DMATARGADDR - DMA Target Address Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5001128C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DMA Target Address Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="12">UTARGADDR
|
|
<br>0x100</td>
|
|
|
|
<td align="center" colspan="20">LTARGADDR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:20</td>
|
|
<td>UTARGADDR</td>
|
|
<td>RO</td>
|
|
<td>SRAM Target<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>19:0</td>
|
|
<td>LTARGADDR</td>
|
|
<td>RW</td>
|
|
<td>DMA Target Address. This register is not updated with the current address of the DMA, but will remain static with the original address during the DMA transfer.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMASTAT" class="panel-title">DMASTAT - DMA Status Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50011290</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DMA Status Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="29">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DMAERR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DMACPL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DMATIP
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>DMAERR</td>
|
|
<td>RW</td>
|
|
<td>DMA Error<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>DMACPL</td>
|
|
<td>RW</td>
|
|
<td>DMA Transfer Complete<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>DMATIP</td>
|
|
<td>RW</td>
|
|
<td>DMA Transfer In Progress<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
</body>
|
|
|
|
<hr size="1">
|
|
<body>
|
|
<div id="footer" align="right">
|
|
<small>
|
|
AmbiqSuite Register Documentation
|
|
<a href="http://www.ambiqmicro.com">
|
|
<img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>   Copyright © 2019  <br />
|
|
This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.  <br/>
|
|
</small>
|
|
</div>
|
|
</body>
|
|
</html>
|
|
|