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<div id="projectname">Apollo Register Documentation &#160;<span id="projectnumber">v2.4.2</span></div>
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<div class="title">MSPI - Multibit SPI Master</div>
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<body>
<br>
<div class="panel panel-default">
<div class="panel-heading">
<h3 class="panel-title"> MSPI Register Index</h3>
</div>
<div class="panel-body">
<table>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000000:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CTRL" target="_self">CTRL - MSPI PIO Transfer Control/Status Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000004:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CFG" target="_self">CFG - MSPI Transfer Configuration Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000008:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#ADDR" target="_self">ADDR - MSPI Transfer Address Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x0000000C:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#INSTR" target="_self">INSTR - MSPI Transfer Instruction</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000010:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#TXFIFO" target="_self">TXFIFO - TX Data FIFO</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000014:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#RXFIFO" target="_self">RXFIFO - RX Data FIFO</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000018:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#TXENTRIES" target="_self">TXENTRIES - TX FIFO Entries</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x0000001C:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#RXENTRIES" target="_self">RXENTRIES - RX FIFO Entries</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000020:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#THRESHOLD" target="_self">THRESHOLD - TX/RX FIFO Threshhold Levels</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000100:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#MSPICFG" target="_self">MSPICFG - MSPI Module Configuration</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000104:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#PADCFG" target="_self">PADCFG - MSPI Output Pad Configuration</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000108:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#PADOUTEN" target="_self">PADOUTEN - MSPI Output Enable Pad Configuration</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x0000010C:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#FLASH" target="_self">FLASH - Configuration for XIP/DMA support of SPI flash modules.</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000120:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#SCRAMBLING" target="_self">SCRAMBLING - External Flash Scrambling Controls</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000200:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#INTEN" target="_self">INTEN - MSPI Master Interrupts: Enable</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000204:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#INTSTAT" target="_self">INTSTAT - MSPI Master Interrupts: Status</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000208:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#INTCLR" target="_self">INTCLR - MSPI Master Interrupts: Clear</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x0000020C:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#INTSET" target="_self">INTSET - MSPI Master Interrupts: Set</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000250:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#DMACFG" target="_self">DMACFG - DMA Configuration Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000254:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#DMASTAT" target="_self">DMASTAT - DMA Status Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000258:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#DMATARGADDR" target="_self">DMATARGADDR - DMA Target Address Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x0000025C:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#DMADEVADDR" target="_self">DMADEVADDR - DMA Device Address Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000260:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#DMATOTCOUNT" target="_self">DMATOTCOUNT - DMA Total Transfer Count</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000264:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#DMABCOUNT" target="_self">DMABCOUNT - DMA BYTE Transfer Count</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x00000278:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#DMATHRESH" target="_self">DMATHRESH - DMA Transmit Trigger Threshhold</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002A0:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQCFG" target="_self">CQCFG - Command Queue Configuration Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002A8:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQADDR" target="_self">CQADDR - CQ Target Read Address Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002AC:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQSTAT" target="_self">CQSTAT - Command Queue Status Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002B0:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQFLAGS" target="_self">CQFLAGS - Command Queue Flag Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002B4:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQSETCLEAR" target="_self">CQSETCLEAR - Command Queue Flag Set/Clear Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002B8:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQPAUSE" target="_self">CQPAUSE - Command Queue Pause Mask Register</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002C0:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQCURIDX" target="_self">CQCURIDX - Command Queue Current Index</a>
</td>
</tr>
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x000002C4:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<a class="el" href="#CQENDIDX" target="_self">CQENDIDX - Command Queue End Index</a>
</td>
</tr>
</table>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CTRL" class="panel-title">CTRL - MSPI PIO Transfer Control/Status Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014000</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer, and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="16">XFERBYTES
<br>0x0</td>
<td align="center" colspan="4">RSVD
<br>0x0</td>
<td align="center" colspan="1">PIOSCRAMBLE
<br>0x0</td>
<td align="center" colspan="1">TXRX
<br>0x0</td>
<td align="center" colspan="1">SENDI
<br>0x0</td>
<td align="center" colspan="1">SENDA
<br>0x0</td>
<td align="center" colspan="1">ENTURN
<br>0x0</td>
<td align="center" colspan="1">BIGENDIAN
<br>0x0</td>
<td align="center" colspan="2">RSVD
<br>0x0</td>
<td align="center" colspan="1">QUADCMD
<br>0x0</td>
<td align="center" colspan="1">BUSY
<br>0x0</td>
<td align="center" colspan="1">STATUS
<br>0x0</td>
<td align="center" colspan="1">START
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:16</td>
<td>XFERBYTES</td>
<td>RW</td>
<td>Number of bytes to transmit or receive (based on TXRX bit)<br><br>
</td>
</tr>
<tr>
<td>15:12</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>11</td>
<td>PIOSCRAMBLE</td>
<td>RW</td>
<td>Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device.<br><br>
</td>
</tr>
<tr>
<td>10</td>
<td>TXRX</td>
<td>RW</td>
<td>1 Indicates a TX operation, 0 indicates an RX operation of XFERBYTES<br><br>
</td>
</tr>
<tr>
<td>9</td>
<td>SENDI</td>
<td>RW</td>
<td>Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)<br><br>
</td>
</tr>
<tr>
<td>8</td>
<td>SENDA</td>
<td>RW</td>
<td>Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)<br><br>
</td>
</tr>
<tr>
<td>7</td>
<td>ENTURN</td>
<td>RW</td>
<td>Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register).<br><br>
</td>
</tr>
<tr>
<td>6</td>
<td>BIGENDIAN</td>
<td>RW</td>
<td>1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default, LSB first).<br><br>
</td>
</tr>
<tr>
<td>5:4</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>QUADCMD</td>
<td>RW</td>
<td>Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers).<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>BUSY</td>
<td>RO</td>
<td>Command status: 1 indicates controller is busy (command in progress)<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>STATUS</td>
<td>RO</td>
<td>Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer.<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>START</td>
<td>RW</td>
<td>Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set).<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CFG" class="panel-title">CFG - MSPI Transfer Configuration Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014004</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Command formatting for PIO based transactions (initiated by writes to CTRL register)</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="14">RSVD
<br>0x0</td>
<td align="center" colspan="1">CPOL
<br>0x0</td>
<td align="center" colspan="1">CPHA
<br>0x0</td>
<td align="center" colspan="2">RSVD
<br>0x0</td>
<td align="center" colspan="6">TURNAROUND
<br>0x0</td>
<td align="center" colspan="1">SEPIO
<br>0x0</td>
<td align="center" colspan="1">ISIZE
<br>0x0</td>
<td align="center" colspan="2">ASIZE
<br>0x0</td>
<td align="center" colspan="4">DEVCFG
<br>0x1</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:18</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>17</td>
<td>CPOL</td>
<td>RW</td>
<td>Serial clock polarity.<br><br>
LOW = 0x0 - Clock inactive state is low.<br>
HIGH = 0x1 - Clock inactive state is high.</td>
</tr>
<tr>
<td>16</td>
<td>CPHA</td>
<td>RW</td>
<td>Serial clock phase.<br><br>
MIDDLE = 0x0 - Clock toggles in middle of data bit.<br>
START = 0x1 - Clock toggles at start of data bit.</td>
</tr>
<tr>
<td>15:14</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>13:8</td>
<td>TURNAROUND</td>
<td>RW</td>
<td>Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field.<br><br>
</td>
</tr>
<tr>
<td>7</td>
<td>SEPIO</td>
<td>RW</td>
<td>Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins.<br><br>
</td>
</tr>
<tr>
<td>6</td>
<td>ISIZE</td>
<td>RW</td>
<td>Instruction Size
enum
name = I8
value = 0x0
desc = Instruction is 1 byte
enum
name = I16
value = 0x1
desc = Instruction is 2 bytes<br><br>
</td>
</tr>
<tr>
<td>5:4</td>
<td>ASIZE</td>
<td>RW</td>
<td>Address Size. Address bytes to send from ADDR register
name = A1
value = 0x0
desc = Send one address byte
enum
name = A2
value = 0x1
desc = Send two address bytes
enum
name = A3
value = 0x2
desc = Send three address bytes
enum
name = A4
value = 0x3
desc = Send four address bytes<br><br>
</td>
</tr>
<tr>
<td>3:0</td>
<td>DEVCFG</td>
<td>RW</td>
<td>Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format).<br><br>
SERIAL0 = 0x1 - Single bit SPI flash on chip select 0<br>
SERIAL1 = 0x2 - Single bit SPI flash on chip select 1<br>
DUAL0 = 0x5 - Dual SPI flash on chip select 0<br>
DUAL1 = 0x6 - Dual bit SPI flash on chip select 1<br>
QUAD0 = 0x9 - Quad SPI flash on chip select 0<br>
QUAD1 = 0xA - Quad SPI flash on chip select 1<br>
OCTAL0 = 0xD - Octal SPI flash on chip select 0<br>
OCTAL1 = 0xE - Octal SPI flash on chip select 1<br>
QUADPAIRED = 0xF - Dual Quad SPI flash on chip selects 0/1.<br>
QUADPAIRED_SERIAL = 0x3 - Dual Quad SPI flash on chip selects 0/1, but transmit in serial mode for initialization operations</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="ADDR" class="panel-title">ADDR - MSPI Transfer Address Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014008</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Optional Address field to send for PIO transfers</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="32">ADDR
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:0</td>
<td>ADDR</td>
<td>RW</td>
<td>Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="INSTR" class="panel-title">INSTR - MSPI Transfer Instruction</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x5001400C</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Optional Instruction field to send for PIO transfers</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="16">RSVD
<br>0x0</td>
<td align="center" colspan="16">INSTR
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:16</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>15:0</td>
<td>INSTR</td>
<td>RW</td>
<td>Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="TXFIFO" class="panel-title">TXFIFO - TX Data FIFO</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014010</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>TX Data FIFO</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="32">TXFIFO
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:0</td>
<td>TXFIFO</td>
<td>WO</td>
<td>Data to be transmitted. Data should normall be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="RXFIFO" class="panel-title">RXFIFO - RX Data FIFO</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014014</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>RX Data FIFO</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="32">RXFIFO
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:0</td>
<td>RXFIFO</td>
<td>RO</td>
<td>Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="TXENTRIES" class="panel-title">TXENTRIES - TX FIFO Entries</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014018</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Number of words in TX FIFO</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="27">RSVD
<br>0x0</td>
<td align="center" colspan="5">TXENTRIES
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:5</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>4:0</td>
<td>TXENTRIES</td>
<td>RO</td>
<td>Number of 32-bit words/entries in TX FIFO<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="RXENTRIES" class="panel-title">RXENTRIES - RX FIFO Entries</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x5001401C</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Number of words in RX FIFO</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="27">RSVD
<br>0x0</td>
<td align="center" colspan="5">RXENTRIES
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:5</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>4:0</td>
<td>RXENTRIES</td>
<td>RO</td>
<td>Number of 32-bit words/entries in RX FIFO<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="THRESHOLD" class="panel-title">THRESHOLD - TX/RX FIFO Threshhold Levels</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014020</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Threshold levels that trigger RXFull and TXEmpty interrupts</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="16">RSVD
<br>0x0</td>
<td align="center" colspan="3">RSVD
<br>0x0</td>
<td align="center" colspan="5">RXTHRESH
<br>0x0</td>
<td align="center" colspan="3">RSVD
<br>0x0</td>
<td align="center" colspan="5">TXTHRESH
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:16</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>15:13</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>12:8</td>
<td>RXTHRESH</td>
<td>RW</td>
<td>Number of entries in TX FIFO that cause RXE interrupt<br><br>
</td>
</tr>
<tr>
<td>7:5</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>4:0</td>
<td>TXTHRESH</td>
<td>RW</td>
<td>Number of entries in TX FIFO that cause TXF interrupt<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="MSPICFG" class="panel-title">MSPICFG - MSPI Module Configuration</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014100</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Timing configuration bits for the MSPI module. PRSTN, IPRSTN, and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="1">PRSTN
<br>0x1</td>
<td align="center" colspan="1">IPRSTN
<br>0x1</td>
<td align="center" colspan="1">FIFORESET
<br>0x0</td>
<td align="center" colspan="15">RSVD
<br>0x0</td>
<td align="center" colspan="6">CLKDIV
<br>0x2</td>
<td align="center" colspan="1">RSVD
<br>0x0</td>
<td align="center" colspan="3">IOMSEL
<br>0x0</td>
<td align="center" colspan="1">TXNEG
<br>0x0</td>
<td align="center" colspan="1">RXNEG
<br>0x0</td>
<td align="center" colspan="1">RXCAP
<br>0x0</td>
<td align="center" colspan="1">APBCLK
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31</td>
<td>PRSTN</td>
<td>RW</td>
<td>Peripheral reset. Master reset to the entire MSPI module (DMA, XIP, and transfer state machines). 1=normal operation, 0=in reset.<br><br>
</td>
</tr>
<tr>
<td>30</td>
<td>IPRSTN</td>
<td>RW</td>
<td>IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus.<br><br>
</td>
</tr>
<tr>
<td>29</td>
<td>FIFORESET</td>
<td>RW</td>
<td>Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal operation. May be used to manually flush the FIFO in error handling.<br><br>
</td>
</tr>
<tr>
<td>28:14</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>13:8</td>
<td>CLKDIV</td>
<td>RW</td>
<td>Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency, but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock pulse (to allow longer round-trip for read data).<br><br>
CLK24 = 0x2 - 24 MHz MSPI clock<br>
CLK12 = 0x4 - 12 MHz MSPI clock<br>
CLK6 = 0x8 - 6 MHz MSPI clock<br>
CLK3 = 0x10 - 3 MHz MSPI clock<br>
CLK1_5 = 0x20 - 1.5 MHz MSPI clock</td>
</tr>
<tr>
<td>7</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>6:4</td>
<td>IOMSEL</td>
<td>RW</td>
<td>Selects which IOM is selected for CQ handshake status.<br><br>
IOM0 = 0x0 - ERROR: desc VALUE MISSING<br>
IOM1 = 0x1 - ERROR: desc VALUE MISSING<br>
IOM2 = 0x2 - ERROR: desc VALUE MISSING<br>
IOM3 = 0x3 - ERROR: desc VALUE MISSING<br>
IOM4 = 0x4 - ERROR: desc VALUE MISSING<br>
IOM5 = 0x5 - ERROR: desc VALUE MISSING<br>
DISABLED = 0x7 - No IOM selected. Signals always zero.</td>
</tr>
<tr>
<td>3</td>
<td>TXNEG</td>
<td>RW</td>
<td>Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL).<br><br>
NORMAL = 0x0 - TX launched from posedge internal clock<br>
NEGEDGE = 0x1 - TX data launched from negedge of internal clock</td>
</tr>
<tr>
<td>2</td>
<td>RXNEG</td>
<td>RW</td>
<td>Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation, it is expected that RXNEG will be set to 0.<br><br>
NORMAL = 0x0 - RX data sampled on posedge of internal clock<br>
NEGEDGE = 0x1 - RX data sampled on negedge of internal clock</td>
</tr>
<tr>
<td>1</td>
<td>RXCAP</td>
<td>RW</td>
<td>Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However, to accomodate chip/pad/board delays, a setting of RXCAP of 1 is expected to be used to align the capture point with the return data window. This bit is used in conjunction with RXNEG to provide 4 unique capture points, all about 10ns apart.<br><br>
NORMAL = 0x0 - RX Capture phase aligns with CPHA setting<br>
DELAY = 0x1 - RX Capture phase is delayed from CPHA setting by one clock edge</td>
</tr>
<tr>
<td>0</td>
<td>APBCLK</td>
<td>RW</td>
<td>Enable continuous APB clock. For power-efficient operation, APBCLK should be set to 0.<br><br>
DIS = 0x0 - Disable continuous clock.<br>
EN = 0x1 - Enable continuous clock.</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="PADCFG" class="panel-title">PADCFG - MSPI Output Pad Configuration</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014104</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Configuration bits for the MSPI pads. Allows pads associated with the upper quad to be mapped to corresponding bits on the lower quad. Use of Quad0 pins is recommended for optimal timing.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="10">RSVD
<br>0x0</td>
<td align="center" colspan="1">REVCS
<br>0x0</td>
<td align="center" colspan="1">IN3
<br>0x0</td>
<td align="center" colspan="1">IN2
<br>0x0</td>
<td align="center" colspan="1">IN1
<br>0x0</td>
<td align="center" colspan="2">IN0
<br>0x0</td>
<td align="center" colspan="11">RSVD
<br>0x0</td>
<td align="center" colspan="1">OUT7
<br>0x0</td>
<td align="center" colspan="1">OUT6
<br>0x0</td>
<td align="center" colspan="1">OUT5
<br>0x0</td>
<td align="center" colspan="1">OUT4
<br>0x0</td>
<td align="center" colspan="1">OUT3
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:22</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>21</td>
<td>REVCS</td>
<td>RW</td>
<td>Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines<br><br>
</td>
</tr>
<tr>
<td>20</td>
<td>IN3</td>
<td>RW</td>
<td>Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]<br><br>
</td>
</tr>
<tr>
<td>19</td>
<td>IN2</td>
<td>RW</td>
<td>Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]<br><br>
</td>
</tr>
<tr>
<td>18</td>
<td>IN1</td>
<td>RW</td>
<td>Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]<br><br>
</td>
</tr>
<tr>
<td>17:16</td>
<td>IN0</td>
<td>RW</td>
<td>Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]<br><br>
</td>
</tr>
<tr>
<td>15:5</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>4</td>
<td>OUT7</td>
<td>RW</td>
<td>Output pad 7 configuration. 0=data[7] 1=data[3]<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>OUT6</td>
<td>RW</td>
<td>Output pad 6 configuration. 0=data[6] 1=data[2]<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>OUT5</td>
<td>RW</td>
<td>Output pad 5 configuration. 0=data[5] 1=data[1]<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>OUT4</td>
<td>RW</td>
<td>Output pad 4 configuration. 0=data[4] 1=data[0]<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>OUT3</td>
<td>RW</td>
<td>Output pad 3 configuration. 0=data[3] 1=CLK<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="PADOUTEN" class="panel-title">PADOUTEN - MSPI Output Enable Pad Configuration</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014108</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="23">RSVD
<br>0x0</td>
<td align="center" colspan="9">OUTEN
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:9</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>8:0</td>
<td>OUTEN</td>
<td>RW</td>
<td>Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data, [7:4] are Quad1 data, and [8] is clock.<br><br>
QUAD0 = 0x10F - Quad0 (4 data + 1 clock)<br>
QUAD1 = 0x1F0 - Quad1 (4 data + 1 clock)<br>
OCTAL = 0x1FF - Octal (8 data + 1 clock)<br>
SERIAL0 = 0x103 - Serial (2 data + 1 clock)</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="FLASH" class="panel-title">FLASH - Configuration for XIP/DMA support of SPI flash modules.</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x5001410C</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>When any SPI flash is configured, this register must be properly programmed before XIP or AUTO DMA operations commence.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="8">READINSTR
<br>0xb</td>
<td align="center" colspan="8">WRITEINSTR
<br>0x6</td>
<td align="center" colspan="5">RSVD
<br>0x0</td>
<td align="center" colspan="3">XIPMIXED
<br>0x0</td>
<td align="center" colspan="1">XIPSENDI
<br>0x0</td>
<td align="center" colspan="1">XIPSENDA
<br>0x0</td>
<td align="center" colspan="1">XIPENTURN
<br>0x0</td>
<td align="center" colspan="1">XIPBIGENDIAN
<br>0x0</td>
<td align="center" colspan="2">XIPACK
<br>0x0</td>
<td align="center" colspan="1">RSVD
<br>0x0</td>
<td align="center" colspan="1">XIPEN
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:24</td>
<td>READINSTR</td>
<td>RW</td>
<td>Read command sent to flash for DMA/XIP operations<br><br>
</td>
</tr>
<tr>
<td>23:16</td>
<td>WRITEINSTR</td>
<td>RW</td>
<td>Write command sent for DMA operations<br><br>
</td>
</tr>
<tr>
<td>15:11</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>10:8</td>
<td>XIPMIXED</td>
<td>RW</td>
<td>Reserved. Set to 0x0<br><br>
</td>
</tr>
<tr>
<td>7</td>
<td>XIPSENDI</td>
<td>RW</td>
<td>Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)<br><br>
</td>
</tr>
<tr>
<td>6</td>
<td>XIPSENDA</td>
<td>RW</td>
<td>Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)<br><br>
</td>
</tr>
<tr>
<td>5</td>
<td>XIPENTURN</td>
<td>RW</td>
<td>Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles<br><br>
</td>
</tr>
<tr>
<td>4</td>
<td>XIPBIGENDIAN</td>
<td>RW</td>
<td>Indicates whether XIP/AUTO DMA data transfers are in big or little endian format<br><br>
</td>
</tr>
<tr>
<td>3:2</td>
<td>XIPACK</td>
<td>RW</td>
<td>Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)<br><br>
NOACK = 0x0 - No acknowledege sent. Data IOs are tristated the first turnaround cycle<br>
ACK = 0x2 - Positive acknowledege sent. Data IOs are driven to 0 the first turnaround cycle to acknowledge XIP mode<br>
TERMINATE = 0x3 - Negative acknowledege sent. Data IOs are driven to 1 the first turnaround cycle to terminate XIP mode. XIPSENDI should be reenabled for the next transfer</td>
</tr>
<tr>
<td>1</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>XIPEN</td>
<td>RW</td>
<td>Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="SCRAMBLING" class="panel-title">SCRAMBLING - External Flash Scrambling Controls</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014120</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="1">SCRENABLE
<br>0x0</td>
<td align="center" colspan="5">RSVD
<br>0x0</td>
<td align="center" colspan="10">SCREND
<br>0x0</td>
<td align="center" colspan="6">RSVD
<br>0x0</td>
<td align="center" colspan="10">SCRSTART
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31</td>
<td>SCRENABLE</td>
<td>RW</td>
<td>Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0, data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range.<br><br>
</td>
</tr>
<tr>
<td>30:26</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>25:16</td>
<td>SCREND</td>
<td>RW</td>
<td>Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range.<br><br>
</td>
</tr>
<tr>
<td>15:10</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>9:0</td>
<td>SCRSTART</td>
<td>RW</td>
<td>Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="INTEN" class="panel-title">INTEN - MSPI Master Interrupts: Enable</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014200</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Set bits in this register to allow this module to generate the corresponding interrupt.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="19">RSVD
<br>0x0</td>
<td align="center" colspan="1">SCRERR
<br>0x0</td>
<td align="center" colspan="1">CQERR
<br>0x0</td>
<td align="center" colspan="1">CQPAUSED
<br>0x0</td>
<td align="center" colspan="1">CQUPD
<br>0x0</td>
<td align="center" colspan="1">CQCMP
<br>0x0</td>
<td align="center" colspan="1">DERR
<br>0x0</td>
<td align="center" colspan="1">DCMP
<br>0x0</td>
<td align="center" colspan="1">RXF
<br>0x0</td>
<td align="center" colspan="1">RXO
<br>0x0</td>
<td align="center" colspan="1">RXU
<br>0x0</td>
<td align="center" colspan="1">TXO
<br>0x0</td>
<td align="center" colspan="1">TXE
<br>0x0</td>
<td align="center" colspan="1">CMDCMP
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:13</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>12</td>
<td>SCRERR</td>
<td>RW</td>
<td>Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.<br><br>
</td>
</tr>
<tr>
<td>11</td>
<td>CQERR</td>
<td>RW</td>
<td>Command Queue Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>10</td>
<td>CQPAUSED</td>
<td>RW</td>
<td>Command Queue is Paused.<br><br>
</td>
</tr>
<tr>
<td>9</td>
<td>CQUPD</td>
<td>RW</td>
<td>Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.<br><br>
</td>
</tr>
<tr>
<td>8</td>
<td>CQCMP</td>
<td>RW</td>
<td>Command Queue Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>7</td>
<td>DERR</td>
<td>RW</td>
<td>DMA Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>6</td>
<td>DCMP</td>
<td>RW</td>
<td>DMA Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>5</td>
<td>RXF</td>
<td>RW</td>
<td>Receive FIFO full<br><br>
</td>
</tr>
<tr>
<td>4</td>
<td>RXO</td>
<td>RW</td>
<td>Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>RXU</td>
<td>RW</td>
<td>Receive FIFO underflow (only occurs when SW reads from an empty FIFO)<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>TXO</td>
<td>RW</td>
<td>Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>TXE</td>
<td>RW</td>
<td>Transmit FIFO empty.<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>CMDCMP</td>
<td>RW</td>
<td>Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signalled simultaneously<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="INTSTAT" class="panel-title">INTSTAT - MSPI Master Interrupts: Status</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014204</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Read bits from this register to discover the cause of a recent interrupt.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="19">RSVD
<br>0x0</td>
<td align="center" colspan="1">SCRERR
<br>0x0</td>
<td align="center" colspan="1">CQERR
<br>0x0</td>
<td align="center" colspan="1">CQPAUSED
<br>0x0</td>
<td align="center" colspan="1">CQUPD
<br>0x0</td>
<td align="center" colspan="1">CQCMP
<br>0x0</td>
<td align="center" colspan="1">DERR
<br>0x0</td>
<td align="center" colspan="1">DCMP
<br>0x0</td>
<td align="center" colspan="1">RXF
<br>0x0</td>
<td align="center" colspan="1">RXO
<br>0x0</td>
<td align="center" colspan="1">RXU
<br>0x0</td>
<td align="center" colspan="1">TXO
<br>0x0</td>
<td align="center" colspan="1">TXE
<br>0x0</td>
<td align="center" colspan="1">CMDCMP
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:13</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>12</td>
<td>SCRERR</td>
<td>RW</td>
<td>Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.<br><br>
</td>
</tr>
<tr>
<td>11</td>
<td>CQERR</td>
<td>RW</td>
<td>Command Queue Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>10</td>
<td>CQPAUSED</td>
<td>RW</td>
<td>Command Queue is Paused.<br><br>
</td>
</tr>
<tr>
<td>9</td>
<td>CQUPD</td>
<td>RW</td>
<td>Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.<br><br>
</td>
</tr>
<tr>
<td>8</td>
<td>CQCMP</td>
<td>RW</td>
<td>Command Queue Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>7</td>
<td>DERR</td>
<td>RW</td>
<td>DMA Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>6</td>
<td>DCMP</td>
<td>RW</td>
<td>DMA Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>5</td>
<td>RXF</td>
<td>RW</td>
<td>Receive FIFO full<br><br>
</td>
</tr>
<tr>
<td>4</td>
<td>RXO</td>
<td>RW</td>
<td>Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>RXU</td>
<td>RW</td>
<td>Receive FIFO underflow (only occurs when SW reads from an empty FIFO)<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>TXO</td>
<td>RW</td>
<td>Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>TXE</td>
<td>RW</td>
<td>Transmit FIFO empty.<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>CMDCMP</td>
<td>RW</td>
<td>Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signalled simultaneously<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="INTCLR" class="panel-title">INTCLR - MSPI Master Interrupts: Clear</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014208</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Write a 1 to a bit in this register to clear the interrupt status associated with that bit.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="19">RSVD
<br>0x0</td>
<td align="center" colspan="1">SCRERR
<br>0x0</td>
<td align="center" colspan="1">CQERR
<br>0x0</td>
<td align="center" colspan="1">CQPAUSED
<br>0x0</td>
<td align="center" colspan="1">CQUPD
<br>0x0</td>
<td align="center" colspan="1">CQCMP
<br>0x0</td>
<td align="center" colspan="1">DERR
<br>0x0</td>
<td align="center" colspan="1">DCMP
<br>0x0</td>
<td align="center" colspan="1">RXF
<br>0x0</td>
<td align="center" colspan="1">RXO
<br>0x0</td>
<td align="center" colspan="1">RXU
<br>0x0</td>
<td align="center" colspan="1">TXO
<br>0x0</td>
<td align="center" colspan="1">TXE
<br>0x0</td>
<td align="center" colspan="1">CMDCMP
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:13</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>12</td>
<td>SCRERR</td>
<td>RW</td>
<td>Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.<br><br>
</td>
</tr>
<tr>
<td>11</td>
<td>CQERR</td>
<td>RW</td>
<td>Command Queue Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>10</td>
<td>CQPAUSED</td>
<td>RW</td>
<td>Command Queue is Paused.<br><br>
</td>
</tr>
<tr>
<td>9</td>
<td>CQUPD</td>
<td>RW</td>
<td>Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.<br><br>
</td>
</tr>
<tr>
<td>8</td>
<td>CQCMP</td>
<td>RW</td>
<td>Command Queue Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>7</td>
<td>DERR</td>
<td>RW</td>
<td>DMA Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>6</td>
<td>DCMP</td>
<td>RW</td>
<td>DMA Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>5</td>
<td>RXF</td>
<td>RW</td>
<td>Receive FIFO full<br><br>
</td>
</tr>
<tr>
<td>4</td>
<td>RXO</td>
<td>RW</td>
<td>Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>RXU</td>
<td>RW</td>
<td>Receive FIFO underflow (only occurs when SW reads from an empty FIFO)<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>TXO</td>
<td>RW</td>
<td>Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>TXE</td>
<td>RW</td>
<td>Transmit FIFO empty.<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>CMDCMP</td>
<td>RW</td>
<td>Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signalled simultaneously<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="INTSET" class="panel-title">INTSET - MSPI Master Interrupts: Set</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x5001420C</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="19">RSVD
<br>0x0</td>
<td align="center" colspan="1">SCRERR
<br>0x0</td>
<td align="center" colspan="1">CQERR
<br>0x0</td>
<td align="center" colspan="1">CQPAUSED
<br>0x0</td>
<td align="center" colspan="1">CQUPD
<br>0x0</td>
<td align="center" colspan="1">CQCMP
<br>0x0</td>
<td align="center" colspan="1">DERR
<br>0x0</td>
<td align="center" colspan="1">DCMP
<br>0x0</td>
<td align="center" colspan="1">RXF
<br>0x0</td>
<td align="center" colspan="1">RXO
<br>0x0</td>
<td align="center" colspan="1">RXU
<br>0x0</td>
<td align="center" colspan="1">TXO
<br>0x0</td>
<td align="center" colspan="1">TXE
<br>0x0</td>
<td align="center" colspan="1">CMDCMP
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:13</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>12</td>
<td>SCRERR</td>
<td>RW</td>
<td>Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.<br><br>
</td>
</tr>
<tr>
<td>11</td>
<td>CQERR</td>
<td>RW</td>
<td>Command Queue Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>10</td>
<td>CQPAUSED</td>
<td>RW</td>
<td>Command Queue is Paused.<br><br>
</td>
</tr>
<tr>
<td>9</td>
<td>CQUPD</td>
<td>RW</td>
<td>Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.<br><br>
</td>
</tr>
<tr>
<td>8</td>
<td>CQCMP</td>
<td>RW</td>
<td>Command Queue Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>7</td>
<td>DERR</td>
<td>RW</td>
<td>DMA Error Interrupt<br><br>
</td>
</tr>
<tr>
<td>6</td>
<td>DCMP</td>
<td>RW</td>
<td>DMA Complete Interrupt<br><br>
</td>
</tr>
<tr>
<td>5</td>
<td>RXF</td>
<td>RW</td>
<td>Receive FIFO full<br><br>
</td>
</tr>
<tr>
<td>4</td>
<td>RXO</td>
<td>RW</td>
<td>Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>RXU</td>
<td>RW</td>
<td>Receive FIFO underflow (only occurs when SW reads from an empty FIFO)<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>TXO</td>
<td>RW</td>
<td>Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>TXE</td>
<td>RW</td>
<td>Transmit FIFO empty.<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>CMDCMP</td>
<td>RW</td>
<td>Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signalled simultaneously<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="DMACFG" class="panel-title">DMACFG - DMA Configuration Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014250</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>DMA Configuration Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="13">RSVD
<br>0x0</td>
<td align="center" colspan="1">DMAPWROFF
<br>0x0</td>
<td align="center" colspan="13">RSVD
<br>0x0</td>
<td align="center" colspan="2">DMAPRI
<br>0x0</td>
<td align="center" colspan="1">DMADIR
<br>0x0</td>
<td align="center" colspan="2">DMAEN
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:19</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED.<br><br>
</td>
</tr>
<tr>
<td>18</td>
<td>DMAPWROFF</td>
<td>RW</td>
<td>Power off MSPI domain upon completion of DMA operation.<br><br>
</td>
</tr>
<tr>
<td>17:5</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED.<br><br>
</td>
</tr>
<tr>
<td>4:3</td>
<td>DMAPRI</td>
<td>RW</td>
<td>Sets the Priority of the DMA request<br><br>
LOW = 0x0 - Low Priority (service as best effort)<br>
HIGH = 0x1 - High Priority (service immediately)<br>
AUTO = 0x2 - Auto Priority (priority raised once TX FIFO empties or RX FIFO fills)</td>
</tr>
<tr>
<td>2</td>
<td>DMADIR</td>
<td>RW</td>
<td>Direction<br><br>
P2M = 0x0 - Peripheral to Memory (SRAM) transaction<br>
M2P = 0x1 - Memory to Peripheral transaction</td>
</tr>
<tr>
<td>1:0</td>
<td>DMAEN</td>
<td>RW</td>
<td>DMA Enable. Setting this bit to EN will start the DMA operation<br><br>
DIS = 0x0 - Disable DMA Function<br>
EN = 0x3 - Enable HW controlled DMA Function to manage DMA to flash devices. HW will automatically handle issuance of instruction/address bytes based on settings in the FLASH register.</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="DMASTAT" class="panel-title">DMASTAT - DMA Status Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014254</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>DMA Status Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="28">RSVD
<br>0x0</td>
<td align="center" colspan="1">SCRERR
<br>0x0</td>
<td align="center" colspan="1">DMAERR
<br>0x0</td>
<td align="center" colspan="1">DMACPL
<br>0x0</td>
<td align="center" colspan="1">DMATIP
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:4</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED.<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>SCRERR</td>
<td>RW</td>
<td>Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR.<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>DMAERR</td>
<td>RW</td>
<td>DMA Error. This active high bit signals that an error was encountered during the DMA operation.<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>DMACPL</td>
<td>RW</td>
<td>DMA Transfer Complete. This signals the end of the DMA operation.<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>DMATIP</td>
<td>RO</td>
<td>DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="DMATARGADDR" class="panel-title">DMATARGADDR - DMA Target Address Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014258</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>DMA Target Address Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="32">TARGADDR
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:0</td>
<td>TARGADDR</td>
<td>RW</td>
<td>Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="DMADEVADDR" class="panel-title">DMADEVADDR - DMA Device Address Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x5001425C</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>DMA Device Address Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="32">DEVADDR
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:0</td>
<td>DEVADDR</td>
<td>RW</td>
<td>SPI Device address for automated DMA transactions (both read and write).<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="DMATOTCOUNT" class="panel-title">DMATOTCOUNT - DMA Total Transfer Count</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014260</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>DMA Total Transfer Count</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="16">RSVD
<br>0x0</td>
<td align="center" colspan="16">TOTCOUNT
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:16</td>
<td>RSVD</td>
<td>RO</td>
<td>Reserved<br><br>
</td>
</tr>
<tr>
<td>15:0</td>
<td>TOTCOUNT</td>
<td>RW</td>
<td>Total Transfer Count in bytes.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="DMABCOUNT" class="panel-title">DMABCOUNT - DMA BYTE Transfer Count</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014264</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>DMA BYTE Transfer Count</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="24">RSVD
<br>0x0</td>
<td align="center" colspan="8">BCOUNT
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:8</td>
<td>RSVD</td>
<td>RO</td>
<td>Reserved<br><br>
</td>
</tr>
<tr>
<td>7:0</td>
<td>BCOUNT</td>
<td>RW</td>
<td>Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended values are 16 or 32.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="DMATHRESH" class="panel-title">DMATHRESH - DMA Transmit Trigger Threshhold</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x50014278</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Indicates FIFO level at which a DMA should be triggered. For most configurations, a setting of 8 is recommended for both read and write operations.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="28">RSVD
<br>0x0</td>
<td align="center" colspan="4">DMATHRESH
<br>0x8</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:4</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED<br><br>
</td>
</tr>
<tr>
<td>3:0</td>
<td>DMATHRESH</td>
<td>RW</td>
<td>DMA transfer FIFO level trigger. For read operations, DMA is triggered when the FIFO level is greater than this value. For write operations, DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT bytes.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQCFG" class="panel-title">CQCFG - Command Queue Configuration Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142A0</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>This register controls Command Queueing (CQ) operations in a manner similar to the DMACFG register.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="28">RSVD
<br>0x0</td>
<td align="center" colspan="1">CQAUTOCLEARMASK
<br>0x0</td>
<td align="center" colspan="1">CQPWROFF
<br>0x0</td>
<td align="center" colspan="1">CQPRI
<br>0x0</td>
<td align="center" colspan="1">CQEN
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:4</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED.<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>CQAUTOCLEARMASK</td>
<td>RW</td>
<td>Eanble clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ.<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>CQPWROFF</td>
<td>RW</td>
<td>Power off MSPI domain upon completion of DMA operation.<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>CQPRI</td>
<td>RW</td>
<td>Sets the Priority of the command queue dma request<br><br>
LOW = 0x0 - Low Priority (service as best effort)<br>
HIGH = 0x1 - High Priority (service immediately)</td>
</tr>
<tr>
<td>0</td>
<td>CQEN</td>
<td>RW</td>
<td>Command queue enable. When set, will enable the processing of the command queue<br><br>
DIS = 0x0 - Disable CQ Function<br>
EN = 0x1 - Enable CQ Function</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQADDR" class="panel-title">CQADDR - CQ Target Read Address Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142A8</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled, however the command queue script itself may update CQADDR in order to perform queue management functions (like resetting the pointers)</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="3">RSVD
<br>0x0</td>
<td align="center" colspan="29">CQADDR
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:29</td>
<td>RSVD</td>
<td>RO</td>
<td>Reserved<br><br>
</td>
</tr>
<tr>
<td>28:0</td>
<td>CQADDR</td>
<td>RW</td>
<td>Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQSTAT" class="panel-title">CQSTAT - Command Queue Status Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142AC</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Command Queue Status Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="28">RSVD
<br>0x0</td>
<td align="center" colspan="1">CQPAUSED
<br>0x0</td>
<td align="center" colspan="1">CQERR
<br>0x0</td>
<td align="center" colspan="1">CQCPL
<br>0x0</td>
<td align="center" colspan="1">CQTIP
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:4</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED.<br><br>
</td>
</tr>
<tr>
<td>3</td>
<td>CQPAUSED</td>
<td>RO</td>
<td>Command queue is currently paused status.<br><br>
</td>
</tr>
<tr>
<td>2</td>
<td>CQERR</td>
<td>RW</td>
<td>Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.<br><br>
</td>
</tr>
<tr>
<td>1</td>
<td>CQCPL</td>
<td>RW</td>
<td>Command queue operation Complete. This signals the end of the command queue operation.<br><br>
</td>
</tr>
<tr>
<td>0</td>
<td>CQTIP</td>
<td>RO</td>
<td>Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQFLAGS" class="panel-title">CQFLAGS - Command Queue Flag Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142B0</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Command Queue Flag Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="16">RSVD
<br>0x0</td>
<td align="center" colspan="16">CQFLAGS
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:16</td>
<td>RSVD</td>
<td>RO</td>
<td>Reserved<br><br>
</td>
</tr>
<tr>
<td>15:0</td>
<td>CQFLAGS</td>
<td>RO</td>
<td>Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.<br><br>
STOP = 0x8000 - CQ Stop Flag. When set, CQ processing will complete.<br>
CQIDX = 0x4000 - CQ Index Pointers (CURIDX/ENDIDX) match.<br>
DMACPL = 0x800 - DMA Complete Status (hardwired DMACPL bit in DMASTAT)<br>
CMDCPL = 0x400 - PIO Operation completed (STATUS bit in CTRL register)<br>
IOM1READY = 0x200 - IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.<br>
IOM0READY = 0x100 - IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.<br>
SWFLAG7 = 0x80 - Software flag 7. Can be used by software to start/pause operations<br>
SWFLAG6 = 0x40 - Software flag 6. Can be used by software to start/pause operatoins<br>
SWFLAG5 = 0x20 - Software flag 5. Can be used by software to start/pause operations<br>
SWFLAG4 = 0x10 - Software flag 4. Can be used by software to start/pause operatoins<br>
SWFLAG3 = 0x8 - Software flag 3. Can be used by software to start/pause operations<br>
SWFLAG2 = 0x4 - Software flag 2. Can be used by software to start/pause operatoins<br>
SWFLAG1 = 0x2 - Software flag 1. Can be used by software to start/pause operations<br>
SWFLAG0 = 0x1 - Software flag 0. Can be used by software to start/pause operatoins<br>
IOM1START = 0x2 - IOM Buffer 1 status (same as SWFLAG1). When linked to IOM, indicates to IOM that buffer 1 is ready.<br>
IOM0START = 0x1 - IOM Buffer 0 status (same as SWFLAG0). When linked to IOM, indicates to IOM that buffer 0 is ready.</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQSETCLEAR" class="panel-title">CQSETCLEAR - Command Queue Flag Set/Clear Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142B4</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Command Queue Flag Set/Clear Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="8">RSVD
<br>0x0</td>
<td align="center" colspan="8">CQFCLR
<br>0x0</td>
<td align="center" colspan="8">CQFTOGGLE
<br>0x0</td>
<td align="center" colspan="8">CQFSET
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:24</td>
<td>RSVD</td>
<td>RO</td>
<td>Reserved<br><br>
</td>
</tr>
<tr>
<td>23:16</td>
<td>CQFCLR</td>
<td>WO</td>
<td>Clear CQFlag status bits.<br><br>
</td>
</tr>
<tr>
<td>15:8</td>
<td>CQFTOGGLE</td>
<td>RO</td>
<td>Toggle CQFlag status bits<br><br>
</td>
</tr>
<tr>
<td>7:0</td>
<td>CQFSET</td>
<td>WO</td>
<td>Set CQFlag status bits. Set has priority over clear if both are high.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQPAUSE" class="panel-title">CQPAUSE - Command Queue Pause Mask Register</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142B8</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Command Queue Pause Mask Register</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="16">RSVD
<br>0x0</td>
<td align="center" colspan="16">CQMASK
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:16</td>
<td>RSVD</td>
<td>RO</td>
<td>Reserved<br><br>
</td>
</tr>
<tr>
<td>15:0</td>
<td>CQMASK</td>
<td>RW</td>
<td>CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK&CQPAUSE)==CQMASK.<br><br>
STOP = 0x8000 - CQ Stop Flag. When set, CQ processing will complete.<br>
CQIDX = 0x4000 - CQ Index Pointers (CURIDX/ENDIDX) match.<br>
DMACPL = 0x800 - DMA Complete Status (hardwired DMACPL bit in DMASTAT)<br>
CMDCPL = 0x400 - PIO Operation completed (STATUS bit in CTRL register)<br>
IOM1READY = 0x200 - IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.<br>
IOM0READY = 0x100 - IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.<br>
SWFLAG7 = 0x80 - Software flag 7. Can be used by software to start/pause operations<br>
SWFLAG6 = 0x40 - Software flag 6. Can be used by software to start/pause operatoins<br>
SWFLAG5 = 0x20 - Software flag 5. Can be used by software to start/pause operations<br>
SWFLAG4 = 0x10 - Software flag 4. Can be used by software to start/pause operatoins<br>
SWFLAG3 = 0x8 - Software flag 3. Can be used by software to start/pause operations<br>
SWFLAG2 = 0x4 - Software flag 2. Can be used by software to start/pause operatoins<br>
SWFLAG1 = 0x2 - Software flag 1. Can be used by software to start/pause operations<br>
SWFLAG0 = 0x1 - Software flag 0. Can be used by software to start/pause operatoins<br>
IOM1START = 0x2 - IOM Buffer 1 status (same as SWFLAG1). When linked to IOM, indicates to IOM that buffer 1 is ready.<br>
IOM0START = 0x1 - IOM Buffer 0 status (same as SWFLAG0). When linked to IOM, indicates to IOM that buffer 0 is ready.</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQCURIDX" class="panel-title">CQCURIDX - Command Queue Current Index</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142C0</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value, which will cause the CQ to be paused when enabled. Software may then add entries to the command queue (in SRAM) and update CQENDIDX. The command queue operations will then increment CQCURIDX as it processes operations. Once CQCURIDX==CQENDIDX, the command queue hardware will automatically pause since no additional operations have been appended to the queue.</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="24">RSVD
<br>0x0</td>
<td align="center" colspan="8">CQCURIDX
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:8</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED.<br><br>
</td>
</tr>
<tr>
<td>7:0</td>
<td>CQCURIDX</td>
<td>RW</td>
<td>Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal, allowing SW to pause the CQ processing until the end index is updated.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
<div class="panel panel-default">
<div class="panel-heading">
<h3 id="CQENDIDX" class="panel-title">CQENDIDX - Command Queue End Index</h3>
</div>
<div class="panel-body">
<h3>Address:</h3>
<table style="margin:10px">
<tr id="row_0_0_">
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">Instance 0 Address:</span>
</td>
<td class="entry">
<span style="width:32px;display:inline-block;">&#160;</span>
<span class="h5">0x500142C4</span>
</td>
</tr>
</table>
<h3>Description:</h3>
<p>Command Queue End Index</p>
<h3>Example Macro Usage:</h3>
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:
// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
<h3>Register Fields:</h3>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>31</th>
<th>30</th>
<th>29</th>
<th>28</th>
<th>27</th>
<th>26</th>
<th>25</th>
<th>24</th>
<th>23</th>
<th>22</th>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>15</th>
<th>14</th>
<th>13</th>
<th>12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>5</th>
<th>4</th>
<th>3</th>
<th>2</th>
<th>1</th>
<th>0</th>
</tr>
</thead>
<tbody>
<tr>
<td align="center" colspan="24">RSVD
<br>0x0</td>
<td align="center" colspan="8">CQENDIDX
<br>0x0</td>
</tr>
</tbody>
</table>
<br>
<table style="margin:10px" class="table table-bordered table-condensed">
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>RW</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>31:8</td>
<td>RSVD</td>
<td>RO</td>
<td>RESERVED.<br><br>
</td>
</tr>
<tr>
<td>7:0</td>
<td>CQENDIDX</td>
<td>RW</td>
<td>Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer.<br><br>
</td>
</tr>
</tbody>
</table>
<br>
</div>
</div>
</body>
<hr size="1">
<body>
<div id="footer" align="right">
<small>
AmbiqSuite Register Documentation&nbsp;
<a href="http://www.ambiqmicro.com">
<img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>&nbsp&nbsp Copyright &copy; 2019&nbsp&nbsp<br />
This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.&nbsp&nbsp<br/>
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