6627 lines
292 KiB
HTML
6627 lines
292 KiB
HTML
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<title>AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview</title>
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<table cellspacing="0" cellpadding="0">
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<tbody>
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<tr style="height: 56px;">
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<td id="projectlogo">
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<img alt="Logo" src="../resources/am_logo.png" />
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</td>
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<td style="padding-left: 0.5em;">
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<div id="projectname">Apollo Register Documentation  <span id="projectnumber">v2.4.2</span></div>
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</td>
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</tr>
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</tbody>
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</table>
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</div>
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<!-- end header part -->
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<div id="navrow1" class="tabs">
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<ul class="tablist">
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<li class="current"><a href="../index.html"><span>Main Page</span></a>
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</li>
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</div>
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</li>
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</ul>
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</div>
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</div>
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<!-- top -->
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<!-- window showing the filter options -->
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<div class="header">
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<div class="headertitle">
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<div class="title">MCUCTRL - MCU Miscellaneous Control Logic</div>
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</div>
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</div>
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<!--header-->
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<body>
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<br>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 class="panel-title"> MCUCTRL Register Index</h3>
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</div>
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<div class="panel-body">
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<table>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000000:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CHIPPN" target="_self">CHIPPN - Chip Information Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000004:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CHIPID0" target="_self">CHIPID0 - Unique Chip ID 0</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000008:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CHIPID1" target="_self">CHIPID1 - Unique Chip ID 1</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000000C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CHIPREV" target="_self">CHIPREV - Chip Revision</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000010:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#VENDORID" target="_self">VENDORID - Unique Vendor ID</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000014:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SKU" target="_self">SKU - Unique Chip SKU</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000018:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FEATUREENABLE" target="_self">FEATUREENABLE - Feature Enable on Burst and BLE</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000020:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DEBUGGER" target="_self">DEBUGGER - Debugger Control</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000100:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#BODCTRL" target="_self">BODCTRL - BOD control Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000104:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ADCPWRDLY" target="_self">ADCPWRDLY - ADC Power Up Delay Control</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000010C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ADCCAL" target="_self">ADCCAL - ADC Calibration Control</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000110:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ADCBATTLOAD" target="_self">ADCBATTLOAD - ADC Battery Load Enable</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000118:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ADCTRIM" target="_self">ADCTRIM - ADC Trims</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000011C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ADCREFCOMP" target="_self">ADCREFCOMP - ADC Referece Keeper and Comparator Control</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000120:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#XTALCTRL" target="_self">XTALCTRL - XTAL Oscillator Control</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000124:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#XTALGENCTRL" target="_self">XTALGENCTRL - XTAL Oscillator General Control</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000198:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#MISCCTRL" target="_self">MISCCTRL - Miscellaneous control register.</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x000001A0:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#BOOTLOADER" target="_self">BOOTLOADER - Bootloader and secure boot functions</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x000001A4:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SHADOWVALID" target="_self">SHADOWVALID - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x000001B0:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SCRATCH0" target="_self">SCRATCH0 - Scratch register that is not reset by any reset</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">0x000001B4:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SCRATCH1" target="_self">SCRATCH1 - Scratch register that is not reset by any reset</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x000001C0:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ICODEFAULTADDR" target="_self">ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred.</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x000001C4:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DCODEFAULTADDR" target="_self">DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred.</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">0x000001C8:</span>
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</td>
|
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SYSFAULTADDR" target="_self">SYSFAULTADDR - System bus address which was present when a bus fault occurred.</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x000001CC:</span>
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</td>
|
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FAULTSTATUS" target="_self">FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x000001D0:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FAULTCAPTUREEN" target="_self">FAULTCAPTUREEN - Enable the fault capture registers</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000200:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DBGR1" target="_self">DBGR1 - Read-only debug register 1</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">0x00000204:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DBGR2" target="_self">DBGR2 - Read-only debug register 2</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">0x00000220:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#PMUENABLE" target="_self">PMUENABLE - Control bit to enable/disable the PMU</a>
|
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">0x00000250:</span>
|
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</td>
|
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#TPIUCTRL" target="_self">TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
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|
<span class="h5">0x00000264:</span>
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</td>
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#OTAPOINTER" target="_self">OTAPOINTER - OTA (Over the Air) Update Pointer/Status. Reset only by POA</a>
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</td>
|
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x00000280:</span>
|
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</td>
|
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<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
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<a class="el" href="#APBDMACTRL" target="_self">APBDMACTRL - DMA Control Register. Determines misc settings for DMA operation</a>
|
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</td>
|
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x00000284:</span>
|
|
</td>
|
|
<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SRAMMODE" target="_self">SRAMMODE - SRAM Controller mode bits</a>
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</td>
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</tr>
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<tr id="row_0_0_">
|
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x00000348:</span>
|
|
</td>
|
|
<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#KEXTCLKSEL" target="_self">KEXTCLKSEL - Key Register to enable the use of external clock selects via the EXTCLKSEL reg</a>
|
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</td>
|
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x0000035C:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
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<a class="el" href="#SIMOBUCK4" target="_self">SIMOBUCK4 - SIMO Buck Control Reg1</a>
|
|
</td>
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</tr>
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|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x00000368:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#BLEBUCK2" target="_self">BLEBUCK2 - BLEBUCK2 Control Reg</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003A0:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#FLASHWPROT0" target="_self">FLASHWPROT0 - Flash Write Protection Bits</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003A4:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#FLASHWPROT1" target="_self">FLASHWPROT1 - Flash Write Protection Bits</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003B0:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#FLASHRPROT0" target="_self">FLASHRPROT0 - Flash Read Protection Bits</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003B4:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#FLASHRPROT1" target="_self">FLASHRPROT1 - Flash Read Protection Bits</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003C0:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#DMASRAMWRITEPROTECT0" target="_self">DMASRAMWRITEPROTECT0 - SRAM write-protection bits.</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003C4:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#DMASRAMWRITEPROTECT1" target="_self">DMASRAMWRITEPROTECT1 - SRAM write-protection bits.</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003D0:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#DMASRAMREADPROTECT0" target="_self">DMASRAMREADPROTECT0 - SRAM read-protection bits.</a>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x000003D4:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<a class="el" href="#DMASRAMREADPROTECT1" target="_self">DMASRAMREADPROTECT1 - SRAM read-protection bits.</a>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CHIPPN" class="panel-title">CHIPPN - Chip Information Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020000</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Chip Information Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">PARTNUM
|
|
<br>0x4000000</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>PARTNUM</td>
|
|
<td>RO</td>
|
|
<td>BCD part number.<br><br>
|
|
APOLLO3 = 0x6000000 - Apollo3 part number is 0x06xxxxxx.<br>
|
|
APOLLO2 = 0x3000000 - Apollo2 part number is 0x03xxxxxx.<br>
|
|
APOLLO = 0x1000000 - Apollo part number is 0x01xxxxxx.<br>
|
|
PN_M = 0xFF000000 - Mask for the part number field.<br>
|
|
PN_S = 0x18 - Bit position for the part number field.<br>
|
|
FLASHSIZE_M = 0xF00000 - Mask for the FLASH_SIZE field.
|
|
Values:
|
|
0: 16KB
|
|
1: 32KB
|
|
2: 64KB
|
|
3: 128KB
|
|
4: 256KB
|
|
5: 512KB
|
|
6: 1MB
|
|
7: 2MB<br>
|
|
FLASHSIZE_S = 0x14 - Bit position for the FLASH_SIZE field.<br>
|
|
SRAMSIZE_M = 0xF0000 - Mask for the SRAM_SIZE field.
|
|
Values:
|
|
0: 16KB
|
|
1: 32KB
|
|
2: 64KB
|
|
3: 128KB
|
|
4: 256KB
|
|
5: 512KB
|
|
6: 1MB
|
|
7: 384KB<br>
|
|
SRAMSIZE_S = 0x10 - Bit position for the SRAM_SIZE field.<br>
|
|
REV_M = 0xFF00 - Mask for the revision field. Bits [15:12] are major rev, [11:8] are minor rev.
|
|
Values:
|
|
0: Major Rev A, Minor Rev 0
|
|
1: Major Rev B, Minor Rev 1<br>
|
|
REV_S = 0x8 - Bit position for the revision field.<br>
|
|
PKG_M = 0xC0 - Mask for the package field.
|
|
Values:
|
|
0: SIP
|
|
1: QFN
|
|
2: BGA
|
|
3: CSP<br>
|
|
PKG_S = 0x6 - Bit position for the package field.<br>
|
|
PINS_M = 0x38 - Mask for the pins field.
|
|
Values:
|
|
0: 25 pins
|
|
1: 49 pins
|
|
2: 64 pins
|
|
3: 81 pins<br>
|
|
PINS_S = 0x3 - Bit position for the pins field.<br>
|
|
TEMP_M = 0x6 - Mask for the temperature field.
|
|
Values:
|
|
0: Commercial
|
|
1: Military
|
|
2: Automative
|
|
3: Industrial<br>
|
|
TEMP_S = 0x1 - Bit position for the temperature field.<br>
|
|
QUAL_M = 0x1 - Mask for the qualified field.
|
|
Values:
|
|
0: Prototype/Sample
|
|
1: Qualified<br>
|
|
QUAL_S = 0x0 - Bit position for the qualified field.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CHIPID0" class="panel-title">CHIPID0 - Unique Chip ID 0</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020004</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Unique Chip ID 0</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">CHIPID0
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>CHIPID0</td>
|
|
<td>RO</td>
|
|
<td>Unique chip ID 0.<br><br>
|
|
APOLLO3 = 0x0 - Apollo3 CHIPID0.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CHIPID1" class="panel-title">CHIPID1 - Unique Chip ID 1</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020008</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Unique Chip ID 1</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">CHIPID1
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>CHIPID1</td>
|
|
<td>RO</td>
|
|
<td>Unique chip ID 1.<br><br>
|
|
APOLLO3 = 0x0 - Apollo3 CHIPID1.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CHIPREV" class="panel-title">CHIPREV - Chip Revision</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x4002000C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Chip Revision</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="12">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="12">SIPART
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="4">REVMAJ
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="4">REVMIN
|
|
<br>0x1</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:20</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>19:8</td>
|
|
<td>SIPART</td>
|
|
<td>RO</td>
|
|
<td>Silicon Part ID<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:4</td>
|
|
<td>REVMAJ</td>
|
|
<td>RO</td>
|
|
<td>Major Revision ID.<br><br>
|
|
B = 0x2 - Apollo3 revision B<br>
|
|
A = 0x1 - Apollo3 revision A</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3:0</td>
|
|
<td>REVMIN</td>
|
|
<td>RO</td>
|
|
<td>Minor Revision ID.<br><br>
|
|
REV1 = 0x2 - Apollo3 minor rev 1.<br>
|
|
REV0 = 0x1 - Apollo3 minor rev 0. Minor revision value, succeeding minor revisions will increment from this value.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="VENDORID" class="panel-title">VENDORID - Unique Vendor ID</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020010</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Unique Vendor ID</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">VENDORID
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>VENDORID</td>
|
|
<td>RO</td>
|
|
<td>Unique Vendor ID<br><br>
|
|
AMBIQ = 0x414D4251 - Ambiq Vendor ID</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="SKU" class="panel-title">SKU - Unique Chip SKU</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020014</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Unique Chip SKU</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="29">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SECBOOT
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ALLOWBLE
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ALLOWBURST
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>SECBOOT</td>
|
|
<td>RO</td>
|
|
<td>Secure boot feature allowed<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>ALLOWBLE</td>
|
|
<td>RO</td>
|
|
<td>Allow BLE feature<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>ALLOWBURST</td>
|
|
<td>RO</td>
|
|
<td>Allow Burst feature<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FEATUREENABLE" class="panel-title">FEATUREENABLE - Feature Enable on Burst and BLE</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020018</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Feature Enable on Burst and BLE</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="25">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BURSTAVAIL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BURSTACK
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BURSTREQ
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BLEAVAIL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BLEACK
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BLEREQ
|
|
<br>0x1</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:7</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>6</td>
|
|
<td>BURSTAVAIL</td>
|
|
<td>RO</td>
|
|
<td>Availability of Burst functionality<br><br>
|
|
AVAIL = 0x1 - Burst functionality available<br>
|
|
NOTAVAIL = 0x0 - Burst functionality not available</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>BURSTACK</td>
|
|
<td>RO</td>
|
|
<td>ACK for BURSTREQ<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>BURSTREQ</td>
|
|
<td>RW</td>
|
|
<td>Controls the Burst functionality<br><br>
|
|
EN = 0x1 - Enable the Burst functionality<br>
|
|
DIS = 0x0 - Disable the Burst functionality</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>BLEAVAIL</td>
|
|
<td>RO</td>
|
|
<td>AVAILABILITY of the BLE functionality<br><br>
|
|
AVAIL = 0x1 - BLE functionality available<br>
|
|
NOTAVAIL = 0x0 - BLE functionality not available</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>BLEACK</td>
|
|
<td>RO</td>
|
|
<td>ACK for BLEREQ<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>BLEREQ</td>
|
|
<td>RW</td>
|
|
<td>Controls the BLE functionality<br><br>
|
|
EN = 0x1 - Enable the BLE functionality<br>
|
|
DIS = 0x0 - Disable the BLE functionality</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DEBUGGER" class="panel-title">DEBUGGER - Debugger Control</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020020</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Debugger Control</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="31">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">LOCKOUT
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>LOCKOUT</td>
|
|
<td>RW</td>
|
|
<td>Lockout of debugger (SWD).<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="BODCTRL" class="panel-title">BODCTRL - BOD control Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020100</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>BOD control Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="26">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BODHVREFSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BODLVREFSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BODFPWD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BODCPWD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BODHPWD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BODLPWD
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:6</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>BODHVREFSEL</td>
|
|
<td>RW</td>
|
|
<td>BODH External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>BODLVREFSEL</td>
|
|
<td>RW</td>
|
|
<td>BODL External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>BODFPWD</td>
|
|
<td>RW</td>
|
|
<td>BODF Power Down.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>BODCPWD</td>
|
|
<td>RW</td>
|
|
<td>BODC Power Down.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>BODHPWD</td>
|
|
<td>RW</td>
|
|
<td>BODH Power Down.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>BODLPWD</td>
|
|
<td>RW</td>
|
|
<td>BODL Power Down.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="ADCPWRDLY" class="panel-title">ADCPWRDLY - ADC Power Up Delay Control</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020104</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>ADC Power Up Delay Control</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="16">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">ADCPWR1
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">ADCPWR0
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:16</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:8</td>
|
|
<td>ADCPWR1</td>
|
|
<td>RW</td>
|
|
<td>ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:0</td>
|
|
<td>ADCPWR0</td>
|
|
<td>RW</td>
|
|
<td>ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="ADCCAL" class="panel-title">ADCCAL - ADC Calibration Control</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x4002010C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>ADC Calibration Control</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="30">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ADCCALIBRATED
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">CALONPWRUP
|
|
<br>0x1</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:2</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>ADCCALIBRATED</td>
|
|
<td>RO</td>
|
|
<td>Status for ADC Calibration<br><br>
|
|
FALSE = 0x0 - ADC is not calibrated<br>
|
|
TRUE = 0x1 - ADC is calibrated</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>CALONPWRUP</td>
|
|
<td>RW</td>
|
|
<td>Run ADC Calibration on initial power up sequence<br><br>
|
|
DIS = 0x0 - Disable automatic calibration on initial power up<br>
|
|
EN = 0x1 - Enable automatic calibration on initial power up</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="ADCBATTLOAD" class="panel-title">ADCBATTLOAD - ADC Battery Load Enable</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020110</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>ADC Battery Load Enable</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="31">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BATTLOAD
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>BATTLOAD</td>
|
|
<td>RW</td>
|
|
<td>Enable the ADC battery load resistor<br><br>
|
|
DIS = 0x0 - Battery load is disconnected<br>
|
|
EN = 0x1 - Battery load is enabled</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="ADCTRIM" class="panel-title">ADCTRIM - ADC Trims</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020118</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>ADC Trims</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="19">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">ADCRFBUFIBTRIM
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="5">ADCREFBUFTRIM
|
|
<br>0x8</td>
|
|
|
|
<td align="center" colspan="4">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">ADCREFKEEPIBTRIM
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:13</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>12:11</td>
|
|
<td>ADCRFBUFIBTRIM</td>
|
|
<td>RW</td>
|
|
<td>ADC reference buffer input bias trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10:6</td>
|
|
<td>ADCREFBUFTRIM</td>
|
|
<td>RW</td>
|
|
<td>ADC Reference buffer trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5:2</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1:0</td>
|
|
<td>ADCREFKEEPIBTRIM</td>
|
|
<td>RW</td>
|
|
<td>ADC Reference Ibias trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="ADCREFCOMP" class="panel-title">ADCREFCOMP - ADC Referece Keeper and Comparator Control</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x4002011C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>ADC Referece Keeper and Comparator Control</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="15">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ADCRFCMPEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="3">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="5">ADCREFKEEPTRIM
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="7">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ADC_REFCOMP_OUT
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:17</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>16</td>
|
|
<td>ADCRFCMPEN</td>
|
|
<td>RW</td>
|
|
<td>ADC Reference comparator power down<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:13</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>12:8</td>
|
|
<td>ADCREFKEEPTRIM</td>
|
|
<td>RW</td>
|
|
<td>ADC Reference Keeper Trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>ADC_REFCOMP_OUT</td>
|
|
<td>RO</td>
|
|
<td>Output of the ADC reference comparator<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="XTALCTRL" class="panel-title">XTALCTRL - XTAL Oscillator Control</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020120</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>XTAL Oscillator Control</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="22">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">XTALICOMPTRIM
|
|
<br>0x3</td>
|
|
|
|
<td align="center" colspan="2">XTALIBUFTRIM
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">PWDBODXTAL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">PDNBCMPRXTAL
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">PDNBCOREXTAL
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">BYPCMPRXTAL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FDBKDSBLXTAL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">XTALSWE
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:10</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9:8</td>
|
|
<td>XTALICOMPTRIM</td>
|
|
<td>RW</td>
|
|
<td>XTAL ICOMP trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:6</td>
|
|
<td>XTALIBUFTRIM</td>
|
|
<td>RW</td>
|
|
<td>XTAL IBUFF trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>PWDBODXTAL</td>
|
|
<td>RW</td>
|
|
<td>XTAL Power down on brown out.<br><br>
|
|
PWRUPBOD = 0x0 - Power up xtal on BOD<br>
|
|
PWRDNBOD = 0x1 - Power down XTAL on BOD.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>PDNBCMPRXTAL</td>
|
|
<td>RW</td>
|
|
<td>XTAL Oscillator Power Down Comparator.<br><br>
|
|
PWRUPCOMP = 0x1 - Power up XTAL oscillator comparator.<br>
|
|
PWRDNCOMP = 0x0 - Power down XTAL oscillator comparator.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>PDNBCOREXTAL</td>
|
|
<td>RW</td>
|
|
<td>XTAL Oscillator Power Down Core.<br><br>
|
|
PWRUPCORE = 0x1 - Power up XTAL oscillator core.<br>
|
|
PWRDNCORE = 0x0 - Power down XTAL oscillator core.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>BYPCMPRXTAL</td>
|
|
<td>RW</td>
|
|
<td>XTAL Oscillator Bypass Comparator.<br><br>
|
|
USECOMP = 0x0 - Use the XTAL oscillator comparator.<br>
|
|
BYPCOMP = 0x1 - Bypass the XTAL oscillator comparator.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>FDBKDSBLXTAL</td>
|
|
<td>RW</td>
|
|
<td>XTAL Oscillator Disable Feedback.<br><br>
|
|
EN = 0x0 - Enable XTAL oscillator comparator.<br>
|
|
DIS = 0x1 - Disable XTAL oscillator comparator.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>XTALSWE</td>
|
|
<td>RW</td>
|
|
<td>XTAL Software Override Enable.<br><br>
|
|
OVERRIDE_DIS = 0x0 - XTAL Software Override Disable.<br>
|
|
OVERRIDE_EN = 0x1 - XTAL Software Override Enable.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="XTALGENCTRL" class="panel-title">XTALGENCTRL - XTAL Oscillator General Control</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020124</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>XTAL Oscillator General Control</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="18">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="6">XTALKSBIASTRIM
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="6">XTALBIASTRIM
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">ACWARMUP
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:14</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>13:8</td>
|
|
<td>XTALKSBIASTRIM</td>
|
|
<td>RW</td>
|
|
<td>XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:2</td>
|
|
<td>XTALBIASTRIM</td>
|
|
<td>RW</td>
|
|
<td>XTAL BIAS trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1:0</td>
|
|
<td>ACWARMUP</td>
|
|
<td>RW</td>
|
|
<td>Auto-calibration delay control<br><br>
|
|
SEC1 = 0x0 - Warmup period of 1-2 seconds<br>
|
|
SEC2 = 0x1 - Warmup period of 2-4 seconds<br>
|
|
SEC4 = 0x2 - Warmup period of 4-8 seconds<br>
|
|
SEC8 = 0x3 - Warmup period of 8-16 seconds</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="MISCCTRL" class="panel-title">MISCCTRL - Miscellaneous control register.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020198</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Miscellaneous control register.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="26">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">BLE_RESETN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="5">RESERVED_RW_0
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:6</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>BLE_RESETN</td>
|
|
<td>RW</td>
|
|
<td>BLE reset signal.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4:0</td>
|
|
<td>RESERVED_RW_0</td>
|
|
<td>RW</td>
|
|
<td>Reserved bits, always leave unchanged. The MISCCTRL register must be modified via atomic RMW, leaving this bitfield completely unmodified. Failure to do so will result in unpredictable behavior.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="BOOTLOADER" class="panel-title">BOOTLOADER - Bootloader and secure boot functions</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201A0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Bootloader and secure boot functions</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="2">SECBOOTONRST
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">SECBOOT
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">SECBOOTFEATURE
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="23">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">PROTLOCK
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">SBLOCK
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">BOOTLOADERLOW
|
|
<br>0x1</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:30</td>
|
|
<td>SECBOOTONRST</td>
|
|
<td>RO</td>
|
|
<td>Indicates whether the secure boot on warm reset is enabled<br><br>
|
|
DISABLED = 0x0 - Secure boot disabled<br>
|
|
ENABLED = 0x1 - Secure boot enabled<br>
|
|
ERROR = 0x2 - Error in secure boot configuration</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>29:28</td>
|
|
<td>SECBOOT</td>
|
|
<td>RO</td>
|
|
<td>Indicates whether the secure boot on cold reset is enabled<br><br>
|
|
DISABLED = 0x0 - Secure boot disabled<br>
|
|
ENABLED = 0x1 - Secure boot enabled<br>
|
|
ERROR = 0x2 - Error in secure boot configuration</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>27:26</td>
|
|
<td>SECBOOTFEATURE</td>
|
|
<td>RO</td>
|
|
<td>Indicates whether the secure boot feature is enabled.<br><br>
|
|
DISABLED = 0x0 - Secure boot disabled<br>
|
|
ENABLED = 0x1 - Secure boot enabled<br>
|
|
ERROR = 0x2 - Error in secure boot configuration</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>25:3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>PROTLOCK</td>
|
|
<td>RW</td>
|
|
<td>Flash protection lock. Always resets to 1, write 1 to clear. Enables writes to flash protection register set.<br><br>
|
|
LOCK = 0x1 - Enable the secure boot lock</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>SBLOCK</td>
|
|
<td>RW</td>
|
|
<td>Secure boot lock. Always resets to 1, write 1 to clear. Enables system visibility to bootloader until set.<br><br>
|
|
LOCK = 0x1 - Enable the secure boot lock</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>BOOTLOADERLOW</td>
|
|
<td>RW</td>
|
|
<td>Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1, write 1 to clear.<br><br>
|
|
ADDR0 = 0x1 - Bootloader code at 0x00000000.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="SHADOWVALID" class="panel-title">SHADOWVALID - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201A4</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="29">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">INFO0_VALID
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">BLDSLEEP
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">VALID
|
|
<br>0x1</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>INFO0_VALID</td>
|
|
<td>RO</td>
|
|
<td>Indicates whether info0 contains valid data<br><br>
|
|
VALID = 0x1 - Flash info0 (customer) space contains valid data.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>BLDSLEEP</td>
|
|
<td>RO</td>
|
|
<td>Indicates whether the bootloader should sleep or deep sleep if no image loaded.<br><br>
|
|
DEEPSLEEP = 0x1 - Bootloader will go to deep sleep if no flash image loaded</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>VALID</td>
|
|
<td>RO</td>
|
|
<td>Indicates whether the shadow registers contain valid data from the Flash Information Space.<br><br>
|
|
VALID = 0x1 - Flash information space contains valid data.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="SCRATCH0" class="panel-title">SCRATCH0 - Scratch register that is not reset by any reset</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201B0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Scratch register that is not reset by any reset</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">SCRATCH0
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>SCRATCH0</td>
|
|
<td>RW</td>
|
|
<td>Scratch register 0.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="SCRATCH1" class="panel-title">SCRATCH1 - Scratch register that is not reset by any reset</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201B4</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Scratch register that is not reset by any reset</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">SCRATCH1
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>SCRATCH1</td>
|
|
<td>RW</td>
|
|
<td>Scratch register 1.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="ICODEFAULTADDR" class="panel-title">ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201C0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>ICODE bus address which was present when a bus fault occurred.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">ICODEFAULTADDR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>ICODEFAULTADDR</td>
|
|
<td>RO</td>
|
|
<td>The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DCODEFAULTADDR" class="panel-title">DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201C4</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DCODE bus address which was present when a bus fault occurred.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">DCODEFAULTADDR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>DCODEFAULTADDR</td>
|
|
<td>RO</td>
|
|
<td>The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="SYSFAULTADDR" class="panel-title">SYSFAULTADDR - System bus address which was present when a bus fault occurred.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201C8</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>System bus address which was present when a bus fault occurred.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">SYSFAULTADDR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>SYSFAULTADDR</td>
|
|
<td>RO</td>
|
|
<td>SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FAULTSTATUS" class="panel-title">FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201CC</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="29">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SYSFAULT
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DCODEFAULT
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ICODEFAULT
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>SYSFAULT</td>
|
|
<td>RW</td>
|
|
<td>SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.<br><br>
|
|
NOFAULT = 0x0 - No bus fault has been detected.<br>
|
|
FAULT = 0x1 - Bus fault detected.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>DCODEFAULT</td>
|
|
<td>RW</td>
|
|
<td>DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.<br><br>
|
|
NOFAULT = 0x0 - No DCODE fault has been detected.<br>
|
|
FAULT = 0x1 - DCODE fault detected.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>ICODEFAULT</td>
|
|
<td>RW</td>
|
|
<td>The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.<br><br>
|
|
NOFAULT = 0x0 - No ICODE fault has been detected.<br>
|
|
FAULT = 0x1 - ICODE fault detected.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FAULTCAPTUREEN" class="panel-title">FAULTCAPTUREEN - Enable the fault capture registers</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400201D0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Enable the fault capture registers</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="31">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FAULTCAPTUREEN
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>FAULTCAPTUREEN</td>
|
|
<td>RW</td>
|
|
<td>Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.<br><br>
|
|
DIS = 0x0 - Disable fault capture.<br>
|
|
EN = 0x1 - Enable fault capture.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DBGR1" class="panel-title">DBGR1 - Read-only debug register 1</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Read-only debug register 1</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">ONETO8
|
|
<br>0x12345678</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>ONETO8</td>
|
|
<td>RO</td>
|
|
<td>Read-only register for communication validation<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DBGR2" class="panel-title">DBGR2 - Read-only debug register 2</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Read-only debug register 2</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">COOLCODE
|
|
<br>0xc001c0de</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>COOLCODE</td>
|
|
<td>RO</td>
|
|
<td>Read-only register for communication validation<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="PMUENABLE" class="panel-title">PMUENABLE - Control bit to enable/disable the PMU</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020220</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Control bit to enable/disable the PMU</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="31">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ENABLE
|
|
<br>0x1</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>ENABLE</td>
|
|
<td>RW</td>
|
|
<td>PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode.<br><br>
|
|
DIS = 0x0 - Disable MCU power management.<br>
|
|
EN = 0x1 - Enable MCU power management.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="TPIUCTRL" class="panel-title">TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020250</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="21">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="3">CLKSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="7">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ENABLE
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:11</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10:8</td>
|
|
<td>CLKSEL</td>
|
|
<td>RW</td>
|
|
<td>This field selects the frequency of the ARM M4 TPIU port.<br><br>
|
|
LOWPWR = 0x0 - Low power state.<br>
|
|
HFRCDIV2 = 0x1 - Selects HFRC divided by 2 as the source TPIU clk<br>
|
|
HFRCDIV8 = 0x2 - Selects HFRC divided by 8 as the source TPIU clk<br>
|
|
HFRCDIV16 = 0x3 - Selects HFRC divided by 16 as the source TPIU clk<br>
|
|
HFRCDIV32 = 0x4 - Selects HFRC divided by 32 as the source TPIU clk<br>
|
|
LOW_PWR = 0x0 - Deprecated-do not use. Low power state.<br>
|
|
HFRC_DIV_2 = 0x1 - Deprecated-do not use. Selects HFRC divided by 2 as the source TPIU clk<br>
|
|
HFRC_DIV_8 = 0x2 - Deprecated-do not use. Selects HFRC divided by 8 as the source TPIU clk<br>
|
|
HFRC_DIV_16 = 0x3 - Deprecated-do not use. Selects HFRC divided by 16 as the source TPIU clk<br>
|
|
HFRC_DIV_32 = 0x4 - Deprecated-do not use. Selects HFRC divided by 32 as the source TPIU clk</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:1</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>ENABLE</td>
|
|
<td>RW</td>
|
|
<td>TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.<br><br>
|
|
DIS = 0x0 - Disable the TPIU.<br>
|
|
EN = 0x1 - Enable the TPIU.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="OTAPOINTER" class="panel-title">OTAPOINTER - OTA (Over the Air) Update Pointer/Status. Reset only by POA</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020264</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>OTA (Over the Air) Update Pointer/Status. Reset only by POA</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="30">OTAPOINTER
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">OTASBLUPDATE
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">OTAVALID
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:2</td>
|
|
<td>OTAPOINTER</td>
|
|
<td>RW</td>
|
|
<td>Flash page pointer with updated OTA image<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>OTASBLUPDATE</td>
|
|
<td>RW</td>
|
|
<td>Indicates that the sbl_init has been updated<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>OTAVALID</td>
|
|
<td>RW</td>
|
|
<td>Indicates that an OTA update is valid<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="APBDMACTRL" class="panel-title">APBDMACTRL - DMA Control Register. Determines misc settings for DMA operation</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020280</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>DMA Control Register. Determines misc settings for DMA operation</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="16">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">HYSTERESIS
|
|
<br>0x2</td>
|
|
|
|
<td align="center" colspan="6">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DECODEABORT
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">DMA_ENABLE
|
|
<br>0x1</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:16</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:8</td>
|
|
<td>HYSTERESIS</td>
|
|
<td>RW</td>
|
|
<td>This field determines how long the DMA will remain active during deep sleep before shutting down and returning the system to full deep sleep. Values are based on a 94KHz clock and are roughly 10us increments for a range of ~10us to 2.55ms<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:2</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>DECODEABORT</td>
|
|
<td>RW</td>
|
|
<td>APB Decode Abort. When set, the APB bridge will issue a data abort (bus fault) on transactions to peripherals that are powered down. When set to 0, writes are quietly discarded and reads return 0.<br><br>
|
|
DISABLE = 0x0 - Bus operations to powered down peripherals are quietly discarded<br>
|
|
ENABLE = 0x1 - Bus operations to powered down peripherals result in a bus fault.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>DMA_ENABLE</td>
|
|
<td>RW</td>
|
|
<td>Enable the DMA controller. When disabled, DMA requests will be ignored by the controller<br><br>
|
|
DISABLE = 0x0 - DMA operations disabled<br>
|
|
ENABLE = 0x1 - DMA operations enabled</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="SRAMMODE" class="panel-title">SRAMMODE - SRAM Controller mode bits</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020284</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>SRAM Controller mode bits</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="24">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DPREFETCH_CACHE
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DPREFETCH
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IPREFETCH_CACHE
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IPREFETCH
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:8</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:6</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>DPREFETCH_CACHE</td>
|
|
<td>RW</td>
|
|
<td>Secondary prefetch feature that will cache prefetched data across bus waitstates (requires DPREFETCH to be set).<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>DPREFETCH</td>
|
|
<td>RW</td>
|
|
<td>When set, data bus accesses to the SRAM banks will be prefetched (normally 2 cycle read access). Use of this mode bit is only recommended if the work flow has a large number of sequential accesses.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3:2</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>IPREFETCH_CACHE</td>
|
|
<td>RW</td>
|
|
<td>Secondary prefetch feature that will cache prefetched data across bus waitstates (requires IPREFETCH to be set).<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>IPREFETCH</td>
|
|
<td>RW</td>
|
|
<td>When set, instruction accesses to the SRAM banks will be prefetched (normally 2 cycle read access). Generally, this mode bit should be set for improved performance when executing instructions from SRAM.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="KEXTCLKSEL" class="panel-title">KEXTCLKSEL - Key Register to enable the use of external clock selects via the EXTCLKSEL reg</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020348</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Key Register to enable the use of external clock selects via the EXTCLKSEL reg</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">KEXTCLKSEL
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>KEXTCLKSEL</td>
|
|
<td>RW</td>
|
|
<td>Key register value.<br><br>
|
|
Key = 0x53 - Key</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="SIMOBUCK4" class="panel-title">SIMOBUCK4 - SIMO Buck Control Reg1</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x4002035C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>SIMO Buck Control Reg1</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="4">SIMOBUCKIBIASTRIM
|
|
<br>0x3</td>
|
|
|
|
<td align="center" colspan="2">SIMOBUCKUVLOMODE
|
|
<br>0x3</td>
|
|
|
|
<td align="center" colspan="1">SIMOBUCKPRIORITYSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SIMOBUCKCOMP2TIMEOUTEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SIMOBUCKCOMP2LPEN
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="2">SIMOBUCKCLKDIVSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SIMOBUCKEXTCLKSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="3">SIMOBUCKUVLODRVSTRTRIM
|
|
<br>0x6</td>
|
|
|
|
<td align="center" colspan="3">SIMOBUCKUVLOCNTRTRIM
|
|
<br>0x6</td>
|
|
|
|
<td align="center" colspan="4">SIMOBUCKZXTRIM
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">SIMOBUCKMEMLEAKAGETRIM
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">SIMOBUCKMEMLPDRVSTRTRIM
|
|
<br>0x2</td>
|
|
|
|
<td align="center" colspan="2">SIMOBUCKMEMACTDRVSTRTRIM
|
|
<br>0x2</td>
|
|
|
|
<td align="center" colspan="4">SIMOBUCKMEMLPLOWTONTRIM
|
|
<br>0xa</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:28</td>
|
|
<td>SIMOBUCKIBIASTRIM</td>
|
|
<td>RW</td>
|
|
<td>simobuck_bias_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>27:26</td>
|
|
<td>SIMOBUCKUVLOMODE</td>
|
|
<td>RW</td>
|
|
<td>simobuck_uvlo_mode. In B0, these bits are used as SIMOBUCK mode bits. uvlo_mode[0] enables use of tonclk_lp for all operations and uvlo_mode[1] controls core_low/mem_low synchronization.<br><br>
|
|
USE_LP_CLOCK = 0x1 - LP clock is used for simobuck in both active and low-power mode.<br>
|
|
X_LOW_NOSYNC = 0x2 - No synchronization is applied to core_low/mem_low inputs (A1 behavior)<br>
|
|
X_LOW_SYNC = 0x0 - Synchronization is applied to core_low/mem_low inputs</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>25</td>
|
|
<td>SIMOBUCKPRIORITYSEL</td>
|
|
<td>RW</td>
|
|
<td>simobuck_priority_sel<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>24</td>
|
|
<td>SIMOBUCKCOMP2TIMEOUTEN</td>
|
|
<td>RW</td>
|
|
<td>simobuck_comp2_timeout_en<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>23</td>
|
|
<td>SIMOBUCKCOMP2LPEN</td>
|
|
<td>RW</td>
|
|
<td>simobuck_comp2_lp_en<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>22:21</td>
|
|
<td>SIMOBUCKCLKDIVSEL</td>
|
|
<td>RW</td>
|
|
<td>simobuck_clkdiv_sel<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>20</td>
|
|
<td>SIMOBUCKEXTCLKSEL</td>
|
|
<td>RW</td>
|
|
<td>simobuck_extclk_sel<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>19:17</td>
|
|
<td>SIMOBUCKUVLODRVSTRTRIM</td>
|
|
<td>RW</td>
|
|
<td>simobuck_uvlo_drvstr_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>16:14</td>
|
|
<td>SIMOBUCKUVLOCNTRTRIM</td>
|
|
<td>RW</td>
|
|
<td>For B0, this register has been redefined as mode bits for the Simobuck. Each bit is independent: [0]=always enable LP clock [1]=enable priority_state [2]=enable zx_comp reset removal fix<br><br>
|
|
ENABLE_LP_CLK = 0x1 - When set to 1, the LP clock will always be activated. When 0, the logic will request the clock when needed<br>
|
|
DISABLE_PRIORITY_STATE = 0x2 - (Inverse polarity mode bit) When set to 1, the priority state logic will be disabled and when set to 0, priority_state will enforce that both core and mem bucks get equal priority.<br>
|
|
ENABLE_ZXCOMP_SYNC = 0x4 - When set to 1, ZXCOMP will be routed through a flop and removal synchronized to the internal clock. When set to 0, logic will act like A1 logic and will be asynchronous.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>13:10</td>
|
|
<td>SIMOBUCKZXTRIM</td>
|
|
<td>RW</td>
|
|
<td>simobuck_zx_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9:8</td>
|
|
<td>SIMOBUCKMEMLEAKAGETRIM</td>
|
|
<td>RW</td>
|
|
<td>simobuck_mem_leakage_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:6</td>
|
|
<td>SIMOBUCKMEMLPDRVSTRTRIM</td>
|
|
<td>RW</td>
|
|
<td>simobuck_mem_lp_drvstr_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5:4</td>
|
|
<td>SIMOBUCKMEMACTDRVSTRTRIM</td>
|
|
<td>RW</td>
|
|
<td>simobuck_mem_act_drvstr_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3:0</td>
|
|
<td>SIMOBUCKMEMLPLOWTONTRIM</td>
|
|
<td>RW</td>
|
|
<td>simobuck_mem_lp_low_ton_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="BLEBUCK2" class="panel-title">BLEBUCK2 - BLEBUCK2 Control Reg</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x40020368</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>BLEBUCK2 Control Reg</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="14">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="6">BLEBUCKTOND2ATRIM
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="6">BLEBUCKTONHITRIM
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="6">BLEBUCKTONLOWTRIM
|
|
<br>0xe</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:18</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>17:12</td>
|
|
<td>BLEBUCKTOND2ATRIM</td>
|
|
<td>RO</td>
|
|
<td>blebuck_ton_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>11:6</td>
|
|
<td>BLEBUCKTONHITRIM</td>
|
|
<td>RW</td>
|
|
<td>blebuck_ton_hi_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5:0</td>
|
|
<td>BLEBUCKTONLOWTRIM</td>
|
|
<td>RW</td>
|
|
<td>blebuck_ton_low_trim<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FLASHWPROT0" class="panel-title">FLASHWPROT0 - Flash Write Protection Bits</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203A0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits write-protect flash in 16KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">FW0BITS
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>FW0BITS</td>
|
|
<td>RW</td>
|
|
<td>Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FLASHWPROT1" class="panel-title">FLASHWPROT1 - Flash Write Protection Bits</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203A4</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits write-protect flash in 16KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">FW1BITS
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>FW1BITS</td>
|
|
<td>RW</td>
|
|
<td>Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FLASHRPROT0" class="panel-title">FLASHRPROT0 - Flash Read Protection Bits</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203B0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits read-protect flash in 16KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">FR0BITS
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>FR0BITS</td>
|
|
<td>RW</td>
|
|
<td>Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FLASHRPROT1" class="panel-title">FLASHRPROT1 - Flash Read Protection Bits</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203B4</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits read-protect flash in 16KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">FR1BITS
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>FR1BITS</td>
|
|
<td>RW</td>
|
|
<td>Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMASRAMWRITEPROTECT0" class="panel-title">DMASRAMWRITEPROTECT0 - SRAM write-protection bits.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203C0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits write-protect system SRAM from DMA operations in 8KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">DMA_WPROT0
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>DMA_WPROT0</td>
|
|
<td>RW</td>
|
|
<td>Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMASRAMWRITEPROTECT1" class="panel-title">DMASRAMWRITEPROTECT1 - SRAM write-protection bits.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203C4</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits write-protect system SRAM from DMA operations in 8KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="16">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="16">DMA_WPROT1
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:16</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:0</td>
|
|
<td>DMA_WPROT1</td>
|
|
<td>RW</td>
|
|
<td>Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMASRAMREADPROTECT0" class="panel-title">DMASRAMREADPROTECT0 - SRAM read-protection bits.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203D0</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits read-protect system SRAM from DMA operations in 8KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">DMA_RPROT0
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>DMA_RPROT0</td>
|
|
<td>RW</td>
|
|
<td>Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DMASRAMREADPROTECT1" class="panel-title">DMASRAMREADPROTECT1 - SRAM read-protection bits.</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x400203D4</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>These bits read-protect system SRAM from DMA operations in 8KB chunks.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// Register access is all performed through the standard CMSIS structure-based
|
|
// interface. This includes module-level structure definitions with members and
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
|
// for directly accessing memory by address.
|
|
//
|
|
// The following examples show how to use these structures and macros:
|
|
|
|
// Setting the ADC configuration register...</span>
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
|
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="16">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="16">DMA_RPROT1
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:16</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:0</td>
|
|
<td>DMA_RPROT1</td>
|
|
<td>RW</td>
|
|
<td>Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
</body>
|
|
|
|
<hr size="1">
|
|
<body>
|
|
<div id="footer" align="right">
|
|
<small>
|
|
AmbiqSuite Register Documentation
|
|
<a href="http://www.ambiqmicro.com">
|
|
<img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>   Copyright © 2019  <br />
|
|
This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.  <br/>
|
|
</small>
|
|
</div>
|
|
</body>
|
|
</html>
|
|
|