3630 lines
154 KiB
HTML
3630 lines
154 KiB
HTML
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<title>AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview</title>
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<td id="projectlogo">
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<img alt="Logo" src="../resources/am_logo.png" />
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</td>
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<td style="padding-left: 0.5em;">
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<div id="projectname">Apollo Register Documentation  <span id="projectnumber">v2.4.2</span></div>
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</td>
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</tr>
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</tbody>
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</ul>
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</div>
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</div>
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<!-- top -->
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<!-- window showing the filter options -->
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<div class="header">
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<div class="headertitle">
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<div class="title">IOMSTR - I2C/SPI Master</div>
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</div>
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</div>
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<!--header-->
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<body>
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<br>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 class="panel-title"> IOMSTR Register Index</h3>
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</div>
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<div class="panel-body">
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<table>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000000:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFO" target="_self">FIFO - FIFO Access Port</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000100:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOPTR" target="_self">FIFOPTR - Current FIFO Pointers</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000104:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#TLNGTH" target="_self">TLNGTH - Transfer Length</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000108:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOTHR" target="_self">FIFOTHR - FIFO Threshold Configuration</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000010C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CLKCFG" target="_self">CLKCFG - I/O Clock Configuration</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000110:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CMD" target="_self">CMD - Command Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000114:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CMDRPT" target="_self">CMDRPT - Command Repeat Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000118:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#STATUS" target="_self">STATUS - Status Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000011C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CFG" target="_self">CFG - I/O Master Configuration</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000200:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTEN" target="_self">INTEN - IO Master Interrupts: Enable</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000204:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTSTAT" target="_self">INTSTAT - IO Master Interrupts: Status</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000208:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTCLR" target="_self">INTCLR - IO Master Interrupts: Clear</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000020C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTSET" target="_self">INTSET - IO Master Interrupts: Set</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000300:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DBG0" target="_self">DBG0 - </a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000304:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#DBG1" target="_self">DBG1 - </a>
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</td>
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</tr>
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</table>
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</div>
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</div>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 id="FIFO" class="panel-title">FIFO - FIFO Access Port</h3>
|
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</div>
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<div class="panel-body">
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<h3>Address:</h3>
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<table style="margin:10px">
|
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">Instance 0 Address:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x50004000</span>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">Instance 1 Address:</span>
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</td>
|
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x50005000</span>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">Instance 2 Address:</span>
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</td>
|
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x50006000</span>
|
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</td>
|
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</tr>
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|
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<tr id="row_0_0_">
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">Instance 3 Address:</span>
|
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</td>
|
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<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007000</span>
|
|
</td>
|
|
</tr>
|
|
|
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<tr id="row_0_0_">
|
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<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">Instance 4 Address:</span>
|
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</td>
|
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<td class="entry">
|
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<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">0x50008000</span>
|
|
</td>
|
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</tr>
|
|
|
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<tr id="row_0_0_">
|
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<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
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<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009000</span>
|
|
</td>
|
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</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>FIFO Access Port</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
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// All macro-based register writes follow the same basic format. For
|
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// single-instance modules, you may use the simpler AM_REG macro. For
|
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// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
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//
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// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
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// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
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//
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// For registers that do not have specific enumeration values, you may use this alternate format instead.
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//
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// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
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//
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// For example, the following three lines of code are equivalent methods of
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// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
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//</span>
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AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
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AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
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AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
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<h3>Register Fields:</h3>
|
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<table style="margin:10px" class="table table-bordered table-condensed">
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<thead>
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<tr>
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<th>31</th>
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<th>30</th>
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<th>29</th>
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<th>28</th>
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<th>27</th>
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<th>26</th>
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<th>25</th>
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<th>24</th>
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<th>23</th>
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<th>22</th>
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<th>21</th>
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<th>20</th>
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<th>19</th>
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<th>18</th>
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<th>17</th>
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<th>16</th>
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<th>15</th>
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<th>14</th>
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<th>13</th>
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<th>12</th>
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<th>11</th>
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<th>10</th>
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<th>9</th>
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<th>8</th>
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<th>7</th>
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<th>6</th>
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<th>5</th>
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<th>4</th>
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<th>3</th>
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<th>2</th>
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<th>1</th>
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<th>0</th>
|
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</tr>
|
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</thead>
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<tbody>
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<tr>
|
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<td align="center" colspan="32">FIFO
|
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<br>0x0</td>
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|
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</tr>
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</tbody>
|
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</table>
|
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<br>
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<table style="margin:10px" class="table table-bordered table-condensed">
|
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<thead>
|
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<tr>
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<th>Bits</th>
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<th>Name</th>
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<th>RW</th>
|
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<th>Description</th>
|
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</tr>
|
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</thead>
|
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<tbody>
|
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<tr>
|
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<td>31:0</td>
|
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<td>FIFO</td>
|
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<td>RW</td>
|
|
<td>FIFO access port.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
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</tbody>
|
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</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FIFOPTR" class="panel-title">FIFOPTR - Current FIFO Pointers</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004100</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005100</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006100</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007100</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008100</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009100</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Current FIFO Pointers</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="8">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">FIFOREM
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">FIFOSIZ
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:24</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>23:16</td>
|
|
<td>FIFOREM</td>
|
|
<td>RO</td>
|
|
<td>The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ).<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:8</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:0</td>
|
|
<td>FIFOSIZ</td>
|
|
<td>RO</td>
|
|
<td>The number of bytes currently in the FIFO.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="TLNGTH" class="panel-title">TLNGTH - Transfer Length</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004104</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005104</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006104</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007104</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008104</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009104</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Transfer Length</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="20">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="12">TLNGTH
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:12</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>11:0</td>
|
|
<td>TLNGTH</td>
|
|
<td>RO</td>
|
|
<td>Remaining transfer length.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="FIFOTHR" class="panel-title">FIFOTHR - FIFO Threshold Configuration</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004108</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005108</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006108</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007108</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008108</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009108</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>FIFO Threshold Configuration</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="17">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="7">FIFOWTHR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="7">FIFORTHR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:15</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>14:8</td>
|
|
<td>FIFOWTHR</td>
|
|
<td>RW</td>
|
|
<td>FIFO write threshold.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>6:0</td>
|
|
<td>FIFORTHR</td>
|
|
<td>RW</td>
|
|
<td>FIFO read threshold.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CLKCFG" class="panel-title">CLKCFG - I/O Clock Configuration</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000410C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000510C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000610C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000710C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000810C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000910C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>I/O Clock Configuration</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="8">TOTPER
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">LOWPER
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="3">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DIVEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">DIV3
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="3">FSEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="8">RSVD
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:24</td>
|
|
<td>TOTPER</td>
|
|
<td>RW</td>
|
|
<td>Clock total count minus 1.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>23:16</td>
|
|
<td>LOWPER</td>
|
|
<td>RW</td>
|
|
<td>Clock low count minus 1.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>15:13</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>12</td>
|
|
<td>DIVEN</td>
|
|
<td>RW</td>
|
|
<td>Enable clock division by TOTPER.<br><br>
|
|
DIS = 0x0 - Disable TOTPER division.<br>
|
|
EN = 0x1 - Enable TOTPER division.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>11</td>
|
|
<td>DIV3</td>
|
|
<td>RW</td>
|
|
<td>Enable divide by 3.<br><br>
|
|
DIS = 0x0 - Select divide by 1.<br>
|
|
EN = 0x1 - Select divide by 3.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10:8</td>
|
|
<td>FSEL</td>
|
|
<td>RW</td>
|
|
<td>Select the input clock frequency.<br><br>
|
|
HFRC_DIV64 = 0x0 - Selects the HFRC / 64 as the input clock.<br>
|
|
HFRC = 0x1 - Selects the HFRC as the input clock.<br>
|
|
HFRC_DIV2 = 0x2 - Selects the HFRC / 2 as the input clock.<br>
|
|
HFRC_DIV4 = 0x3 - Selects the HFRC / 4 as the input clock.<br>
|
|
HFRC_DIV8 = 0x4 - Selects the HFRC / 8 as the input clock.<br>
|
|
HFRC_DIV16 = 0x5 - Selects the HFRC / 16 as the input clock.<br>
|
|
HFRC_DIV32 = 0x6 - Selects the HFRC / 32 as the input clock.<br>
|
|
RSVD = 0x7 - Reserved.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:0</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CMD" class="panel-title">CMD - Command Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004110</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005110</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006110</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007110</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008110</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009110</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Command Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">CMD
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>CMD</td>
|
|
<td>RW</td>
|
|
<td>This register is the I/O Command. The command fields are as follow:<br><br>
|
|
POS_LENGTH = 0x0 - LSB bit position of the CMD LENGTH field.<br>
|
|
POS_OFFSET = 0x8 - LSB bit position of the CMD OFFSET field.<br>
|
|
POS_ADDRESS = 0x16 - LSB bit position of the I2C CMD ADDRESS field.<br>
|
|
POS_CHNL = 0x16 - LSB bit position of the SPI CMD CHANNEL field.<br>
|
|
POS_UPLNGTH = 0x23 - LSB bit position of the SPI CMD UPLNGTH field.<br>
|
|
POS_10BIT = 0x26 - LSB bit position of the I2C CMD 10-bit field.<br>
|
|
POS_LSB = 0x27 - LSB bit position of the CMD LSB-first field.<br>
|
|
POS_CONT = 0x28 - LSB bit position of the CMD CONTinue field.<br>
|
|
POS_OPER = 0x29 - LSB bit position of the CMD OPERation field.<br>
|
|
MSK_LENGTH = 0xFF - LSB bit mask of the CMD LENGTH field.<br>
|
|
MSK_OFFSET = 0xFF00 - LSB bit mask of the CMD OFFSET field.<br>
|
|
MSK_ADDRESS = 0xFF0000 - LSB bit mask of the I2C CMD ADDRESS field.<br>
|
|
MSK_CHNL = 0x70000 - LSB bit mask of the SPI CMD CHANNEL field.<br>
|
|
MSK_UPLNGTH = 0x7800000 - LSB bit mask of the SPI CMD UPLNGTH field.<br>
|
|
MSK_10BIT = 0x4000000 - LSB bit mask of the I2C CMD 10-bit field.<br>
|
|
MSK_LSB = 0x8000000 - LSB bit mask of the CMD LSB-first field.<br>
|
|
MSK_CONT = 0x10000000 - LSB bit mask of the CMD CONTinue field.<br>
|
|
MSK_OPER = 0xE0000000 - LSB bit mask of the CMD OPERation field.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CMDRPT" class="panel-title">CMDRPT - Command Repeat Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004114</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005114</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006114</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007114</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008114</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009114</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Command Repeat Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="27">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="5">CMDRPT
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:5</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4:0</td>
|
|
<td>CMDRPT</td>
|
|
<td>RW</td>
|
|
<td>These bits hold the Command repeat count.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="STATUS" class="panel-title">STATUS - Status Register</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004118</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005118</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006118</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007118</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008118</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009118</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Status Register</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="29">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IDLEST
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">CMDACT
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ERR
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:3</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>IDLEST</td>
|
|
<td>RO</td>
|
|
<td>This bit indicates if the I/O state machine is IDLE.<br><br>
|
|
IDLE = 0x1 - The I/O state machine is in the idle state.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>CMDACT</td>
|
|
<td>RO</td>
|
|
<td>This bit indicates if the I/O Command is active.<br><br>
|
|
ACTIVE = 0x1 - An I/O command is active.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>ERR</td>
|
|
<td>RO</td>
|
|
<td>This bit indicates if an error interrupt has occurred.<br><br>
|
|
ERROR = 0x1 - An error has been indicated by the IOM.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="CFG" class="panel-title">CFG - I/O Master Configuration</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000411C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000511C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000611C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000711C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000811C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000911C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>I/O Master Configuration</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="1">IFCEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="16">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">RDFCPOL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">WTFCPOL
|
|
<br>0x1</td>
|
|
|
|
<td align="center" colspan="1">WTFCIRQ
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FCDEL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">MOSIINV
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">RDFC
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">WTFC
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="2">STARTRD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FULLDUP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SPHA
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">SPOL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IFCSEL
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31</td>
|
|
<td>IFCEN</td>
|
|
<td>RW</td>
|
|
<td>This bit enables the IO Master.<br><br>
|
|
DIS = 0x0 - Disable the IO Master.<br>
|
|
EN = 0x1 - Enable the IO Master.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>30:15</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>14</td>
|
|
<td>RDFCPOL</td>
|
|
<td>RW</td>
|
|
<td>This bit selects the read flow control signal polarity.<br><br>
|
|
HIGH = 0x0 - Flow control signal high creates flow control.<br>
|
|
LOW = 0x1 - Flow control signal low creates flow control.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>13</td>
|
|
<td>WTFCPOL</td>
|
|
<td>RW</td>
|
|
<td>This bit selects the write flow control signal polarity.<br><br>
|
|
HIGH = 0x0 - Flow control signal high creates flow control.<br>
|
|
LOW = 0x1 - Flow control signal low creates flow control.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>12</td>
|
|
<td>WTFCIRQ</td>
|
|
<td>RW</td>
|
|
<td>This bit selects the write mode flow control signal.<br><br>
|
|
MISO = 0x0 - MISO is used as the write mode flow control signal.<br>
|
|
IRQ = 0x1 - IRQ is used as the write mode flow control signal.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>11</td>
|
|
<td>FCDEL</td>
|
|
<td>RW</td>
|
|
<td>This bit enables a pause cycle in flow control mode.<br><br>
|
|
DIS = 0x0 - No pause cycle is inserted.<br>
|
|
EN = 0x1 - One pause cycle is inserted.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10</td>
|
|
<td>MOSIINV</td>
|
|
<td>RW</td>
|
|
<td>This bit invewrts MOSI when flow control is enabled.<br><br>
|
|
NORMAL = 0x0 - MOSI is set to 0 in read mode and 1 in write mode.<br>
|
|
INVERT = 0x1 - MOSI is set to 1 in read mode and 0 in write mode.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9</td>
|
|
<td>RDFC</td>
|
|
<td>RW</td>
|
|
<td>This bit enables read mode flow control.<br><br>
|
|
DIS = 0x0 - Read mode flow control disabled.<br>
|
|
EN = 0x1 - Read mode flow control enabled.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8</td>
|
|
<td>WTFC</td>
|
|
<td>RW</td>
|
|
<td>This bit enables write mode flow control.<br><br>
|
|
DIS = 0x0 - Write mode flow control disabled.<br>
|
|
EN = 0x1 - Write mode flow control enabled.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7:6</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5:4</td>
|
|
<td>STARTRD</td>
|
|
<td>RW</td>
|
|
<td>This bit selects the preread timing.<br><br>
|
|
PRERD0 = 0x0 - 0 read delay cycles.<br>
|
|
PRERD1 = 0x1 - 1 read delay cycles.<br>
|
|
PRERD2 = 0x2 - 2 read delay cycles.<br>
|
|
PRERD3 = 0x3 - 3 read delay cycles.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>FULLDUP</td>
|
|
<td>RW</td>
|
|
<td>This bit selects full duplex mode.<br><br>
|
|
NORMAL = 0x0 - 128 byte FIFO in half duplex mode.<br>
|
|
FULLDUP = 0x1 - 64 byte FIFO in full duplex mode.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>SPHA</td>
|
|
<td>RW</td>
|
|
<td>This bit selects SPI phase.<br><br>
|
|
SAMPLE_LEADING_EDGE = 0x0 - Sample on the leading (first) clock edge.<br>
|
|
SAMPLE_TRAILING_EDGE = 0x1 - Sample on the trailing (second) clock edge.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>SPOL</td>
|
|
<td>RW</td>
|
|
<td>This bit selects SPI polarity.<br><br>
|
|
CLK_BASE_0 = 0x0 - The base value of the clock is 0.<br>
|
|
CLK_BASE_1 = 0x1 - The base value of the clock is 1.</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>IFCSEL</td>
|
|
<td>RW</td>
|
|
<td>This bit selects the I/O interface.<br><br>
|
|
I2C = 0x0 - Selects I2C interface for the I/O Master.<br>
|
|
SPI = 0x1 - Selects SPI interface for the I/O Master.</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTEN" class="panel-title">INTEN - IO Master Interrupts: Enable</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009200</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Set bits in this register to allow this module to generate the corresponding interrupt.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="21">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ARB
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">STOP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">START
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ICMD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IACC
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">WTLEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">NAK
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FOVFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FUNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">CMDCMP
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:11</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10</td>
|
|
<td>ARB</td>
|
|
<td>RW</td>
|
|
<td>This is the arbitration loss interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9</td>
|
|
<td>STOP</td>
|
|
<td>RW</td>
|
|
<td>This is the STOP command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8</td>
|
|
<td>START</td>
|
|
<td>RW</td>
|
|
<td>This is the START command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7</td>
|
|
<td>ICMD</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>6</td>
|
|
<td>IACC</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal FIFO access interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>WTLEN</td>
|
|
<td>RW</td>
|
|
<td>This is the write length mismatch interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>NAK</td>
|
|
<td>RW</td>
|
|
<td>This is the I2C NAK interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>FOVFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Read FIFO Overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>FUNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Write FIFO Underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO Threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>CMDCMP</td>
|
|
<td>RW</td>
|
|
<td>This is the Command Complete interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTSTAT" class="panel-title">INTSTAT - IO Master Interrupts: Status</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009204</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Read bits from this register to discover the cause of a recent interrupt.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="21">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ARB
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">STOP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">START
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ICMD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IACC
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">WTLEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">NAK
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FOVFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FUNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">CMDCMP
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:11</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10</td>
|
|
<td>ARB</td>
|
|
<td>RW</td>
|
|
<td>This is the arbitration loss interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9</td>
|
|
<td>STOP</td>
|
|
<td>RW</td>
|
|
<td>This is the STOP command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8</td>
|
|
<td>START</td>
|
|
<td>RW</td>
|
|
<td>This is the START command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7</td>
|
|
<td>ICMD</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>6</td>
|
|
<td>IACC</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal FIFO access interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>WTLEN</td>
|
|
<td>RW</td>
|
|
<td>This is the write length mismatch interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>NAK</td>
|
|
<td>RW</td>
|
|
<td>This is the I2C NAK interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>FOVFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Read FIFO Overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>FUNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Write FIFO Underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO Threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>CMDCMP</td>
|
|
<td>RW</td>
|
|
<td>This is the Command Complete interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTCLR" class="panel-title">INTCLR - IO Master Interrupts: Clear</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004208</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005208</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006208</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007208</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008208</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009208</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Write a 1 to a bit in this register to clear the interrupt status associated with that bit.</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="21">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ARB
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">STOP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">START
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ICMD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IACC
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">WTLEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">NAK
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FOVFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FUNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">CMDCMP
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:11</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10</td>
|
|
<td>ARB</td>
|
|
<td>RW</td>
|
|
<td>This is the arbitration loss interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9</td>
|
|
<td>STOP</td>
|
|
<td>RW</td>
|
|
<td>This is the STOP command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8</td>
|
|
<td>START</td>
|
|
<td>RW</td>
|
|
<td>This is the START command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7</td>
|
|
<td>ICMD</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>6</td>
|
|
<td>IACC</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal FIFO access interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>WTLEN</td>
|
|
<td>RW</td>
|
|
<td>This is the write length mismatch interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>NAK</td>
|
|
<td>RW</td>
|
|
<td>This is the I2C NAK interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>FOVFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Read FIFO Overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>FUNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Write FIFO Underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO Threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>CMDCMP</td>
|
|
<td>RW</td>
|
|
<td>This is the Command Complete interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="INTSET" class="panel-title">INTSET - IO Master Interrupts: Set</h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000420C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000520C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000620C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000720C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000820C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x5000920C</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p>Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).</p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="21">RSVD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ARB
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">STOP
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">START
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">ICMD
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">IACC
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">WTLEN
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">NAK
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FOVFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">FUNDFL
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">THR
|
|
<br>0x0</td>
|
|
|
|
<td align="center" colspan="1">CMDCMP
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:11</td>
|
|
<td>RSVD</td>
|
|
<td>RO</td>
|
|
<td>RESERVED<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>10</td>
|
|
<td>ARB</td>
|
|
<td>RW</td>
|
|
<td>This is the arbitration loss interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>9</td>
|
|
<td>STOP</td>
|
|
<td>RW</td>
|
|
<td>This is the STOP command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>8</td>
|
|
<td>START</td>
|
|
<td>RW</td>
|
|
<td>This is the START command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>7</td>
|
|
<td>ICMD</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal command interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>6</td>
|
|
<td>IACC</td>
|
|
<td>RW</td>
|
|
<td>This is the illegal FIFO access interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>5</td>
|
|
<td>WTLEN</td>
|
|
<td>RW</td>
|
|
<td>This is the write length mismatch interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>4</td>
|
|
<td>NAK</td>
|
|
<td>RW</td>
|
|
<td>This is the I2C NAK interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>3</td>
|
|
<td>FOVFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Read FIFO Overflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>2</td>
|
|
<td>FUNDFL</td>
|
|
<td>RW</td>
|
|
<td>This is the Write FIFO Underflow interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>1</td>
|
|
<td>THR</td>
|
|
<td>RW</td>
|
|
<td>This is the FIFO Threshold interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td>0</td>
|
|
<td>CMDCMP</td>
|
|
<td>RW</td>
|
|
<td>This is the Command Complete interrupt.<br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DBG0" class="panel-title">DBG0 - </h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004300</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005300</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006300</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007300</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008300</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009300</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p></p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">DBG0
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>DBG0</td>
|
|
<td>RO</td>
|
|
<td><br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
<div class="panel panel-default">
|
|
<div class="panel-heading">
|
|
<h3 id="DBG1" class="panel-title">DBG1 - </h3>
|
|
</div>
|
|
<div class="panel-body">
|
|
<h3>Address:</h3>
|
|
<table style="margin:10px">
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 0 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50004304</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 1 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50005304</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 2 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50006304</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 3 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50007304</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 4 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50008304</span>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr id="row_0_0_">
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">Instance 5 Address:</span>
|
|
</td>
|
|
<td class="entry">
|
|
<span style="width:32px;display:inline-block;"> </span>
|
|
<span class="h5">0x50009304</span>
|
|
</td>
|
|
</tr>
|
|
|
|
</table>
|
|
<h3>Description:</h3>
|
|
<p></p>
|
|
<h3>Example Macro Usage:</h3>
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
|
// All macro-based register writes follow the same basic format. For
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
|
// multi-instance macros, you will need to specify the instance number using
|
|
// the AM_REGn macro format.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
|
//
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
|
//
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
|
//
|
|
// For example, the following three lines of code are equivalent methods of
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
|
//</span>
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
|
<h3>Register Fields:</h3>
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th>0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td align="center" colspan="32">DBG1
|
|
<br>0x0</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
|
<thead>
|
|
<tr>
|
|
<th>Bits</th>
|
|
<th>Name</th>
|
|
<th>RW</th>
|
|
<th>Description</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>31:0</td>
|
|
<td>DBG1</td>
|
|
<td>RO</td>
|
|
<td><br><br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
</div>
|
|
</div>
|
|
|
|
</body>
|
|
|
|
<hr size="1">
|
|
<body>
|
|
<div id="footer" align="right">
|
|
<small>
|
|
AmbiqSuite Register Documentation
|
|
<a href="http://www.ambiqmicro.com">
|
|
<img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>   Copyright © 2014  <br />
|
|
This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.  <br/>
|
|
</small>
|
|
</div>
|
|
</body>
|
|
</html>
|
|
|