210 lines
7.2 KiB
Plaintext
210 lines
7.2 KiB
Plaintext
/*********************************************************************
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* (c) SEGGER Microcontroller GmbH & Co. KG *
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* The Embedded Experts *
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* www.segger.com *
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**********************************************************************
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-------------------------- END-OF-HEADER -----------------------------
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File : AMA3B2KK-KBR.JLinkScript
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Purpose : Handle reset for AmbiqMicro AMA3B2KK series of MCUs
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Literature:
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[1] J-Link User Guide (UM08001_JLink.pdf)
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Additional information:
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For more information about public functions that can be implemented
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in order to customize J-Link actions, please refer to [1]
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*********************************************************************/
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/*********************************************************************
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*
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* ResetTarget()
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* Reset and wait until CPU is halted.
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*********************************************************************/
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void ResetTarget(void) {
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// Register Address Values
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int AIRCR_ADDR ;
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int DHCSR_ADDR ;
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int DEMCR_ADDR ;
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int AHBAP_REG_CTRL ;
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int AHBAP_REG_ADDR ;
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int AHBAP_REG_DATA ;
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int DP_REG_SELECT ;
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int MCUCTRL_SCRATCH0 ;
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int MCUCTRL_BOOTLDR ;
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int JDEC_PID ;
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// Internal Variables
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int Ctrl;
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int demcr;
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int scratch0;
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int bootldr;
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int jdecpid;
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int v;
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int Tries;
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int Done;
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int nonsecure;
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int timeout;
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// Initialize the Register Address and Internal vars.
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AIRCR_ADDR = 0xE000ED0C;
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DHCSR_ADDR = 0xE000EDF0;
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DEMCR_ADDR = 0xE000EDFC;
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MCUCTRL_SCRATCH0 = 0x400401B0;
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MCUCTRL_BOOTLDR = 0x400401A0;
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JDEC_PID = 0xF0000FE0;
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AHBAP_REG_CTRL = 0;
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AHBAP_REG_ADDR = 1;
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AHBAP_REG_DATA = 3;
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DP_REG_SELECT = 2;
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nonsecure = 1;
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timeout = 0;
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// Check global variable to detect whether debugger is using JTAG or SWO and configure JTAG is necessary.
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if (MAIN_ActiveTIF == JLINK_TIF_JTAG) {
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JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
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} else {
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JLINK_CORESIGHT_Configure(""); // For SWD, no special setup is needed, just output the switching sequence
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}
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// Power-up complete DAP
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Ctrl = 0
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| (1 << 30) // System power-up
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| (1 << 28) // Debug popwer-up
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| (1 << 5) // Clear STICKYERR
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;
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JLINK_CORESIGHT_WriteDP(1, Ctrl);
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// Select AHB-AP and configure it
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JLINK_CORESIGHT_WriteDP(DP_REG_SELECT, (0 << 4) | (0 << 24)); // Select AP[0] (AHB-AP) bank 0
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_CTRL, (1 << 4) | (1 << 24) | (1 << 25) | (1 << 29) | (2 << 0)); // Auto-increment, Private access, HMASTER = DEBUG, Access size: word
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// Enable Debug and Halt the MCU Core.
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
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v = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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v &= 0x3F; // Mask out "debug" bits
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v |= 0xA05F0000; // Debug key to make a write to the DHCSR a valid one
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v |= 0x00000002; // Halt the core
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v |= 0x00000001; // Enable debug functionalities of the core
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, v);
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// Read the Peripheral ID.
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, JDEC_PID);
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jdecpid = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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Report1("JDEC PID ", jdecpid);
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// Is this Apollo3-Blue or Apollo3-Blue-Plus MCU?
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if ((jdecpid & 0xF0) == 0xC0)
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{
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// Apollo3-Blue or Apollo3-Blue-Plus
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Report("Ambiq Apollo3-Blue ResetTarget");
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// Read MCUCTRL_BOOTLDR to determine if it is a secure or non-secure chip
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, MCUCTRL_BOOTLDR);
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bootldr = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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Report1("Bootldr = ", bootldr);
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if ((bootldr & 0x0C000000) == 0x04000000)
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{
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Report("Secure Part.");
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nonsecure = 0;
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}
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}
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if (nonsecure == 0)
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{
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// Set MCUCTRL Scratch0, indicating that the Bootloader needs to run, then halt when it is finished.
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Report("Secure Chip. Bootloader needs to run which will then halt when finish.");
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, MCUCTRL_SCRATCH0);
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scratch0 = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, MCUCTRL_SCRATCH0);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, scratch0 | 0x1);
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} else
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{
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// Set VC_CORERESET in the DEMCR.
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Report("Non-Secure Chip. Following normal Reset procedure.");
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
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demcr = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, demcr | 0x00000001);
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}
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// Set the SYSRESETREQ bit in the AIRCR.
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// This will request the MCU Core to reset.
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, AIRCR_ADDR);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x05FA0004);
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// Wait until CPU is halted
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Tries = 0;
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Done = 0;
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do {
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
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v = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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// Check if CPU is halted. If so, we are done
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if (Tries >= 25) // wait for up to 2.5 seconds.
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{
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Report("Apollo3 (connect): Timeout while waiting for CPU to halt after reset. Manually halting CPU.");
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Done = 1;
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timeout = 1;
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}
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else if ((v != 0xFFFFFFFF) && (v & 0x00020000)) // Bit 17: S_HALT in the DHCSR.
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{
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Report1("CPU halted after reset. Num Tries = ", Tries);
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Done = 1;
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}
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Tries = Tries + 1;
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SYS_Sleep(100); // Go to sleep for 100 msec.
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} while(Done == 0);
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// Let's try one more time using regular reset method
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if ((timeout == 1) && (nonsecure == 0))
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{
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// Set VC_CORERESET
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Report("Secure Part Reset timed out. Reverting to normal Reset procedure.");
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
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demcr = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, demcr | 0x00000001);
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// SYSRESETREQ
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, AIRCR_ADDR);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x05FA0004);
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//
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// Wait until CPU is halted
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//
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Tries = 0;
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Done = 0;
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do {
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
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v = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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// Check if CPU is halted. If so, we are done
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if (Tries >= 25) // wait for up to 2.5 seconds.
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{
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Report("Apollo3 (connect): Timeout while waiting for CPU to halt after reset. Manually halting CPU.");
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Done = 1;
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timeout = 1;
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}
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else if ((v != 0xFFFFFFFF) && (v & 0x00020000)) // Bit 17: S_HALT in the DHCSR.
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{
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Report1("CPU halted after reset. Num Tries = ", Tries);
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Done = 1;
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}
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Tries = Tries + 1;
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SYS_Sleep(100); // Go to sleep for 100 msec.
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} while(Done == 0);
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}
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// If non-secure part,...
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if (nonsecure == 1)
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{
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// Clear VC_CORERESET in the DEMCR.
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
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demcr = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
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JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, (demcr & 0xFFFFFFFE));
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}
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}
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