27302 lines
1.0 MiB
27302 lines
1.0 MiB
<?xml version="1.0" encoding="utf-8"?>
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<!-- File naming: <vendor>_<part/series name>.svd -->
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<!--
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Copyright (C) 2012-2014 ARM Limited. All rights reserved.
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Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
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This is a description of a none-existent and incomplete device
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for demonstration purposes only.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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-->
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>Ambiq Micro</vendor> <!-- device vendor name -->
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<vendorID>Ambiq</vendorID> <!-- device vendor short name -->
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<name>apollo2</name> <!-- name of part-->
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<series>Apollo</series> <!-- device series the device belongs to -->
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<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
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<description>Ultra-Low power ARM Cortex-M4 MCU from Ambiq Micro</description>
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<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
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Copyright (c) 2019, Ambiq Micro\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\nthis list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\nnotice, this list of conditions and the following disclaimer in the\ndocumentation and/or other materials provided with the distribution.\n\n3. Neither the name of the copyright holder nor the names of its\ncontributors may be used to endorse or promote products derived from this\nsoftware without specific prior written permission.\n\nThird party software included in this distribution is subject to the\nadditional license terms as defined in the /docs/licenses directory.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n
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</licenseText>
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<cpu> <!-- details about the cpu embedded in the device -->
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<name>CM4</name>
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<revision>r1p0</revision>
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<endian>little</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<nvicPrioBits>3</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
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<width>32</width> <!-- bus width is 32 bits -->
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<!-- default settings implicitly inherited by subsequent sections -->
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<size>32</size> <!-- this is the default size (number of bits) of all peripherals
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and register that do not define "size" themselves -->
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<access>read-write</access> <!-- default access permission for all subsequent registers -->
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<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
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<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
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<peripherals>
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<peripheral>
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<name>ADC</name>
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<version>1.0</version>
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<description>Analog Digital Converter Control</description>
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<!-- <groupName>GROUP_ADC</groupName> -->
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<baseAddress>0x50010000</baseAddress>
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<size>32</size>
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<access>read-write</access>
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<addressBlock>
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<offset>0</offset>
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<size>0x00000210</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>ADC</name>
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<value>16</value>
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</interrupt>
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<registers>
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<register>
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<name>CFG</name>
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<description>Configuration Register</description>
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<addressOffset>0x00000000</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x030F031D</resetMask>
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<fields>
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<field>
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<name>CLKSEL</name>
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<description>Select the source and frequency for the ADC clock. All values not enumerated below are undefined.</description>
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<bitRange>[25:24]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>OFF</name>
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<description>Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>HFRC</name>
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<description>HFRC Core Clock Frequency</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>HFRC_DIV2</name>
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<description>HFRC Core Clock / 2</description>
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<value>2</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>TRIGPOL</name>
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<description>This bit selects the ADC trigger polarity for external off chip triggers.</description>
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<bitRange>[19:19]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>RISING_EDGE</name>
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<description>Trigger on rising edge.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGE</name>
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<description>Trigger on falling edge.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>TRIGSEL</name>
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<description>Select the ADC trigger source.</description>
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<bitRange>[18:16]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>EXT0</name>
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<description>Off chip External Trigger0 (ADC_ET0)</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EXT1</name>
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<description>Off chip External Trigger1 (ADC_ET1)</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EXT2</name>
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<description>Off chip External Trigger2 (ADC_ET2)</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EXT3</name>
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<description>Off chip External Trigger3 (ADC_ET3)</description>
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<value>3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>VCOMP</name>
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<description>Voltage Comparator Output</description>
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<value>4</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SWT</name>
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<description>Software Trigger</description>
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<value>7</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>REFSEL</name>
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<description>Select the ADC reference voltage.</description>
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<bitRange>[9:8]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>INT2P0</name>
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<description>Internal 2.0V Bandgap Reference Voltage</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>INT1P5</name>
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<description>Internal 1.5V Bandgap Reference Voltage</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EXT2P0</name>
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<description>Off Chip 2.0V Reference</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EXT1P5</name>
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<description>Off Chip 1.5V Reference</description>
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<value>3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>CKMODE</name>
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<description>Clock mode register</description>
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<bitRange>[4:4]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>LPCKMODE</name>
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<description>Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>LLCKMODE</name>
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<description>Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>LPMODE</name>
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<description>Select power mode to enter between active scans.</description>
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<bitRange>[3:3]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>MODE0</name>
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<description>Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>MODE1</name>
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<description>Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>RPTEN</name>
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<description>This bit enables Repeating Scan Mode.</description>
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<bitRange>[2:2]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>SINGLE_SCAN</name>
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<description>In Single Scan Mode, the ADC will complete a single scan upon each trigger event.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>REPEATING_SCAN</name>
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<description>In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>ADCEN</name>
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<description>This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'.</description>
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<bitRange>[0:0]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>DIS</name>
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<description>Disable the ADC module.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EN</name>
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<description>Enable the ADC module.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>STAT</name>
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<description>ADC Power Status</description>
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<addressOffset>0x00000004</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x00000001</resetMask>
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<fields>
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<field>
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<name>PWDSTAT</name>
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<description>Indicates the power-status of the ADC.</description>
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<bitRange>[0:0]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>ON</name>
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<description>Powered on.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>POWERED_DOWN</name>
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<description>ADC Low Power Mode 1.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>SWT</name>
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<description>Software trigger</description>
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<addressOffset>0x00000008</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x000000FF</resetMask>
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<fields>
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<field>
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<name>SWT</name>
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<description>Writing 0x37 to this register generates a software trigger.</description>
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<bitRange>[7:0]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>GEN_SW_TRIGGER</name>
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<description>Writing this value generates a software trigger.</description>
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<value>55</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>SL0CFG</name>
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<description>Slot 0 Configuration Register</description>
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<addressOffset>0x0000000C</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x07030F03</resetMask>
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<fields>
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<field>
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<name>ADSEL0</name>
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<description>Select the number of measurements to average in the accumulate divide module for this slot.</description>
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<bitRange>[26:24]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>AVG_1_MSRMT</name>
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<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>AVG_2_MSRMTS</name>
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<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>AVG_4_MSRMTS</name>
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<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>AVG_8_MSRMT</name>
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<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
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<value>3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>AVG_16_MSRMTS</name>
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<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
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<value>4</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>AVG_32_MSRMTS</name>
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<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
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<value>5</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>AVG_64_MSRMTS</name>
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<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
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<value>6</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>AVG_128_MSRMTS</name>
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<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
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<value>7</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>PRMODE0</name>
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<description>Set the Precision Mode For Slot.</description>
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<bitRange>[17:16]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>P14B</name>
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<description>14-bit precision mode</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>P12B</name>
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<description>12-bit precision mode</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
|
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<name>P10B</name>
|
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<description>10-bit precision mode</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
|
|
<name>P8B</name>
|
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<description>8-bit precision mode</description>
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<value>3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>CHSEL0</name>
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<description>Select one of the 14 channel inputs for this slot.</description>
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<bitRange>[11:8]</bitRange>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
|
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<name>SE0</name>
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<description>single ended external GPIO connection to pad16.</description>
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<value>0</value>
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</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
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<description>single ended external GPIO connection to pad29.</description>
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<value>1</value>
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</enumeratedValue>
|
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<enumeratedValue>
|
|
<name>SE2</name>
|
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<description>single ended external GPIO connection to pad11.</description>
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<value>2</value>
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</enumeratedValue>
|
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<enumeratedValue>
|
|
<name>SE3</name>
|
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<description>single ended external GPIO connection to pad31.</description>
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<value>3</value>
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</enumeratedValue>
|
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<enumeratedValue>
|
|
<name>SE4</name>
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<description>single ended external GPIO connection to pad32.</description>
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<value>4</value>
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</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
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<description>single ended external GPIO connection to pad33.</description>
|
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<value>5</value>
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</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN0</name>
|
|
<description>This bit enables the window compare function for slot 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN0</name>
|
|
<description>This bit enables slot 0 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 0 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SL1CFG</name>
|
|
<description>Slot 1 Configuration Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07030F03</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADSEL1</name>
|
|
<description>Select the number of measurements to average in the accumulate divide module for this slot.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVG_1_MSRMT</name>
|
|
<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_2_MSRMTS</name>
|
|
<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_4_MSRMTS</name>
|
|
<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_8_MSRMT</name>
|
|
<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_16_MSRMTS</name>
|
|
<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_32_MSRMTS</name>
|
|
<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_64_MSRMTS</name>
|
|
<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_128_MSRMTS</name>
|
|
<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRMODE1</name>
|
|
<description>Set the Precision Mode For Slot.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P14B</name>
|
|
<description>14-bit precision mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P12B</name>
|
|
<description>12-bit precision mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10B</name>
|
|
<description>10-bit precision mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8B</name>
|
|
<description>8-bit precision mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL1</name>
|
|
<description>Select one of the 14 channel inputs for this slot.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>single ended external GPIO connection to pad16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
|
|
<description>single ended external GPIO connection to pad29.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2</name>
|
|
<description>single ended external GPIO connection to pad11.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE3</name>
|
|
<description>single ended external GPIO connection to pad31.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4</name>
|
|
<description>single ended external GPIO connection to pad32.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
|
<description>single ended external GPIO connection to pad33.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN1</name>
|
|
<description>This bit enables the window compare function for slot 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN1</name>
|
|
<description>This bit enables slot 1 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 1 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SL2CFG</name>
|
|
<description>Slot 2 Configuration Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07030F03</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADSEL2</name>
|
|
<description>Select the number of measurements to average in the accumulate divide module for this slot.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVG_1_MSRMT</name>
|
|
<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_2_MSRMTS</name>
|
|
<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_4_MSRMTS</name>
|
|
<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_8_MSRMT</name>
|
|
<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_16_MSRMTS</name>
|
|
<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_32_MSRMTS</name>
|
|
<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_64_MSRMTS</name>
|
|
<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_128_MSRMTS</name>
|
|
<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRMODE2</name>
|
|
<description>Set the Precision Mode For Slot.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P14B</name>
|
|
<description>14-bit precision mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P12B</name>
|
|
<description>12-bit precision mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10B</name>
|
|
<description>10-bit precision mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8B</name>
|
|
<description>8-bit precision mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL2</name>
|
|
<description>Select one of the 14 channel inputs for this slot.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>single ended external GPIO connection to pad16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
|
|
<description>single ended external GPIO connection to pad29.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2</name>
|
|
<description>single ended external GPIO connection to pad11.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE3</name>
|
|
<description>single ended external GPIO connection to pad31.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4</name>
|
|
<description>single ended external GPIO connection to pad32.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
|
<description>single ended external GPIO connection to pad33.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN2</name>
|
|
<description>This bit enables the window compare function for slot 2.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN2</name>
|
|
<description>This bit enables slot 2 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 2 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SL3CFG</name>
|
|
<description>Slot 3 Configuration Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07030F03</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADSEL3</name>
|
|
<description>Select the number of measurements to average in the accumulate divide module for this slot.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVG_1_MSRMT</name>
|
|
<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_2_MSRMTS</name>
|
|
<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_4_MSRMTS</name>
|
|
<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_8_MSRMT</name>
|
|
<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_16_MSRMTS</name>
|
|
<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_32_MSRMTS</name>
|
|
<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_64_MSRMTS</name>
|
|
<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_128_MSRMTS</name>
|
|
<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRMODE3</name>
|
|
<description>Set the Precision Mode For Slot.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P14B</name>
|
|
<description>14-bit precision mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P12B</name>
|
|
<description>12-bit precision mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10B</name>
|
|
<description>10-bit precision mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8B</name>
|
|
<description>8-bit precision mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL3</name>
|
|
<description>Select one of the 14 channel inputs for this slot.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>single ended external GPIO connection to pad16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
|
|
<description>single ended external GPIO connection to pad29.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2</name>
|
|
<description>single ended external GPIO connection to pad11.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE3</name>
|
|
<description>single ended external GPIO connection to pad31.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4</name>
|
|
<description>single ended external GPIO connection to pad32.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
|
<description>single ended external GPIO connection to pad33.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN3</name>
|
|
<description>This bit enables the window compare function for slot 3.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN3</name>
|
|
<description>This bit enables slot 3 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 3 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SL4CFG</name>
|
|
<description>Slot 4 Configuration Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07030F03</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADSEL4</name>
|
|
<description>Select the number of measurements to average in the accumulate divide module for this slot.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVG_1_MSRMT</name>
|
|
<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_2_MSRMTS</name>
|
|
<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_4_MSRMTS</name>
|
|
<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_8_MSRMT</name>
|
|
<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_16_MSRMTS</name>
|
|
<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_32_MSRMTS</name>
|
|
<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_64_MSRMTS</name>
|
|
<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_128_MSRMTS</name>
|
|
<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRMODE4</name>
|
|
<description>Set the Precision Mode For Slot.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P14B</name>
|
|
<description>14-bit precision mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P12B</name>
|
|
<description>12-bit precision mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10B</name>
|
|
<description>10-bit precision mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8B</name>
|
|
<description>8-bit precision mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL4</name>
|
|
<description>Select one of the 14 channel inputs for this slot.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>single ended external GPIO connection to pad16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
|
|
<description>single ended external GPIO connection to pad29.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2</name>
|
|
<description>single ended external GPIO connection to pad11.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE3</name>
|
|
<description>single ended external GPIO connection to pad31.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4</name>
|
|
<description>single ended external GPIO connection to pad32.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
|
<description>single ended external GPIO connection to pad33.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN4</name>
|
|
<description>This bit enables the window compare function for slot 4.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN4</name>
|
|
<description>This bit enables slot 4 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 4 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SL5CFG</name>
|
|
<description>Slot 5 Configuration Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07030F03</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADSEL5</name>
|
|
<description>Select number of measurements to average in the accumulate divide module for this slot.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVG_1_MSRMT</name>
|
|
<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_2_MSRMTS</name>
|
|
<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_4_MSRMTS</name>
|
|
<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_8_MSRMT</name>
|
|
<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_16_MSRMTS</name>
|
|
<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_32_MSRMTS</name>
|
|
<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_64_MSRMTS</name>
|
|
<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_128_MSRMTS</name>
|
|
<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRMODE5</name>
|
|
<description>Set the Precision Mode For Slot.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P14B</name>
|
|
<description>14-bit precision mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P12B</name>
|
|
<description>12-bit precision mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10B</name>
|
|
<description>10-bit precision mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8B</name>
|
|
<description>8-bit precision mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL5</name>
|
|
<description>Select one of the 14 channel inputs for this slot.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>single ended external GPIO connection to pad16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
|
|
<description>single ended external GPIO connection to pad29.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2</name>
|
|
<description>single ended external GPIO connection to pad11.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE3</name>
|
|
<description>single ended external GPIO connection to pad31.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4</name>
|
|
<description>single ended external GPIO connection to pad32.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
|
<description>single ended external GPIO connection to pad33.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN5</name>
|
|
<description>This bit enables the window compare function for slot 5.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN5</name>
|
|
<description>This bit enables slot 5 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 5 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SL6CFG</name>
|
|
<description>Slot 6 Configuration Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07030F03</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADSEL6</name>
|
|
<description>Select the number of measurements to average in the accumulate divide module for this slot.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVG_1_MSRMT</name>
|
|
<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_2_MSRMTS</name>
|
|
<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_4_MSRMTS</name>
|
|
<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_8_MSRMT</name>
|
|
<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_16_MSRMTS</name>
|
|
<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_32_MSRMTS</name>
|
|
<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_64_MSRMTS</name>
|
|
<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_128_MSRMTS</name>
|
|
<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRMODE6</name>
|
|
<description>Set the Precision Mode For Slot.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P14B</name>
|
|
<description>14-bit precision mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P12B</name>
|
|
<description>12-bit precision mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10B</name>
|
|
<description>10-bit precision mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8B</name>
|
|
<description>8-bit precision mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL6</name>
|
|
<description>Select one of the 14 channel inputs for this slot.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>single ended external GPIO connection to pad16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
|
|
<description>single ended external GPIO connection to pad29.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2</name>
|
|
<description>single ended external GPIO connection to pad11.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE3</name>
|
|
<description>single ended external GPIO connection to pad31.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4</name>
|
|
<description>single ended external GPIO connection to pad32.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
|
<description>single ended external GPIO connection to pad33.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN6</name>
|
|
<description>This bit enables the window compare function for slot 6.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN6</name>
|
|
<description>This bit enables slot 6 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 6 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SL7CFG</name>
|
|
<description>Slot 7 Configuration Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07030F03</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADSEL7</name>
|
|
<description>Select the number of measurements to average in the accumulate divide module for this slot.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVG_1_MSRMT</name>
|
|
<description>Average in 1 measurement in the accumulate divide module for this slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_2_MSRMTS</name>
|
|
<description>Average in 2 measurements in the accumulate divide module for this slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_4_MSRMTS</name>
|
|
<description>Average in 4 measurements in the accumulate divide module for this slot.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_8_MSRMT</name>
|
|
<description>Average in 8 measurements in the accumulate divide module for this slot.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_16_MSRMTS</name>
|
|
<description>Average in 16 measurements in the accumulate divide module for this slot.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_32_MSRMTS</name>
|
|
<description>Average in 32 measurements in the accumulate divide module for this slot.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_64_MSRMTS</name>
|
|
<description>Average in 64 measurements in the accumulate divide module for this slot.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVG_128_MSRMTS</name>
|
|
<description>Average in 128 measurements in the accumulate divide module for this slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRMODE7</name>
|
|
<description>Set the Precision Mode For Slot.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P14B</name>
|
|
<description>14-bit precision mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P12B</name>
|
|
<description>12-bit precision mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P10B</name>
|
|
<description>10-bit precision mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P8B</name>
|
|
<description>8-bit precision mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL7</name>
|
|
<description>Select one of the 14 channel inputs for this slot.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>single ended external GPIO connection to pad16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1</name>
|
|
<description>single ended external GPIO connection to pad29.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2</name>
|
|
<description>single ended external GPIO connection to pad11.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE3</name>
|
|
<description>single ended external GPIO connection to pad31.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4</name>
|
|
<description>single ended external GPIO connection to pad32.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE5</name>
|
|
<description>single ended external GPIO connection to pad33.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE6</name>
|
|
<description>single ended external GPIO connection to pad34.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE7</name>
|
|
<description>single ended external GPIO connection to pad35.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE8</name>
|
|
<description>single ended external GPIO connection to pad13.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE9</name>
|
|
<description>single ended external GPIO connection to pad12.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF0</name>
|
|
<description>differential external GPIO connections to pad12(N) and pad13(P).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DF1</name>
|
|
<description>differential external GPIO connections to pad15(N) and pad14(P).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>internal temperature sensor.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BATT</name>
|
|
<description>internal voltage divide-by-3 connection.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>Input VSS</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEN7</name>
|
|
<description>This bit enables the window compare function for slot 7.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEN</name>
|
|
<description>Enable the window compare for slot 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEN7</name>
|
|
<description>This bit enables slot 7 for ADC conversions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEN</name>
|
|
<description>Enable slot 7 for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WULIM</name>
|
|
<description>Window Comparator Upper Limits Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ULIM</name>
|
|
<description>Sets the upper limit for the wondow comparator.</description>
|
|
<bitRange>[19:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WLLIM</name>
|
|
<description>Window Comparator Lower Limits Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>LLIM</name>
|
|
<description>Sets the lower limit for the wondow comparator.</description>
|
|
<bitRange>[19:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<description>FIFO Data and Valid Count Register</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>RSVD</name>
|
|
<description>RESERVED.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLOTNUM</name>
|
|
<description>Slot number associated with this FIFO data.</description>
|
|
<bitRange>[30:28]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of valid entries in the ADC FIFO.</description>
|
|
<bitRange>[27:20]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Oldest data in the FIFO.</description>
|
|
<bitRange>[19:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>ADC Interrupt registers: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WCINC</name>
|
|
<description>Window comparator voltage incursion interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCINCINT</name>
|
|
<description>Window comparitor voltage incursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEXC</name>
|
|
<description>Window comparator voltage excursion interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEXCINT</name>
|
|
<description>Window comparitor voltage excursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR2</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFOFULLINT</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR1</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFO75INT</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCNCMP</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCNCMPINT</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNVCMP</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CNVCMPINT</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>ADC Interrupt registers: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WCINC</name>
|
|
<description>Window comparator voltage incursion interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCINCINT</name>
|
|
<description>Window comparitor voltage incursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEXC</name>
|
|
<description>Window comparator voltage excursion interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEXCINT</name>
|
|
<description>Window comparitor voltage excursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR2</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFOFULLINT</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR1</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFO75INT</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCNCMP</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCNCMPINT</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNVCMP</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CNVCMPINT</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>ADC Interrupt registers: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WCINC</name>
|
|
<description>Window comparator voltage incursion interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCINCINT</name>
|
|
<description>Window comparitor voltage incursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEXC</name>
|
|
<description>Window comparator voltage excursion interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEXCINT</name>
|
|
<description>Window comparitor voltage excursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR2</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFOFULLINT</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR1</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFO75INT</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCNCMP</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCNCMPINT</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNVCMP</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CNVCMPINT</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>ADC Interrupt registers: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WCINC</name>
|
|
<description>Window comparator voltage incursion interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCINCINT</name>
|
|
<description>Window comparitor voltage incursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCEXC</name>
|
|
<description>Window comparator voltage excursion interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCEXCINT</name>
|
|
<description>Window comparitor voltage excursion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR2</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFOFULLINT</name>
|
|
<description>FIFO 100 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFOOVR1</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIFO75INT</name>
|
|
<description>FIFO 75 percent full interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCNCMP</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCNCMPINT</name>
|
|
<description>ADC scan complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNVCMP</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CNVCMPINT</name>
|
|
<description>ADC conversion complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>CACHECTRL</name>
|
|
<version>1.0</version>
|
|
<description>Flash Cache Controller</description>
|
|
<!-- <groupName>GROUP_CACHECTRL</groupName> -->
|
|
<baseAddress>0x40018000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000240</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CACHECFG</name>
|
|
<description>Flash Cache Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00166C50</resetValue>
|
|
<resetMask>0x011FFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_MONITOR</name>
|
|
<description>Enable Cache Monitoring Stats. Only enable this for debug/performance analysis since it will consume additional power. See IMON/DMON registers for data.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DATA_CLKGATE</name>
|
|
<description>Enable clock gating of entire cache data array subsystem. This should be enabled for normal operation.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SMDLY</name>
|
|
<description>Unused. Should be left at default value.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Unused. Should be left at default value.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CACHE_LS</name>
|
|
<description>Enable LS (light sleep) of cache RAMs. This should not be enabled for normal operation. When this bit is set, the cache's RAMS will be put into light sleep mode while inactive. NOTE: if the cache is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CACHE_CLKGATE</name>
|
|
<description>Enable clock gating of individual cache RAMs. This bit should be enabled for normal operation for lowest power consumption.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCACHE_ENABLE</name>
|
|
<description>Enable Flash Data Caching. When set to 1, all instruction accesses to flash will be cached.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ICACHE_ENABLE</name>
|
|
<description>Enable Flash Instruction Caching. When set to 1, all instruction accesses to flash will be cached.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SERIAL</name>
|
|
<description>Bitfield should always be programmed to 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CONFIG</name>
|
|
<description>Sets the cache configuration. Only a single configuration of 0x5 is valid.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>W2_128B_512E</name>
|
|
<description>Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active)</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_NC1</name>
|
|
<description>Enable Non-cacheable region 1. See the NCR1 registers to set the region boundaries and size.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_NC0</name>
|
|
<description>Enable Non-cacheable region 0. See the NCR0 registers to set the region boundaries and size.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LRU</name>
|
|
<description>Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM and is recommended.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enables the main flash cache controller logic and enables power to the cache RAMs. Instruction and Data caching need to be enabled independently using the ICACHE_ENABLE and DCACHE_ENABLE bits.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLASHCFG</name>
|
|
<description>Flash Control Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>RD_WAIT</name>
|
|
<description>Sets read waitstates for flash accesses (in clock cycles). This should be left at the default value for normal flash operation.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Cache Control</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000777</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FLASH1_SLM_ENABLE</name>
|
|
<description>Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASH1_SLM_DISABLE</name>
|
|
<description>Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASH1_SLM_STATUS</name>
|
|
<description>Flash Sleep Mode Status. When 1, flash instance 1 is asleep.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASH0_SLM_ENABLE</name>
|
|
<description>Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASH0_SLM_DISABLE</name>
|
|
<description>Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASH0_SLM_STATUS</name>
|
|
<description>Flash Sleep Mode Status. When 1, flash instance 0 is asleep.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CACHE_READY</name>
|
|
<description>Cache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESET_STAT</name>
|
|
<description>Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear Cache Stats</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVALIDATE</name>
|
|
<description>Writing a 1 to this bitfield invalidates the flash cache contents.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GO</name>
|
|
<description>Initiate a programming operation to flash info.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NCR0START</name>
|
|
<description>Flash Cache Noncachable Region 0 Start Address.</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFF0</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Start address for non-cacheable region 0. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).</description>
|
|
<bitRange>[19:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NCR0END</name>
|
|
<description>Flash Cache Noncachable Region 0 End</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFF0</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>End address for non-cacheable region 0. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).</description>
|
|
<bitRange>[19:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NCR1START</name>
|
|
<description>Flash Cache Noncachable Region 1 Start</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFF0</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Start address for non-cacheable region 1. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).</description>
|
|
<bitRange>[19:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NCR1END</name>
|
|
<description>Flash Cache Noncachable Region 1 End</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFF0</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>End address for non-cacheable region 1. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).</description>
|
|
<bitRange>[19:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACHEMODE</name>
|
|
<description>Flash Cache Mode Register. Used to trim performance/power.</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>THROTTLE6</name>
|
|
<description>Disallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value should be left at zero for optimal performance.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THROTTLE5</name>
|
|
<description>Disallow Data RAM reads (from line hits) during lookup read ops. Value should be left at zero for optimal performance.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THROTTLE4</name>
|
|
<description>Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should be left at zero for optimal performance.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THROTTLE3</name>
|
|
<description>Disallow cache data RAM writes on data RAM read cycles. Value should be left at zero for optimal performance.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THROTTLE2</name>
|
|
<description>Disallow cache data RAM writes on tag RAM read cycles. Value should be left at zero for optimal performance.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THROTTLE1</name>
|
|
<description>Disallow cache data RAM writes on tag RAM fill cycles. Value should be left at zero for optimal performance.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMON0</name>
|
|
<description>Data Cache Total Accesses</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>DACCESS_COUNT</name>
|
|
<description>Total accesses to data cache</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMON1</name>
|
|
<description>Data Cache Tag Lookups</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>DLOOKUP_COUNT</name>
|
|
<description>Total tag lookups from data cache</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMON2</name>
|
|
<description>Data Cache Hits</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>DHIT_COUNT</name>
|
|
<description>Cache hits from lookup operations</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMON3</name>
|
|
<description>Data Cache Line Hits</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>DLINE_COUNT</name>
|
|
<description>Cache hits from line cache</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMON0</name>
|
|
<description>Instruction Cache Total Accesses</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IACCESS_COUNT</name>
|
|
<description>Total accesses to Instruction cache</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMON1</name>
|
|
<description>Instruction Cache Tag Lookups</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ILOOKUP_COUNT</name>
|
|
<description>Total tag lookups from Instruction cache</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMON2</name>
|
|
<description>Instruction Cache Hits</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IHIT_COUNT</name>
|
|
<description>Cache hits from lookup operations</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMON3</name>
|
|
<description>Instruction Cache Line Hits</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ILINE_COUNT</name>
|
|
<description>Cache hits from line cache</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>CLKGEN</name>
|
|
<version>1.0</version>
|
|
<description>Clock Generator</description>
|
|
<!-- <groupName>GROUP_CLKGEN</groupName> -->
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000110</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CLKGEN_RTC</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CALXT</name>
|
|
<description>XT Oscillator Control</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CALXT</name>
|
|
<description>XT Oscillator calibration value</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALRC</name>
|
|
<description>RC Oscillator Control</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CALRC</name>
|
|
<description>LFRC Oscillator calibration value</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACALCTR</name>
|
|
<description>Autocalibration Counter</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ACALCTR</name>
|
|
<description>Autocalibration Counter result.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCTRL</name>
|
|
<description>Oscillator Control</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007C3</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ACAL</name>
|
|
<description>Autocalibration control</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable Autocalibration</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024SEC</name>
|
|
<description>Autocalibrate every 1024 seconds</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512SEC</name>
|
|
<description>Autocalibrate every 512 seconds</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTFREQ</name>
|
|
<description>Frequency measurement using XT</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTFREQ</name>
|
|
<description>Frequency measurement using external clock</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSEL</name>
|
|
<description>Selects the RTC oscillator (1 => LFRC, 0 => XT)</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XT</name>
|
|
<description>RTC uses the XT</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_LFRC</name>
|
|
<description>RTC uses the LFRC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FOS</name>
|
|
<description>Oscillator switch on failure function</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the oscillator switch on failure function</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the oscillator switch on failure function</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPRC</name>
|
|
<description>Stop the LFRC Oscillator to the RTC</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the LFRC Oscillator to drive the RTC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the LFRC Oscillator when driving the RTC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPXT</name>
|
|
<description>Stop the XT Oscillator to the RTC</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the XT Oscillator to drive the RTC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the XT Oscillator when driving the RTC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUT</name>
|
|
<description>CLKOUT Frequency Select</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000BF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CKEN</name>
|
|
<description>Enable the CLKOUT signal</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable CLKOUT</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable CLKOUT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKSEL</name>
|
|
<description>CLKOUT signal select. Note that HIGH_DRIVE should be selected if any high frequencies (such as from HFRC) are selected for CLKOUT.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>LFRC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>XT / 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV4</name>
|
|
<description>XT / 4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV8</name>
|
|
<description>XT / 8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>XT / 16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV32</name>
|
|
<description>XT / 32</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_1Hz</name>
|
|
<description>1 Hz as selected in RTC</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2M</name>
|
|
<description>XT / 2^21</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>XT</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CG_100Hz</name>
|
|
<description>100 Hz as selected in CLKGEN</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC</name>
|
|
<description>HFRC</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>HFRC / 4</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV8</name>
|
|
<description>HFRC / 8</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>HFRC / 16</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV64</name>
|
|
<description>HFRC / 64</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV128</name>
|
|
<description>HFRC / 128</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>HFRC / 256</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV512</name>
|
|
<description>HFRC / 512</description>
|
|
<value>32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_CLK</name>
|
|
<description>Flash Clock</description>
|
|
<value>34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>LFRC / 2</description>
|
|
<value>35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>LFRC / 32</description>
|
|
<value>36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV512</name>
|
|
<description>LFRC / 512</description>
|
|
<value>37</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32K</name>
|
|
<description>LFRC / 32768</description>
|
|
<value>38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>XT / 256</description>
|
|
<value>39</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV8K</name>
|
|
<description>XT / 8192</description>
|
|
<value>40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV64K</name>
|
|
<description>XT / 2^16</description>
|
|
<value>41</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRC_DIV16</name>
|
|
<description>Uncal LFRC / 16</description>
|
|
<value>42</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRC_DIV128</name>
|
|
<description>Uncal LFRC / 128</description>
|
|
<value>43</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRC_1Hz</name>
|
|
<description>Uncal LFRC / 1024</description>
|
|
<value>44</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRC_DIV4K</name>
|
|
<description>Uncal LFRC / 4096</description>
|
|
<value>45</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRC_DIV1M</name>
|
|
<description>Uncal LFRC / 2^20</description>
|
|
<value>46</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV64K</name>
|
|
<description>HFRC / 2^16</description>
|
|
<value>47</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16M</name>
|
|
<description>HFRC / 2^24</description>
|
|
<value>48</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2M</name>
|
|
<description>LFRC / 2^20</description>
|
|
<value>49</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRCNE</name>
|
|
<description>HFRC (not autoenabled)</description>
|
|
<value>50</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRCNE_DIV8</name>
|
|
<description>HFRC / 8 (not autoenabled)</description>
|
|
<value>51</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTNE</name>
|
|
<description>XT (not autoenabled)</description>
|
|
<value>53</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTNE_DIV16</name>
|
|
<description>XT / 16 (not autoenabled)</description>
|
|
<value>54</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCNE_DIV32</name>
|
|
<description>LFRC / 32 (not autoenabled)</description>
|
|
<value>55</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCNE</name>
|
|
<description>LFRC (not autoenabled) - Default for undefined values</description>
|
|
<value>57</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKKEY</name>
|
|
<description>Key Register for Clock Control Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CLKKEY</name>
|
|
<description>Key register value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Key</name>
|
|
<description>Key</description>
|
|
<value>71</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCTRL</name>
|
|
<description>HFRC Clock Control</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CORESEL</name>
|
|
<description>Core Clock divisor</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFRC</name>
|
|
<description>Core Clock is HFRC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV2</name>
|
|
<description>Core Clock is HFRC / 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Clock Generator Status</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OSCF</name>
|
|
<description>XT Oscillator is enabled but not oscillating</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OMODE</name>
|
|
<description>Current RTC oscillator (1 => LFRC, 0 => XT)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFADJ</name>
|
|
<description>HFRC Adjustment</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0025B800</resetValue>
|
|
<resetMask>0x00FFFF0F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>HFADJ_GAIN</name>
|
|
<description>Gain control for HFRC adjustment</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Gain_of_1</name>
|
|
<description>HF Adjust with Gain of 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Gain_of_1_in_2</name>
|
|
<description>HF Adjust with Gain of 0.5</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Gain_of_1_in_4</name>
|
|
<description>HF Adjust with Gain of 0.25</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Gain_of_1_in_8</name>
|
|
<description>HF Adjust with Gain of 0.125</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Gain_of_1_in_16</name>
|
|
<description>HF Adjust with Gain of 0.0625</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Gain_of_1_in_32</name>
|
|
<description>HF Adjust with Gain of 0.03125</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFWARMUP</name>
|
|
<description>XT warmup period for HFRC adjustment</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1SEC</name>
|
|
<description>Autoadjust XT warmup period = 1-2 seconds</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2SEC</name>
|
|
<description>Autoadjust XT warmup period = 2-4 seconds</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXTADJ</name>
|
|
<description>Target HFRC adjustment value.</description>
|
|
<bitRange>[19:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HFADJCK</name>
|
|
<description>Repeat period for HFRC adjustment</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4SEC</name>
|
|
<description>Autoadjust repeat period = 4 seconds</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16SEC</name>
|
|
<description>Autoadjust repeat period = 16 seconds</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32SEC</name>
|
|
<description>Autoadjust repeat period = 32 seconds</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64SEC</name>
|
|
<description>Autoadjust repeat period = 64 seconds</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128SEC</name>
|
|
<description>Autoadjust repeat period = 128 seconds</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256SEC</name>
|
|
<description>Autoadjust repeat period = 256 seconds</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512SEC</name>
|
|
<description>Autoadjust repeat period = 512 seconds</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024SEC</name>
|
|
<description>Autoadjust repeat period = 1024 seconds</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFADJEN</name>
|
|
<description>HFRC adjustment control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the HFRC adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the HFRC adjustment</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCKEN</name>
|
|
<description>Clock Enable Status</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CLOCKEN</name>
|
|
<description>Clock enable status</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_CLKEN</name>
|
|
<description>Clock enable for the ADC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER_CLKEN</name>
|
|
<description>Clock enable for the CTIMER.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER0A_CLKEN</name>
|
|
<description>Clock enable for the CTIMER0A.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER0B_CLKEN</name>
|
|
<description>Clock enable for the CTIMER0B.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER1A_CLKEN</name>
|
|
<description>Clock enable for the CTIMER1A.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER1B_CLKEN</name>
|
|
<description>Clock enable for the CTIMER1B.</description>
|
|
<value>32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER2A_CLKEN</name>
|
|
<description>Clock enable for the CTIMER2A.</description>
|
|
<value>64</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER2B_CLKEN</name>
|
|
<description>Clock enable for the CTIMER2B.</description>
|
|
<value>128</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER3A_CLKEN</name>
|
|
<description>Clock enable for the CTIMER3A.</description>
|
|
<value>256</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER3B_CLKEN</name>
|
|
<description>Clock enable for the CTIMER3B.</description>
|
|
<value>512</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTR0_CLKEN</name>
|
|
<description>Clock enable for the IO Master 0.</description>
|
|
<value>1024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTR1_CLKEN</name>
|
|
<description>Clock enable for the IO Master 1.</description>
|
|
<value>2048</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTR2_CLKEN</name>
|
|
<description>Clock enable for the IO Master 2.</description>
|
|
<value>4096</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTR3_CLKEN</name>
|
|
<description>Clock enable for the IO Master 3.</description>
|
|
<value>8192</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTR4_CLKEN</name>
|
|
<description>Clock enable for the IO Master 4.</description>
|
|
<value>16384</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTR5_CLKEN</name>
|
|
<description>Clock enable for the IO Master 5.</description>
|
|
<value>32768</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTRIFC0_CLKEN</name>
|
|
<description>Clock enable for the IO Master IFC0.</description>
|
|
<value>65536</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTRIFC1_CLKEN</name>
|
|
<description>Clock enable for the IO Master IFC1.</description>
|
|
<value>131072</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTRIFC2_CLKEN</name>
|
|
<description>Clock enable for the IO Master IFC2.</description>
|
|
<value>262144</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTRIFC3_CLKEN</name>
|
|
<description>Clock enable for the IO Master IFC3.</description>
|
|
<value>524288</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTRIFC4_CLKEN</name>
|
|
<description>Clock enable for the IO Master IFC4.</description>
|
|
<value>1048576</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMSTRIFC5_CLKEN</name>
|
|
<description>Clock enable for the IO Master IFC5.</description>
|
|
<value>2097152</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOSLAVE_CLKEN</name>
|
|
<description>Clock enable for the IO Slave.</description>
|
|
<value>4194304</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM_CLKEN</name>
|
|
<description>Clock enable for the PDM.</description>
|
|
<value>8388608</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDMIFC_CLKEN</name>
|
|
<description>Clock enable for the PDM IFC.</description>
|
|
<value>16777216</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RSTGEN_CLKEN</name>
|
|
<description>Clock enable for the RSTGEN.</description>
|
|
<value>33554432</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM_WIPE_CLKEN</name>
|
|
<description>Clock enable for the SRAM_WIPE.</description>
|
|
<value>67108864</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STIMER_CLKEN</name>
|
|
<description>Clock enable for the STIMER.</description>
|
|
<value>134217728</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STIMER_CNT_CLKEN</name>
|
|
<description>Clock enable for the STIMER_CNT.</description>
|
|
<value>268435456</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TPIU_CLKEN</name>
|
|
<description>Clock enable for the TPIU.</description>
|
|
<value>536870912</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0_HCLK_CLKEN</name>
|
|
<description>Clock enable for the UART0_HCLK.</description>
|
|
<value>1073741824</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0HF_CLKEN</name>
|
|
<description>Clock enable for the UART0HF.</description>
|
|
<value>2147483648</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCKEN2</name>
|
|
<description>Clock Enable Status</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CLOCKEN2</name>
|
|
<description>Clock enable status 2</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART1_HCLK_CLKEN</name>
|
|
<description>Clock enable for the UART1_HCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1HF_CLKEN</name>
|
|
<description>Clock enable for the UART1HF.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_CLKEN</name>
|
|
<description>Clock enable for the WDT.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_32KHz_EN</name>
|
|
<description>Clock enable for the XT_32KHz.</description>
|
|
<value>1073741824</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRCHFRC</name>
|
|
<description>Force HFRC On Status.</description>
|
|
<value>2147483648</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCKEN3</name>
|
|
<description>Clock Enable Status</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CLOCKEN3</name>
|
|
<description>Clock enable status 3</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>periph_all_xtal_en</name>
|
|
<description>At least 1 peripherial is requesting for XTAL Clock</description>
|
|
<value>16777216</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>periph_all_hfrc_en</name>
|
|
<description>At least 1 peripherial is requesting for HFRC Clock</description>
|
|
<value>33554432</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFADJEN</name>
|
|
<description>HFRC Adjust Enable Status</description>
|
|
<value>67108864</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_en_out</name>
|
|
<description>HFRC is enabled during adjustment status</description>
|
|
<value>134217728</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_SOURCE</name>
|
|
<description>Selects the RTC oscillator (0 => LFRC, 1 => XT)</description>
|
|
<value>268435456</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTAL_EN</name>
|
|
<description>XT is enabled Status</description>
|
|
<value>536870912</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_EN</name>
|
|
<description>HFRC is enabled Status</description>
|
|
<value>1073741824</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASHCLK_EN</name>
|
|
<description>Flash Clock is enabled Status</description>
|
|
<value>2147483648</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UARTEN</name>
|
|
<description>UART Enable</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000303</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>UART1EN</name>
|
|
<description>UART1 system clock control</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the UART1 system clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the UART1 system clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REDUCE_FREQ</name>
|
|
<description>Run UART_Hclk at the same frequency as UART_hfclk</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_POWER_SAV</name>
|
|
<description>Enable UART_hclk to reduce to UART_hfclk at low power mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0EN</name>
|
|
<description>UART0 system clock control</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the UART0 system clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the UART0 system clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REDUCE_FREQ</name>
|
|
<description>Run UART_Hclk at the same frequency as UART_hfclk</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_POWER_SAV</name>
|
|
<description>Enable UART_hclk to reduce to UART_hfclk at low power mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>CLKGEN Interrupt Register: Enable</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>CLKGEN Interrupt Register: Status</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>CLKGEN Interrupt Register: Clear</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>CLKGEN Interrupt Register: Set</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>CTIMER</name>
|
|
<version>1.0</version>
|
|
<description>Counter/Timer</description>
|
|
<!-- <groupName>GROUP_CTIMER</groupName> -->
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000310</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CTIMER</name>
|
|
<value>13</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER</name>
|
|
<value>18</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR0</name>
|
|
<value>19</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR1</name>
|
|
<value>20</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR2</name>
|
|
<value>21</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR3</name>
|
|
<value>22</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR4</name>
|
|
<value>23</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR5</name>
|
|
<value>24</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR6</name>
|
|
<value>25</value>
|
|
</interrupt> <interrupt>
|
|
<name>STIMER_CMPR7</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TMR0</name>
|
|
<description>Counter/Timer Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTTMRB0</name>
|
|
<description>Counter/Timer B0.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTTMRA0</name>
|
|
<description>Counter/Timer A0.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRA0</name>
|
|
<description>Counter/Timer A0 Compare Registers</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1A0</name>
|
|
<description>Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0A0</name>
|
|
<description>Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRB0</name>
|
|
<description>Counter/Timer B0 Compare Registers</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1B0</name>
|
|
<description>Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0B0</name>
|
|
<description>Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL0</name>
|
|
<description>Counter/Timer Control</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xBFFF3FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTLINK0</name>
|
|
<description>Counter/Timer A0/B0 Link bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TWO_16BIT_TIMERS</name>
|
|
<description>Use A0/B0 timers as two independent 16-bit timers (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BIT_TIMER</name>
|
|
<description>Link A0/B0 timers into a single 32-bit timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0PE</name>
|
|
<description>Counter/Timer B0 Output Enable bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B holds the TMRPINB signal at the value TMRB0POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B0 to generate a signal on TMRPINB.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0POL</name>
|
|
<description>Counter/Timer B0 output polarity.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINB0 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINB0 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0CLR</name>
|
|
<description>Counter/Timer B0 Clear bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer B0 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer B0 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0IE1</name>
|
|
<description>Counter/Timer B0 Interrupt Enable bit for COMPR1.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B0 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B0 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0IE0</name>
|
|
<description>Counter/Timer B0 Interrupt Enable bit for COMPR0.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B0 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B0 to generate an interrupt based on COMPR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0FN</name>
|
|
<description>Counter/Timer B0 Function Select.</description>
|
|
<bitRange>[24:22]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0B0, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0CLK</name>
|
|
<description>Counter/Timer B0 Clock Select.</description>
|
|
<bitRange>[21:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINB.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK</name>
|
|
<description>Clock source is HCLK.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKB</name>
|
|
<description>Clock source is buck converter stream from CORE Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB0EN</name>
|
|
<description>Counter/Timer B0 Enable bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B0 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer B0 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0PE</name>
|
|
<description>Counter/Timer A0 Output Enable bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A holds the TMRPINA signal at the value TMRA0POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A0 to generate a signal on TMRPINA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0POL</name>
|
|
<description>Counter/Timer A0 output polarity.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINA0 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINA0 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0CLR</name>
|
|
<description>Counter/Timer A0 Clear bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer A0 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer A0 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0IE1</name>
|
|
<description>Counter/Timer A0 Interrupt Enable bit based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A0 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A0 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0IE0</name>
|
|
<description>Counter/Timer A0 Interrupt Enable bit based on COMPR0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A0 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A0 to generate an interrupt based on COMPR0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0FN</name>
|
|
<description>Counter/Timer A0 Function Select.</description>
|
|
<bitRange>[8:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0A0, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1A0, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0CLK</name>
|
|
<description>Counter/Timer A0 Clock Select.</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK_DIV4</name>
|
|
<description>Clock source is HCLK / 4.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKA</name>
|
|
<description>Clock source is buck converter stream from MEM Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA0EN</name>
|
|
<description>Counter/Timer A0 Enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A0 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer A0 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMR1</name>
|
|
<description>Counter/Timer Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTTMRB1</name>
|
|
<description>Counter/Timer B1.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTTMRA1</name>
|
|
<description>Counter/Timer A1.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRA1</name>
|
|
<description>Counter/Timer A1 Compare Registers</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1A1</name>
|
|
<description>Counter/Timer A1 Compare Register 1.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0A1</name>
|
|
<description>Counter/Timer A1 Compare Register 0.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRB1</name>
|
|
<description>Counter/Timer B1 Compare Registers</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1B1</name>
|
|
<description>Counter/Timer B1 Compare Register 1.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0B1</name>
|
|
<description>Counter/Timer B1 Compare Register 0.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL1</name>
|
|
<description>Counter/Timer Control</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xBFFF3FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTLINK1</name>
|
|
<description>Counter/Timer A1/B1 Link bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TWO_16BIT_TIMERS</name>
|
|
<description>Use A1/B1 timers as two independent 16-bit timers (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BIT_TIMER</name>
|
|
<description>Link A1/B1 timers into a single 32-bit timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1PE</name>
|
|
<description>Counter/Timer B1 Output Enable bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B holds the TMRPINB signal at the value TMRB1POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B1 to generate a signal on TMRPINB.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1POL</name>
|
|
<description>Counter/Timer B1 output polarity.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINB1 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINB1 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1CLR</name>
|
|
<description>Counter/Timer B1 Clear bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer B1 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer B1 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1IE1</name>
|
|
<description>Counter/Timer B1 Interrupt Enable bit for COMPR1.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B1 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B1 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1IE0</name>
|
|
<description>Counter/Timer B1 Interrupt Enable bit for COMPR0.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B1 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B1 to generate an interrupt based on COMPR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1FN</name>
|
|
<description>Counter/Timer B1 Function Select.</description>
|
|
<bitRange>[24:22]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0B1, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B1, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1CLK</name>
|
|
<description>Counter/Timer B1 Clock Select.</description>
|
|
<bitRange>[21:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINB.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK</name>
|
|
<description>Clock source is HCLK.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKB</name>
|
|
<description>Clock source is buck converter stream from CORE Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB1EN</name>
|
|
<description>Counter/Timer B1 Enable bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B1 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer B1 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1PE</name>
|
|
<description>Counter/Timer A1 Output Enable bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A holds the TMRPINA signal at the value TMRA1POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A1 to generate a signal on TMRPINA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1POL</name>
|
|
<description>Counter/Timer A1 output polarity.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINA1 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINA1 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1CLR</name>
|
|
<description>Counter/Timer A1 Clear bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer A1 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer A1 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1IE1</name>
|
|
<description>Counter/Timer A1 Interrupt Enable bit based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A1 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A1 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1IE0</name>
|
|
<description>Counter/Timer A1 Interrupt Enable bit based on COMPR0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A1 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A1 to generate an interrupt based on COMPR0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1FN</name>
|
|
<description>Counter/Timer A1 Function Select.</description>
|
|
<bitRange>[8:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0A1, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1A1, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1CLK</name>
|
|
<description>Counter/Timer A1 Clock Select.</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK</name>
|
|
<description>Clock source is HCLK.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKA</name>
|
|
<description>Clock source is buck converter stream from MEM Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA1EN</name>
|
|
<description>Counter/Timer A1 Enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A1 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer A1 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMR2</name>
|
|
<description>Counter/Timer Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTTMRB2</name>
|
|
<description>Counter/Timer B2.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTTMRA2</name>
|
|
<description>Counter/Timer A2.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRA2</name>
|
|
<description>Counter/Timer A2 Compare Registers</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1A2</name>
|
|
<description>Counter/Timer A2 Compare Register 1.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0A2</name>
|
|
<description>Counter/Timer A2 Compare Register 0.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRB2</name>
|
|
<description>Counter/Timer B2 Compare Registers</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1B2</name>
|
|
<description>Counter/Timer B2 Compare Register 1.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0B2</name>
|
|
<description>Counter/Timer B2 Compare Register 0.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL2</name>
|
|
<description>Counter/Timer Control</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xBFFF3FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTLINK2</name>
|
|
<description>Counter/Timer A2/B2 Link bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TWO_16BIT_TIMERS</name>
|
|
<description>Use A2/B2 timers as two independent 16-bit timers (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BIT_TIMER</name>
|
|
<description>Link A2/B2 timers into a single 32-bit timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2PE</name>
|
|
<description>Counter/Timer B2 Output Enable bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B holds the TMRPINB signal at the value TMRB2POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B2 to generate a signal on TMRPINB.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2POL</name>
|
|
<description>Counter/Timer B2 output polarity.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINB2 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINB2 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2CLR</name>
|
|
<description>Counter/Timer B2 Clear bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer B2 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer B2 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2IE1</name>
|
|
<description>Counter/Timer B2 Interrupt Enable bit for COMPR1.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B2 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B2 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2IE0</name>
|
|
<description>Counter/Timer B2 Interrupt Enable bit for COMPR0.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B2 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B2 to generate an interrupt based on COMPR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2FN</name>
|
|
<description>Counter/Timer B2 Function Select.</description>
|
|
<bitRange>[24:22]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0B2, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2CLK</name>
|
|
<description>Counter/Timer B2 Clock Select.</description>
|
|
<bitRange>[21:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINB.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK</name>
|
|
<description>Clock source is HCLK.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKA</name>
|
|
<description>Clock source is buck converter stream from MEM Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB2EN</name>
|
|
<description>Counter/Timer B2 Enable bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B2 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer B2 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2PE</name>
|
|
<description>Counter/Timer A2 Output Enable bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A holds the TMRPINA signal at the value TMRA2POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A2 to generate a signal on TMRPINA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2POL</name>
|
|
<description>Counter/Timer A2 output polarity.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINA2 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINA2 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2CLR</name>
|
|
<description>Counter/Timer A2 Clear bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer A2 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer A2 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2IE1</name>
|
|
<description>Counter/Timer A2 Interrupt Enable bit based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A2 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A2 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2IE0</name>
|
|
<description>Counter/Timer A2 Interrupt Enable bit based on COMPR0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A2 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A2 to generate an interrupt based on COMPR0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2FN</name>
|
|
<description>Counter/Timer A2 Function Select.</description>
|
|
<bitRange>[8:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0A2, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1A2, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2CLK</name>
|
|
<description>Counter/Timer A2 Clock Select.</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK</name>
|
|
<description>Clock source is HCLK.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKB</name>
|
|
<description>Clock source is buck converter stream from CORE Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA2EN</name>
|
|
<description>Counter/Timer A2 Enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A2 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer A2 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMR3</name>
|
|
<description>Counter/Timer Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTTMRB3</name>
|
|
<description>Counter/Timer B3.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTTMRA3</name>
|
|
<description>Counter/Timer A3.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRA3</name>
|
|
<description>Counter/Timer A3 Compare Registers</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1A3</name>
|
|
<description>Counter/Timer A3 Compare Register 1.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0A3</name>
|
|
<description>Counter/Timer A3 Compare Register 0.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPRB3</name>
|
|
<description>Counter/Timer B3 Compare Registers</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMPR1B3</name>
|
|
<description>Counter/Timer B3 Compare Register 1.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMPR0B3</name>
|
|
<description>Counter/Timer B3 Compare Register 0.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL3</name>
|
|
<description>Counter/Timer Control</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xBFFFBFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTLINK3</name>
|
|
<description>Counter/Timer A3/B3 Link bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TWO_16BIT_TIMERS</name>
|
|
<description>Use A3/B3 timers as two independent 16-bit timers (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BIT_TIMER</name>
|
|
<description>Link A3/B3 timers into a single 32-bit timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3PE</name>
|
|
<description>Counter/Timer B3 Output Enable bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B holds the TMRPINB signal at the value TMRB3POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B3 to generate a signal on TMRPINB.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3POL</name>
|
|
<description>Counter/Timer B3 output polarity.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINB3 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINB3 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3CLR</name>
|
|
<description>Counter/Timer B3 Clear bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer B3 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer B3 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3IE1</name>
|
|
<description>Counter/Timer B3 Interrupt Enable bit for COMPR1.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B3 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B3 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3IE0</name>
|
|
<description>Counter/Timer B3 Interrupt Enable bit for COMPR0.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer B3 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer B3 to generate an interrupt based on COMPR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3FN</name>
|
|
<description>Counter/Timer B3 Function Select.</description>
|
|
<bitRange>[24:22]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0B3, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B3, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3CLK</name>
|
|
<description>Counter/Timer B3 Clock Select.</description>
|
|
<bitRange>[21:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINB.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK</name>
|
|
<description>Clock source is HCLK.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKA</name>
|
|
<description>Clock source is buck converter stream from MEM Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRB3EN</name>
|
|
<description>Counter/Timer B3 Enable bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer B3 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer B3 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCEN</name>
|
|
<description>Special Timer A3 enable for ADC function.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TMRA3PE</name>
|
|
<description>Counter/Timer A3 Output Enable bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A holds the TMRPINA signal at the value TMRA3POL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A3 to generate a signal on TMRPINA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA3POL</name>
|
|
<description>Counter/Timer A3 output polarity.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The polarity of the TMRPINA3 pin is the same as the timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The polarity of the TMRPINA3 pin is the inverse of the timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA3CLR</name>
|
|
<description>Counter/Timer A3 Clear bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow counter/timer A3 to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Holds counter/timer A3 at 0x0000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA3IE1</name>
|
|
<description>Counter/Timer A3 Interrupt Enable bit based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A3 from generating an interrupt based on COMPR1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A3 to generate an interrupt based on COMPR1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA3IE0</name>
|
|
<description>Counter/Timer A3 Interrupt Enable bit based on COMPR0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable counter/timer A3 from generating an interrupt based on COMPR0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable counter/timer A3 to generate an interrupt based on COMPR0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA3FN</name>
|
|
<description>Counter/Timer A3 Function Select.</description>
|
|
<bitRange>[8:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLECOUNT</name>
|
|
<description>Single count (output toggles and sticks). Count to CMPR0A3, stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATEDCOUNT</name>
|
|
<description>Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_ONCE</name>
|
|
<description>Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1A3, deassert, stop.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE_CONT</name>
|
|
<description>Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous run (aka Free Run). Count continuously.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA3CLK</name>
|
|
<description>Counter/Timer A3 Clock Select.</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TMRPIN</name>
|
|
<description>Clock source is TMRPINA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Clock source is HFRC / 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Clock source is HFRC / 16</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>Clock source is HFRC / 256</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV1024</name>
|
|
<description>Clock source is HFRC / 1024</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4K</name>
|
|
<description>Clock source is HFRC / 4096</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Clock source is the XT (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV2</name>
|
|
<description>Clock source is XT / 2</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV16</name>
|
|
<description>Clock source is XT / 16</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XT_DIV256</name>
|
|
<description>Clock source is XT / 256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV2</name>
|
|
<description>Clock source is LFRC / 2</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV32</name>
|
|
<description>Clock source is LFRC / 32</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1K</name>
|
|
<description>Clock source is LFRC / 1024</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC</name>
|
|
<description>Clock source is LFRC</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_100HZ</name>
|
|
<description>Clock source is 100 Hz from the current RTC oscillator.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HCLK</name>
|
|
<description>Clock source is HCLK.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCKB</name>
|
|
<description>Clock source is buck converter stream from CORE Buck.</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRA3EN</name>
|
|
<description>Counter/Timer A3 Enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter/Timer A3 Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter/Timer A3 Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCFG</name>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xC000FF0F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FREEZE</name>
|
|
<description>Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>THAW</name>
|
|
<description>Let the COUNTER register run on its input clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREEZE</name>
|
|
<description>Stop the COUNTER register for loading.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Let the COUNTER register run on its input clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Stop the COUNTER register for loading.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_H_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare H disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare H enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_G_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare G disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare G enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_F_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare F disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare F enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_E_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare E disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare E enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_D_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare D disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare D enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_C_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare C disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare C enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_B_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare B disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare B enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE_A_EN</name>
|
|
<description>Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Compare A disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Compare A enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Selects an appropriate clock source and divider to use for the System Timer clock.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOCLK</name>
|
|
<description>No clock enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>3MHz from the HFRC clock divider.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV256</name>
|
|
<description>187.5KHz from the HFRC clock divider.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTAL_DIV1</name>
|
|
<description>32768Hz from the crystal oscillator.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTAL_DIV2</name>
|
|
<description>16384Hz from the crystal oscillator.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTAL_DIV32</name>
|
|
<description>1024Hz from the crystal oscillator.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRC_DIV1</name>
|
|
<description>Approximately 1KHz from the LFRC oscillator (uncalibrated).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER0A</name>
|
|
<description>Use CTIMER 0 section A as a prescaler for the clock source.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTIMER0B</name>
|
|
<description>Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STTMR</name>
|
|
<description>System Timer Count Register (Real Time Counter)</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Value of the 32-bit counter as it ticks over.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPTURE_CONTROL</name>
|
|
<description>Capture Control Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CAPTURE_D</name>
|
|
<description>Selects whether capture is enabled for the specified capture register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Capture function disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Capture function enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTURE_C</name>
|
|
<description>Selects whether capture is enabled for the specified capture register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Capture function disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Capture function enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTURE_B</name>
|
|
<description>Selects whether capture is enabled for the specified capture register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Capture function disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Capture function enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTURE_A</name>
|
|
<description>Selects whether capture is enabled for the specified capture register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Capture function disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Capture function enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR0</name>
|
|
<description>Compare Register A</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR1</name>
|
|
<description>Compare Register B</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR2</name>
|
|
<description>Compare Register C</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR3</name>
|
|
<description>Compare Register D</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR4</name>
|
|
<description>Compare Register E</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR5</name>
|
|
<description>Compare Register F</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR6</name>
|
|
<description>Compare Register G</description>
|
|
<addressOffset>0x00000128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMPR7</name>
|
|
<description>Compare Register H</description>
|
|
<addressOffset>0x0000012C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCAPT0</name>
|
|
<description>Capture Register A</description>
|
|
<addressOffset>0x000001E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCAPT1</name>
|
|
<description>Capture Register B</description>
|
|
<addressOffset>0x000001E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCAPT2</name>
|
|
<description>Capture Register C</description>
|
|
<addressOffset>0x000001E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCAPT3</name>
|
|
<description>Capture Register D</description>
|
|
<addressOffset>0x000001EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNVR0</name>
|
|
<description>System Timer NVRAM_A Register</description>
|
|
<addressOffset>0x000001F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Value of the 32-bit counter as it ticks over.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNVR1</name>
|
|
<description>System Timer NVRAM_B Register</description>
|
|
<addressOffset>0x000001F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Value of the 32-bit counter as it ticks over.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNVR2</name>
|
|
<description>System Timer NVRAM_C Register</description>
|
|
<addressOffset>0x000001F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Value of the 32-bit counter as it ticks over.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>Counter/Timer Interrupts: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTMRB3C1INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C1INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C1INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR1.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C1INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C1INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C1INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C1INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C1INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB3C0INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C0INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C0INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C0INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C0INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C0INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C0INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C0INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Counter/Timer Interrupts: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTMRB3C1INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C1INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C1INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR1.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C1INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C1INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C1INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C1INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C1INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB3C0INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C0INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C0INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C0INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C0INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C0INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C0INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C0INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>Counter/Timer Interrupts: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTMRB3C1INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C1INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C1INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR1.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C1INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C1INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C1INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C1INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C1INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB3C0INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C0INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C0INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C0INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C0INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C0INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C0INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C0INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>Counter/Timer Interrupts: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTMRB3C1INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C1INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C1INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR1.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C1INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C1INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C1INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C1INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C1INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB3C0INT</name>
|
|
<description>Counter/Timer B3 interrupt based on COMPR0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA3C0INT</name>
|
|
<description>Counter/Timer A3 interrupt based on COMPR0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB2C0INT</name>
|
|
<description>Counter/Timer B2 interrupt based on COMPR0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA2C0INT</name>
|
|
<description>Counter/Timer A2 interrupt based on COMPR0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB1C0INT</name>
|
|
<description>Counter/Timer B1 interrupt based on COMPR0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA1C0INT</name>
|
|
<description>Counter/Timer A1 interrupt based on COMPR0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRB0C0INT</name>
|
|
<description>Counter/Timer B0 interrupt based on COMPR0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTMRA0C0INT</name>
|
|
<description>Counter/Timer A0 interrupt based on COMPR0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STMINTEN</name>
|
|
<description>STIMER Interrupt registers: Enable</description>
|
|
<addressOffset>0x00000300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CAPTURED</name>
|
|
<description>CAPTURE register D has grabbed the value in the counter</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPD_INT</name>
|
|
<description>Capture D interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREC</name>
|
|
<description>CAPTURE register C has grabbed the value in the counter</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPC_INT</name>
|
|
<description>CAPTURE C interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREB</name>
|
|
<description>CAPTURE register B has grabbed the value in the counter</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPB_INT</name>
|
|
<description>CAPTURE B interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREA</name>
|
|
<description>CAPTURE register A has grabbed the value in the counter</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPA_INT</name>
|
|
<description>CAPTURE A interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVERFLOW</name>
|
|
<description>COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFLOW_INT</name>
|
|
<description>Overflow interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREH</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register H.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREG</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register G.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREF</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register F.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREE</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register E.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register D.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREC</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register C.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREB</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register B.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREA</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register A.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STMINTSTAT</name>
|
|
<description>STIMER Interrupt registers: Status</description>
|
|
<addressOffset>0x00000304</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CAPTURED</name>
|
|
<description>CAPTURE register D has grabbed the value in the counter</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPD_INT</name>
|
|
<description>Capture D interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREC</name>
|
|
<description>CAPTURE register C has grabbed the value in the counter</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPC_INT</name>
|
|
<description>CAPTURE C interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREB</name>
|
|
<description>CAPTURE register B has grabbed the value in the counter</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPB_INT</name>
|
|
<description>CAPTURE B interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREA</name>
|
|
<description>CAPTURE register A has grabbed the value in the counter</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPA_INT</name>
|
|
<description>CAPTURE A interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVERFLOW</name>
|
|
<description>COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFLOW_INT</name>
|
|
<description>Overflow interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREH</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register H.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREG</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register G.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREF</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register F.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREE</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register E.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register D.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREC</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register C.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREB</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register B.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREA</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register A.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STMINTCLR</name>
|
|
<description>STIMER Interrupt registers: Clear</description>
|
|
<addressOffset>0x00000308</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CAPTURED</name>
|
|
<description>CAPTURE register D has grabbed the value in the counter</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPD_INT</name>
|
|
<description>Capture D interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREC</name>
|
|
<description>CAPTURE register C has grabbed the value in the counter</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPC_INT</name>
|
|
<description>CAPTURE C interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREB</name>
|
|
<description>CAPTURE register B has grabbed the value in the counter</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPB_INT</name>
|
|
<description>CAPTURE B interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREA</name>
|
|
<description>CAPTURE register A has grabbed the value in the counter</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPA_INT</name>
|
|
<description>CAPTURE A interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVERFLOW</name>
|
|
<description>COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFLOW_INT</name>
|
|
<description>Overflow interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREH</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register H.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREG</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register G.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREF</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register F.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREE</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register E.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register D.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREC</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register C.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREB</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register B.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREA</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register A.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STMINTSET</name>
|
|
<description>STIMER Interrupt registers: Set</description>
|
|
<addressOffset>0x0000030C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CAPTURED</name>
|
|
<description>CAPTURE register D has grabbed the value in the counter</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPD_INT</name>
|
|
<description>Capture D interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREC</name>
|
|
<description>CAPTURE register C has grabbed the value in the counter</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPC_INT</name>
|
|
<description>CAPTURE C interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREB</name>
|
|
<description>CAPTURE register B has grabbed the value in the counter</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPB_INT</name>
|
|
<description>CAPTURE B interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTUREA</name>
|
|
<description>CAPTURE register A has grabbed the value in the counter</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPA_INT</name>
|
|
<description>CAPTURE A interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVERFLOW</name>
|
|
<description>COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFLOW_INT</name>
|
|
<description>Overflow interrupt status bit was set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREH</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register H.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREG</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register G.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREF</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register F.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREE</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register E.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register D.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREC</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register C.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREB</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register B.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPAREA</name>
|
|
<description>COUNTER is greater than or equal to COMPARE register A.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPARED</name>
|
|
<description>COUNTER greater than or equal to COMPARE register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GPIO</name>
|
|
<version>1.0</version>
|
|
<description>General Purpose IO</description>
|
|
<!-- <groupName>GROUP_GPIO</groupName> -->
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000220</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PADREGA</name>
|
|
<description>Pad Configuration Register A</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3F3FFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD3FNCSEL</name>
|
|
<description>Pad 3 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UA0RTS</name>
|
|
<description>Configure as the UART0 RTS output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLnCE</name>
|
|
<description>Configure as the IOSLAVE SPI nCE signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO3</name>
|
|
<description>Configure as GPIO3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MxnCELB</name>
|
|
<description>Configure as the IOSLAVE SPI nCE loopback signal from IOMSTRx</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR2</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG1</name>
|
|
<description>Configure as the ADC Trigger 1 signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_WCLK</name>
|
|
<description>Configure as the I2S Word Clock input</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD3STRNG</name>
|
|
<description>Pad 3 drive strength.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD3INPEN</name>
|
|
<description>Pad 3 input enable.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD3PULL</name>
|
|
<description>Pad 3 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD2FNCSEL</name>
|
|
<description>Pad 2 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLWIR3</name>
|
|
<description>Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMOSI</name>
|
|
<description>Configure as the IOSLAVE SPI MOSI signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0RX</name>
|
|
<description>Configure as the UART0 RX input</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO2</name>
|
|
<description>Configure as GPIO2</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MxMOSILB</name>
|
|
<description>Configure as the IOSLAVE SPI MOSI loopback signal from IOMSTRx</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2MOSI</name>
|
|
<description>Configure as the IOMSTR2 SPI MOSI output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MxWIR3LB</name>
|
|
<description>Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback signal from IOMSTRx</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2WIR3</name>
|
|
<description>Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD2STRNG</name>
|
|
<description>Pad 2 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD2INPEN</name>
|
|
<description>Pad 2 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD2PULL</name>
|
|
<description>Pad 2 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD1RSEL</name>
|
|
<description>Pad 1 pullup resistor selection.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD1FNCSEL</name>
|
|
<description>Pad 1 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLSDA</name>
|
|
<description>Configure as the IOSLAVE I2C SDA signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMISO</name>
|
|
<description>Configure as the IOSLAVE SPI MISO signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0TX</name>
|
|
<description>Configure as the UART0 TX output signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO1</name>
|
|
<description>Configure as GPIO1</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MxMISOLB</name>
|
|
<description>Configure as the IOSLAVE SPI MISO loopback signal from IOMSTRx</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2MISO</name>
|
|
<description>Configure as the IOMSTR2 SPI MISO input signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MxSDALB</name>
|
|
<description>Configure as the IOSLAVE I2C SDA loopback signal from IOMSTRx</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SDA</name>
|
|
<description>Configure as the IOMSTR2 I2C Serial data I/O signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD1STRNG</name>
|
|
<description>Pad 1 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD1INPEN</name>
|
|
<description>Pad 1 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD1PULL</name>
|
|
<description>Pad 1 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD0RSEL</name>
|
|
<description>Pad 0 pullup resistor selection.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD0FNCSEL</name>
|
|
<description>Pad 0 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLSCL</name>
|
|
<description>Configure as the IOSLAVE I2C SCL signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLSCK</name>
|
|
<description>Configure as the IOSLAVE SPI SCK signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as the CLKOUT signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO0</name>
|
|
<description>Configure as GPIO0</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MxSCKLB</name>
|
|
<description>Configure as the IOSLAVE SPI SCK loopback signal from IOMSTRx</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SCK</name>
|
|
<description>Configure as the IOMSTR2 SPI SCK output</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MxSCLLB</name>
|
|
<description>Configure as the IOSLAVE I2C SCL loopback signal from IOMSTRx</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SCL</name>
|
|
<description>Configure as the IOMSTR2 I2C SCL clock I/O signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD0STRNG</name>
|
|
<description>Pad 0 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD0INPEN</name>
|
|
<description>Pad 0 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD0PULL</name>
|
|
<description>Pad 0 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGB</name>
|
|
<description>Pad Configuration Register B</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3FFFFFBF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD7FNCSEL</name>
|
|
<description>Pad 7 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M0WIR3</name>
|
|
<description>Configure as the IOMSTR0 SPI 3-wire MOSI/MISO signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0MOSI</name>
|
|
<description>Configure as the IOMSTR0 SPI MOSI signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as the CLKOUT signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO7</name>
|
|
<description>Configure as GPIO7</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG0</name>
|
|
<description>Configure as the ADC Trigger 0 signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0TX</name>
|
|
<description>Configure as the UART0 TX output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLWIR3LB</name>
|
|
<description>Configure as the IOMSTR0 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR1</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD7STRNG</name>
|
|
<description>Pad 7 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD7INPEN</name>
|
|
<description>Pad 7 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD7PULL</name>
|
|
<description>Pad 7 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD6RSEL</name>
|
|
<description>Pad 6 pullup resistor selection.</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD6FNCSEL</name>
|
|
<description>Pad 6 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M0SDA</name>
|
|
<description>Configure as the IOMSTR0 I2C SDA signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0MISO</name>
|
|
<description>Configure as the IOMSTR0 SPI MISO signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0CTS</name>
|
|
<description>Configure as the UART0 CTS input signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO6</name>
|
|
<description>Configure as GPIO6</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMISOLB</name>
|
|
<description>Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLSDALB</name>
|
|
<description>Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_DAT</name>
|
|
<description>Configure as the I2S Data output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD6STRNG</name>
|
|
<description>Pad 6 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD6INPEN</name>
|
|
<description>Pad 6 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD6PULL</name>
|
|
<description>Pad 6 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD5RSEL</name>
|
|
<description>Pad 5 pullup resistor selection.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD5FNCSEL</name>
|
|
<description>Pad 5 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M0SCL</name>
|
|
<description>Configure as the IOMSTR0 I2C SCL signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0SCK</name>
|
|
<description>Configure as the IOMSTR0 SPI SCK signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0RTS</name>
|
|
<description>Configure as the UART0 RTS signal output</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO5</name>
|
|
<description>Configure as GPIO5</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0SCKLB</name>
|
|
<description>Configure as the IOMSTR0 SPI SCK loopback signal from IOSLAVE</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTHFA</name>
|
|
<description>Configure as the External HFA input clock</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0SCLLB</name>
|
|
<description>Configure as the IOMSTR0 I2C SCL loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE2</name>
|
|
<description>Configure as the SPI Channel 2 nCE signal from IOMSTR1</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD5STRNG</name>
|
|
<description>Pad 5 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD5INPEN</name>
|
|
<description>Pad 5 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD5PULL</name>
|
|
<description>Pad 5 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD4PWRDN</name>
|
|
<description>Pad 4 VSS power switch enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Power switch disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Power switch enabled (switch to GND)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD4FNCSEL</name>
|
|
<description>Pad 4 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UA0CTS</name>
|
|
<description>Configure as the UART0 CTS input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLINT</name>
|
|
<description>Configure as the IOSLAVE interrupt out signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO4</name>
|
|
<description>Configure as GPIO4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLINTGP</name>
|
|
<description>Configure as the IOSLAVE interrupt loopback signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR2</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as the CLKOUT signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32khz_XT</name>
|
|
<description>Configure as the 32kHz crystal output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD4STRNG</name>
|
|
<description>Pad 4 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD4INPEN</name>
|
|
<description>Pad 4 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD4PULL</name>
|
|
<description>Pad 4 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGC</name>
|
|
<description>Pad Configuration Register C</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3F3FFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD11FNCSEL</name>
|
|
<description>Pad 11 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE2</name>
|
|
<description>Configure as the analog input for ADC single ended input 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as the CLKOUT signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO11</name>
|
|
<description>Configure as GPIO11</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA1CTS</name>
|
|
<description>Configure as the UART1 CTS input signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0RX</name>
|
|
<description>Configure as the UART0 RX input signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM_DATA</name>
|
|
<description>Configure as the PDM Data input signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD11STRNG</name>
|
|
<description>Pad 11 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD11INPEN</name>
|
|
<description>Pad 11 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD11PULL</name>
|
|
<description>Pad 11 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD10FNCSEL</name>
|
|
<description>Pad 10 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M1WIR3</name>
|
|
<description>Configure as the IOMSTR1 SPI 3-wire MOSI/MISO signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1MOSI</name>
|
|
<description>Configure as the IOMSTR1 SPI MOSI signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO10</name>
|
|
<description>Configure as GPIO10</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA1RTS</name>
|
|
<description>Configure as the UART1 RTS output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from the IOMSTR4</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLWIR3LB</name>
|
|
<description>Configure as the IOMSTR1 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD10STRNG</name>
|
|
<description>Pad 10 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD10INPEN</name>
|
|
<description>Pad 10 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD10PULL</name>
|
|
<description>Pad 10 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD9RSEL</name>
|
|
<description>Pad 9 pullup resistor selection</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD9FNCSEL</name>
|
|
<description>Pad 9 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M1SDA</name>
|
|
<description>Configure as the IOMSTR1 I2C SDA signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1MISO</name>
|
|
<description>Configure as the IOMSTR1 SPI MISO signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO9</name>
|
|
<description>Configure as GPIO9</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMISOLB</name>
|
|
<description>Configure as the IOMSTR1 SPI MISO loopback signal from IOSLAVE</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1RX</name>
|
|
<description>Configure as UART1 RX input signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLSDALB</name>
|
|
<description>Configure as the IOMSTR1 I2C SDA loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD9STRNG</name>
|
|
<description>Pad 9 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD9INPEN</name>
|
|
<description>Pad 9 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD9PULL</name>
|
|
<description>Pad 9 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD8RSEL</name>
|
|
<description>Pad 8 pullup resistor selection.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD8FNCSEL</name>
|
|
<description>Pad 8 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M1SCL</name>
|
|
<description>Configure as the IOMSTR1 I2C SCL signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1SCK</name>
|
|
<description>Configure as the IOMSTR1 SPI SCK signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO8</name>
|
|
<description>Configure as GPIO8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1SCKLB</name>
|
|
<description>Configure as the IOMSTR1 SPI SCK loopback signal from IOSLAVE</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1TX</name>
|
|
<description>Configure as the UART1 TX output signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1SCLLB</name>
|
|
<description>Configure as the IOMSTR1 I2C SCL loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD8STRNG</name>
|
|
<description>Pad 8 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD8INPEN</name>
|
|
<description>Pad 8 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD8PULL</name>
|
|
<description>Pad 8 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGD</name>
|
|
<description>Pad Configuration Register D</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3F3F3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD15FNCSEL</name>
|
|
<description>Pad 15 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCD1N</name>
|
|
<description>Configure as the analog ADC differential pair 1 N input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1RX</name>
|
|
<description>Configure as the UART1 RX signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO15</name>
|
|
<description>Configure as GPIO15</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE2</name>
|
|
<description>Configure as the SPI Channel 2 nCE signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTXT</name>
|
|
<description>Configure as the external XTAL oscillator input</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWDIO</name>
|
|
<description>Configure as an alternate port for the SWDIO I/O signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWO</name>
|
|
<description>Configure as an SWO (Serial Wire Trace output)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD15STRNG</name>
|
|
<description>Pad 15 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD15INPEN</name>
|
|
<description>Pad 15 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD15PULL</name>
|
|
<description>Pad 15 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD14FNCSEL</name>
|
|
<description>Pad 14 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCD1P</name>
|
|
<description>Configure as the analog ADC differential pair 1 P input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1TX</name>
|
|
<description>Configure as the UART1 TX output signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO14</name>
|
|
<description>Configure as GPIO14</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTHFS</name>
|
|
<description>Configure as the External HFRC oscillator input select</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWDCK</name>
|
|
<description>Configure as the alternate input for the SWDCK input signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32khz_XT</name>
|
|
<description>Configure as the 32kHz crystal output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD14STRNG</name>
|
|
<description>Pad 14 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD14INPEN</name>
|
|
<description>Pad 14 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD14PULL</name>
|
|
<description>Pad 14 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD13FNCSEL</name>
|
|
<description>Pad 13 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCD0PSE8</name>
|
|
<description>Configure as the ADC Differential pair 0 P, or Single Ended input 8 analog input signal. Determination of the D0P vs SE8 usage is done when the particular channel is selected within the ADC module</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB0</name>
|
|
<description>Configure as the input/output signal from CTIMER B0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO13</name>
|
|
<description>Configure as GPIO13</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTHFB</name>
|
|
<description>Configure as the external HFRC oscillator input</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0RTS</name>
|
|
<description>Configure as the UART0 RTS signal output</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1RX</name>
|
|
<description>Configure as the UART1 RX input signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD13STRNG</name>
|
|
<description>Pad 13 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD13INPEN</name>
|
|
<description>Pad 13 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD13PULL</name>
|
|
<description>Pad 13 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD12FNCSEL</name>
|
|
<description>Pad 12 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCD0NSE9</name>
|
|
<description>Configure as the ADC Differential pair 0 N, or Single Ended input 9 analog input signal. Determination of the D0N vs SE9 usage is done when the particular channel is selected within the ADC module</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA0</name>
|
|
<description>Configure as the input/output signal from CTIMER A0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO12</name>
|
|
<description>Configure as GPIO12</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as CLKOUT signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM_CLK</name>
|
|
<description>Configure as the PDM CLK output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0CTS</name>
|
|
<description>Configure as the UART0 CTS input signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1TX</name>
|
|
<description>Configure as the UART1 TX output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD12STRNG</name>
|
|
<description>Pad 12 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD12INPEN</name>
|
|
<description>Pad 12 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD12PULL</name>
|
|
<description>Pad 12 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGE</name>
|
|
<description>Pad Configuration Register E</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3F3F3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD19FNCSEL</name>
|
|
<description>Pad 19 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPRF0</name>
|
|
<description>Configure as the analog comparator reference 0 signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO19</name>
|
|
<description>Configure as GPIO19</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANATEST1</name>
|
|
<description>Configure as the ANATEST1 I/O signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1RX</name>
|
|
<description>Configure as the UART1 RX input signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_BCLK</name>
|
|
<description>Configure as the I2S Byte clock input signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD19STRNG</name>
|
|
<description>Pad 19 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD19INPEN</name>
|
|
<description>Pad 19 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD19PULL</name>
|
|
<description>Pad 19 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD18FNCSEL</name>
|
|
<description>Pad 18 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPIN1</name>
|
|
<description>Configure as the analog comparator input 1 signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO18</name>
|
|
<description>Configure as GPIO18</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE1</name>
|
|
<description>Configure as the SPI nCE channel 1 from IOMSTR4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANATEST2</name>
|
|
<description>Configure as ANATEST2 I/O signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1TX</name>
|
|
<description>Configure as UART1 TX output signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32khz_XT</name>
|
|
<description>Configure as the 32kHz output clock from the crystal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD18STRNG</name>
|
|
<description>Pad 18 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD18INPEN</name>
|
|
<description>Pad 18 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD18PULL</name>
|
|
<description>Pad 18 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD17FNCSEL</name>
|
|
<description>Pad 17 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPRF1</name>
|
|
<description>Configure as the analog comparator reference signal 1 input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG1</name>
|
|
<description>Configure as the ADC Trigger 1 signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO17</name>
|
|
<description>Configure as GPIO17</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTLF</name>
|
|
<description>Configure as external LFRC oscillator input</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0RX</name>
|
|
<description>Configure as UART0 RX input signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA1CTS</name>
|
|
<description>Configure as UART1 CTS input signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD17STRNG</name>
|
|
<description>Pad 17 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD17INPEN</name>
|
|
<description>Pad 17 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD17PULL</name>
|
|
<description>Pad 17 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD16FNCSEL</name>
|
|
<description>Pad 16 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE0</name>
|
|
<description>Configure as the analog ADC single ended port 0 input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG0</name>
|
|
<description>Configure as the ADC Trigger 0 signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO16</name>
|
|
<description>Configure as GPIO16</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE3</name>
|
|
<description>Configure as SPI channel 3 nCE for IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPIN0</name>
|
|
<description>Configure as comparator input 0 signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0TX</name>
|
|
<description>Configure as UART0 TX output signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA1RTS</name>
|
|
<description>Configure as UART1 RTS output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD16STRNG</name>
|
|
<description>Pad 16 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD16INPEN</name>
|
|
<description>Pad 16 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD16PULL</name>
|
|
<description>Pad 16 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGF</name>
|
|
<description>Pad Configuration Register F</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18180202</resetValue>
|
|
<resetMask>0x3FBF3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD23FNCSEL</name>
|
|
<description>Pad 23 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART0RX</name>
|
|
<description>Configure as the UART0 RX signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB3</name>
|
|
<description>Configure as the input/output signal from CTIMER B3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO23</name>
|
|
<description>Configure as GPIO23</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM_DATA</name>
|
|
<description>Configure as PDM Data input to the PDM module</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPOUT</name>
|
|
<description>Configure as voltage comparitor output</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF7</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD23STRNG</name>
|
|
<description>Pad 23 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD23INPEN</name>
|
|
<description>Pad 23 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD23PULL</name>
|
|
<description>Pad 23 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD22PWRUP</name>
|
|
<description>Pad 22 upper power switch enable</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Power switch disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Power switch enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD22FNCSEL</name>
|
|
<description>Pad 22 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART0TX</name>
|
|
<description>Configure as the UART0 TX signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA3</name>
|
|
<description>Configure as the input/output signal from CTIMER A3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO22</name>
|
|
<description>Configure as GPIO22</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM_CLK</name>
|
|
<description>Configure as the PDM CLK output</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF5</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWO</name>
|
|
<description>Configure as the serial trace data output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD22STRNG</name>
|
|
<description>Pad 22 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD22INPEN</name>
|
|
<description>Pad 22 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD22PULL</name>
|
|
<description>Pad 22 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD21FNCSEL</name>
|
|
<description>Pad 21 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SWDIO</name>
|
|
<description>Configure as the serial wire debug data signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB2</name>
|
|
<description>Configure as the input/output signal from CTIMER B2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO21</name>
|
|
<description>Configure as GPIO21</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0RX</name>
|
|
<description>Configure as UART0 RX input signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1RX</name>
|
|
<description>Configure as UART1 RX input signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF6</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF7</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD21STRNG</name>
|
|
<description>Pad 21 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD21INPEN</name>
|
|
<description>Pad 21 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD21PULL</name>
|
|
<description>Pad 21 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD20FNCSEL</name>
|
|
<description>Pad 20 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SWDCK</name>
|
|
<description>Configure as the serial wire debug clock signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA2</name>
|
|
<description>Configure as the input/output signal from CTIMER A2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO20</name>
|
|
<description>Configure as GPIO20</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0TX</name>
|
|
<description>Configure as UART0 TX output signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1TX</name>
|
|
<description>Configure as UART1 TX output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF6</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF7</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD20STRNG</name>
|
|
<description>Pad 20 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD20INPEN</name>
|
|
<description>Pad 20 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD20PULL</name>
|
|
<description>Pad 20 pulldown enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pulldown disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pulldown enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGG</name>
|
|
<description>Pad Configuration Register G</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0xFF3FFF3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD27RSEL</name>
|
|
<description>Pad 27 pullup resistor selection.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD27FNCSEL</name>
|
|
<description>Pad 27 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EXTHF</name>
|
|
<description>Configure as the external HFRC oscillator input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO27</name>
|
|
<description>Configure as GPIO27</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SCL</name>
|
|
<description>Configure as I2C clock I/O signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SCK</name>
|
|
<description>Configure as SPI clock output signal from IOMSTR2</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SCKLB</name>
|
|
<description>Configure as IOMSTR2 SPI SCK loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SCLLB</name>
|
|
<description>Configure as IOMSTR2 I2C SCL loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD27STRNG</name>
|
|
<description>Pad 27 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD27INPEN</name>
|
|
<description>Pad 27 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD27PULL</name>
|
|
<description>Pad 27 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD26FNCSEL</name>
|
|
<description>Pad 26 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EXTLF</name>
|
|
<description>Configure as the external LFRC oscillator input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB0</name>
|
|
<description>Configure as the input/output signal from CTIMER B0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO26</name>
|
|
<description>Configure as GPIO26</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR2</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR5</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR3</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD26STRNG</name>
|
|
<description>Pad 26 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD26INPEN</name>
|
|
<description>Pad 26 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD26PULL</name>
|
|
<description>Pad 26 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD25RSEL</name>
|
|
<description>Pad 25 pullup resistor selection.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD25FNCSEL</name>
|
|
<description>Pad 25 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EXTXT</name>
|
|
<description>Configure as the external XTAL oscillator input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA0</name>
|
|
<description>Configure as the input/output signal from CTIMER A0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO25</name>
|
|
<description>Configure as GPIO25</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2SDA</name>
|
|
<description>Configure as the IOMSTR2 I2C Serial data I/O signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2MISO</name>
|
|
<description>Configure as the IOMSTR2 SPI MISO input signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMISOLB</name>
|
|
<description>Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLSDALB</name>
|
|
<description>Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD25STRNG</name>
|
|
<description>Pad 25 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD25INPEN</name>
|
|
<description>Pad 25 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD25PULL</name>
|
|
<description>Pad 25 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD24FNCSEL</name>
|
|
<description>Pad 24 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M2nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as the CLKOUT signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO24</name>
|
|
<description>Configure as GPIO24</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR5</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_BCLK</name>
|
|
<description>Configure as the I2S Byte clock input signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWO</name>
|
|
<description>Configure as the serial trace data output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD24STRNG</name>
|
|
<description>Pad 24 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD24INPEN</name>
|
|
<description>Pad 24 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD24PULL</name>
|
|
<description>Pad 24 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGH</name>
|
|
<description>Pad Configuration Register H</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3F3F3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD31FNCSEL</name>
|
|
<description>Pad 31 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE3</name>
|
|
<description>Configure as the analog input for ADC single ended input 3</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA3</name>
|
|
<description>Configure as the input/output signal from CTIMER A3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO31</name>
|
|
<description>Configure as GPIO31</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0RX</name>
|
|
<description>Configure as the UART0 RX input signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF6</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF7</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD31STRNG</name>
|
|
<description>Pad 31 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD31INPEN</name>
|
|
<description>Pad 31 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD31PULL</name>
|
|
<description>Pad 31 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD30FNCSEL</name>
|
|
<description>Pad 30 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNDEF0</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB2</name>
|
|
<description>Configure as the input/output signal from CTIMER B2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO30</name>
|
|
<description>Configure as GPIO30</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART0TX</name>
|
|
<description>Configure as UART0 TX output signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA1RTS</name>
|
|
<description>Configure as UART1 RTS output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF6</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_DAT</name>
|
|
<description>Configure as the I2S Data output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD30STRNG</name>
|
|
<description>Pad 30 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD30INPEN</name>
|
|
<description>Pad 30 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD30PULL</name>
|
|
<description>Pad 30 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD29FNCSEL</name>
|
|
<description>Pad 29 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE1</name>
|
|
<description>Configure as the analog input for ADC single ended input 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA2</name>
|
|
<description>Configure as the input/output signal from CTIMER A2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO29</name>
|
|
<description>Configure as GPIO29</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0CTS</name>
|
|
<description>Configure as the UART0 CTS signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA1CTS</name>
|
|
<description>Configure as the UART1 CTS signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR4</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM_DATA</name>
|
|
<description>Configure as PDM DATA input</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD29STRNG</name>
|
|
<description>Pad 29 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD29INPEN</name>
|
|
<description>Pad 29 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD29PULL</name>
|
|
<description>Pad 29 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD28FNCSEL</name>
|
|
<description>Pad 28 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>I2S_WCLK</name>
|
|
<description>Configure as the I2S Word Clock input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO28</name>
|
|
<description>Configure as GPIO28</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2WIR3</name>
|
|
<description>Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2MOSI</name>
|
|
<description>Configure as the IOMSTR2 SPI MOSI output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR5</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLWIR3LB</name>
|
|
<description>Configure as the IOMSTR2 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD28STRNG</name>
|
|
<description>Pad 28 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD28INPEN</name>
|
|
<description>Pad 28 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD28PULL</name>
|
|
<description>Pad 28 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGI</name>
|
|
<description>Pad Configuration Register I</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3F3F3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD35FNCSEL</name>
|
|
<description>Pad 35 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE7</name>
|
|
<description>Configure as the analog input for ADC single ended input 7</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1TX</name>
|
|
<description>Configure as the UART1 TX signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO35</name>
|
|
<description>Configure as GPIO35</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0RTS</name>
|
|
<description>Configure as the UART0 RTS output</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR3</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD35STRNG</name>
|
|
<description>Pad 35 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD35INPEN</name>
|
|
<description>Pad 35 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD35PULL</name>
|
|
<description>Pad 35 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD34FNCSEL</name>
|
|
<description>Pad 34 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE6</name>
|
|
<description>Configure as the analog input for ADC single ended input 6</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO34</name>
|
|
<description>Configure as GPIO34</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPRF2</name>
|
|
<description>Configure as the analog comparator reference 2 signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR3</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR4</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR5</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD34STRNG</name>
|
|
<description>Pad 34 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD34INPEN</name>
|
|
<description>Pad 34 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD34PULL</name>
|
|
<description>Pad 34 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD33FNCSEL</name>
|
|
<description>Pad 33 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE5</name>
|
|
<description>Configure as the analog ADC single ended port 5 input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32khz_XT</name>
|
|
<description>Configure as the 32kHz crystal output signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO33</name>
|
|
<description>Configure as GPIO33</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF4</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR3</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWO</name>
|
|
<description>Configure as the serial trace data output signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD33STRNG</name>
|
|
<description>Pad 33 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD33INPEN</name>
|
|
<description>Pad 33 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD33PULL</name>
|
|
<description>Pad 33 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD32FNCSEL</name>
|
|
<description>Pad 32 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCSE4</name>
|
|
<description>Configure as the analog input for ADC single ended input 4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB3</name>
|
|
<description>Configure as the input/output signal from CTIMER B3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO32</name>
|
|
<description>Configure as GPIO32</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF4</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF6</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEF7</name>
|
|
<description>Undefined/should not be used</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD32STRNG</name>
|
|
<description>Pad 32 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD32INPEN</name>
|
|
<description>Pad 32 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD32PULL</name>
|
|
<description>Pad 32 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGJ</name>
|
|
<description>Pad Configuration Register J</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0xFF3F3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD39RSEL</name>
|
|
<description>Pad 39 pullup resistor selection.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD39FNCSEL</name>
|
|
<description>Pad 39 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART0TX</name>
|
|
<description>Configure as the UART0 TX Signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1TX</name>
|
|
<description>Configure as the UART1 TX signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as the CLKOUT signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO39</name>
|
|
<description>Configure as GPIO39</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4SCL</name>
|
|
<description>Configure as the IOMSTR4 I2C SCL signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4SCK</name>
|
|
<description>Configure as the IOMSTR4 SPI SCK signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4SCKLB</name>
|
|
<description>Configure as the IOMSTR4 SPI SCK loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4SCLLB</name>
|
|
<description>Configure as the IOMSTR4 I2C SCL loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD39STRNG</name>
|
|
<description>Pad 39 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD39INPEN</name>
|
|
<description>Pad 39 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD39PULL</name>
|
|
<description>Pad 39 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD38FNCSEL</name>
|
|
<description>Pad 38 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRIG3</name>
|
|
<description>Configure as the ADC Trigger 3 signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0CTS</name>
|
|
<description>Configure as the UART0 CTS signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO38</name>
|
|
<description>Configure as GPIO38</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3WIR3</name>
|
|
<description>Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3MOSI</name>
|
|
<description>Configure as the IOMSTR3 SPI MOSI output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR4</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLWIR3LB</name>
|
|
<description>Configure as the IOMSTR3 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD38STRNG</name>
|
|
<description>Pad 38 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD38INPEN</name>
|
|
<description>Pad 38 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD38PULL</name>
|
|
<description>Pad 38 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD37FNCSEL</name>
|
|
<description>Pad 37 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRIG2</name>
|
|
<description>Configure as the ADC Trigger 2 signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0RTS</name>
|
|
<description>Configure as the UART0 RTS signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO37</name>
|
|
<description>Configure as GPIO37</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR3</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR4</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM_CLK</name>
|
|
<description>Configure as the PDM CLK output signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD37STRNG</name>
|
|
<description>Pad 37 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD37INPEN</name>
|
|
<description>Pad 37 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD37PULL</name>
|
|
<description>Pad 37 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD36FNCSEL</name>
|
|
<description>Pad 36 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRIG1</name>
|
|
<description>Configure as the ADC Trigger 1 signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M1nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1RX</name>
|
|
<description>Configure as the UART1 RX signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO36</name>
|
|
<description>Configure as GPIO36</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32khz_XT</name>
|
|
<description>Configure as the 32kHz output clock from the crystal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M2nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR2</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0CTS</name>
|
|
<description>Configure as the UART0 CTS signal</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR3</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD36STRNG</name>
|
|
<description>Pad 36 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD36INPEN</name>
|
|
<description>Pad 36 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD36PULL</name>
|
|
<description>Pad 36 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGK</name>
|
|
<description>Pad Configuration Register K</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0xFFFFBFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD43RSEL</name>
|
|
<description>Pad 43 pullup resistor selection.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD43FNCSEL</name>
|
|
<description>Pad 43 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M2nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB0</name>
|
|
<description>Configure as the input/output signal from CTIMER B0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO43</name>
|
|
<description>Configure as GPIO43</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3SDA</name>
|
|
<description>Configure as the IOMSTR3 I2C SDA signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3MISO</name>
|
|
<description>Configure as the IOMSTR3 SPI MISO signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMISOLB</name>
|
|
<description>Configure as the IOMSTR3 SPI MISO loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLSDALB</name>
|
|
<description>Configure as the IOMSTR3 I2C SDA loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD43STRNG</name>
|
|
<description>Pad 43 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD43INPEN</name>
|
|
<description>Pad 43 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD43PULL</name>
|
|
<description>Pad 43 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD42RSEL</name>
|
|
<description>Pad 42 pullup resistor selection.</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD42FNCSEL</name>
|
|
<description>Pad 42 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M2nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE0</name>
|
|
<description>Configure as the SPI channel 0 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA0</name>
|
|
<description>Configure as the input/output signal from CTIMER A0</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO42</name>
|
|
<description>Configure as GPIO42</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3SCL</name>
|
|
<description>Configure as the IOMSTR3 I2C SCL clock I/O signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3SCK</name>
|
|
<description>Configure as the IOMSTR3 SPI SCK output</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3SCKLB</name>
|
|
<description>Configure as the IOMSTR3 SPI clock loopback to the IOSLAVE device</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3SCLLB</name>
|
|
<description>Configure as the IOMSTR3 I2C clock loopback to the IOSLAVE device</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD42STRNG</name>
|
|
<description>Pad 42 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD42INPEN</name>
|
|
<description>Pad 42 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD42PULL</name>
|
|
<description>Pad 42 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD41PWRUP</name>
|
|
<description>Pad 41 upper power switch enable</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Power switch disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Power switch enabled (VDD switch)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD41FNCSEL</name>
|
|
<description>Pad 41 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M2nCE1</name>
|
|
<description>Configure as the SPI channel 1 nCE signal from IOMSTR2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Configure as the CLKOUT signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWO</name>
|
|
<description>Configure as the serial wire debug SWO signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO41</name>
|
|
<description>Configure as GPIO41</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR3</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR4</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UA0RTS</name>
|
|
<description>Configure as the UART0 RTS output</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD41STRNG</name>
|
|
<description>Pad 41 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD41INPEN</name>
|
|
<description>Pad 41 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD41PULL</name>
|
|
<description>Pad 41 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD40RSEL</name>
|
|
<description>Pad 40 pullup resistor selection.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD40FNCSEL</name>
|
|
<description>Pad 40 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART0RX</name>
|
|
<description>Configure as the UART0 RX input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1RX</name>
|
|
<description>Configure as the UART1 RX input signal</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG0</name>
|
|
<description>Configure as the ADC Trigger 0 signal</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO40</name>
|
|
<description>Configure as GPIO40</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4SDA</name>
|
|
<description>Configure as the IOMSTR4 I2C serial data I/O signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4MISO</name>
|
|
<description>Configure as the IOMSTR4 SPI MISO input signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMISOLB</name>
|
|
<description>Configure as the IOMSTR4 SPI MISO loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLSDALB</name>
|
|
<description>Configure as the IOMSTR4 I2C SDA loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD40STRNG</name>
|
|
<description>Pad 40 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD40INPEN</name>
|
|
<description>Pad 40 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD40PULL</name>
|
|
<description>Pad 40 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGL</name>
|
|
<description>Pad Configuration Register L</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18181818</resetValue>
|
|
<resetMask>0x3F3F3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD47FNCSEL</name>
|
|
<description>Pad 47 function select</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M2nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB2</name>
|
|
<description>Configure as the input/output signal from CTIMER B2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO47</name>
|
|
<description>Configure as GPIO47</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5WIR3</name>
|
|
<description>Configure as the IOMSTR5 SPI 3-wire MOSI/MISO signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5MOSI</name>
|
|
<description>Configure as the IOMSTR5 SPI MOSI output signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR4</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLWIR3LB</name>
|
|
<description>Configure as the IOMSTR5 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD47STRNG</name>
|
|
<description>Pad 47 drive strength</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD47INPEN</name>
|
|
<description>Pad 47 input enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD47PULL</name>
|
|
<description>Pad 47 pullup enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD46FNCSEL</name>
|
|
<description>Pad 46 function select</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>32khz_XT</name>
|
|
<description>Configure as the 32kHz output clock from the crystal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA2</name>
|
|
<description>Configure as the input/output signal from CTIMER A2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO46</name>
|
|
<description>Configure as GPIO46</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR5</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE4</name>
|
|
<description>Configure as the SPI channel 4 nCE signal from IOMSTR4</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWO</name>
|
|
<description>Configure as the serial wire debug SWO signal</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD46STRNG</name>
|
|
<description>Pad 46 drive strength</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD46INPEN</name>
|
|
<description>Pad 46 input enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD46PULL</name>
|
|
<description>Pad 46 pullup enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD45FNCSEL</name>
|
|
<description>Pad 45 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UA1CTS</name>
|
|
<description>Configure as the UART1 CTS input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB1</name>
|
|
<description>Configure as the input/output signal from CTIMER B1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO45</name>
|
|
<description>Configure as GPIO45</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4nCE3</name>
|
|
<description>Configure as the SPI channel 3 nCE signal from IOMSTR4</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M3nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR3</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE5</name>
|
|
<description>Configure as the SPI channel 5 nCE signal from IOMSTR5</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD45STRNG</name>
|
|
<description>Pad 45 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD45INPEN</name>
|
|
<description>Pad 45 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD45PULL</name>
|
|
<description>Pad 45 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD44FNCSEL</name>
|
|
<description>Pad 44 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UA1RTS</name>
|
|
<description>Configure as the UART1 RTS output signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE2</name>
|
|
<description>Configure as the SPI channel 2 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA1</name>
|
|
<description>Configure as the input/output signal from CTIMER A1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO44</name>
|
|
<description>Configure as GPIO44</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4WIR3</name>
|
|
<description>Configure as the IOMSTR4 SPI 3-wire MOSI/MISO signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M4MOSI</name>
|
|
<description>Configure as the IOMSTR4 SPI MOSI signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR5</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLWIR3LB</name>
|
|
<description>Configure as the IOMSTR4 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD44STRNG</name>
|
|
<description>Pad 44 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD44INPEN</name>
|
|
<description>Pad 44 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD44PULL</name>
|
|
<description>Pad 44 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADREGM</name>
|
|
<description>Pad Configuration Register M</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001818</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD49RSEL</name>
|
|
<description>Pad 49 pullup resistor selection.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD49FNCSEL</name>
|
|
<description>Pad 49 function select</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M2nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE7</name>
|
|
<description>Configure as the SPI channel 7 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTB3</name>
|
|
<description>Configure as the input/output signal from CTIMER B3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO49</name>
|
|
<description>Configure as GPIO49</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5SDA</name>
|
|
<description>Configure as the IOMSTR5 I2C serial data I/O signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5MISO</name>
|
|
<description>Configure as the IOMSTR5 SPI MISO input signal</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLMISOLB</name>
|
|
<description>Configure as the IOMSTR5 SPI MISO loopback signal from IOSLAVE</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLSDALB</name>
|
|
<description>Configure as the IOMSTR5 I2C SDA loopback signal from IOSLAVE</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD49STRNG</name>
|
|
<description>Pad 49 drive strength</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD49INPEN</name>
|
|
<description>Pad 49 input enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD49PULL</name>
|
|
<description>Pad 49 pullup enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD48RSEL</name>
|
|
<description>Pad 48 pullup resistor selection.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PULL1_5K</name>
|
|
<description>Pullup is ~1.5 KOhms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL6K</name>
|
|
<description>Pullup is ~6 KOhms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL12K</name>
|
|
<description>Pullup is ~12 KOhms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL24K</name>
|
|
<description>Pullup is ~24 KOhms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD48FNCSEL</name>
|
|
<description>Pad 48 function select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M2nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M0nCE6</name>
|
|
<description>Configure as the SPI channel 6 nCE signal from IOMSTR0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCTA3</name>
|
|
<description>Configure as the input/output signal from CTIMER A3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO48</name>
|
|
<description>Configure as GPIO48</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5SCL</name>
|
|
<description>Configure as the IOMSTR5 I2C SCL clock I/O signal</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5SCK</name>
|
|
<description>Configure as the IOMSTR5 SPI SCK output</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5SCKLB</name>
|
|
<description>Configure as the IOMSTR5 SPI clock loopback to the IOSLAVE device</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M5SCLLB</name>
|
|
<description>Configure as the IOMSTR5 I2C clock loopback to the IOSLAVE device</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD48STRNG</name>
|
|
<description>Pad 48 drive strength</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low drive strength</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High drive strength</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD48INPEN</name>
|
|
<description>Pad 48 input enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pad input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pad input enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD48PULL</name>
|
|
<description>Pad 48 pullup enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Pullup disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Pullup enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGA</name>
|
|
<description>GPIO Configuration Register A</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO7INTD</name>
|
|
<description>GPIO7 interrupt direction.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO7OUTCFG</name>
|
|
<description>GPIO7 output configuration.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO7INCFG</name>
|
|
<description>GPIO7 input enable.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO6INTD</name>
|
|
<description>GPIO6 interrupt direction.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO6OUTCFG</name>
|
|
<description>GPIO6 output configuration.</description>
|
|
<bitRange>[26:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO6INCFG</name>
|
|
<description>GPIO6 input enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO5INTD</name>
|
|
<description>GPIO5 interrupt direction.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO5OUTCFG</name>
|
|
<description>GPIO5 output configuration.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO5INCFG</name>
|
|
<description>GPIO5 input enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO4INTD</name>
|
|
<description>GPIO4 interrupt direction.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO4OUTCFG</name>
|
|
<description>GPIO4 output configuration.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO4INCFG</name>
|
|
<description>GPIO4 input enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO3INTD</name>
|
|
<description>GPIO3 interrupt direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO3OUTCFG</name>
|
|
<description>GPIO3 output configuration.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO3INCFG</name>
|
|
<description>GPIO3 input enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO2INTD</name>
|
|
<description>GPIO2 interrupt direction.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO2OUTCFG</name>
|
|
<description>GPIO2 output configuration.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO2INCFG</name>
|
|
<description>GPIO2 input enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO1INTD</name>
|
|
<description>GPIO1 interrupt direction.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO1OUTCFG</name>
|
|
<description>GPIO1 output configuration.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO1INCFG</name>
|
|
<description>GPIO1 input enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO0INTD</name>
|
|
<description>GPIO0 interrupt direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO0OUTCFG</name>
|
|
<description>GPIO0 output configuration.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO0INCFG</name>
|
|
<description>GPIO0 input enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGB</name>
|
|
<description>GPIO Configuration Register B</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO15INTD</name>
|
|
<description>GPIO15 interrupt direction.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO15OUTCFG</name>
|
|
<description>GPIO15 output configuration.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO15INCFG</name>
|
|
<description>GPIO15 input enable.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO14INTD</name>
|
|
<description>GPIO14 interrupt direction.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO14OUTCFG</name>
|
|
<description>GPIO14 output configuration.</description>
|
|
<bitRange>[26:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO14INCFG</name>
|
|
<description>GPIO14 input enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO13INTD</name>
|
|
<description>GPIO13 interrupt direction.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO13OUTCFG</name>
|
|
<description>GPIO13 output configuration.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO13INCFG</name>
|
|
<description>GPIO13 input enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO12INTD</name>
|
|
<description>GPIO12 interrupt direction.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO12OUTCFG</name>
|
|
<description>GPIO12 output configuration.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO12INCFG</name>
|
|
<description>GPIO12 input enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO11INTD</name>
|
|
<description>GPIO11 interrupt direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO11OUTCFG</name>
|
|
<description>GPIO11 output configuration.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO11INCFG</name>
|
|
<description>GPIO11 input enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO10INTD</name>
|
|
<description>GPIO10 interrupt direction.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO10OUTCFG</name>
|
|
<description>GPIO10 output configuration.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO10INCFG</name>
|
|
<description>GPIO10 input enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO9INTD</name>
|
|
<description>GPIO9 interrupt direction.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO9OUTCFG</name>
|
|
<description>GPIO9 output configuration.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO9INCFG</name>
|
|
<description>GPIO9 input enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO8INTD</name>
|
|
<description>GPIO8 interrupt direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO8OUTCFG</name>
|
|
<description>GPIO8 output configuration.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO8INCFG</name>
|
|
<description>GPIO8 input enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGC</name>
|
|
<description>GPIO Configuration Register C</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00110000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO23INTD</name>
|
|
<description>GPIO23 interrupt direction.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO23OUTCFG</name>
|
|
<description>GPIO23 output configuration.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO23INCFG</name>
|
|
<description>GPIO23 input enable.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO22INTD</name>
|
|
<description>GPIO22 interrupt direction.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO22OUTCFG</name>
|
|
<description>GPIO22 output configuration.</description>
|
|
<bitRange>[26:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO22INCFG</name>
|
|
<description>GPIO22 input enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO21INTD</name>
|
|
<description>GPIO21 interrupt direction.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO21OUTCFG</name>
|
|
<description>GPIO21 output configuration.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO21INCFG</name>
|
|
<description>GPIO21 input enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO20INTD</name>
|
|
<description>GPIO20 interrupt direction.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO20OUTCFG</name>
|
|
<description>GPIO20 output configuration.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO20INCFG</name>
|
|
<description>GPIO20 input enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO19INTD</name>
|
|
<description>GPIO19 interrupt direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO19OUTCFG</name>
|
|
<description>GPIO19 output configuration.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO19INCFG</name>
|
|
<description>GPIO19 input enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO18INTD</name>
|
|
<description>GPIO18 interrupt direction.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO18OUTCFG</name>
|
|
<description>GPIO18 output configuration.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO18INCFG</name>
|
|
<description>GPIO18 input enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO17INTD</name>
|
|
<description>GPIO17 interrupt direction.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO17OUTCFG</name>
|
|
<description>GPIO17 output configuration.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO17INCFG</name>
|
|
<description>GPIO17 input enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO16INTD</name>
|
|
<description>GPIO16 interrupt direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO16OUTCFG</name>
|
|
<description>GPIO16 output configuration.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO16INCFG</name>
|
|
<description>GPIO16 input enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGD</name>
|
|
<description>GPIO Configuration Register D</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO31INTD</name>
|
|
<description>GPIO31 interrupt direction.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO31OUTCFG</name>
|
|
<description>GPIO31 output configuration.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO31INCFG</name>
|
|
<description>GPIO31 input enable.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO30INTD</name>
|
|
<description>GPIO30 interrupt direction.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO30OUTCFG</name>
|
|
<description>GPIO30 output configuration.</description>
|
|
<bitRange>[26:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO30INCFG</name>
|
|
<description>GPIO30 input enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO29INTD</name>
|
|
<description>GPIO29 interrupt direction.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO29OUTCFG</name>
|
|
<description>GPIO29 output configuration.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO29INCFG</name>
|
|
<description>GPIO29 input enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO28INTD</name>
|
|
<description>GPIO28 interrupt direction.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO28OUTCFG</name>
|
|
<description>GPIO28 output configuration.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO28INCFG</name>
|
|
<description>GPIO28 input enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO27INTD</name>
|
|
<description>GPIO27 interrupt direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO27OUTCFG</name>
|
|
<description>GPIO27 output configuration.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO27INCFG</name>
|
|
<description>GPIO27 input enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO26INTD</name>
|
|
<description>GPIO26 interrupt direction.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO26OUTCFG</name>
|
|
<description>GPIO26 output configuration.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO26INCFG</name>
|
|
<description>GPIO26 input enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO25INTD</name>
|
|
<description>GPIO25 interrupt direction.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO25OUTCFG</name>
|
|
<description>GPIO25 output configuration.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO25INCFG</name>
|
|
<description>GPIO25 input enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO24INTD</name>
|
|
<description>GPIO24 interrupt direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO24OUTCFG</name>
|
|
<description>GPIO24 output configuration.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO24INCFG</name>
|
|
<description>GPIO24 input enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGE</name>
|
|
<description>GPIO Configuration Register E</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO39INTD</name>
|
|
<description>GPIO39 interrupt direction.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO39OUTCFG</name>
|
|
<description>GPIO39 output configuration.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO39INCFG</name>
|
|
<description>GPIO39 input enable.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO38INTD</name>
|
|
<description>GPIO38 interrupt direction.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO38OUTCFG</name>
|
|
<description>GPIO38 output configuration.</description>
|
|
<bitRange>[26:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO38INCFG</name>
|
|
<description>GPIO38 input enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO37INTD</name>
|
|
<description>GPIO37 interrupt direction.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO37OUTCFG</name>
|
|
<description>GPIO37 output configuration.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO37INCFG</name>
|
|
<description>GPIO37 input enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO36INTD</name>
|
|
<description>GPIO36 interrupt direction.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO36OUTCFG</name>
|
|
<description>GPIO36 output configuration.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO36INCFG</name>
|
|
<description>GPIO36 input enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO35INTD</name>
|
|
<description>GPIO35 interrupt direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO35OUTCFG</name>
|
|
<description>GPIO35 output configuration.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO35INCFG</name>
|
|
<description>GPIO35 input enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO34INTD</name>
|
|
<description>GPIO34 interrupt direction.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO34OUTCFG</name>
|
|
<description>GPIO34 output configuration.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO34INCFG</name>
|
|
<description>GPIO34 input enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO33INTD</name>
|
|
<description>GPIO33 interrupt direction.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO33OUTCFG</name>
|
|
<description>GPIO33 output configuration.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO33INCFG</name>
|
|
<description>GPIO33 input enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO32INTD</name>
|
|
<description>GPIO32 interrupt direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO32OUTCFG</name>
|
|
<description>GPIO32 output configuration.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO32INCFG</name>
|
|
<description>GPIO32 input enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGF</name>
|
|
<description>GPIO Configuration Register F</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO47INTD</name>
|
|
<description>GPIO47 interrupt direction.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO47OUTCFG</name>
|
|
<description>GPIO47 output configuration.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO47INCFG</name>
|
|
<description>GPIO47 input enable.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO46INTD</name>
|
|
<description>GPIO46 interrupt direction.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO46OUTCFG</name>
|
|
<description>GPIO46 output configuration.</description>
|
|
<bitRange>[26:25]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO46INCFG</name>
|
|
<description>GPIO46 input enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO45INTD</name>
|
|
<description>GPIO45 interrupt direction.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO45OUTCFG</name>
|
|
<description>GPIO45 output configuration.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO45INCFG</name>
|
|
<description>GPIO45 input enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO44INTD</name>
|
|
<description>GPIO44 interrupt direction.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO44OUTCFG</name>
|
|
<description>GPIO44 output configuration.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO44INCFG</name>
|
|
<description>GPIO44 input enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO43INTD</name>
|
|
<description>GPIO43 interrupt direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO43OUTCFG</name>
|
|
<description>GPIO43 output configuration.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO43INCFG</name>
|
|
<description>GPIO43 input enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO42INTD</name>
|
|
<description>GPIO42 interrupt direction.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO42OUTCFG</name>
|
|
<description>GPIO42 output configuration.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO42INCFG</name>
|
|
<description>GPIO42 input enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO41INTD</name>
|
|
<description>GPIO41 interrupt direction.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO41OUTCFG</name>
|
|
<description>GPIO41 output configuration.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO41INCFG</name>
|
|
<description>GPIO41 input enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO40INTD</name>
|
|
<description>GPIO40 interrupt direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO40OUTCFG</name>
|
|
<description>GPIO40 output configuration.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO40INCFG</name>
|
|
<description>GPIO40 input enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGG</name>
|
|
<description>GPIO Configuration Register G</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO49INTD</name>
|
|
<description>GPIO49 interrupt direction.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO49OUTCFG</name>
|
|
<description>GPIO49 output configuration.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO49INCFG</name>
|
|
<description>GPIO49 input enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO48INTD</name>
|
|
<description>GPIO48 interrupt direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTLH</name>
|
|
<description>Interrupt on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHL</name>
|
|
<description>Interrupt on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO48OUTCFG</name>
|
|
<description>GPIO48 output configuration.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Output is push-pull</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OD</name>
|
|
<description>Output is open drain</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Output is tri-state</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO48INCFG</name>
|
|
<description>GPIO48 input enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read the GPIO pin data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDZERO</name>
|
|
<description>Readback will always be zero</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADKEY</name>
|
|
<description>Key Register for all pad configuration registers</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PADKEY</name>
|
|
<description>Key register value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Key</name>
|
|
<description>Key</description>
|
|
<value>115</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDA</name>
|
|
<description>GPIO Input Register A</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>RDA</name>
|
|
<description>GPIO31-0 read data.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDB</name>
|
|
<description>GPIO Input Register B</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>RDB</name>
|
|
<description>GPIO49-32 read data.</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WTA</name>
|
|
<description>GPIO Output Register A</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WTA</name>
|
|
<description>GPIO31-0 write data.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WTB</name>
|
|
<description>GPIO Output Register B</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WTB</name>
|
|
<description>GPIO49-32 write data.</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WTSA</name>
|
|
<description>GPIO Output Register A Set</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WTSA</name>
|
|
<description>Set the GPIO31-0 write data.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WTSB</name>
|
|
<description>GPIO Output Register B Set</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WTSB</name>
|
|
<description>Set the GPIO49-32 write data.</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WTCA</name>
|
|
<description>GPIO Output Register A Clear</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WTCA</name>
|
|
<description>Clear the GPIO31-0 write data.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WTCB</name>
|
|
<description>GPIO Output Register B Clear</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WTCB</name>
|
|
<description>Clear the GPIO49-32 write data.</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENA</name>
|
|
<description>GPIO Enable Register A</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>GPIO31-0 output enables</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENB</name>
|
|
<description>GPIO Enable Register B</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>GPIO49-32 output enables</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENSA</name>
|
|
<description>GPIO Enable Register A Set</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENSA</name>
|
|
<description>Set the GPIO31-0 output enables</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENSB</name>
|
|
<description>GPIO Enable Register B Set</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENSB</name>
|
|
<description>Set the GPIO49-32 output enables</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENCA</name>
|
|
<description>GPIO Enable Register A Clear</description>
|
|
<addressOffset>0x000000B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENCA</name>
|
|
<description>Clear the GPIO31-0 output enables</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENCB</name>
|
|
<description>GPIO Enable Register B Clear</description>
|
|
<addressOffset>0x000000B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENCB</name>
|
|
<description>Clear the GPIO49-32 output enables</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STMRCAP</name>
|
|
<description>STIMER Capture Control</description>
|
|
<addressOffset>0x000000BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3F3F3F3F</resetValue>
|
|
<resetMask>0x7F7F7F7F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>STPOL3</name>
|
|
<description>STIMER Capture 3 Polarity.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPLH</name>
|
|
<description>Capture on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPHL</name>
|
|
<description>Capture on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STSEL3</name>
|
|
<description>STIMER Capture 3 Select.</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STPOL2</name>
|
|
<description>STIMER Capture 2 Polarity.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPLH</name>
|
|
<description>Capture on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPHL</name>
|
|
<description>Capture on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STSEL2</name>
|
|
<description>STIMER Capture 2 Select.</description>
|
|
<bitRange>[21:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STPOL1</name>
|
|
<description>STIMER Capture 1 Polarity.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPLH</name>
|
|
<description>Capture on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPHL</name>
|
|
<description>Capture on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STSEL1</name>
|
|
<description>STIMER Capture 1 Select.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STPOL0</name>
|
|
<description>STIMER Capture 0 Polarity.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPLH</name>
|
|
<description>Capture on low to high GPIO transition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPHL</name>
|
|
<description>Capture on high to low GPIO transition</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STSEL0</name>
|
|
<description>STIMER Capture 0 Select.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOM0IRQ</name>
|
|
<description>IOM0 Flow Control IRQ Select</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOM0IRQ</name>
|
|
<description>IOMSTR0 IRQ pad select.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOM1IRQ</name>
|
|
<description>IOM1 Flow Control IRQ Select</description>
|
|
<addressOffset>0x000000C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOM1IRQ</name>
|
|
<description>IOMSTR1 IRQ pad select.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOM2IRQ</name>
|
|
<description>IOM2 Flow Control IRQ Select</description>
|
|
<addressOffset>0x000000C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOM2IRQ</name>
|
|
<description>IOMSTR2 IRQ pad select.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOM3IRQ</name>
|
|
<description>IOM3 Flow Control IRQ Select</description>
|
|
<addressOffset>0x000000CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOM3IRQ</name>
|
|
<description>IOMSTR3 IRQ pad select.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOM4IRQ</name>
|
|
<description>IOM4 Flow Control IRQ Select</description>
|
|
<addressOffset>0x000000D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOM4IRQ</name>
|
|
<description>IOMSTR4 IRQ pad select.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOM5IRQ</name>
|
|
<description>IOM5 Flow Control IRQ Select</description>
|
|
<addressOffset>0x000000D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOM5IRQ</name>
|
|
<description>IOMSTR5 IRQ pad select.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOOPBACK</name>
|
|
<description>IOM to IOS Loopback Control</description>
|
|
<addressOffset>0x000000D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>LOOPBACK</name>
|
|
<description>IOM to IOS loopback control.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOOP0</name>
|
|
<description>Loop IOM0 to IOS</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOP1</name>
|
|
<description>Loop IOM1 to IOS</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOP2</name>
|
|
<description>Loop IOM2 to IOS</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOP3</name>
|
|
<description>Loop IOM3 to IOS</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOP4</name>
|
|
<description>Loop IOM4 to IOS</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOP5</name>
|
|
<description>Loop IOM5 to IOS</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOPNONE</name>
|
|
<description>No loopback connections</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIOOBS</name>
|
|
<description>GPIO Observation Mode Sample register</description>
|
|
<addressOffset>0x000000DC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OBS_DATA</name>
|
|
<description>Sample of the data output on the GPIO observation port. May have async sampling issues, as the data is not synronized to the read operation. Intended for debug purposes only</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGA</name>
|
|
<description>Alternate Pad Configuration reg0 (Pads 3,2,1,0)</description>
|
|
<addressOffset>0x000000E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD3_SR</name>
|
|
<description>Pad 3 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD3_DS1</name>
|
|
<description>Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD2_SR</name>
|
|
<description>Pad 2 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD2_DS1</name>
|
|
<description>Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD1_SR</name>
|
|
<description>Pad 1 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD1_DS1</name>
|
|
<description>Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD0_SR</name>
|
|
<description>Pad 0 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD0_DS1</name>
|
|
<description>Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGB</name>
|
|
<description>Alternate Pad Configuration reg1 (Pads 7,6,5,4)</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD7_SR</name>
|
|
<description>Pad 7 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD7_DS1</name>
|
|
<description>Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD6_SR</name>
|
|
<description>Pad 6 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD6_DS1</name>
|
|
<description>Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD5_SR</name>
|
|
<description>Pad 5 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD5_DS1</name>
|
|
<description>Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD4_SR</name>
|
|
<description>Pad 4 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD4_DS1</name>
|
|
<description>Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGC</name>
|
|
<description>Alternate Pad Configuration reg2 (Pads 11,10,9,8)</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD11_SR</name>
|
|
<description>Pad 11 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD11_DS1</name>
|
|
<description>Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD10_SR</name>
|
|
<description>Pad 10 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD10_DS1</name>
|
|
<description>Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD9_SR</name>
|
|
<description>Pad 9 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD9_DS1</name>
|
|
<description>Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD8_SR</name>
|
|
<description>Pad 8 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD8_DS1</name>
|
|
<description>Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGD</name>
|
|
<description>Alternate Pad Configuration reg3 (Pads 15,14,13,12)</description>
|
|
<addressOffset>0x000000EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD15_SR</name>
|
|
<description>Pad 15 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD15_DS1</name>
|
|
<description>Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD14_SR</name>
|
|
<description>Pad 14 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD14_DS1</name>
|
|
<description>Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD13_SR</name>
|
|
<description>Pad 13 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD13_DS1</name>
|
|
<description>Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD12_SR</name>
|
|
<description>Pad 12 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD12_DS1</name>
|
|
<description>Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGE</name>
|
|
<description>Alternate Pad Configuration reg4 (Pads 19,18,17,16)</description>
|
|
<addressOffset>0x000000F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD19_SR</name>
|
|
<description>Pad 19 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD19_DS1</name>
|
|
<description>Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD18_SR</name>
|
|
<description>Pad 18 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD18_DS1</name>
|
|
<description>Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD17_SR</name>
|
|
<description>Pad 17 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD17_DS1</name>
|
|
<description>Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD16_SR</name>
|
|
<description>Pad 16 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD16_DS1</name>
|
|
<description>Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGF</name>
|
|
<description>Alternate Pad Configuration reg5 (Pads 23,22,21,20)</description>
|
|
<addressOffset>0x000000F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD23_SR</name>
|
|
<description>Pad 23 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD23_DS1</name>
|
|
<description>Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD22_SR</name>
|
|
<description>Pad 22 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD22_DS1</name>
|
|
<description>Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD21_SR</name>
|
|
<description>Pad 21 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD21_DS1</name>
|
|
<description>Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD20_SR</name>
|
|
<description>Pad 20 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD20_DS1</name>
|
|
<description>Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGG</name>
|
|
<description>Alternate Pad Configuration reg6 (Pads 27,26,25,24)</description>
|
|
<addressOffset>0x000000F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD27_SR</name>
|
|
<description>Pad 27 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD27_DS1</name>
|
|
<description>Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD26_SR</name>
|
|
<description>Pad 26 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD26_DS1</name>
|
|
<description>Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD25_SR</name>
|
|
<description>Pad 25 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD25_DS1</name>
|
|
<description>Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD24_SR</name>
|
|
<description>Pad 24 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD24_DS1</name>
|
|
<description>Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGH</name>
|
|
<description>Alternate Pad Configuration reg7 (Pads 31,30,29,28)</description>
|
|
<addressOffset>0x000000FC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD31_SR</name>
|
|
<description>Pad 31 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD31_DS1</name>
|
|
<description>Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD30_SR</name>
|
|
<description>Pad 30 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD30_DS1</name>
|
|
<description>Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD29_SR</name>
|
|
<description>Pad 29 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD29_DS1</name>
|
|
<description>Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD28_SR</name>
|
|
<description>Pad 28 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD28_DS1</name>
|
|
<description>Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGI</name>
|
|
<description>Alternate Pad Configuration reg8 (Pads 35,34,33,32)</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD35_SR</name>
|
|
<description>Pad 35 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD35_DS1</name>
|
|
<description>Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD34_SR</name>
|
|
<description>Pad 34 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD34_DS1</name>
|
|
<description>Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD33_SR</name>
|
|
<description>Pad 33 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD33_DS1</name>
|
|
<description>Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD32_SR</name>
|
|
<description>Pad 32 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD32_DS1</name>
|
|
<description>Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGJ</name>
|
|
<description>Alternate Pad Configuration reg9 (Pads 39,38,37,36)</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD39_SR</name>
|
|
<description>Pad 39 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD39_DS1</name>
|
|
<description>Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD38_SR</name>
|
|
<description>Pad 38 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD38_DS1</name>
|
|
<description>Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD37_SR</name>
|
|
<description>Pad 37 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD37_DS1</name>
|
|
<description>Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD36_SR</name>
|
|
<description>Pad 36 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD36_DS1</name>
|
|
<description>Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGK</name>
|
|
<description>Alternate Pad Configuration reg10 (Pads 43,42,41,40)</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD43_SR</name>
|
|
<description>Pad 43 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD43_DS1</name>
|
|
<description>Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD42_SR</name>
|
|
<description>Pad 42 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD42_DS1</name>
|
|
<description>Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD41_SR</name>
|
|
<description>Pad 41 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD41_DS1</name>
|
|
<description>Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD40_SR</name>
|
|
<description>Pad 40 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD40_DS1</name>
|
|
<description>Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGL</name>
|
|
<description>Alternate Pad Configuration reg11 (Pads 47,46,45,44)</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD47_SR</name>
|
|
<description>Pad 47 slew rate selection.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD47_DS1</name>
|
|
<description>Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD46_SR</name>
|
|
<description>Pad 46 slew rate selection.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD46_DS1</name>
|
|
<description>Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD45_SR</name>
|
|
<description>Pad 45 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD45_DS1</name>
|
|
<description>Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD44_SR</name>
|
|
<description>Pad 44 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD44_DS1</name>
|
|
<description>Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTPADCFGM</name>
|
|
<description>Alternate Pad Configuration reg12 (Pads 49,48)</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001111</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PAD49_SR</name>
|
|
<description>Pad 49 slew rate selection.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD49_DS1</name>
|
|
<description>Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PAD48_SR</name>
|
|
<description>Pad 48 slew rate selection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_EN</name>
|
|
<description>Enables Slew rate control on pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAD48_DS1</name>
|
|
<description>Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT0EN</name>
|
|
<description>GPIO Interrupt Registers 31-0: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO31</name>
|
|
<description>GPIO31 interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO30</name>
|
|
<description>GPIO30 interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO29</name>
|
|
<description>GPIO29 interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO28</name>
|
|
<description>GPIO28 interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO27</name>
|
|
<description>GPIO27 interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO26</name>
|
|
<description>GPIO26 interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO25</name>
|
|
<description>GPIO25 interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO24</name>
|
|
<description>GPIO24 interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO23</name>
|
|
<description>GPIO23 interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO22</name>
|
|
<description>GPIO22 interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO21</name>
|
|
<description>GPIO21 interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO20</name>
|
|
<description>GPIO20 interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO19</name>
|
|
<description>GPIO19 interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO18</name>
|
|
<description>GPIO18interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO17</name>
|
|
<description>GPIO17 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO16</name>
|
|
<description>GPIO16 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO15</name>
|
|
<description>GPIO15 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO14</name>
|
|
<description>GPIO14 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO13</name>
|
|
<description>GPIO13 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO12</name>
|
|
<description>GPIO12 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO11</name>
|
|
<description>GPIO11 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO10</name>
|
|
<description>GPIO10 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO9</name>
|
|
<description>GPIO9 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO8</name>
|
|
<description>GPIO8 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO7</name>
|
|
<description>GPIO7 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO6</name>
|
|
<description>GPIO6 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO5</name>
|
|
<description>GPIO5 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO4</name>
|
|
<description>GPIO4 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO3</name>
|
|
<description>GPIO3 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO2</name>
|
|
<description>GPIO2 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO1</name>
|
|
<description>GPIO1 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO0</name>
|
|
<description>GPIO0 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT0STAT</name>
|
|
<description>GPIO Interrupt Registers 31-0: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO31</name>
|
|
<description>GPIO31 interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO30</name>
|
|
<description>GPIO30 interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO29</name>
|
|
<description>GPIO29 interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO28</name>
|
|
<description>GPIO28 interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO27</name>
|
|
<description>GPIO27 interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO26</name>
|
|
<description>GPIO26 interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO25</name>
|
|
<description>GPIO25 interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO24</name>
|
|
<description>GPIO24 interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO23</name>
|
|
<description>GPIO23 interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO22</name>
|
|
<description>GPIO22 interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO21</name>
|
|
<description>GPIO21 interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO20</name>
|
|
<description>GPIO20 interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO19</name>
|
|
<description>GPIO19 interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO18</name>
|
|
<description>GPIO18interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO17</name>
|
|
<description>GPIO17 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO16</name>
|
|
<description>GPIO16 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO15</name>
|
|
<description>GPIO15 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO14</name>
|
|
<description>GPIO14 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO13</name>
|
|
<description>GPIO13 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO12</name>
|
|
<description>GPIO12 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO11</name>
|
|
<description>GPIO11 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO10</name>
|
|
<description>GPIO10 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO9</name>
|
|
<description>GPIO9 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO8</name>
|
|
<description>GPIO8 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO7</name>
|
|
<description>GPIO7 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO6</name>
|
|
<description>GPIO6 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO5</name>
|
|
<description>GPIO5 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO4</name>
|
|
<description>GPIO4 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO3</name>
|
|
<description>GPIO3 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO2</name>
|
|
<description>GPIO2 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO1</name>
|
|
<description>GPIO1 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO0</name>
|
|
<description>GPIO0 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT0CLR</name>
|
|
<description>GPIO Interrupt Registers 31-0: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO31</name>
|
|
<description>GPIO31 interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO30</name>
|
|
<description>GPIO30 interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO29</name>
|
|
<description>GPIO29 interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO28</name>
|
|
<description>GPIO28 interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO27</name>
|
|
<description>GPIO27 interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO26</name>
|
|
<description>GPIO26 interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO25</name>
|
|
<description>GPIO25 interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO24</name>
|
|
<description>GPIO24 interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO23</name>
|
|
<description>GPIO23 interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO22</name>
|
|
<description>GPIO22 interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO21</name>
|
|
<description>GPIO21 interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO20</name>
|
|
<description>GPIO20 interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO19</name>
|
|
<description>GPIO19 interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO18</name>
|
|
<description>GPIO18interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO17</name>
|
|
<description>GPIO17 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO16</name>
|
|
<description>GPIO16 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO15</name>
|
|
<description>GPIO15 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO14</name>
|
|
<description>GPIO14 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO13</name>
|
|
<description>GPIO13 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO12</name>
|
|
<description>GPIO12 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO11</name>
|
|
<description>GPIO11 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO10</name>
|
|
<description>GPIO10 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO9</name>
|
|
<description>GPIO9 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO8</name>
|
|
<description>GPIO8 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO7</name>
|
|
<description>GPIO7 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO6</name>
|
|
<description>GPIO6 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO5</name>
|
|
<description>GPIO5 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO4</name>
|
|
<description>GPIO4 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO3</name>
|
|
<description>GPIO3 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO2</name>
|
|
<description>GPIO2 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO1</name>
|
|
<description>GPIO1 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO0</name>
|
|
<description>GPIO0 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT0SET</name>
|
|
<description>GPIO Interrupt Registers 31-0: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO31</name>
|
|
<description>GPIO31 interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO30</name>
|
|
<description>GPIO30 interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO29</name>
|
|
<description>GPIO29 interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO28</name>
|
|
<description>GPIO28 interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO27</name>
|
|
<description>GPIO27 interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO26</name>
|
|
<description>GPIO26 interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO25</name>
|
|
<description>GPIO25 interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO24</name>
|
|
<description>GPIO24 interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO23</name>
|
|
<description>GPIO23 interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO22</name>
|
|
<description>GPIO22 interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO21</name>
|
|
<description>GPIO21 interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO20</name>
|
|
<description>GPIO20 interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO19</name>
|
|
<description>GPIO19 interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO18</name>
|
|
<description>GPIO18interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO17</name>
|
|
<description>GPIO17 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO16</name>
|
|
<description>GPIO16 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO15</name>
|
|
<description>GPIO15 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO14</name>
|
|
<description>GPIO14 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO13</name>
|
|
<description>GPIO13 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO12</name>
|
|
<description>GPIO12 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO11</name>
|
|
<description>GPIO11 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO10</name>
|
|
<description>GPIO10 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO9</name>
|
|
<description>GPIO9 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO8</name>
|
|
<description>GPIO8 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO7</name>
|
|
<description>GPIO7 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO6</name>
|
|
<description>GPIO6 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO5</name>
|
|
<description>GPIO5 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO4</name>
|
|
<description>GPIO4 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO3</name>
|
|
<description>GPIO3 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO2</name>
|
|
<description>GPIO2 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO1</name>
|
|
<description>GPIO1 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO0</name>
|
|
<description>GPIO0 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT1EN</name>
|
|
<description>GPIO Interrupt Registers 49-32: Enable</description>
|
|
<addressOffset>0x00000210</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO49</name>
|
|
<description>GPIO49 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO48</name>
|
|
<description>GPIO48 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO47</name>
|
|
<description>GPIO47 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO46</name>
|
|
<description>GPIO46 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO45</name>
|
|
<description>GPIO45 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO44</name>
|
|
<description>GPIO44 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO43</name>
|
|
<description>GPIO43 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO42</name>
|
|
<description>GPIO42 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO41</name>
|
|
<description>GPIO41 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO40</name>
|
|
<description>GPIO40 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO39</name>
|
|
<description>GPIO39 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO38</name>
|
|
<description>GPIO38 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO37</name>
|
|
<description>GPIO37 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO36</name>
|
|
<description>GPIO36 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO35</name>
|
|
<description>GPIO35 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO34</name>
|
|
<description>GPIO34 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO33</name>
|
|
<description>GPIO33 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO32</name>
|
|
<description>GPIO32 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT1STAT</name>
|
|
<description>GPIO Interrupt Registers 49-32: Status</description>
|
|
<addressOffset>0x00000214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO49</name>
|
|
<description>GPIO49 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO48</name>
|
|
<description>GPIO48 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO47</name>
|
|
<description>GPIO47 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO46</name>
|
|
<description>GPIO46 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO45</name>
|
|
<description>GPIO45 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO44</name>
|
|
<description>GPIO44 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO43</name>
|
|
<description>GPIO43 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO42</name>
|
|
<description>GPIO42 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO41</name>
|
|
<description>GPIO41 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO40</name>
|
|
<description>GPIO40 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO39</name>
|
|
<description>GPIO39 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO38</name>
|
|
<description>GPIO38 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO37</name>
|
|
<description>GPIO37 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO36</name>
|
|
<description>GPIO36 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO35</name>
|
|
<description>GPIO35 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO34</name>
|
|
<description>GPIO34 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO33</name>
|
|
<description>GPIO33 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO32</name>
|
|
<description>GPIO32 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT1CLR</name>
|
|
<description>GPIO Interrupt Registers 49-32: Clear</description>
|
|
<addressOffset>0x00000218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO49</name>
|
|
<description>GPIO49 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO48</name>
|
|
<description>GPIO48 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO47</name>
|
|
<description>GPIO47 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO46</name>
|
|
<description>GPIO46 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO45</name>
|
|
<description>GPIO45 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO44</name>
|
|
<description>GPIO44 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO43</name>
|
|
<description>GPIO43 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO42</name>
|
|
<description>GPIO42 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO41</name>
|
|
<description>GPIO41 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO40</name>
|
|
<description>GPIO40 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO39</name>
|
|
<description>GPIO39 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO38</name>
|
|
<description>GPIO38 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO37</name>
|
|
<description>GPIO37 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO36</name>
|
|
<description>GPIO36 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO35</name>
|
|
<description>GPIO35 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO34</name>
|
|
<description>GPIO34 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO33</name>
|
|
<description>GPIO33 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO32</name>
|
|
<description>GPIO32 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT1SET</name>
|
|
<description>GPIO Interrupt Registers 49-32: Set</description>
|
|
<addressOffset>0x0000021C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GPIO49</name>
|
|
<description>GPIO49 interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO48</name>
|
|
<description>GPIO48 interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO47</name>
|
|
<description>GPIO47 interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO46</name>
|
|
<description>GPIO46 interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO45</name>
|
|
<description>GPIO45 interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO44</name>
|
|
<description>GPIO44 interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO43</name>
|
|
<description>GPIO43 interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO42</name>
|
|
<description>GPIO42 interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO41</name>
|
|
<description>GPIO41 interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO40</name>
|
|
<description>GPIO40 interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO39</name>
|
|
<description>GPIO39 interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO38</name>
|
|
<description>GPIO38 interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO37</name>
|
|
<description>GPIO37 interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO36</name>
|
|
<description>GPIO36 interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO35</name>
|
|
<description>GPIO35 interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO34</name>
|
|
<description>GPIO34 interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO33</name>
|
|
<description>GPIO33 interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GPIO32</name>
|
|
<description>GPIO32 interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>IOMSTR0</name>
|
|
<version>1.0</version>
|
|
<description>I2C/SPI Master</description>
|
|
<!-- <groupName>GROUP_IOMSTR</groupName> -->
|
|
<baseAddress>0x50004000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000308</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>IOMSTR0</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<description>FIFO Access Port</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFO</name>
|
|
<description>FIFO access port.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOPTR</name>
|
|
<description>Current FIFO Pointers</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FF00FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOREM</name>
|
|
<description>The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)).</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOSIZ</name>
|
|
<description>The number of bytes currently in the FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TLNGTH</name>
|
|
<description>Transfer Length</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>TLNGTH</name>
|
|
<description>Remaining transfer length.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOTHR</name>
|
|
<description>FIFO Threshold Configuration</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00007F7F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOWTHR</name>
|
|
<description>FIFO write threshold.</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFORTHR</name>
|
|
<description>FIFO read threshold.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKCFG</name>
|
|
<description>I/O Clock Configuration</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFF1F00</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>TOTPER</name>
|
|
<description>Clock total count minus 1.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LOWPER</name>
|
|
<description>Clock low count minus 1.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIVEN</name>
|
|
<description>Enable clock division by TOTPER.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable TOTPER division.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable TOTPER division.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV3</name>
|
|
<description>Enable divide by 3.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Select divide by 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Select divide by 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>Select the input clock frequency.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MIN_PWR</name>
|
|
<description>Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC</name>
|
|
<description>Selects the HFRC as the input clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV2</name>
|
|
<description>Selects the HFRC / 2 as the input clock.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV4</name>
|
|
<description>Selects the HFRC / 4 as the input clock.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV8</name>
|
|
<description>Selects the HFRC / 8 as the input clock.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV16</name>
|
|
<description>Selects the HFRC / 16 as the input clock.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV32</name>
|
|
<description>Selects the HFRC / 32 as the input clock.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV64</name>
|
|
<description>Selects the HFRC / 64 as the input clock.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>This register holds the I/O Command</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDRPT</name>
|
|
<description>Command Repeat Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CMDRPT</name>
|
|
<description>These bits hold the Command repeat count.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IDLEST</name>
|
|
<description>This bit indicates if the I/O state machine is IDLE.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>The I/O state machine is in the idle state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDACT</name>
|
|
<description>This bit indicates if the I/O Command is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>An I/O command is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>This bit indicates if an error interrupt has occurred.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>An error has been indicated by the IOM.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>I/O Master Configuration</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002000</resetValue>
|
|
<resetMask>0x80007F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IFCEN</name>
|
|
<description>This bit enables the IO Master.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the IO Master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the IO Master.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDFCPOL</name>
|
|
<description>This bit selects the read flow control signal polarity.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Flow control signal high creates flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Flow control signal low creates flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WTFCPOL</name>
|
|
<description>This bit selects the write flow control signal polarity.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Flow control signal high creates flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Flow control signal low creates flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WTFCIRQ</name>
|
|
<description>This bit selects the write mode flow control signal.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MISO</name>
|
|
<description>MISO is used as the write mode flow control signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRQ</name>
|
|
<description>IRQ is used as the write mode flow control signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCDEL</name>
|
|
<description>This bit must be left at the default value of 0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MOSIINV</name>
|
|
<description>This bit invewrts MOSI when flow control is enabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>MOSI is set to 0 in read mode and 1 in write mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERT</name>
|
|
<description>MOSI is set to 1 in read mode and 0 in write mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDFC</name>
|
|
<description>This bit enables read mode flow control.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Read mode flow control disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Read mode flow control enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WTFC</name>
|
|
<description>This bit enables write mode flow control.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Write mode flow control disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Write mode flow control enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STARTRD</name>
|
|
<description>This bit selects the preread timing.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRERD0</name>
|
|
<description>0 read delay cycles.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRERD1</name>
|
|
<description>1 read delay cycles.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRERD2</name>
|
|
<description>2 read delay cycles.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRERD3</name>
|
|
<description>3 read delay cycles.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FULLDUP</name>
|
|
<description>This bit selects full duplex mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>128 byte FIFO in half duplex mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULLDUP</name>
|
|
<description>64 byte FIFO in full duplex mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPHA</name>
|
|
<description>This bit selects SPI phase.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAMPLE_LEADING_EDGE</name>
|
|
<description>Sample on the leading (first) clock edge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLE_TRAILING_EDGE</name>
|
|
<description>Sample on the trailing (second) clock edge.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>This bit selects SPI polarity.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_BASE_0</name>
|
|
<description>The base value of the clock is 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_BASE_1</name>
|
|
<description>The base value of the clock is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFCSEL</name>
|
|
<description>This bit selects the I/O interface.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>I2C</name>
|
|
<description>Selects I2C interface for the I/O Master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI</name>
|
|
<description>Selects SPI interface for the I/O Master.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>IO Master Interrupts: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>This is the STOP command interrupt. A STOP bit was detected by the IOM.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ICMD</name>
|
|
<description>This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IACC</name>
|
|
<description>This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WTLEN</name>
|
|
<description>This is the WTLEN interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO Threshold interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMDCMP</name>
|
|
<description>This is the Command Complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>IO Master Interrupts: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>This is the STOP command interrupt. A STOP bit was detected by the IOM.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ICMD</name>
|
|
<description>This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IACC</name>
|
|
<description>This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WTLEN</name>
|
|
<description>This is the WTLEN interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO Threshold interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMDCMP</name>
|
|
<description>This is the Command Complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>IO Master Interrupts: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>This is the STOP command interrupt. A STOP bit was detected by the IOM.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ICMD</name>
|
|
<description>This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IACC</name>
|
|
<description>This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WTLEN</name>
|
|
<description>This is the WTLEN interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO Threshold interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMDCMP</name>
|
|
<description>This is the Command Complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>IO Master Interrupts: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>This is the STOP command interrupt. A STOP bit was detected by the IOM.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ICMD</name>
|
|
<description>This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IACC</name>
|
|
<description>This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WTLEN</name>
|
|
<description>This is the WTLEN interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO Threshold interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMDCMP</name>
|
|
<description>This is the Command Complete interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="IOMSTR0">
|
|
<name>IOMSTR1</name>
|
|
<baseAddress>0x50005000</baseAddress>
|
|
<interrupt>
|
|
<name>IOMSTR1</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
</peripheral> <peripheral derivedFrom="IOMSTR0">
|
|
<name>IOMSTR2</name>
|
|
<baseAddress>0x50006000</baseAddress>
|
|
<interrupt>
|
|
<name>IOMSTR2</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
</peripheral> <peripheral derivedFrom="IOMSTR0">
|
|
<name>IOMSTR3</name>
|
|
<baseAddress>0x50007000</baseAddress>
|
|
<interrupt>
|
|
<name>IOMSTR3</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
</peripheral> <peripheral derivedFrom="IOMSTR0">
|
|
<name>IOMSTR4</name>
|
|
<baseAddress>0x50008000</baseAddress>
|
|
<interrupt>
|
|
<name>IOMSTR4</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
</peripheral> <peripheral derivedFrom="IOMSTR0">
|
|
<name>IOMSTR5</name>
|
|
<baseAddress>0x50009000</baseAddress>
|
|
<interrupt>
|
|
<name>IOMSTR5</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>IOSLAVE</name>
|
|
<version>1.0</version>
|
|
<description>I2C/SPI Slave</description>
|
|
<!-- <groupName>GROUP_IOSLAVE</groupName> -->
|
|
<baseAddress>0x50000000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000220</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>IOSLAVE</name>
|
|
<value>4</value>
|
|
</interrupt> <interrupt>
|
|
<name>IOSLAVEACC</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FIFOPTR</name>
|
|
<description>Current FIFO Pointer</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOSIZ</name>
|
|
<description>The number of bytes currently in the hardware FIFO.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOPTR</name>
|
|
<description>Current FIFO pointer.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCFG</name>
|
|
<description>FIFO Configuration</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0x3F003F1F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ROBASE</name>
|
|
<description>Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOOBASE*8-1)</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOMAX</name>
|
|
<description>These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOBASE</name>
|
|
<description>These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOTHR</name>
|
|
<description>FIFO Threshold Configuration</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOTHR</name>
|
|
<description>FIFO size interrupt threshold.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FUPD</name>
|
|
<description>FIFO Update Status</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOREAD</name>
|
|
<description>This bitfield indicates an IO read is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOUPD</name>
|
|
<description>This bit indicates that a FIFO update is underway.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCTR</name>
|
|
<description>Overall FIFO Counter</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOCTR</name>
|
|
<description>Virtual FIFO byte count</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOINC</name>
|
|
<description>Overall FIFO Counter Increment</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOINC</name>
|
|
<description>Increment the Overall FIFO Counter by this value on a write</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>I/O Slave Configuration</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x800FFF17</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IFCEN</name>
|
|
<description>IOSLAVE interface enable.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the IOSLAVE</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the IOSLAVE</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2CADDR</name>
|
|
<description>7-bit or 10-bit I2C device address.</description>
|
|
<bitRange>[19:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STARTRD</name>
|
|
<description>This bit holds the cycle to initiate an I/O RAM read.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LATE</name>
|
|
<description>Initiate I/O RAM read late in each transferred byte.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EARLY</name>
|
|
<description>Initiate I/O RAM read early in each transferred byte.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSB</name>
|
|
<description>This bit selects the transfer bit ordering.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSB_FIRST</name>
|
|
<description>Data is assumed to be sent and received with MSB first.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB_FIRST</name>
|
|
<description>Data is assumed to be sent and received with LSB first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>This bit selects SPI polarity.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPI_MODES_0_3</name>
|
|
<description>Polarity 0, handles SPI modes 0 and 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MODES_1_2</name>
|
|
<description>Polarity 1, handles SPI modes 1 and 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFCSEL</name>
|
|
<description>This bit selects the I/O interface.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>I2C</name>
|
|
<description>Selects I2C interface for the IO Slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI</name>
|
|
<description>Selects SPI interface for the IO Slave.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRENC</name>
|
|
<description>I/O Slave Interrupt Priority Encode</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PRENC</name>
|
|
<description>These bits hold the priority encode of the REGACC interrupts.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOINTCTL</name>
|
|
<description>I/O Interrupt Control</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFF01FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOINTSET</name>
|
|
<description>These bits set the IOINT interrupts when written with a 1.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOINTCLR</name>
|
|
<description>This bit clears all of the IOINT interrupts when written with a 1.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOINT</name>
|
|
<description>These bits read the IOINT interrupts.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOINTEN</name>
|
|
<description>These read-only bits indicate whether the IOINT interrupts are enabled.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GENADD</name>
|
|
<description>General Address Data</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>GADATA</name>
|
|
<description>The data supplied on the last General Address reference.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>IO Slave Interrupts: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>XCMPWR</name>
|
|
<description>Transfer complete interrupt, write to register space.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPWF</name>
|
|
<description>Transfer complete interrupt, write to FIFO space.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRR</name>
|
|
<description>Transfer complete interrupt, read from register space.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRF</name>
|
|
<description>Transfer complete interrupt, read from FIFO space.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOINTW</name>
|
|
<description>I2C Interrupt Write interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GENAD</name>
|
|
<description>I2C General Address interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FRDERR</name>
|
|
<description>FIFO Read Error interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>FIFO Underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>FIFO Overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FSIZE</name>
|
|
<description>FIFO Size interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>IO Slave Interrupts: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>XCMPWR</name>
|
|
<description>Transfer complete interrupt, write to register space.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPWF</name>
|
|
<description>Transfer complete interrupt, write to FIFO space.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRR</name>
|
|
<description>Transfer complete interrupt, read from register space.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRF</name>
|
|
<description>Transfer complete interrupt, read from FIFO space.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOINTW</name>
|
|
<description>I2C Interrupt Write interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GENAD</name>
|
|
<description>I2C General Address interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FRDERR</name>
|
|
<description>FIFO Read Error interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>FIFO Underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>FIFO Overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FSIZE</name>
|
|
<description>FIFO Size interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>IO Slave Interrupts: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>XCMPWR</name>
|
|
<description>Transfer complete interrupt, write to register space.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPWF</name>
|
|
<description>Transfer complete interrupt, write to FIFO space.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRR</name>
|
|
<description>Transfer complete interrupt, read from register space.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRF</name>
|
|
<description>Transfer complete interrupt, read from FIFO space.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOINTW</name>
|
|
<description>I2C Interrupt Write interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GENAD</name>
|
|
<description>I2C General Address interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FRDERR</name>
|
|
<description>FIFO Read Error interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>FIFO Underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>FIFO Overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FSIZE</name>
|
|
<description>FIFO Size interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>IO Slave Interrupts: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>XCMPWR</name>
|
|
<description>Transfer complete interrupt, write to register space.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPWF</name>
|
|
<description>Transfer complete interrupt, write to FIFO space.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRR</name>
|
|
<description>Transfer complete interrupt, read from register space.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XCMPRF</name>
|
|
<description>Transfer complete interrupt, read from FIFO space.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOINTW</name>
|
|
<description>I2C Interrupt Write interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GENAD</name>
|
|
<description>I2C General Address interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FRDERR</name>
|
|
<description>FIFO Read Error interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FUNDFL</name>
|
|
<description>FIFO Underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FOVFL</name>
|
|
<description>FIFO Overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FSIZE</name>
|
|
<description>FIFO Size interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGACCINTEN</name>
|
|
<description>Register Access Interrupts: Enable</description>
|
|
<addressOffset>0x00000210</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>REGACC</name>
|
|
<description>Register access interrupts.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGACCINTSTAT</name>
|
|
<description>Register Access Interrupts: Status</description>
|
|
<addressOffset>0x00000214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>REGACC</name>
|
|
<description>Register access interrupts.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGACCINTCLR</name>
|
|
<description>Register Access Interrupts: Clear</description>
|
|
<addressOffset>0x00000218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>REGACC</name>
|
|
<description>Register access interrupts.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGACCINTSET</name>
|
|
<description>Register Access Interrupts: Set</description>
|
|
<addressOffset>0x0000021C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>REGACC</name>
|
|
<description>Register access interrupts.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>MCUCTRL</name>
|
|
<version>1.0</version>
|
|
<description>MCU Miscellaneous Control Logic</description>
|
|
<!-- <groupName>GROUP_MCUCTRL</groupName> -->
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x0000034C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>BROWNOUT</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CHIP_INFO</name>
|
|
<description>Chip Information Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x03000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PARTNUM</name>
|
|
<description>BCD part number.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APOLLO2</name>
|
|
<description>Apollo2 part number is 0x03XXXXXX.</description>
|
|
<value>50331648</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>APOLLO</name>
|
|
<description>Apollo part number is 0x01XXXXXX.</description>
|
|
<value>16777216</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PN_M</name>
|
|
<description>Mask for the PN field.</description>
|
|
<value>4278190080</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHIPID0</name>
|
|
<description>Unique Chip ID 0</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Unique chip ID 0.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APOLLO2</name>
|
|
<description>Apollo2 CHIPID0. The lower 32-bits of the 64-bit CHIPID value, which is unique for each part.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHIPID1</name>
|
|
<description>Unique Chip ID 1</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Unique chip ID 1.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APOLLO2</name>
|
|
<description>Apollo2 CHIPID1. The upper 32-bits of the 64-bit CHIPID value, which is unique for each part.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHIPREV</name>
|
|
<description>Chip Revision</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000011</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>REVMAJ</name>
|
|
<description>Major Revision ID.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B</name>
|
|
<description>Apollo2 revision B</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A</name>
|
|
<description>Apollo2 revision A</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REVMIN</name>
|
|
<description>Minor Revision ID.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REV0</name>
|
|
<description>Apollo2 minor revision value. Succeeding minor revisions will increment from this value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REV2</name>
|
|
<description>Apollo2 minor revision value.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VENDORID</name>
|
|
<description>Unique Vendor ID</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Unique Vendor ID</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AMBIQ</name>
|
|
<description>Ambiq Vendor ID</description>
|
|
<value>1095582289</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUGGER</name>
|
|
<description>Debugger Access Control</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>LOCKOUT</name>
|
|
<description>Lockout of debugger (SWD).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUCK</name>
|
|
<description>Analog Buck Control</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>MEMBUCKRST</name>
|
|
<description>Reset control override for Mem Buck; 0=enabled, 1=reset; Value is propagated only when the BUCKSWE bit is active, otherwise contrl is from the power control module.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKRST</name>
|
|
<description>Reset control override for Core Buck; 0=enabled, 1=reset; Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BYPBUCKMEM</name>
|
|
<description>Not used. Additional control of buck is available in the power control module</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEMBUCKPWD</name>
|
|
<description>Memory buck power down override. 1=Powered Down; 0=Enabled; Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Memory Buck Enable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPBUCKANA</name>
|
|
<description>HFRC clkgen bit 0 override. When set, this will override to 0 bit 0 of the hfrc_freq_clkgen internal bus (see internal Shelby-1473)</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKPWD</name>
|
|
<description>Core buck power down override. 1=Powered Down; 0=Enabled; Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Core Buck enable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPBUCKCORE</name>
|
|
<description>Not used. Additional control of buck is available in the power control module</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BUCKSWE</name>
|
|
<description>Buck Register Software Override Enable. This will enable the override values for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, MEMBUCKRST, all to be propagated to the control logic, instead of the normal power control module signal. Note - Must take care to have correct value for ALL the register bits when this SWE is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OVERRIDE_DIS</name>
|
|
<description>BUCK Software Override Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVERRIDE_EN</name>
|
|
<description>BUCK Software Override Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUCK3</name>
|
|
<description>Buck control reg 3</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003FFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>MEMBUCKLOTON</name>
|
|
<description>MEM Buck low TON trim value</description>
|
|
<bitRange>[21:18]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEMBUCKBURSTEN</name>
|
|
<description>MEM Buck burst enable 0=disable, 0=disabled, 1=enable.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEMBUCKZXTRIM</name>
|
|
<description>Memory buck zero crossing trim value</description>
|
|
<bitRange>[16:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEMBUCKHYSTTRIM</name>
|
|
<description>Hysterisis trim for mem buck</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKLOTON</name>
|
|
<description>Core Buck low TON trim value</description>
|
|
<bitRange>[10:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKBURSTEN</name>
|
|
<description>Core Buck burst enable. 0=disabled, 1=enabled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKZXTRIM</name>
|
|
<description>Core buck zero crossing trim value</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKHYSTTRIM</name>
|
|
<description>Hysterisis trim for core buck</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LDOREG1</name>
|
|
<description>Analog LDO Reg 1</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x001FFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CORELDOIBSTRM</name>
|
|
<description>CORE LDO IBIAS Trim</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CORELDOLPTRIM</name>
|
|
<description>CORE LDO Low Power Trim</description>
|
|
<bitRange>[19:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIMCORELDOR3</name>
|
|
<description>CORE LDO tempco trim (R3).</description>
|
|
<bitRange>[13:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIMCORELDOR1</name>
|
|
<description>CORE LDO Active mode ouput trim (R1).</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LDOREG3</name>
|
|
<description>LDO Control Register 3</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>TRIMMEMLDOR1</name>
|
|
<description>MEM LDO active mode trim (R1).</description>
|
|
<bitRange>[17:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEMLDOLPALTTRIM</name>
|
|
<description>MEM LDO TRIM for low power mode with ADC active</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEMLDOLPTRIM</name>
|
|
<description>MEM LDO TRIM for low power mode with ADC inactive</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BODPORCTRL</name>
|
|
<description>BOD and PDR control Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>BODEXTREFSEL</name>
|
|
<description>BOD External Reference Select.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELECT</name>
|
|
<description>BOD external reference select.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDREXTREFSEL</name>
|
|
<description>PDR External Reference Select.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELECT</name>
|
|
<description>PDR external reference select.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWDBOD</name>
|
|
<description>BOD Power Down.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWR_DN</name>
|
|
<description>BOD power down.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWDPDR</name>
|
|
<description>PDR Power Down.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWR_DN</name>
|
|
<description>PDR power down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCPWRDLY</name>
|
|
<description>ADC Power Up Delay Control</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADCPWR1</name>
|
|
<description>ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADCPWR0</name>
|
|
<description>ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCCAL</name>
|
|
<description>ADC Calibration Control</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADCCALIBRATED</name>
|
|
<description>Status for ADC Calibration</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FALSE</name>
|
|
<description>ADC is not calibrated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRUE</name>
|
|
<description>ADC is calibrated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALONPWRUP</name>
|
|
<description>Run ADC Calibration on initial power up sequence</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable automatic calibration on initial power up</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable automatic calibration on initial power up</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCBATTLOAD</name>
|
|
<description>ADC Battery Load Enable</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>BATTLOAD</name>
|
|
<description>Enable the ADC battery load resistor</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Battery load is disconnected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Battery load is enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUCKTRIM</name>
|
|
<description>Trim settings for Core and Mem buck modules</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3F0F3F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>RESERVED.</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKR1_HI</name>
|
|
<description>Core Buck voltage output trim bits[9:6]. Concatenate with field COREBUCKR1_LO for the full trim value.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKR1_LO</name>
|
|
<description>Core Buck voltage output trim bits[5:0], Concatenate with field COREBUCKR1_HI for the full trim value.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEMBUCKR1</name>
|
|
<description>Trim values for BUCK regulator.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XTALGENCTRL</name>
|
|
<description>XTAL Oscillator General Control</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00003FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>XTALKSBIASTRIM</name>
|
|
<description>XTAL IBIAS Kick start trim . This trim value is used during the startup process to enable a faster lock and is applied when the kickstart signal is active.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XTALBIASTRIM</name>
|
|
<description>XTAL IBIAS trim</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACWARMUP</name>
|
|
<description>Auto-calibration delay control</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1SEC</name>
|
|
<description>Warmup period of 1-2 seconds</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2SEC</name>
|
|
<description>Warmup period of 2-4 seconds</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4SEC</name>
|
|
<description>Warmup period of 4-8 seconds</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8SEC</name>
|
|
<description>Warmup period of 8-16 seconds</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOOTLOADERLOW</name>
|
|
<description>Determines whether the bootloader code is visible at address 0x00000000</description>
|
|
<addressOffset>0x000001A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Determines whether the bootloader code is visible at address 0x00000000 or not.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADDR0</name>
|
|
<description>Bootloader code at 0x00000000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHADOWVALID</name>
|
|
<description>Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.</description>
|
|
<addressOffset>0x000001A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>BL_DSLEEP</name>
|
|
<description>Indicates whether the bootloader should sleep or deep sleep if no image loaded.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEEPSLEEP</name>
|
|
<description>Bootloader will go to deep sleep if no flash image loaded</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>Indicates whether the shadow registers contain valid data from the Flash Information Space.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>Flash information space contains valid data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICODEFAULTADDR</name>
|
|
<description>ICODE bus address which was present when a bus fault occurred.</description>
|
|
<addressOffset>0x000001C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCODEFAULTADDR</name>
|
|
<description>DCODE bus address which was present when a bus fault occurred.</description>
|
|
<addressOffset>0x000001C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSFAULTADDR</name>
|
|
<description>System bus address which was present when a bus fault occurred.</description>
|
|
<addressOffset>0x000001C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAULTSTATUS</name>
|
|
<description>Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.</description>
|
|
<addressOffset>0x000001CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>SYS</name>
|
|
<description>SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOFAULT</name>
|
|
<description>No bus fault has been detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAULT</name>
|
|
<description>Bus fault detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCODE</name>
|
|
<description>DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOFAULT</name>
|
|
<description>No DCODE fault has been detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAULT</name>
|
|
<description>DCODE fault detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICODE</name>
|
|
<description>The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOFAULT</name>
|
|
<description>No ICODE fault has been detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAULT</name>
|
|
<description>ICODE fault detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAULTCAPTUREEN</name>
|
|
<description>Enable the fault capture registers</description>
|
|
<addressOffset>0x000001D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable fault capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable fault capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGR1</name>
|
|
<description>Read-only debug register 1</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12345678</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ONETO8</name>
|
|
<description>Read-only register for communication validation</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGR2</name>
|
|
<description>Read-only debug register 2</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC001C0DE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>COOLCODE</name>
|
|
<description>Read-only register for communication validation</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMUENABLE</name>
|
|
<description>Control bit to enable/disable the PMU</description>
|
|
<addressOffset>0x00000220</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable MCU power management.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable MCU power management.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPIUCTRL</name>
|
|
<description>TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.</description>
|
|
<addressOffset>0x00000250</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000701</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>This field selects the frequency of the ARM M4 TPIU port.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_PWR</name>
|
|
<description>Low power state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV_2</name>
|
|
<description>Selects HFRC divided by 2 as the source TPIU clk</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV_8</name>
|
|
<description>Selects HFRC divided by 8 as the source TPIU clk</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV_16</name>
|
|
<description>Selects HFRC divided by 16 as the source TPIU clk</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRC_DIV_32</name>
|
|
<description>Selects HFRC divided by 32 as the source TPIU clk</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the TPIU.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the TPIU.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>PDM</name>
|
|
<version>1.0</version>
|
|
<description>PDM Audio</description>
|
|
<!-- <groupName>GROUP_PDM</groupName> -->
|
|
<baseAddress>0x50011000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000210</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PDM</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PCFG</name>
|
|
<description>PDM Configuration Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000C365</resetValue>
|
|
<resetMask>0xFF87FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>LRSWAP</name>
|
|
<description>Left/right channel swap.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Swap left and right channels (FIFO Read RIGHT_LEFT).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOSWAP</name>
|
|
<description>No channel swapping (IFO Read LEFT_RIGHT).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGARIGHT</name>
|
|
<description>Right channel PGA gain.</description>
|
|
<bitRange>[30:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M15DB</name>
|
|
<description>-1.5 db gain.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M300DB</name>
|
|
<description>-3.0 db gain.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M45DB</name>
|
|
<description>-4.5 db gain.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M60DB</name>
|
|
<description>-6.0 db gain.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M75DB</name>
|
|
<description>-7.5 db gain.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M90DB</name>
|
|
<description>-9.0 db gain.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M105DB</name>
|
|
<description>-10.5 db gain.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M120DB</name>
|
|
<description>-12.0 db gain.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P105DB</name>
|
|
<description>10.5 db gain.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P90DB</name>
|
|
<description>9.0 db gain.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P75DB</name>
|
|
<description>7.5 db gain.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P60DB</name>
|
|
<description>6.0 db gain.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P45DB</name>
|
|
<description>4.5 db gain.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P30DB</name>
|
|
<description>3.0 db gain.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P15DB</name>
|
|
<description>1.5 db gain.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0DB</name>
|
|
<description>0.0 db gain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGALEFT</name>
|
|
<description>Left channel PGA gain.</description>
|
|
<bitRange>[26:23]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M15DB</name>
|
|
<description>-1.5 db gain.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M300DB</name>
|
|
<description>-3.0 db gain.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M45DB</name>
|
|
<description>-4.5 db gain.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M60DB</name>
|
|
<description>-6.0 db gain.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M75DB</name>
|
|
<description>-7.5 db gain.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M90DB</name>
|
|
<description>-9.0 db gain.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M105DB</name>
|
|
<description>-10.5 db gain.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M120DB</name>
|
|
<description>-12.0 db gain.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P105DB</name>
|
|
<description>10.5 db gain.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P90DB</name>
|
|
<description>9.0 db gain.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P75DB</name>
|
|
<description>7.5 db gain.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P60DB</name>
|
|
<description>6.0 db gain.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P45DB</name>
|
|
<description>4.5 db gain.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P30DB</name>
|
|
<description>3.0 db gain.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P15DB</name>
|
|
<description>1.5 db gain.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0DB</name>
|
|
<description>0.0 db gain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCLKDIV</name>
|
|
<description>PDM_CLK frequency divisor.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCKDIV4</name>
|
|
<description>Divide input clock by 4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCKDIV3</name>
|
|
<description>Divide input clock by 3</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCKDIV2</name>
|
|
<description>Divide input clock by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCKDIV1</name>
|
|
<description>Divide input clock by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SINCRATE</name>
|
|
<description>SINC decimation rate.</description>
|
|
<bitRange>[16:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADCHPD</name>
|
|
<description>High pass filter disable.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable high pass filter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable high pass filter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPCUTOFF</name>
|
|
<description>High pass filter coefficients.</description>
|
|
<bitRange>[8:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CYCLES</name>
|
|
<description>Number of clocks during gain-setting changes.</description>
|
|
<bitRange>[4:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SOFTMUTE</name>
|
|
<description>Soft mute control.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable Soft Mute.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable Soft Mute.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDMCORE</name>
|
|
<description>Data Streaming Control.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable Data Streaming.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable Data Streaming.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VCFG</name>
|
|
<description>Voice Configuration Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xFC1B0118</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>IOCLKEN</name>
|
|
<description>Enable the IO clock.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable FIFO read.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable FIFO read.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTB</name>
|
|
<description>Reset the IP core.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the core.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORM</name>
|
|
<description>Enable the core.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDMCLKSEL</name>
|
|
<description>Select the PDM input clock.</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Static value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12MHz</name>
|
|
<description>PDM clock is 12 MHz.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6MHz</name>
|
|
<description>PDM clock is 6 MHz.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3MHz</name>
|
|
<description>PDM clock is 3 MHz.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_5MHz</name>
|
|
<description>PDM clock is 1.5 MHz.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>750KHz</name>
|
|
<description>PDM clock is 750 KHz.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>375KHz</name>
|
|
<description>PDM clock is 375 KHz.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>187KHz</name>
|
|
<description>PDM clock is 187.5 KHz.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDMCLK</name>
|
|
<description>Enable the serial clock.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable serial clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable serial clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2SMODE</name>
|
|
<description>I2S interface enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable I2S interface.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable I2S interface.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLKINV</name>
|
|
<description>I2S BCLK input inversion.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INV</name>
|
|
<description>BCLK inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORM</name>
|
|
<description>BCLK not inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMICKDEL</name>
|
|
<description>PDM clock sampling delay.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0CYC</name>
|
|
<description>No delay.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1CYC</name>
|
|
<description>1 cycle delay.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELAP</name>
|
|
<description>Select PDM input clock source.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>I2S</name>
|
|
<description>Clock source from I2S BCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL</name>
|
|
<description>Clock source from internal clock generator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCMPACK</name>
|
|
<description>PCM data packing enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable PCM packing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable PCM packing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSET</name>
|
|
<description>Set PCM channels.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Channel disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Mono left channel.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Mono right channel.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STEREO</name>
|
|
<description>Stereo channels.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<description>Voice Status Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOCNT</name>
|
|
<description>Valid 32-bit entries currently in the FIFO.</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRD</name>
|
|
<description>FIFO Read</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOREAD</name>
|
|
<description>FIFO read data.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLUSH</name>
|
|
<description>FIFO Flush</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOFLUSH</name>
|
|
<description>FIFO FLUSH.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTHR</name>
|
|
<description>FIFO Threshold</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>FIFOTHR</name>
|
|
<description>FIFO interrupt threshold.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>IO Master Interrupts: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>UNDFL</name>
|
|
<description>This is the FIFO underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>This is the FIFO overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO threshold interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>IO Master Interrupts: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>UNDFL</name>
|
|
<description>This is the FIFO underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>This is the FIFO overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO threshold interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>IO Master Interrupts: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>UNDFL</name>
|
|
<description>This is the FIFO underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>This is the FIFO overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO threshold interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>IO Master Interrupts: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>UNDFL</name>
|
|
<description>This is the FIFO underflow interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>This is the FIFO overflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>This is the FIFO threshold interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>PWRCTRL</name>
|
|
<version>1.0</version>
|
|
<description>PWR Controller Register Bank</description>
|
|
<!-- <groupName>GROUP_PWRCTRL</groupName> -->
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000024</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>SUPPLYSRC</name>
|
|
<description>Memory and Core Voltage Supply Source Select Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000004</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>SWITCH_LDO_IN_SLEEP</name>
|
|
<description>Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in DEEP SLEEP. If all the devices are off then this does not matter and LDO (low power mode) is used</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Automatically switch from CORE BUCK to CORE LDO when CPU is in DEEP SLEEP</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COREBUCKEN</name>
|
|
<description>Enables and Selects the Core Buck as the supply for the low-voltage power domain.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the Core Buck for the low-voltage power domain.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMBUCKEN</name>
|
|
<description>Enables and select the Memory Buck as the supply for the Flash and SRAM power domain.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the Memory Buck as the supply for flash and SRAM.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWERSTATUS</name>
|
|
<description>Power Status Register for MCU supplies and peripherals</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>COREBUCKON</name>
|
|
<description>Indicates whether the Core low-voltage domain is supplied from the LDO or the Buck.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDO</name>
|
|
<description>Indicates the the LDO is supplying the Core low-voltage.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCK</name>
|
|
<description>Indicates the the Buck is supplying the Core low-voltage.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMBUCKON</name>
|
|
<description>Indicate whether the Memory power domain is supplied from the LDO or the Buck.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDO</name>
|
|
<description>Indicates the LDO is supplying the memory power domain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCK</name>
|
|
<description>Indicates the Buck is supplying the memory power domain.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEEN</name>
|
|
<description>DEVICE ENABLES for SHELBY</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PWRPDM</name>
|
|
<description>Enable PDM Digital Block</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable PDM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables PDM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWRADC</name>
|
|
<description>Enable ADC Digital Block</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable ADC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables ADC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWRUART1</name>
|
|
<description>Enable UART 1</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable UART 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables UART 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWRUART0</name>
|
|
<description>Enable UART 0</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable UART 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables UART 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IO_MASTER5</name>
|
|
<description>Enable IO MASTER 5</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable IO MASTER 5</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables IO MASTER 5</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IO_MASTER4</name>
|
|
<description>Enable IO MASTER 4</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable IO MASTER 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables IO MASTER 4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IO_MASTER3</name>
|
|
<description>Enable IO MASTER 3</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable IO MASTER 3</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables IO MASTER 3</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IO_MASTER2</name>
|
|
<description>Enable IO MASTER 2</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable IO MASTER 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables IO MASTER 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IO_MASTER1</name>
|
|
<description>Enable IO MASTER 1</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable IO MASTER 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables IO MASTER 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IO_MASTER0</name>
|
|
<description>Enable IO MASTER 0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable IO MASTER 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables IO MASTER 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IO_SLAVE</name>
|
|
<description>Enable IO SLAVE</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable IO SLAVE</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables IO SLAVE</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRAMPWDINSLEEP</name>
|
|
<description>Powerdown an SRAM Banks in Deep Sleep mode</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x800007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CACHE_PWD_SLP</name>
|
|
<description>Enable CACHE BANKS to power down in deep sleep</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>CACHE BANKS POWER DOWN in CORE SLEEP</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>CACHE BANKS STAYS in Retention in CORE SLEEP</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAMSLEEPPOWERDOWN</name>
|
|
<description>Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>All banks retained</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM0</name>
|
|
<description>0KB-8KB SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM1</name>
|
|
<description>8KB-16KB SRAM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM2</name>
|
|
<description>16KB-24KB SRAM</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM3</name>
|
|
<description>24KB-32KB SRAM</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP1</name>
|
|
<description>32KB-64KB SRAMs</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP2</name>
|
|
<description>64KB-96KB SRAMs</description>
|
|
<value>32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP3</name>
|
|
<description>96KB-128KB SRAMs</description>
|
|
<value>64</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP4</name>
|
|
<description>128KB-160KB SRAMs</description>
|
|
<value>128</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP5</name>
|
|
<description>160KB-192KB SRAMs</description>
|
|
<value>256</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP6</name>
|
|
<description>192KB-224KB SRAMs</description>
|
|
<value>512</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP7</name>
|
|
<description>224KB-256KB SRAMs</description>
|
|
<value>1024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM16K</name>
|
|
<description>Do not Retain lower 16KB</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM32K</name>
|
|
<description>Do not Retain lower 32KB</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM64K</name>
|
|
<description>Do not Retain lower 64KB</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM128K</name>
|
|
<description>Do not Retain lower 128KB</description>
|
|
<value>127</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALLBUTLOWER8K</name>
|
|
<description>All banks but lower 8k powered down.</description>
|
|
<value>2046</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALLBUTLOWER16K</name>
|
|
<description>All banks but lower 16k powered down.</description>
|
|
<value>2044</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALLBUTLOWER24K</name>
|
|
<description>All banks but lower 24k powered down.</description>
|
|
<value>2040</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALLBUTLOWER32K</name>
|
|
<description>All banks but lower 32k powered down.</description>
|
|
<value>2032</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALLBUTLOWER64K</name>
|
|
<description>All banks but lower 64k powered down.</description>
|
|
<value>2016</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALLBUTLOWER128K</name>
|
|
<description>All banks but lower 128k powered down.</description>
|
|
<value>1920</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL</name>
|
|
<description>All banks powered down.</description>
|
|
<value>2047</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEMEN</name>
|
|
<description>Disables individual banks of the MEMORY array</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA0001FFF</resetValue>
|
|
<resetMask>0xA0001FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CACHEB2</name>
|
|
<description>Enable CACHE BANK 2</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable CACHE BANK 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable CACHE BANK 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CACHEB0</name>
|
|
<description>Enable CACHE BANK 0</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable CACHE BANK 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable CACHE BANK 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH1</name>
|
|
<description>Enable FLASH1</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable FLASH1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables FLASH1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH0</name>
|
|
<description>Enable FLASH 0</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable FLASH 0</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables FLASH 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAMEN</name>
|
|
<description>Enables power for selected SRAM banks (else an access to its address space to generate a Hard Fault).</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>All banks disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM0</name>
|
|
<description>0KB-8KB SRAM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM1</name>
|
|
<description>8KB-16KB SRAM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM2</name>
|
|
<description>16KB-24KB SRAM</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP0_SRAM3</name>
|
|
<description>24KB-32KB SRAM</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP1</name>
|
|
<description>32KB-64KB SRAMs</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP2</name>
|
|
<description>64KB-96KB SRAMs</description>
|
|
<value>32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP3</name>
|
|
<description>96KB-128KB SRAMs</description>
|
|
<value>64</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP4</name>
|
|
<description>128KB-160KB SRAMs</description>
|
|
<value>128</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP5</name>
|
|
<description>160KB-192KB SRAMs</description>
|
|
<value>256</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP6</name>
|
|
<description>192KB-224KB SRAMs</description>
|
|
<value>512</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GROUP7</name>
|
|
<description>224KB-256KB SRAMs</description>
|
|
<value>1024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM16K</name>
|
|
<description>ENABLE lower 16KB</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM32K</name>
|
|
<description>ENABLE lower 32KB</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM64K</name>
|
|
<description>ENABLE lower 64KB</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM128K</name>
|
|
<description>ENABLE lower 128KB</description>
|
|
<value>127</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM256K</name>
|
|
<description>ENABLE lower 256KB</description>
|
|
<value>2047</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWRONSTATUS</name>
|
|
<description>POWER ON Status</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x002FFFFE</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PD_CACHEB2</name>
|
|
<description>This bit is 1 if power is supplied to CACHE BANK 2</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_CACHEB0</name>
|
|
<description>This bit is 1 if power is supplied to CACHE BANK 0</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP7_SRAM</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_GRP7</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP6_SRAM</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_GRP6</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP5_SRAM</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_GRP5</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP4_SRAM</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_GRP4</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP3_SRAM</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_GRP3</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP2_SRAM</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_GRP2</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP1_SRAM</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_GRP1</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP0_SRAM3</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP0_SRAM2</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP0_SRAM1</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain SRAM0_1</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_GRP0_SRAM0</name>
|
|
<description>This bit is 1 if power is supplied to SRAM domain SRAM0_0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PDADC</name>
|
|
<description>This bit is 1 if power is supplied to domain PD_ADC</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_FLAM1</name>
|
|
<description>This bit is 1 if power is supplied to domain PD_FLAM1</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_FLAM0</name>
|
|
<description>This bit is 1 if power is supplied to domain PD_FLAM0</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PD_PDM</name>
|
|
<description>This bit is 1 if power is supplied to domain PD_PDM</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PDC</name>
|
|
<description>This bit is 1 if power is supplied to power domain C, which supplies IOM3-5.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PDB</name>
|
|
<description>This bit is 1 if power is supplied to power domain B, which supplies IOM0-2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PDA</name>
|
|
<description>This bit is 1 if power is supplied to power domain A, which supplies IOS and UART0,1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRAMCTRL</name>
|
|
<description>SRAM Control register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>SRAM_MASTER_CLKGATE</name>
|
|
<description>Enables top-level clock gating in the SRAM block. This bit should be enabled for lowest power operation.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable Master SRAM Clock Gate</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables Master SRAM Clock Gating</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAM_CLKGATE</name>
|
|
<description>Enables individual per-RAM clock gating in the SRAM block. This bit should be enabled for lowest power operation.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable Individual SRAM Clock Gating</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables Individual SRAM Clock Gating</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAM_LIGHT_SLEEP</name>
|
|
<description>Enable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will be put into light sleep mode while inactive. NOTE: if the SRAM is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable LIGHT SLEEP for SRAMs</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disables LIGHT SLEEP for SRAMs</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCSTATUS</name>
|
|
<description>Power Status Register for ADC Block</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ADC_REFBUF_PWD</name>
|
|
<description>This bit indicates that the ADC REFBUF is powered down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADC_REFKEEP_PWD</name>
|
|
<description>This bit indicates that the ADC REFKEEP is powered down</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADC_VBAT_PWD</name>
|
|
<description>This bit indicates that the ADC VBAT resistor divider is powered down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADC_VPTAT_PWD</name>
|
|
<description>This bit indicates that the ADC temperature sensor input buffer is powered down</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADC_BGT_PWD</name>
|
|
<description>This bit indicates that the ADC Band Gap is powered down</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADC_PWD</name>
|
|
<description>This bit indicates that the ADC is powered down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISCOPT</name>
|
|
<description>Power Optimization Control Bits</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000004</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>DIS_LDOLPMODE_TIMERS</name>
|
|
<description>Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep even when the ctimers or stimers are running</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>RSTGEN</name>
|
|
<version>1.0</version>
|
|
<description>MCU Reset Generator</description>
|
|
<!-- <groupName>GROUP_RSTGEN</groupName> -->
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000210</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WDREN</name>
|
|
<description>Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BODHREN</name>
|
|
<description>Brown out high (2.1v) reset enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWPOI</name>
|
|
<description>Software POI Reset</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>SWPOIKEY</name>
|
|
<description>0x1B generates a software POI reset.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KEYVALUE</name>
|
|
<description>Writing 0x1B key value generates a software POI reset.</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWPOR</name>
|
|
<description>Software POR Reset</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>SWPORKEY</name>
|
|
<description>0xD4 generates a software POR reset.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KEYVALUE</name>
|
|
<description>Writing 0xD4 key value generates a software POR reset.</description>
|
|
<value>212</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000007F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WDRSTAT</name>
|
|
<description>Reset was initiated by a Watchdog Timer Reset.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DBGRSTAT</name>
|
|
<description>Reset was a initiated by Debugger Reset.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>POIRSTAT</name>
|
|
<description>Reset was a initiated by Software POI Reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SWRSTAT</name>
|
|
<description>Reset was a initiated by SW POR or AIRCR Reset.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BORSTAT</name>
|
|
<description>Reset was initiated by a Brown-Out Reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORSTAT</name>
|
|
<description>Reset was initiated by a Power-On Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EXRSTAT</name>
|
|
<description>Reset was initiated by an External Reset.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLRSTAT</name>
|
|
<description>Clear the status register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CLRSTAT</name>
|
|
<description>Writing a 1 to this bit clears all bits in the RST_STAT.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPIU_RST</name>
|
|
<description>TPIU reset</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>TPIURST</name>
|
|
<description>Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>Reset Interrupt register: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>BODH</name>
|
|
<description>Enables an interrupt that triggers when VCC is below BODH level.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Reset Interrupt register: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>BODH</name>
|
|
<description>Enables an interrupt that triggers when VCC is below BODH level.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>Reset Interrupt register: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>BODH</name>
|
|
<description>Enables an interrupt that triggers when VCC is below BODH level.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>Reset Interrupt register: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>BODH</name>
|
|
<description>Enables an interrupt that triggers when VCC is below BODH level.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<version>1.0</version>
|
|
<description>Real Time Clock</description>
|
|
<!-- <groupName>GROUP_RTC</groupName> -->
|
|
<baseAddress>0x40004040</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x000000D0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRLOW</name>
|
|
<description>RTC Counters Lower</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0x3F7F7FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTRHR</name>
|
|
<description>Hours Counter</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTRMIN</name>
|
|
<description>Minutes Counter</description>
|
|
<bitRange>[22:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTRSEC</name>
|
|
<description>Seconds Counter</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTR100</name>
|
|
<description>100ths of a second Counter</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRUP</name>
|
|
<description>RTC Counters Upper</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x9FFF1F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTERR</name>
|
|
<description>Counter read error status</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No read error occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDERR</name>
|
|
<description>Read error occurred</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEB</name>
|
|
<description>Century enable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Disable the Century bit from changing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Enable the Century bit to change</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB</name>
|
|
<description>Century</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>2000</name>
|
|
<description>Century is 2000s</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1900_2100</name>
|
|
<description>Century is 1900s/2100s</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTRWKDY</name>
|
|
<description>Weekdays Counter</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTRYR</name>
|
|
<description>Years Counter</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTRMO</name>
|
|
<description>Months Counter</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTRDATE</name>
|
|
<description>Date Counter</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALMLOW</name>
|
|
<description>RTC Alarms Lower</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3F7F7FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALMHR</name>
|
|
<description>Hours Alarm</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ALMMIN</name>
|
|
<description>Minutes Alarm</description>
|
|
<bitRange>[22:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ALMSEC</name>
|
|
<description>Seconds Alarm</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ALM100</name>
|
|
<description>100ths of a second Alarm</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALMUP</name>
|
|
<description>RTC Alarms Upper</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00071F3F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALMWKDY</name>
|
|
<description>Weekdays Alarm</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ALMMO</name>
|
|
<description>Months Alarm</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ALMDATE</name>
|
|
<description>Date Alarm</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCCTL</name>
|
|
<description>RTC Control Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>HR1224</name>
|
|
<description>Hours Counter mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>24HR</name>
|
|
<description>Hours in 24 hour mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12HR</name>
|
|
<description>Hours in 12 hour mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTOP</name>
|
|
<description>RTC input clock control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Allow the RTC input clock to run</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the RTC input clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPT</name>
|
|
<description>Alarm repeat interval</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Alarm interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YEAR</name>
|
|
<description>Interrupt every year</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONTH</name>
|
|
<description>Interrupt every month</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WEEK</name>
|
|
<description>Interrupt every week</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAY</name>
|
|
<description>Interrupt every day</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HR</name>
|
|
<description>Interrupt every hour</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MIN</name>
|
|
<description>Interrupt every minute</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEC</name>
|
|
<description>Interrupt every second/10th/100th</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRTC</name>
|
|
<description>Counter write control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Counter writes are disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Counter writes are enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>RTC Interrupt Register: Enable</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>RTC Interrupt Register: Status</description>
|
|
<addressOffset>0x000000C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>RTC Interrupt Register: Clear</description>
|
|
<addressOffset>0x000000C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>RTC Interrupt Register: Set</description>
|
|
<addressOffset>0x000000CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ALM</name>
|
|
<description>RTC Alarm interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>XT Oscillator Fail interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Autocalibration Complete interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>Autocalibration Fail interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<version>1.0</version>
|
|
<description>Serial UART</description>
|
|
<!-- <groupName>GROUP_UART</groupName> -->
|
|
<baseAddress>0x4001C000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000048</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OEDATA</name>
|
|
<description>This is the overrun error indicator.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART OEDATA, overrun error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART OEDATA, overrun error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEDATA</name>
|
|
<description>This is the break error indicator.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART BEDATA, break error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART BEDATA, break error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEDATA</name>
|
|
<description>This is the parity error indicator.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART PEDATA, parity error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART PEDATA, parity error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEDATA</name>
|
|
<description>This is the framing error indicator.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART FEDATA, framing error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART FEDATA, framing error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>This is the UART data port.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSR</name>
|
|
<description>UART Status Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OESTAT</name>
|
|
<description>This is the overrun error indicator.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART OESTAT, overrun error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART OESTAT, overrun error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BESTAT</name>
|
|
<description>This is the break error indicator.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART BESTAT, break error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART BESTAT, break error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PESTAT</name>
|
|
<description>This is the parity error indicator.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART PESTAT, parity error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART PESTAT, parity error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FESTAT</name>
|
|
<description>This is the framing error indicator.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERR</name>
|
|
<description>No error on UART FESTAT, framing error indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR</name>
|
|
<description>Error on UART FESTAT, framing error indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<description>Flag Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>TXBUSY</name>
|
|
<description>This bit holds the transmit BUSY indicator.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>This bit holds the transmit FIFO empty indicator.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XMTFIFO_EMPTY</name>
|
|
<description>Transmit fifo is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFF</name>
|
|
<description>This bit holds the receive FIFO full indicator.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RCVFIFO_FULL</name>
|
|
<description>Receive fifo is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFF</name>
|
|
<description>This bit holds the transmit FIFO full indicator.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XMTFIFO_FULL</name>
|
|
<description>Transmit fifo is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>This bit holds the receive FIFO empty indicator.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RCVFIFO_EMPTY</name>
|
|
<description>Receive fifo is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>This bit holds the busy indicator.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BUSY</name>
|
|
<description>UART busy indicator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>This bit holds the data carrier detect indicator.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DETECTED</name>
|
|
<description>Data carrier detect detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>This bit holds the data set ready indicator.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READY</name>
|
|
<description>Data set ready.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>This bit holds the clear to send indicator.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLEARTOSEND</name>
|
|
<description>Clear to send is indicated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ILPR</name>
|
|
<description>IrDA Counter</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>ILPDVSR</name>
|
|
<description>These bits hold the IrDA counter divisor.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IBRD</name>
|
|
<description>Integer Baud Rate Divisor</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>DIVINT</name>
|
|
<description>These bits hold the baud integer divisor.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FBRD</name>
|
|
<description>Fractional Baud Rate Divisor</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>DIVFRAC</name>
|
|
<description>These bits hold the baud fractional divisor.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCRH</name>
|
|
<description>Line Control High</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>SPS</name>
|
|
<description>This bit holds the stick parity select.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WLEN</name>
|
|
<description>These bits hold the write length.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FEN</name>
|
|
<description>This bit holds the FIFO enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STP2</name>
|
|
<description>This bit holds the two stop bits select.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPS</name>
|
|
<description>This bit holds the even parity select.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PEN</name>
|
|
<description>This bit holds the parity enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BRK</name>
|
|
<description>This bit holds the break set.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000300</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>This bit enables CTS hardware flow control.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>This bit enables RTS hardware flow control.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OUT2</name>
|
|
<description>This bit holds modem Out2.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OUT1</name>
|
|
<description>This bit holds modem Out1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>This bit enables request to send.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DTR</name>
|
|
<description>This bit enables data transmit ready.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>This bit is the receive enable.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>This bit is the transmit enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LBE</name>
|
|
<description>This bit is the loopback enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>This bitfield is the UART clock select.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOCLK</name>
|
|
<description>No UART clock. This is the low power default.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24MHZ</name>
|
|
<description>24 MHz clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12MHZ</name>
|
|
<description>12 MHz clock.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6MHZ</name>
|
|
<description>6 MHz clock.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3MHZ</name>
|
|
<description>3 MHz clock.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>This bit is the UART clock enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SIRLP</name>
|
|
<description>This bit is the SIR low power select.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SIREN</name>
|
|
<description>This bit is the SIR ENDEC enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>UARTEN</name>
|
|
<description>This bit is the UART enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFLS</name>
|
|
<description>FIFO Interrupt Level Select</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000012</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>RXIFLSEL</name>
|
|
<description>These bits hold the receive FIFO interrupt level.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXIFLSEL</name>
|
|
<description>These bits hold the transmit FIFO interrupt level.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OEIM</name>
|
|
<description>This bit holds the overflow interrupt enable.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BEIM</name>
|
|
<description>This bit holds the break error interrupt enable.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PEIM</name>
|
|
<description>This bit holds the parity error interrupt enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FEIM</name>
|
|
<description>This bit holds the framing error interrupt enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>This bit holds the receive timeout interrupt enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>This bit holds the transmit interrupt enable.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>This bit holds the receive interrupt enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSRMIM</name>
|
|
<description>This bit holds the modem DSR interrupt enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCDMIM</name>
|
|
<description>This bit holds the modem DCD interrupt enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTSMIM</name>
|
|
<description>This bit holds the modem CTS interrupt enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXCMPMIM</name>
|
|
<description>This bit holds the modem TXCMP interrupt enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IES</name>
|
|
<description>Interrupt Status</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OERIS</name>
|
|
<description>This bit holds the overflow interrupt status.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BERIS</name>
|
|
<description>This bit holds the break error interrupt status.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PERIS</name>
|
|
<description>This bit holds the parity error interrupt status.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FERIS</name>
|
|
<description>This bit holds the framing error interrupt status.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTRIS</name>
|
|
<description>This bit holds the receive timeout interrupt status.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXRIS</name>
|
|
<description>This bit holds the transmit interrupt status.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXRIS</name>
|
|
<description>This bit holds the receive interrupt status.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSRMRIS</name>
|
|
<description>This bit holds the modem DSR interrupt status.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCDMRIS</name>
|
|
<description>This bit holds the modem DCD interrupt status.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTSMRIS</name>
|
|
<description>This bit holds the modem CTS interrupt status.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXCMPMRIS</name>
|
|
<description>This bit holds the modem TXCMP interrupt status.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Masked Interrupt Status</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OEMIS</name>
|
|
<description>This bit holds the overflow interrupt status masked.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BEMIS</name>
|
|
<description>This bit holds the break error interrupt status masked.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PEMIS</name>
|
|
<description>This bit holds the parity error interrupt status masked.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FEMIS</name>
|
|
<description>This bit holds the framing error interrupt status masked.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTMIS</name>
|
|
<description>This bit holds the receive timeout interrupt status masked.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXMIS</name>
|
|
<description>This bit holds the transmit interrupt status masked.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXMIS</name>
|
|
<description>This bit holds the receive interrupt status masked.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSRMMIS</name>
|
|
<description>This bit holds the modem DSR interrupt status masked.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCDMMIS</name>
|
|
<description>This bit holds the modem DCD interrupt status masked.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTSMMIS</name>
|
|
<description>This bit holds the modem CTS interrupt status masked.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXCMPMMIS</name>
|
|
<description>This bit holds the modem TXCMP interrupt status masked.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEC</name>
|
|
<description>Interrupt Clear</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OEIC</name>
|
|
<description>This bit holds the overflow interrupt clear.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BEIC</name>
|
|
<description>This bit holds the break error interrupt clear.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PEIC</name>
|
|
<description>This bit holds the parity error interrupt clear.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FEIC</name>
|
|
<description>This bit holds the framing error interrupt clear.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTIC</name>
|
|
<description>This bit holds the receive timeout interrupt clear.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXIC</name>
|
|
<description>This bit holds the transmit interrupt clear.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXIC</name>
|
|
<description>This bit holds the receive interrupt clear.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSRMIC</name>
|
|
<description>This bit holds the modem DSR interrupt clear.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCDMIC</name>
|
|
<description>This bit holds the modem DCD interrupt clear.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTSMIC</name>
|
|
<description>This bit holds the modem CTS interrupt clear.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXCMPMIC</name>
|
|
<description>This bit holds the modem TXCMP interrupt clear.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART1</name>
|
|
<baseAddress>0x4001D000</baseAddress>
|
|
<interrupt>
|
|
<name>UART1</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>VCOMP</name>
|
|
<version>1.0</version>
|
|
<description>Voltage Comparator</description>
|
|
<!-- <groupName>GROUP_VCOMP</groupName> -->
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000210</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>VCOMP</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000F0303</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>LVLSEL</name>
|
|
<description>When the reference input NSEL is set to NSEL_DAC, this bitfield selects the voltage level for the negative input to the comparator.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P58V</name>
|
|
<description>Set Reference input to 0.58 Volts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0P77V</name>
|
|
<description>Set Reference input to 0.77 Volts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0P97V</name>
|
|
<description>Set Reference input to 0.97 Volts.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P16V</name>
|
|
<description>Set Reference input to 1.16 Volts.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P35V</name>
|
|
<description>Set Reference input to 1.35 Volts.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P55V</name>
|
|
<description>Set Reference input to 1.55 Volts.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P74V</name>
|
|
<description>Set Reference input to 1.74 Volts.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P93V</name>
|
|
<description>Set Reference input to 1.93 Volts.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2P13V</name>
|
|
<description>Set Reference input to 2.13 Volts.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2P32V</name>
|
|
<description>Set Reference input to 2.32 Volts.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2P51V</name>
|
|
<description>Set Reference input to 2.51 Volts.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2P71V</name>
|
|
<description>Set Reference input to 2.71 Volts.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2P90V</name>
|
|
<description>Set Reference input to 2.90 Volts.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3P09V</name>
|
|
<description>Set Reference input to 3.09 Volts.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3P29V</name>
|
|
<description>Set Reference input to 3.29 Volts.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3P48V</name>
|
|
<description>Set Reference input to 3.48 Volts.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSEL</name>
|
|
<description>This bitfield selects the negative input to the comparator.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VREFEXT1</name>
|
|
<description>Use external reference 1 for reference input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREFEXT2</name>
|
|
<description>Use external reference 2 for reference input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREFEXT3</name>
|
|
<description>Use external reference 3 for reference input.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>Use DAC output selected by LVLSEL for reference input.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>This bitfield selects the positive input to the comparator.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VDDADJ</name>
|
|
<description>Use VDDADJ for the positive input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VTEMP</name>
|
|
<description>Use the temperature sensor output for the positive input. Note: If this channel is selected for PSEL, the bandap circuit required for temperature comparisons will automatically turn on. The bandgap circuit requires 11us to stabalize.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VEXT1</name>
|
|
<description>Use external voltage 0 for positive input.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VEXT2</name>
|
|
<description>Use external voltage 1 for positive input.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PWDSTAT</name>
|
|
<description>This bit indicates the power down state of the voltage comparator.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>The voltage comparator is powered down.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPOUT</name>
|
|
<description>This bit is 1 if the positive input of the comparator is greater than the negative input.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VOUT_LOW</name>
|
|
<description>The negative input of the comparator is greater than the positive input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VOUT_HIGH</name>
|
|
<description>The positive input of the comparator is greater than the negative input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWDKEY</name>
|
|
<description>Key Register for Powering Down the Voltage Comparator</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>PWDKEY</name>
|
|
<description>Key register value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Key</name>
|
|
<description>Key</description>
|
|
<value>55</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>Voltage Comparator Interrupt registers: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OUTHI</name>
|
|
<description>This bit is the vcompout high interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OUTLOW</name>
|
|
<description>This bit is the vcompout low interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Voltage Comparator Interrupt registers: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OUTHI</name>
|
|
<description>This bit is the vcompout high interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OUTLOW</name>
|
|
<description>This bit is the vcompout low interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>Voltage Comparator Interrupt registers: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OUTHI</name>
|
|
<description>This bit is the vcompout high interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OUTLOW</name>
|
|
<description>This bit is the vcompout low interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>Voltage Comparator Interrupt registers: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>OUTHI</name>
|
|
<description>This bit is the vcompout high interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OUTLOW</name>
|
|
<description>This bit is the vcompout low interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>WDT</name>
|
|
<version>1.0</version>
|
|
<description>Watchdog Timer</description>
|
|
<!-- <groupName>GROUP_WDT</groupName> -->
|
|
<baseAddress>0x40024000</baseAddress>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000210</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDT</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00FFFF00</resetValue>
|
|
<resetMask>0x07FFFF07</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Select the frequency for the WDT. All values not enumerated below are undefined.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Low Power Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128HZ</name>
|
|
<description>128 Hz LFRC clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16HZ</name>
|
|
<description>16 Hz LFRC clock.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1HZ</name>
|
|
<description>1 Hz LFRC clock.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_16HZ</name>
|
|
<description>1/16th Hz LFRC clock.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTVAL</name>
|
|
<description>This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESVAL</name>
|
|
<description>This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESEN</name>
|
|
<description>This bitfield enables the WDT reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDTEN</name>
|
|
<description>This bitfield enables the WDT.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTRT</name>
|
|
<description>Restart the watchdog timer</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>RSTRT</name>
|
|
<description>Writing 0xB2 to WDTRSTRT restarts the watchdog timer.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KEYVALUE</name>
|
|
<description>This is the key value to write to WDTRSTRT to restart the WDT.</description>
|
|
<value>178</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Locks the WDT</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KEYVALUE</name>
|
|
<description>This is the key value to write to WDTLOCK to lock the WDT.</description>
|
|
<value>58</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>Current Counter Value for WDT</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Read-Only current value of the WDT counter</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>WDT Interrupt register: Enable</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WDTINT</name>
|
|
<description>Watchdog Timer Interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>WDT Interrupt register: Status</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WDTINT</name>
|
|
<description>Watchdog Timer Interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>WDT Interrupt register: Clear</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WDTINT</name>
|
|
<description>Watchdog Timer Interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>WDT Interrupt register: Set</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>WDTINT</name>
|
|
<description>Watchdog Timer Interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|