622 lines
22 KiB
C
622 lines
22 KiB
C
//*****************************************************************************
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//
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// am_hal_pwrctrl.c
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//! @file
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//!
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//! @brief Functions for enabling and disabling power domains.
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//!
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//! @addtogroup pwrctrl3p Power Control
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//! @ingroup apollo3phal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//
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// Maximum number of checks to memory power status before declaring error.
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//
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#define AM_HAL_PWRCTRL_MAX_WAIT 20
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//
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// Define the peripheral control structure.
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//
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const struct
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{
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uint32_t ui32PeriphEnable;
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uint32_t ui32PeriphStatus;
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uint32_t ui32PeriphEvent;
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}
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am_hal_pwrctrl_peripheral_control[AM_HAL_PWRCTRL_PERIPH_MAX] =
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{
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{0, 0, 0}, // AM_HAL_PWRCTRL_PERIPH_NONE
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN),
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PWRCTRL_DEVPWRSTATUS_HCPA_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOS
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN),
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PWRCTRL_DEVPWRSTATUS_HCPB_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM0
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN),
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PWRCTRL_DEVPWRSTATUS_HCPB_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM1
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN),
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PWRCTRL_DEVPWRSTATUS_HCPB_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM2
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN),
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PWRCTRL_DEVPWRSTATUS_HCPC_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM3
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN),
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PWRCTRL_DEVPWRSTATUS_HCPC_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM4
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN),
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PWRCTRL_DEVPWRSTATUS_HCPC_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM5
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN),
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PWRCTRL_DEVPWRSTATUS_HCPA_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_UART0
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN),
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PWRCTRL_DEVPWRSTATUS_HCPA_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_UART1
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN),
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PWRCTRL_DEVPWRSTATUS_PWRADC_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_ADCEVEN, PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_ADC
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN),
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PWRCTRL_DEVPWRSTATUS_HCPA_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_SCARD
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI0, PWRCTRL_DEVPWREN_PWRMSPI0_EN),
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PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_MSPIEVEN, PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_MSPI0
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI1, PWRCTRL_DEVPWREN_PWRMSPI1_EN),
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PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_MSPIEVEN, PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_MSPI1
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI2, PWRCTRL_DEVPWREN_PWRMSPI2_EN),
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PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_MSPIEVEN, PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_MSPI2
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN),
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PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_PDMEVEN, PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_PDM
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{_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN),
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PWRCTRL_DEVPWRSTATUS_BLEL_Msk,
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_VAL2FLD(PWRCTRL_DEVPWREVENTEN_BLELEVEN, PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN)} // AM_HAL_PWRCTRL_PERIPH_BLEL
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};
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//
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// Define the memory control structure.
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//
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const struct
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{
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uint32_t ui32MemoryEnable;
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uint32_t ui32MemoryStatus;
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uint32_t ui32MemoryEvent;
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uint32_t ui32MemoryMask;
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uint32_t ui32StatusMask;
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uint32_t ui32PwdSlpEnable;
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}
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am_hal_pwrctrl_memory_control[AM_HAL_PWRCTRL_MEM_MAX] =
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{
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{0, 0, 0, 0, 0, 0},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_128K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_192K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_256K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_320K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_384K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_448K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_448K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_448K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_448K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_512K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_512K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_512K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_512K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_576K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_576K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_576K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_576K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_672K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_672K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_672K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_672K},
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{AM_HAL_PWRCTRL_MEMEN_SRAM_768K,
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_768K,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_768K,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_768K},
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{AM_HAL_PWRCTRL_MEMEN_FLASH_1M,
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AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M,
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AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M},
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{AM_HAL_PWRCTRL_MEMEN_FLASH_2M,
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AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_2M,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_2M,
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AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_2M},
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{AM_HAL_PWRCTRL_MEMEN_CACHE,
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0,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE,
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AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK,
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0,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE},
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{AM_HAL_PWRCTRL_MEMEN_ALL,
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AM_HAL_PWRCTRL_PWRONSTATUS_ALL,
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AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL,
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AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK,
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AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK,
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AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL}
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};
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// ****************************************************************************
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//
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// am_hal_pwrctrl_periph_enable()
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// Enable power for a peripheral.
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//
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// ****************************************************************************
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uint32_t
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am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral)
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{
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//
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// Enable power control for the given device.
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//
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AM_CRITICAL_BEGIN
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PWRCTRL->DEVPWREN |= am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable;
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AM_CRITICAL_END
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for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WAIT; wait_usecs += 10)
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{
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am_hal_flash_delay(FLASH_CYCLES_US(10));
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if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0)
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{
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break;
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}
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}
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//
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// Check the device status.
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//
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if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0 )
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{
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return AM_HAL_STATUS_SUCCESS;
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}
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else
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{
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return AM_HAL_STATUS_FAIL;
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}
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}
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// ****************************************************************************
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//
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// am_hal_pwrctrl_periph_disable()
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// Disable power for a peripheral.
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//
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// ****************************************************************************
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uint32_t
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am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral)
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{
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//
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// Disable power domain for the given device.
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//
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AM_CRITICAL_BEGIN
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PWRCTRL->DEVPWREN &= ~am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable;
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AM_CRITICAL_END
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for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WAIT; wait_usecs += 10)
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{
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am_hal_flash_delay(FLASH_CYCLES_US(10));
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if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) == 0 )
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{
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break;
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}
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}
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//
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// Check the device status.
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//
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if ( ( PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) == 0 )
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{
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return AM_HAL_STATUS_SUCCESS;
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}
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else
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{
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return AM_HAL_STATUS_FAIL;
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}
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}
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//*****************************************************************************
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//
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//! @brief Determine whether a peripheral is currently enabled.
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//!
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//! @param ePeripheral - The peripheral to enable.
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//! @param pui32Enabled - Pointer to a ui32 that will return as 1 or 0.
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//!
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//! This function determines to the caller whether a given peripheral is
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//! currently enabled or disabled.
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//!
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//! @return status - generic or interface specific status.
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//
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//*****************************************************************************
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uint32_t
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am_hal_pwrctrl_periph_enabled(am_hal_pwrctrl_periph_e ePeripheral,
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uint32_t *pui32Enabled)
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{
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uint32_t ui32Mask = 0;
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uint32_t ui32Enabled = 0;
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if ( pui32Enabled == NULL )
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{
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return AM_HAL_STATUS_INVALID_ARG;
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}
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switch ( ePeripheral )
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{
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case AM_HAL_PWRCTRL_PERIPH_NONE:
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case AM_HAL_PWRCTRL_PERIPH_SCARD:
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break;
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case AM_HAL_PWRCTRL_PERIPH_IOS:
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case AM_HAL_PWRCTRL_PERIPH_UART0:
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case AM_HAL_PWRCTRL_PERIPH_UART1:
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ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPA_Msk;
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break;
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case AM_HAL_PWRCTRL_PERIPH_IOM0:
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case AM_HAL_PWRCTRL_PERIPH_IOM1:
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case AM_HAL_PWRCTRL_PERIPH_IOM2:
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ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPB_Msk;
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break;
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case AM_HAL_PWRCTRL_PERIPH_IOM3:
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case AM_HAL_PWRCTRL_PERIPH_IOM4:
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case AM_HAL_PWRCTRL_PERIPH_IOM5:
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ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPC_Msk;
|
|
break;
|
|
case AM_HAL_PWRCTRL_PERIPH_ADC:
|
|
ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRADC_Msk;
|
|
break;
|
|
case AM_HAL_PWRCTRL_PERIPH_MSPI0:
|
|
ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk;
|
|
break;
|
|
case AM_HAL_PWRCTRL_PERIPH_MSPI1:
|
|
ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk;
|
|
break;
|
|
case AM_HAL_PWRCTRL_PERIPH_MSPI2:
|
|
ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk;
|
|
break;
|
|
case AM_HAL_PWRCTRL_PERIPH_PDM:
|
|
ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk;
|
|
break;
|
|
case AM_HAL_PWRCTRL_PERIPH_BLEL:
|
|
ui32Mask = PWRCTRL_DEVPWRSTATUS_BLEL_Msk;
|
|
break;
|
|
default:
|
|
return AM_HAL_STATUS_FAIL;
|
|
}
|
|
|
|
if ( ui32Mask != 0 )
|
|
{
|
|
ui32Enabled = PWRCTRL->DEVPWRSTATUS & ui32Mask ? 1 : 0;
|
|
}
|
|
|
|
*pui32Enabled = ui32Enabled;
|
|
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
}
|
|
|
|
|
|
|
|
// ****************************************************************************
|
|
//
|
|
// am_hal_pwrctrl_memory_enable()
|
|
// Enable a configuration of memory.
|
|
//
|
|
// ****************************************************************************
|
|
uint32_t
|
|
am_hal_pwrctrl_memory_enable(am_hal_pwrctrl_mem_e eMemConfig)
|
|
{
|
|
uint32_t ui32MemEnMask, ui32MemDisMask, ui32MemRegionMask, ui32MemStatusMask;
|
|
|
|
ui32MemEnMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryEnable;
|
|
ui32MemDisMask = ~am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryEnable;
|
|
ui32MemRegionMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryMask;
|
|
ui32MemStatusMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32StatusMask;
|
|
|
|
//
|
|
// Disable unneeded memory. If nothing to be disabled, skip to save time.
|
|
//
|
|
// Note that a deliberate disable step using a disable mask is taken here
|
|
// for 2 reasons: 1) To only affect the specified type of memory, and 2)
|
|
// To avoid inadvertently disabling any memory currently being depended on.
|
|
//
|
|
if ( ui32MemDisMask != 0 )
|
|
{
|
|
PWRCTRL->MEMPWREN &=
|
|
~(ui32MemDisMask & ui32MemRegionMask) |
|
|
(_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0) |
|
|
_VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN));
|
|
am_hal_flash_delay(FLASH_CYCLES_US(1));
|
|
}
|
|
|
|
//
|
|
// Enable the required memory.
|
|
//
|
|
if ( ui32MemEnMask != 0 )
|
|
{
|
|
PWRCTRL->MEMPWREN |= ui32MemEnMask;
|
|
|
|
for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WAIT; wait_usecs += 10)
|
|
{
|
|
am_hal_flash_delay(FLASH_CYCLES_US(10));
|
|
|
|
if ( (PWRCTRL->MEMPWRSTATUS & ui32MemStatusMask) ==
|
|
am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryStatus )
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Return status based on whether the power control memory status has reached the desired state.
|
|
//
|
|
if ( ( PWRCTRL->MEMPWRSTATUS & ui32MemStatusMask) ==
|
|
am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryStatus )
|
|
{
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
}
|
|
else
|
|
{
|
|
return AM_HAL_STATUS_FAIL;
|
|
}
|
|
}
|
|
|
|
// ****************************************************************************
|
|
//
|
|
// am_hal_pwrctrl_memory_deepsleep_powerdown()
|
|
// Power down respective memory.
|
|
//
|
|
// ****************************************************************************
|
|
uint32_t
|
|
am_hal_pwrctrl_memory_deepsleep_powerdown(am_hal_pwrctrl_mem_e eMemConfig)
|
|
{
|
|
if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX )
|
|
{
|
|
return AM_HAL_STATUS_FAIL;
|
|
}
|
|
|
|
//
|
|
// Power down the required memory.
|
|
//
|
|
PWRCTRL->MEMPWDINSLEEP |= am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable;
|
|
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
}
|
|
|
|
// ****************************************************************************
|
|
//
|
|
// am_hal_pwrctrl_memory_deepsleep_retain()
|
|
// Apply retention voltage to respective memory.
|
|
//
|
|
// ****************************************************************************
|
|
uint32_t
|
|
am_hal_pwrctrl_memory_deepsleep_retain(am_hal_pwrctrl_mem_e eMemConfig)
|
|
{
|
|
if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX )
|
|
{
|
|
return AM_HAL_STATUS_FAIL;
|
|
}
|
|
|
|
//
|
|
// Retain the required memory.
|
|
//
|
|
PWRCTRL->MEMPWDINSLEEP &= ~am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable;
|
|
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
}
|
|
|
|
// ****************************************************************************
|
|
//
|
|
// am_hal_pwrctrl_low_power_init()
|
|
// Initialize system for low power configuration.
|
|
//
|
|
// ****************************************************************************
|
|
uint32_t
|
|
am_hal_pwrctrl_low_power_init(void)
|
|
{
|
|
uint32_t ui32Status;
|
|
|
|
//
|
|
// Take a snapshot of the reset status, if not done already
|
|
//
|
|
if (!gAmHalResetStatus)
|
|
{
|
|
gAmHalResetStatus = RSTGEN->STAT;
|
|
}
|
|
|
|
//
|
|
// Adjust the SIMOBUCK LP settings.
|
|
//
|
|
if (APOLLO3_GE_B0)
|
|
{
|
|
MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPHIGHTONTRIM = 2;
|
|
MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPLOWTONTRIM = 3;
|
|
MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPHIGHTOFFTRIM = 5;
|
|
MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPLOWTOFFTRIM = 2;
|
|
MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTOFFTRIM = 6;
|
|
MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPLOWTOFFTRIM = 1;
|
|
MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTONTRIM = 3;
|
|
MCUCTRL->SIMOBUCK4_b.SIMOBUCKMEMLPLOWTONTRIM = 3;
|
|
}
|
|
|
|
//
|
|
// Adjust the SIMOBUCK Timeout settings.
|
|
//
|
|
if (APOLLO3_GE_A1)
|
|
{
|
|
MCUCTRL->SIMOBUCK4_b.SIMOBUCKCOMP2TIMEOUTEN = 0;
|
|
}
|
|
|
|
//
|
|
// Configure cache for low power and performance.
|
|
//
|
|
am_hal_cachectrl_control(AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED, 0);
|
|
|
|
//
|
|
// Check if the BLE is already enabled.
|
|
//
|
|
if ( PWRCTRL->DEVPWRSTATUS_b.BLEL == 0)
|
|
{
|
|
//
|
|
// First request the BLE feature and check that it was available and acknowledged.
|
|
//
|
|
MCUCTRL->FEATUREENABLE_b.BLEREQ = 1;
|
|
ui32Status = am_hal_flash_delay_status_check(10000,
|
|
(uint32_t)&MCUCTRL->FEATUREENABLE,
|
|
(MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk |
|
|
MCUCTRL_FEATUREENABLE_BLEACK_Msk |
|
|
MCUCTRL_FEATUREENABLE_BLEREQ_Msk),
|
|
(MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk |
|
|
MCUCTRL_FEATUREENABLE_BLEACK_Msk |
|
|
MCUCTRL_FEATUREENABLE_BLEREQ_Msk),
|
|
true);
|
|
|
|
if (AM_HAL_STATUS_SUCCESS != ui32Status)
|
|
{
|
|
return AM_HAL_STATUS_TIMEOUT;
|
|
}
|
|
|
|
//
|
|
// Next, enable the BLE Buck.
|
|
//
|
|
PWRCTRL->SUPPLYSRC |= _VAL2FLD(PWRCTRL_SUPPLYSRC_BLEBUCKEN,
|
|
PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN);
|
|
|
|
//
|
|
// Allow the buck to go to low power mode in BLE sleep.
|
|
//
|
|
PWRCTRL->MISC |= _VAL2FLD(PWRCTRL_MISC_MEMVRLPBLE,
|
|
PWRCTRL_MISC_MEMVRLPBLE_EN);
|
|
|
|
}
|
|
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
}
|
|
|
|
void am_hal_pwrctrl_blebuck_trim(void)
|
|
{
|
|
//
|
|
// Enable the BLE buck trim values
|
|
//
|
|
if ( APOLLO3_GE_A1 )
|
|
{
|
|
AM_CRITICAL_BEGIN
|
|
MCUCTRL->BLEBUCK2_b.BLEBUCKTONHITRIM = 0x19;
|
|
MCUCTRL->BLEBUCK2_b.BLEBUCKTONLOWTRIM = 0xC;
|
|
CLKGEN->BLEBUCKTONADJ_b.TONADJUSTEN = CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS;
|
|
AM_CRITICAL_END
|
|
}
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|