564 lines
21 KiB
C
564 lines
21 KiB
C
//*****************************************************************************
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//
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// am_hal_mcuctrl.c
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//! @file
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//!
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//! @brief Functions for interfacing with the MCUCTRL.
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//!
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//! @addtogroup mcuctrl3 MCU Control (MCUCTRL)
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//! @ingroup apollo3hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Global Variables.
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//
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//*****************************************************************************
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//
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// Define the flash sizes from CHIPPN.
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//
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const uint32_t
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g_am_hal_mcuctrl_flash_size[AM_HAL_MCUCTRL_CHIPPN_FLASH_SIZE_N] =
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{
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16 * 1024, /* 0x0 0x00004000 16 KB */
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32 * 1024, /* 0x1 0x00008000 32 KB */
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64 * 1024, /* 0x2 0x00010000 64 KB */
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128 * 1024, /* 0x3 0x00020000 128 KB */
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256 * 1024, /* 0x4 0x00040000 256 KB */
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512 * 1024, /* 0x5 0x00080000 512 KB */
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1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */
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2 * 1024 * 1024, /* 0x7 0x00200000 2 MB */
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3 * 1024 * 1024 / 2, /* 0x8 0x00600000 1.5 MB */
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0, 0, 0, 0, 0, 0, 0
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};
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const uint32_t
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g_am_hal_mcuctrl_sram_size[AM_HAL_MCUCTRL_CHIPPN_SRAM_SIZE_N] =
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{
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16 * 1024, /* 0x0 0x00004000 16 KB */
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32 * 1024, /* 0x1 0x00008000 32 KB */
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64 * 1024, /* 0x2 0x00010000 64 KB */
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128 * 1024, /* 0x3 0x00020000 128 KB */
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256 * 1024, /* 0x4 0x00040000 256 KB */
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512 * 1024, /* 0x5 0x00080000 512 KB */
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1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */
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384 * 1024, /* 0x7 0x00200000 384 KB */
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768 * 1024, /* 0x8 0x000C0000 768 KB */
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0, 0, 0, 0, 0, 0, 0
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};
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// ****************************************************************************
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//
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// device_info_get()
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// Gets all relevant device information.
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//
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// ****************************************************************************
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static void
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device_info_get(am_hal_mcuctrl_device_t *psDevice)
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{
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//
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// Read the Part Number.
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//
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psDevice->ui32ChipPN = MCUCTRL->CHIPPN;
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//
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// Read the Chip ID0.
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//
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psDevice->ui32ChipID0 = MCUCTRL->CHIPID0;
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//
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// Read the Chip ID1.
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//
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psDevice->ui32ChipID1 = MCUCTRL->CHIPID1;
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//
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// Read the Chip Revision.
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//
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psDevice->ui32ChipRev = MCUCTRL->CHIPREV;
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//
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// Read the Chip VENDOR ID.
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//
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psDevice->ui32VendorID = MCUCTRL->VENDORID;
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//
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// Read the SKU (new for Apollo3).
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//
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psDevice->ui32SKU = MCUCTRL->SKU;
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//
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// Qualified from Part Number.
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//
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psDevice->ui32Qualified = (psDevice->ui32ChipPN >> MCUCTRL_CHIPPN_PARTNUM_QUAL_S) & 0x1;
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//
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// Flash size from Part Number.
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//
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psDevice->ui32FlashSize =
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g_am_hal_mcuctrl_flash_size[
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(psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M) >>
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MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S];
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//
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// SRAM size from Part Number.
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//
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psDevice->ui32SRAMSize =
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g_am_hal_mcuctrl_sram_size[
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(psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M) >>
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MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S];
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//
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// Now, let's look at the JEDEC info.
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// The full partnumber is 12 bits total, but is scattered across 2 registers.
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// Bits [11:8] are 0xE.
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// Bits [7:4] are 0xE for Apollo, 0xD for Apollo2, 0xC for Apollo3.
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// Bits [3:0] are defined differently for Apollo and Apollo2/Apollo3.
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// For Apollo, the low nibble is 0x0.
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// For Apollo2/Apollo3, the low nibble indicates flash and SRAM size.
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//
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psDevice->ui32JedecPN = JEDEC->PID0_b.PNL8 << 0;
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psDevice->ui32JedecPN |= JEDEC->PID1_b.PNH4 << 8;
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//
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// JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as
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// 0x1B, with parity bit is 0x9B. It is 8 bits located across 2 registers.
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//
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psDevice->ui32JedecJEPID = JEDEC->PID1_b.JEPIDL << 0;
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psDevice->ui32JedecJEPID |= JEDEC->PID2_b.JEPIDH << 4;
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//
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// CHIPREV is 8 bits located across 2 registers.
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//
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psDevice->ui32JedecCHIPREV = JEDEC->PID2_b.CHIPREVH4 << 4;
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psDevice->ui32JedecCHIPREV |= JEDEC->PID3_b.CHIPREVL4 << 0;
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//
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// Let's get the Coresight ID (32-bits across 4 registers)
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// For Apollo and Apollo2, it's expected to be 0xB105100D.
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//
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psDevice->ui32JedecCID = JEDEC->CID3_b.CID << 24;
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psDevice->ui32JedecCID |= JEDEC->CID2_b.CID << 16;
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psDevice->ui32JedecCID |= JEDEC->CID1_b.CID << 8;
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psDevice->ui32JedecCID |= JEDEC->CID0_b.CID << 0;
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} // device_info_get()
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//*****************************************************************************
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//
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// mcuctrl_fault_status()
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// Gets the fault status and capture registers.
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//
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//*****************************************************************************
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static void
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mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault)
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{
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uint32_t ui32FaultStat;
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//
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// Read the Fault Status Register.
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//
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ui32FaultStat = MCUCTRL->FAULTSTATUS;
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psFault->bICODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk);
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psFault->bDCODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk);
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psFault->bSYS = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_SYSFAULT_Msk);
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//
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// Read the DCODE fault capture address register.
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//
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psFault->ui32DCODE = MCUCTRL->DCODEFAULTADDR;
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//
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// Read the ICODE fault capture address register.
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//
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psFault->ui32ICODE |= MCUCTRL->ICODEFAULTADDR;
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//
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// Read the ICODE fault capture address register.
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//
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psFault->ui32SYS |= MCUCTRL->SYSFAULTADDR;
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} // mcuctrl_fault_status()
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// ****************************************************************************
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//
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// am_hal_mcuctrl_control()
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// Apply various specific commands/controls on the MCUCTRL module.
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//
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// ****************************************************************************
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uint32_t
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am_hal_mcuctrl_control(am_hal_mcuctrl_control_e eControl, void *pArgs)
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{
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uint32_t ui32Tbl;
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switch ( eControl )
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{
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case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE:
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//
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// Enable the Fault Capture registers.
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//
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MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 1;
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break;
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case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE:
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//
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// Disable the Fault Capture registers.
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//
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MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 0;
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break;
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case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE:
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//
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// Configure the bits in XTALCTRL that enable external 32KHz clock.
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//
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MCUCTRL->XTALCTRL &=
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~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk |
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MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk |
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MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk |
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MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk |
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MCUCTRL_XTALCTRL_XTALSWE_Msk);
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MCUCTRL->XTALCTRL |=
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_VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP) |
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_VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE) |
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_VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP) |
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_VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS) |
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_VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN);
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break;
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case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE:
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//
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// Configure the bits in XTALCTRL that disable external 32KHz
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// clock, thus re-configuring for the crystal.
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//
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MCUCTRL->XTALCTRL &=
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~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk |
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MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk |
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MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk |
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MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk |
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MCUCTRL_XTALCTRL_XTALSWE_Msk);
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MCUCTRL->XTALCTRL |=
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_VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP) |
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_VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE) |
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_VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP) |
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_VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN) |
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_VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS);
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break;
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case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH:
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{
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uint32_t ui32SramPrefetch = *(uint32_t*)pArgs;
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uint32_t ui32SetMsk, ui32ClrMsk, ui32SRAMreg;
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//
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// Validate the input flags.
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//
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if ( ui32SramPrefetch &
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~(AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR |
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AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE |
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AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA |
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AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE |
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AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR |
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AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE |
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AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA |
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AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) )
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{
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return AM_HAL_STATUS_INVALID_ARG;
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}
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//
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// Given the rule that NOxxx overrides xxx, and keeping in mind
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// that the cache settings cannot be set unless the regular
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// prefetch is also being set or is already set, the following
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// truth table results.
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// Note - this same TT also applies to data settings.
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// nc=no change.
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// I IC NI NIC: I IC
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// 0x0: 0 0 0 0 : nc nc
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// 0x1: 0 0 0 1 : nc 0
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// 0x2: 0 0 1 0 : 0 0
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// 0x3: 0 0 1 1 : 0 0
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// 0x4: 0 1 0 0 : INVALID
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// 0x5: 0 1 0 1 : nc nc
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// 0x6: 0 1 1 0 : INVALID
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// 0x7: 0 1 1 1 : 0 0
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// 0x8: 1 0 0 0 : 1 0
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// 0x9: 1 0 0 1 : 1 0
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// 0xA: 1 0 1 0 : 0 0
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// 0xB: 1 0 1 1 : 0 0
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// 0xC: 1 1 0 0 : 1 1
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// 0xD: 1 1 0 1 : 1 0
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// 0xE: 1 1 1 0 : INVALID
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// 0xF: 1 1 1 1 : 0 0
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//
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ui32Tbl = 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR) ? (1 << 3) : 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE) ? (1 << 2) : 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR) ? (1 << 1) : 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE) ? (1 << 0) : 0;
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//
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// Now augment the table entries with current register settings.
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//
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ui32SRAMreg = MCUCTRL->SRAMMODE;
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ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_Msk ? (1 << 3) : 0;
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ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk ? (1 << 2) : 0;
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ui32SetMsk = ui32ClrMsk = 0;
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switch ( ui32Tbl )
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{
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case 0x0:
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case 0x5:
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break;
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case 0x1:
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ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
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break;
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case 0x2:
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case 0x3:
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case 0x7:
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case 0xA:
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case 0xB:
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case 0xF:
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ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
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break;
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case 0x4:
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case 0x6:
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case 0xE:
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return AM_HAL_STATUS_INVALID_OPERATION;
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case 0x8:
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case 0x9:
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case 0xD:
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ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk;
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ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
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break;
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case 0xC:
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ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
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break;
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default:
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return AM_HAL_STATUS_INVALID_ARG;
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} // switch()
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//
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// Now, repeat with data settings.
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//
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ui32Tbl = 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA) ? (1 << 3) : 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE) ? (1 << 2) : 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA) ? (1 << 1) : 0;
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ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) ? (1 << 0) : 0;
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//
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// Now augment the table entries with current register settings.
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//
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ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_Msk ? (1 << 3) : 0;
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ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk ? (1 << 2) : 0;
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switch ( ui32Tbl )
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{
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case 0x0:
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case 0x5:
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break;
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case 0x1:
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ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
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break;
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case 0x2:
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case 0x3:
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case 0x7:
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case 0xA:
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case 0xB:
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case 0xF:
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ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
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break;
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case 0x4:
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case 0x6:
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case 0xE:
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return AM_HAL_STATUS_INVALID_OPERATION;
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case 0x8:
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case 0x9:
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case 0xD:
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ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk;
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ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
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break;
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case 0xC:
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ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
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break;
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default:
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return AM_HAL_STATUS_INVALID_ARG;
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} // switch()
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//
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// Arrange the register update such that clrmsk will have precedence
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// over setmsk.
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//
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AM_CRITICAL_BEGIN
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ui32SRAMreg = MCUCTRL->SRAMMODE;
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ui32SRAMreg |= ui32SetMsk;
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ui32SRAMreg &= ~ui32ClrMsk;
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MCUCTRL->SRAMMODE = ui32SRAMreg;
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AM_CRITICAL_END
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} // case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH
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break;
|
|
|
|
default:
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
|
}
|
|
|
|
//
|
|
// Return success status.
|
|
//
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
|
|
} // am_hal_mcuctrl_control()
|
|
|
|
// ****************************************************************************
|
|
//
|
|
// am_hal_mcuctrl_status_get()
|
|
//! This function returns current status of the MCUCTRL as obtained from
|
|
//! various registers of the MCUCTRL block.
|
|
//
|
|
// ****************************************************************************
|
|
uint32_t
|
|
am_hal_mcuctrl_status_get(am_hal_mcuctrl_status_t *psStatus)
|
|
{
|
|
uint32_t ui32Status;
|
|
|
|
if ( psStatus == NULL )
|
|
{
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
|
}
|
|
|
|
ui32Status = MCUCTRL->FEATUREENABLE;
|
|
psStatus->bBurstAck =
|
|
_FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTACK, ui32Status);
|
|
psStatus->bBLEAck =
|
|
_FLD2VAL(MCUCTRL_FEATUREENABLE_BLEACK, ui32Status);
|
|
|
|
psStatus->bDebuggerLockout =
|
|
_FLD2VAL(MCUCTRL_DEBUGGER_LOCKOUT, MCUCTRL->DEBUGGER);
|
|
|
|
psStatus->bADCcalibrated =
|
|
_FLD2VAL(MCUCTRL_ADCCAL_ADCCALIBRATED, MCUCTRL->ADCCAL);
|
|
|
|
psStatus->bBattLoadEnabled =
|
|
_FLD2VAL(MCUCTRL_ADCBATTLOAD_BATTLOAD, MCUCTRL->ADCBATTLOAD);
|
|
|
|
ui32Status = MCUCTRL->BOOTLOADER;
|
|
psStatus->bSecBootOnColdRst =
|
|
_FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOT, ui32Status);
|
|
psStatus->bSecBootOnWarmRst =
|
|
_FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTONRST, ui32Status);
|
|
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
|
|
} // am_hal_mcuctrl_status_get()
|
|
|
|
// ****************************************************************************
|
|
//
|
|
// am_hal_mcuctrl_info_get()
|
|
// Get information of the given MCUCTRL item.
|
|
//
|
|
// ****************************************************************************
|
|
uint32_t
|
|
am_hal_mcuctrl_info_get(am_hal_mcuctrl_infoget_e eInfoGet, void *pInfo)
|
|
{
|
|
am_hal_mcuctrl_feature_t *psFeature;
|
|
uint32_t ui32Feature;
|
|
|
|
if ( pInfo == NULL )
|
|
{
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
|
}
|
|
|
|
switch ( eInfoGet )
|
|
{
|
|
case AM_HAL_MCUCTRL_INFO_FEATURES_AVAIL:
|
|
psFeature = (am_hal_mcuctrl_feature_t*)pInfo;
|
|
ui32Feature = MCUCTRL->FEATUREENABLE;
|
|
psFeature->bBurstAvail =
|
|
_FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTAVAIL, ui32Feature);
|
|
psFeature->bBLEavail =
|
|
_FLD2VAL(MCUCTRL_FEATUREENABLE_BLEAVAIL, ui32Feature);
|
|
|
|
ui32Feature = MCUCTRL->BOOTLOADER;
|
|
psFeature->ui8SecBootFeature =
|
|
_FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTFEATURE, ui32Feature);
|
|
|
|
ui32Feature = MCUCTRL->SKU;
|
|
psFeature->bBLEFeature =
|
|
_FLD2VAL(MCUCTRL_SKU_ALLOWBLE, ui32Feature);
|
|
psFeature->bBurstFeature =
|
|
_FLD2VAL(MCUCTRL_SKU_ALLOWBURST, ui32Feature);
|
|
break;
|
|
|
|
case AM_HAL_MCUCTRL_INFO_DEVICEID:
|
|
device_info_get((am_hal_mcuctrl_device_t *)pInfo);
|
|
break;
|
|
|
|
case AM_HAL_MCUCTRL_INFO_FAULT_STATUS:
|
|
mcuctrl_fault_status((am_hal_mcuctrl_fault_t*)pInfo);
|
|
break;
|
|
|
|
default:
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
|
}
|
|
//
|
|
// Return success status.
|
|
//
|
|
return AM_HAL_STATUS_SUCCESS;
|
|
|
|
} // am_hal_mcuctrl_info_get()
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|