432 lines
13 KiB
C
432 lines
13 KiB
C
//*****************************************************************************
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//
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// am_hal_mcuctrl.c
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//! @file
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//!
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//! @brief Functions for interfacing with the MCUCTRL.
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//!
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//! @addtogroup mcuctrl1 MCU Control (MCUCTRL)
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//! @ingroup apollo1hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Global Variables.
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//
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//*****************************************************************************
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const uint32_t am_hal_mcuctrl_flash_size[] =
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{
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1 << 15, /* 0x0 0x008000 32k */
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1 << 16, /* 0x1 0x010000 64k */
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1 << 17, /* 0x2 0x020000 128k */
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1 << 18, /* 0x3 0x040000 256k */
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1 << 19, /* 0x4 0x080000 512k */
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1 << 20, /* 0x5 0x100000 1024k */
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1 << 21, /* 0x6 0x200000 2048k */
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0, /* 0x7 Invalid */
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0, /* 0x8 Invalid */
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0, /* 0x9 Invalid */
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0, /* 0xA Invalid */
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0, /* 0xB Invalid */
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0, /* 0xC Invalid */
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0, /* 0xD Invalid */
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0, /* 0xE Invalid */
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1 << 14 /* 0xF 0x004000 16k */
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};
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const uint32_t am_hal_mcuctrl_sram_size[] =
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{
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1 << 15, /* 0x0 0x008000 32k */
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1 << 16, /* 0x1 0x010000 64k */
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1 << 17, /* 0x2 0x020000 128k */
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1 << 18, /* 0x3 0x040000 256k */
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1 << 19, /* 0x4 0x080000 512k */
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1 << 20, /* 0x5 0x100000 1024k */
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1 << 21, /* 0x6 0x200000 2048k */
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0, /* 0x7 Invalid */
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0, /* 0x8 Invalid */
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0, /* 0x9 Invalid */
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0, /* 0xA Invalid */
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0, /* 0xB Invalid */
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0, /* 0xC Invalid */
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0, /* 0xD Invalid */
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0, /* 0xE Invalid */
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1 << 14 /* 0xF 0x004000 16k */
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};
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//*****************************************************************************
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//
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//! @brief Gets all relevant device information.
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//!
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//! @param psDevice is a pointer to a structure that will be used to store all
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//! device info.
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//!
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//! This function gets the device part number, chip IDs, and revision and
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//! stores them in the passed structure.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_device_info_get(am_hal_mcuctrl_device_t *psDevice)
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{
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//
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// Read the Part Number.
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//
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psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO);
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//
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// Read the Chip ID0.
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//
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psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0);
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//
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// Read the Chip ID1.
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//
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psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1);
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//
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// Read the Chip Revision.
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//
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psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV);
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//
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// Qualified from Part Number.
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//
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psDevice->ui32Qualified = AM_BFR(MCUCTRL, CHIP_INFO, QUAL);
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//
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// Flash size from Part Number.
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//
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psDevice->ui32FlashSize =
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am_hal_mcuctrl_flash_size[AM_BFR(MCUCTRL, CHIP_INFO, FLASH)];
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//
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// SRAM size from Part Number.
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//
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psDevice->ui32SRAMSize =
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am_hal_mcuctrl_sram_size[AM_BFR(MCUCTRL, CHIP_INFO, RAM)];
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//
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// Now, let's look at the JEDEC info.
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// The full partnumber is 12 bits total, but is scattered across 2 registers.
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// Bits [11:8] are 0xE.
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// Bits [7:4] are 0xE for Apollo, 0xD for Apollo2.
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// Bits [3:0] are defined differently for Apollo and Apollo2.
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// For Apollo, the low nibble is 0x0.
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// For Apollo2, the low nibble indicates flash and SRAM size.
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//
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psDevice->ui32JedecPN = (AM_BFR(JEDEC, PID0, PNL8) << 0);
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psDevice->ui32JedecPN |= (AM_BFR(JEDEC, PID1, PNH4) << 8);
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//
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// JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as
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// 0x1B, with parity bit is 0x9B. It is 8 bits located across 2 registers.
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//
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psDevice->ui32JedecJEPID = (AM_BFR(JEDEC, PID1, JEPIDL) << 0);
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psDevice->ui32JedecJEPID |= (AM_BFR(JEDEC, PID2, JEPIDH) << 4);
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//
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// CHIPREV is 8 bits located across 2 registers.
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//
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psDevice->ui32JedecCHIPREV = (AM_BFR(JEDEC, PID2, CHIPREVH4) << 4);
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psDevice->ui32JedecCHIPREV |= (AM_BFR(JEDEC, PID3, CHIPREVL4) << 0);
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//
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// Let's get the Coresight ID (32-bits across 4 registers)
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// For Apollo and Apollo2, it's expected to be 0xB105100D.
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//
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psDevice->ui32JedecCID = (AM_BFR(JEDEC, CID3, CID) << 24);
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psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID2, CID) << 16);
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psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID1, CID) << 8);
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psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID0, CID) << 0);
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}
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//*****************************************************************************
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//
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//! @brief Enables the fault capture registers.
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//!
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//! This function enables the DCODEFAULTADDR and ICODEFAULTADDR registers.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_fault_capture_enable(void)
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{
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//
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// Enable the Fault Capture registers.
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//
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AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 1);
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}
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//*****************************************************************************
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//
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//! @brief Disables the fault capture registers.
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//!
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//! This function disables the DCODEFAULTADDR and ICODEFAULTADDR registers.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_fault_capture_disable(void)
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{
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//
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// Disable the Fault Capture registers.
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//
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AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 0);
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}
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//*****************************************************************************
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//
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//! @brief Gets the fault status and capture registers.
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//!
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//! @param psFault is a pointer to a structure that will be used to store all
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//! fault info.
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//!
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//! This function gets the status of the ICODE, DCODE, and SYS bus faults and
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//! the addresses associated with the fault.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault)
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{
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uint32_t ui32FaultStat;
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//
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// Read the Fault Status Register.
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//
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ui32FaultStat = AM_REG(MCUCTRL, FAULTSTATUS);
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psFault->bICODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_ICODE_M);
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psFault->bDCODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_DCODE_M);
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psFault->bSYS = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_SYS_M);
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//
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// Read the DCODE fault capture address register.
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//
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psFault->ui32DCODE = AM_REG(MCUCTRL, DCODEFAULTADDR);
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//
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// Read the ICODE fault capture address register.
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//
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psFault->ui32ICODE |= AM_REG(MCUCTRL, ICODEFAULTADDR);
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//
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// Read the ICODE fault capture address register.
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//
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psFault->ui32SYS |= AM_REG(MCUCTRL, SYSFAULTADDR);
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}
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//*****************************************************************************
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//
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//! @brief Set power state of the flash.
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//!
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//! @param ui32FlashPower is the desired flash power configuration.
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//!
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//! This function sets the device power state for the flash banks.
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//!
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//! Valid values for ui32FlashPower are:
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//!
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//! AM_HAL_MCUCTRL_FLASH_POWER_DOWN_NONE
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//! AM_HAL_MCUCTRL_FLASH_POWER_DOWN_0
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//! AM_HAL_MCUCTRL_FLASH_POWER_DOWN_1
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//! AM_HAL_MCUCTRL_FLASH_POWER_DOWN_ALL
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_flash_power_set(uint32_t ui32FlashPower)
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{
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//
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// Write desired flash power state.
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//
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AM_REG(MCUCTRL, FLASHPWRDIS) = ui32FlashPower;
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}
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//*****************************************************************************
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//
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//! @brief Set power state of the SRAM.
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//!
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//! @param ui32SRAMPower is the desired SRAM power configuration.
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//! @param ui32SRAMPowerDeepSleep is the desired SRAM power configuration in
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//! deep sleep.
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//!
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//! This function sets the device power state for the SRAM banks.
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//!
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//! Valid values for ui32SRAMPower and ui32SRAMPowerDeepSleep are:
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//!
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_NONE
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_1
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_2
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_3
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_4
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_5
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_6
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_7
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//! AM_HAL_MCUCTRL_SRAM_POWER_DOWN_ALL
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_sram_power_set(uint32_t ui32SRAMPower,
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uint32_t ui32SRAMPowerDeepSleep)
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{
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//
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// Write desired SRAM power state.
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//
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AM_REG(MCUCTRL, SRAMPWRDIS) = ui32SRAMPower;
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//
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// Write desired SRAM deep sleep power state.
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//
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AM_REG(MCUCTRL, SRAMPWDINSLEEP) = ui32SRAMPowerDeepSleep;
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}
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//*****************************************************************************
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//
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//! @brief Enable the Bandgap.
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//!
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//! This function enables the Bandgap.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_bandgap_enable(void)
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{
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//
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// Enable the Bandgap in the MCUCTRL.
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//
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AM_REG(MCUCTRL, BANDGAPEN) = AM_REG_MCUCTRL_BANDGAPEN_BGPEN_M;
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}
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//*****************************************************************************
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//
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//! @brief Disable the Bandgap.
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//!
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//! This function disables the Bandgap.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_bandgap_disable(void)
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{
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//
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// Disable the Bandgap in the MCUCTRL.
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//
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AM_REG(MCUCTRL, BANDGAPEN) = ~AM_REG_MCUCTRL_BANDGAPEN_BGPEN_M;
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}
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//*****************************************************************************
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//
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//! @brief Enable the core and memory buck converters.
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//!
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//! This function enables the core and memory buck converters.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_bucks_enable(void)
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{
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//
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// Enable the core buck converter in the MCUCTRL.
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//
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AM_BFW(MCUCTRL, SUPPLYSRC, COREBUCKEN, 1);
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//
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// Enable the SRAM buck converter in the MCUCTRL.
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//
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AM_BFW(MCUCTRL, SUPPLYSRC, MEMBUCKEN, 1);
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//
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// Poll until core buck is enabled.
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//
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while( !AM_BFR(MCUCTRL, SUPPLYSTATUS, COREBUCKON) );
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//
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// Poll until SRAM buck is enabled.
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//
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while( !AM_BFR(MCUCTRL, SUPPLYSTATUS, MEMBUCKON) );
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}
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//*****************************************************************************
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//
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//! @brief Disable the core and memory buck converters.
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//!
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//! This function disables the core and memory buck converters.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_mcuctrl_bucks_disable(void)
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{
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//
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// Disable the core buck converter in the MCUCTRL.
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//
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AM_BFW(MCUCTRL, SUPPLYSRC, COREBUCKEN, 0);
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//
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// Disable the SRAM buck converter in the MCUCTRL.
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//
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AM_BFW(MCUCTRL, SUPPLYSRC, MEMBUCKEN, 0);
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}
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//*****************************************************************************
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//
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// End Doxygen group.
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//! @}
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//
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//*****************************************************************************
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