861 lines
33 KiB
C
861 lines
33 KiB
C
//*****************************************************************************
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//
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// am_bsp_pins.h
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//! @file
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//!
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//! @brief BSP pin configuration definitions.
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//!
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//! @addtogroup BSP Board Support Package (BSP)
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//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
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//! @ingroup BSP
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_BSP_PINS_H
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#define AM_BSP_PINS_H
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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// BUTTON0 pin: Labeled BTN2 on the Apollo3 Blue Plus EVB.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_BUTTON0 16
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON0;
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//*****************************************************************************
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//
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// BUTTON1 pin: Labeled BTN3 on the Apollo3 Blue Plus EVB.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_BUTTON1 18
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON1;
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//*****************************************************************************
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//
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// BUTTON2 pin: Labeled BTN4 on the Apollo3 Blue Plus EVB.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_BUTTON2 19
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON2;
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//*****************************************************************************
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//
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// LED0 pin: The LED nearest the end of the board.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_LED0 10
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED0;
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//*****************************************************************************
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//
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// LED1 pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_LED1 30
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED1;
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//*****************************************************************************
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//
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// LED2 pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_LED2 15
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED2;
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//*****************************************************************************
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//
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// LED3 pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_LED3 14
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED3;
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//*****************************************************************************
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//
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// LED4 pin: The LED at the most interior location.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_LED4 17
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED4;
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//*****************************************************************************
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//
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// COM_UART_TX pin: This pin is the COM_UART transmit pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_COM_UART_TX 22
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
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//*****************************************************************************
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//
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// COM_UART_RX pin: This pin is the COM_UART receive pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_COM_UART_RX 23
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
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//*****************************************************************************
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//
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// COM_UART_CTS pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_COM_UART_CTS 38
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_CTS;
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//*****************************************************************************
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//
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// COM_UART_RTS pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_COM_UART_RTS 37
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RTS;
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//*****************************************************************************
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//
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// UART_TX pin: This pin is the COM_UART transmit pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_UART_TX 35
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_UART_TX;
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//*****************************************************************************
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//
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// UART_RX pin: This pin is the COM_UART receive pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_UART_RX 36
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_UART_RX;
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//*****************************************************************************
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//
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// UART_CTS pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_UART_CTS 45
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_UART_CTS;
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//*****************************************************************************
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//
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// UART_RTS pin.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_UART_RTS 44
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_UART_RTS;
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//*****************************************************************************
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//
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// IOM0_CS pin: I/O Master 0 chip select.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM0_CS 11
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
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#define AM_BSP_IOM0_CS_CHNL 0
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//*****************************************************************************
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//
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// IOM0_CS3 pin: I/O Master 0 chip select.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM0_CS3 15
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
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#define AM_BSP_IOM0_CS3_CHNL 3
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//*****************************************************************************
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//
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// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM0_MISO 6
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
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//*****************************************************************************
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//
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// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM0_MOSI 7
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
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//*****************************************************************************
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//
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// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM0_SCK 5
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
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//*****************************************************************************
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//
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// IOM0_SCL pin: I/O Master 0 I2C clock signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM0_SCL 5
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
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//*****************************************************************************
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//
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// IOM0_SDA pin: I/O Master 0 I2C data signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM0_SDA 6
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
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//*****************************************************************************
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//
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// IOM1_CS pin: I/O Master 1 chip select.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM1_CS 34
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
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#define AM_BSP_IOM1_CS_CHNL 2
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//*****************************************************************************
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//
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// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM1_MISO 9
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
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//*****************************************************************************
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//
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// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM1_MOSI 10
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
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//*****************************************************************************
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//
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// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM1_SCK 8
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
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//*****************************************************************************
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//
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// IOM1_SCL pin: I/O Master 1 I2C clock signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM1_SCL 8
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
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//*****************************************************************************
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//
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// IOM1_SDA pin: I/O Master 1 I2C data signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM1_SDA 9
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
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//*****************************************************************************
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//
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// IOM2_CS pin: I/O Master 2 chip select.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM2_CS 15
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
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#define AM_BSP_IOM2_CS_CHNL 3
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//*****************************************************************************
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//
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// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM2_MISO 25
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
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//*****************************************************************************
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//
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// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM2_MOSI 28
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
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//*****************************************************************************
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//
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// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM2_SCK 27
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
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//*****************************************************************************
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//
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// IOM2_SCL pin: I/O Master 2 I2C clock signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM2_SCL 27
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
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//*****************************************************************************
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//
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// IOM2_SDA pin: I/O Master 2 I2C data signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM2_SDA 25
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
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//*****************************************************************************
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//
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// IOM3_CS pin: I/O Master 3 chip select.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM3_CS 29
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
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#define AM_BSP_IOM3_CS_CHNL 0
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//*****************************************************************************
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//
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// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM3_MISO 43
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
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//*****************************************************************************
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//
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// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM3_MOSI 38
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
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//*****************************************************************************
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//
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// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM3_SCK 42
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
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//*****************************************************************************
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//
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// IOM3_SCL pin: I/O Master 3 I2C clock signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM3_SCL 42
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
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//*****************************************************************************
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//
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// IOM3_SDA pin: I/O Master 3 I2C data signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM3_SDA 43
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
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//*****************************************************************************
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//
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// IOM4_CS pin: I/O Master 4 chip select.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM4_CS 13
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
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#define AM_BSP_IOM4_CS_CHNL 1
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//*****************************************************************************
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//
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// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM4_MISO 40
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
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//*****************************************************************************
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//
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// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM4_MOSI 44
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
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//*****************************************************************************
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//
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// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM4_SCK 39
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
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//*****************************************************************************
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//
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// IOM4_SCL pin: I/O Master 4 I2C clock signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM4_SCL 39
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
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//*****************************************************************************
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//
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// IOM4_SDA pin: I/O Master 4 I2C data signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM4_SDA 40
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
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//*****************************************************************************
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//
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// IOM5_CS pin: I/O Master 5 chip select.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM5_CS 16
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
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#define AM_BSP_IOM5_CS_CHNL 0
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//*****************************************************************************
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//
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// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM5_MISO 49
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
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//*****************************************************************************
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//
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// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM5_MOSI 47
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
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//*****************************************************************************
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//
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// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM5_SCK 48
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
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//*****************************************************************************
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//
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// IOM5_SCL pin: I/O Master 5 I2C clock signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM5_SCL 48
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
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//*****************************************************************************
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//
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// IOM5_SDA pin: I/O Master 5 I2C data signal.
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//
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//*****************************************************************************
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#define AM_BSP_GPIO_IOM5_SDA 49
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
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//*****************************************************************************
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//
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// MSPI0_CE0 pin: MSPI0 chip select 0. Note: CE1 must be disabled or tristated when using this pin for CE.
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//
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//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI0_CE0 37
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI0_CE0;
|
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#define AM_BSP_MSPI0_CE0_CHNL 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI0_CE1 pin: MSPI0 chip select 1. Note: CE0 must be disabled or tristated when using this pin for CE.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI0_CE1 12
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI0_CE1;
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#define AM_BSP_MSPI0_CE1_CHNL 0
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI0_D0 pin: MSPI0 data 0.
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|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI0_D0 22
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|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI0_D0;
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI0_D1 pin: MSPI0 data 1.
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|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI0_D1 26
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI0_D1;
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI0_D2 pin: MSPI0 data 2.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI0_D2 4
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|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI0_D2;
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI0_D3 pin: MSPI0 data 3.
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|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI0_D3 23
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI0_D3;
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI0_SCK pin: MSPI0 clock.
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|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI0_SCK 24
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI0_SCK;
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_CE0 pin: MSPI1 chip select 0. Note: CE1 must be disabled or tristated when using this pin for CE.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_CE0 50
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_CE0;
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|
#define AM_BSP_MSPI1_CE0_CHNL 0
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_CE1 pin: MSPI1 chip select 1. Note: CE0 must be disabled or tristated when using this pin for CE.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_CE1 62
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extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_CE1;
|
|
#define AM_BSP_MSPI1_CE1_CHNL 0
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|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D0 pin: MSPI1 data 0.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D0 51
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D0;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D1 pin: MSPI1 data 1.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D1 52
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D1;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D2 pin: MSPI1 data 2.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D2 53
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D2;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D3 pin: MSPI1 data 3.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D3 54
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D3;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D4 pin: MSPI1 data 4.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D4 55
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D4;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D5 pin: MSPI1 data 5.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D5 56
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D5;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D6 pin: MSPI1 data 6.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D6 57
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D6;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_D7 pin: MSPI1 data 7.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_D7 58
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_D7;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_SCK pin: MSPI1 clock.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_SCK 59
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_SCK;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI1_DMDQS pin: MSPI1 DDR Data Strobe.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI1_DMDQS 60
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI1_DMDQS;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI2_CE0 pin: MSPI2 chip select 0. Note: CE2 must be disabled or tristated when using this pin for CE.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI2_CE0 63
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI2_CE0;
|
|
#define AM_BSP_MSPI2_CE0_CHNL 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI2_CE1 pin: MSPI2 chip select 1. Note: CE0 must be disabled or tristated when using this pin for CE.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI2_CE1 61
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI2_CE1;
|
|
#define AM_BSP_MSPI2_CE1_CHNL 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI2_D0 pin: MSPI2 data 0.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI2_D0 64
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI2_D0;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI2_D1 pin: MSPI2 data 1.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI2_D1 65
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI2_D1;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI2_D2 pin: MSPI2 data 2.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI2_D2 66
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI2_D2;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI2_D3 pin: MSPI2 data 3.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI2_D3 67
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI2_D3;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MSPI2_SCK pin: MSPI2 clock.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_MSPI2_SCK 68
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI2_SCK;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// DISPLAY_TE pin: Display TE signal.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_DISPLAY_TE 72
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_DISPLAY_TE;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// DISPLAY_RESET pin: Display reset control.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_DISPLAY_RESET 73
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_DISPLAY_RESET;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// IOS_CE pin: I/O Slave chip select.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_IOS_CE 3
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
|
|
#define AM_BSP_IOS_CE_CHNL 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// IOS_MISO pin: I/O Slave SPI MISO signal.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_IOS_MISO 2
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_IOS_MOSI 1
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// IOS_SCK pin: I/O Slave SPI SCK signal.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_IOS_SCK 0
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// IOS_SCL pin: I/O Slave I2C clock signal.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_IOS_SCL 0
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// IOS_SDA pin: I/O Slave I2C data signal.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_IOS_SDA 1
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// PDMCLK pin: PDM CLK.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_PDMCLK 12
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_PDMCLK;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// PDM_DATA pin: PDM DATA.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_PDM_DATA 11
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_PDM_DATA;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// SCARD_SCCCLK pin: SCARD SCCCLK.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_SCARD_SCCCLK 8
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SCARD_SCCCLK;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// SCARD_SCCIO pin: Fireball device test board chip select.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_SCARD_SCCIO 9
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SCARD_SCCIO;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// SCARD_SCCRST pin: SCARD SCCRST.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_SCARD_SCCRST 46
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SCARD_SCCRST;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// ITM_SWO pin: ITM Serial Wire Output.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_ITM_SWO 41
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// SWDCK pin: Cortex Serial Wire DCK.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_SWDCK 20
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// SWDIO pin: Cortex Serial Wire DIO.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_SWDIO 21
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// FIREBALL_CE pin: Fireball device test board chip select.
|
|
//
|
|
//*****************************************************************************
|
|
#define AM_BSP_GPIO_FIREBALL_CE 30
|
|
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_FIREBALL_CE;
|
|
#define AM_BSP_FIREBALL_CE_CHNL 3
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // AM_BSP_PINS_H
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|