Ambiq Micro Ambiq apollo3 Apollo 1.0 Ultra-Low power ARM Cortex-M4 MCU from Ambiq Micro Copyright (c) 2019, Ambiq Micro\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\nthis list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\nnotice, this list of conditions and the following disclaimer in the\ndocumentation and/or other materials provided with the distribution.\n\n3. Neither the name of the copyright holder nor the names of its\ncontributors may be used to endorse or promote products derived from this\nsoftware without specific prior written permission.\n\nThird party software included in this distribution is subject to the\nadditional license terms as defined in the /docs/licenses directory.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n CM4 r1p0 little true true 3 false 8 32 32 read-write 0x00000000 0xFFFFFFFF ADC 1.0 Analog Digital Converter Control 0x50010000 32 read-write 0 0x00000294 registers ADC 18 CFG Configuration Register 0x00000000 32 read-write 0x00000000 0x030F131D CLKSEL Select the source and frequency for the ADC clock. All values not enumerated below are undefined. [25:24] read-write OFF Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing. 0 HFRC HFRC Core Clock divided by (CORESEL+1) 1 HFRC_DIV2 HFRC Core Clock / 2 further divided by (CORESEL+1) 2 TRIGPOL This bit selects the ADC trigger polarity for external off chip triggers. [19:19] read-write RISING_EDGE Trigger on rising edge. 0 FALLING_EDGE Trigger on falling edge. 1 TRIGSEL Select the ADC trigger source. [18:16] read-write EXT0 Off chip External Trigger0 (ADC_ET0) 0 EXT1 Off chip External Trigger1 (ADC_ET1) 1 EXT2 Off chip External Trigger2 (ADC_ET2) 2 EXT3 Off chip External Trigger3 (ADC_ET3) 3 VCOMP Voltage Comparator Output 4 SWT Software Trigger 7 DFIFORDEN Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register. [12:12] read-write DIS Destructive Reads are prevented. Reads to the FIFOPR register will not POP an entry off the FIFO. 0 EN Reads to the FIFOPR registger will automatically pop an entry off the FIFO. 1 REFSEL Select the ADC reference voltage. [9:8] read-write INT2P0 Internal 2.0V Bandgap Reference Voltage 0 INT1P5 Internal 1.5V Bandgap Reference Voltage 1 EXT2P0 Off Chip 2.0V Reference 2 EXT1P5 Off Chip 1.5V Reference 3 CKMODE Clock mode register [4:4] read-write LPCKMODE Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC. 0 LLCKMODE Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0. 1 LPMODE Select power mode to enter between active scans. [3:3] read-write MODE0 Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection. 0 MODE1 Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode. 1 RPTEN This bit enables Repeating Scan Mode. [2:2] read-write SINGLE_SCAN In Single Scan Mode, the ADC will complete a single scan upon each trigger event. 0 REPEATING_SCAN In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared. 1 ADCEN This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'. [0:0] read-write DIS Disable the ADC module. 0 EN Enable the ADC module. 1 STAT ADC Power Status 0x00000004 32 read-write 0x00000000 0x00000001 PWDSTAT Indicates the power-status of the ADC. [0:0] read-write ON Powered on. 0 POWERED_DOWN ADC Low Power Mode 1. 1 SWT Software trigger 0x00000008 32 read-write 0x00000000 0x000000FF SWT Writing 0x37 to this register generates a software trigger. [7:0] read-write GEN_SW_TRIGGER Writing this value generates a software trigger. 55 SL0CFG Slot 0 Configuration Register 0x0000000C 32 read-write 0x00000000 0x07030F03 ADSEL0 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE0 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL0 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN0 This bit enables the window compare function for slot 0. [1:1] read-write WCEN Enable the window compare for slot 0. 1 SLEN0 This bit enables slot 0 for ADC conversions. [0:0] read-write SLEN Enable slot 0 for ADC conversions. 1 SL1CFG Slot 1 Configuration Register 0x00000010 32 read-write 0x00000000 0x07030F03 ADSEL1 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE1 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL1 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN1 This bit enables the window compare function for slot 1. [1:1] read-write WCEN Enable the window compare for slot 1. 1 SLEN1 This bit enables slot 1 for ADC conversions. [0:0] read-write SLEN Enable slot 1 for ADC conversions. 1 SL2CFG Slot 2 Configuration Register 0x00000014 32 read-write 0x00000000 0x07030F03 ADSEL2 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE2 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL2 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN2 This bit enables the window compare function for slot 2. [1:1] read-write WCEN Enable the window compare for slot 2. 1 SLEN2 This bit enables slot 2 for ADC conversions. [0:0] read-write SLEN Enable slot 2 for ADC conversions. 1 SL3CFG Slot 3 Configuration Register 0x00000018 32 read-write 0x00000000 0x07030F03 ADSEL3 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE3 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL3 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN3 This bit enables the window compare function for slot 3. [1:1] read-write WCEN Enable the window compare for slot 3. 1 SLEN3 This bit enables slot 3 for ADC conversions. [0:0] read-write SLEN Enable slot 3 for ADC conversions. 1 SL4CFG Slot 4 Configuration Register 0x0000001C 32 read-write 0x00000000 0x07030F03 ADSEL4 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE4 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL4 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN4 This bit enables the window compare function for slot 4. [1:1] read-write WCEN Enable the window compare for slot 4. 1 SLEN4 This bit enables slot 4 for ADC conversions. [0:0] read-write SLEN Enable slot 4 for ADC conversions. 1 SL5CFG Slot 5 Configuration Register 0x00000020 32 read-write 0x00000000 0x07030F03 ADSEL5 Select number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE5 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL5 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN5 This bit enables the window compare function for slot 5. [1:1] read-write WCEN Enable the window compare for slot 5. 1 SLEN5 This bit enables slot 5 for ADC conversions. [0:0] read-write SLEN Enable slot 5 for ADC conversions. 1 SL6CFG Slot 6 Configuration Register 0x00000024 32 read-write 0x00000000 0x07030F03 ADSEL6 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE6 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL6 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN6 This bit enables the window compare function for slot 6. [1:1] read-write WCEN Enable the window compare for slot 6. 1 SLEN6 This bit enables slot 6 for ADC conversions. [0:0] read-write SLEN Enable slot 6 for ADC conversions. 1 SL7CFG Slot 7 Configuration Register 0x00000028 32 read-write 0x00000000 0x07030F03 ADSEL7 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 PRMODE7 Set the Precision Mode For Slot. [17:16] read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 CHSEL7 Select one of the 14 channel inputs for this slot. [11:8] read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 WCEN7 This bit enables the window compare function for slot 7. [1:1] read-write WCEN Enable the window compare for slot 7. 1 SLEN7 This bit enables slot 7 for ADC conversions. [0:0] read-write SLEN Enable slot 7 for ADC conversions. 1 WULIM Window Comparator Upper Limits Register 0x0000002C 32 read-write 0x00000000 0x000FFFFF ULIM Sets the upper limit for the window comparator. [19:0] read-write WLLIM Window Comparator Lower Limits Register 0x00000030 32 read-write 0x00000000 0x000FFFFF LLIM Sets the lower limit for the window comparator. [19:0] read-write SCWLIM Scale Window Comparator Limits 0x00000034 32 read-write 0x00000000 0x00000001 SCWLIMEN Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons. [0:0] read-write FIFO FIFO Data and Valid Count Register 0x00000038 32 read-write 0x00000000 0x7FFFFFFF RSVD RESERVED. [31:31] read-write SLOTNUM Slot number associated with this FIFO data. [30:28] read-write COUNT Number of valid entries in the ADC FIFO. [27:20] read-write DATA Oldest data in the FIFO. [19:0] read-write FIFOPR FIFO Data and Valid Count Register 0x0000003C 32 read-write 0x00000000 0xFFFFFFFF RSVDPR RESERVED. [31:31] read-write SLOTNUMPR Slot number associated with this FIFO data. [30:28] read-write COUNT Number of valid entries in the ADC FIFO. [27:20] read-write DATA Oldest data in the FIFO. [19:0] read-write INTEN ADC Interrupt registers: Enable 0x00000200 32 read-write 0x00000000 0x000000FF DERR DMA Error Condition [7:7] read-write DMAERROR DMA Error Condition Occurred 1 DCMP DMA Transfer Complete [6:6] read-write DMACOMPLETE DMA Completed a transfer 1 WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 INTSTAT ADC Interrupt registers: Status 0x00000204 32 read-write 0x00000000 0x000000FF DERR DMA Error Condition [7:7] read-write DMAERROR DMA Error Condition Occurred 1 DCMP DMA Transfer Complete [6:6] read-write DMACOMPLETE DMA Completed a transfer 1 WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 INTCLR ADC Interrupt registers: Clear 0x00000208 32 read-write 0x00000000 0x000000FF DERR DMA Error Condition [7:7] read-write DMAERROR DMA Error Condition Occurred 1 DCMP DMA Transfer Complete [6:6] read-write DMACOMPLETE DMA Completed a transfer 1 WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 INTSET ADC Interrupt registers: Set 0x0000020C 32 read-write 0x00000000 0x000000FF DERR DMA Error Condition [7:7] read-write DMAERROR DMA Error Condition Occurred 1 DCMP DMA Transfer Complete [6:6] read-write DMACOMPLETE DMA Completed a transfer 1 WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 DMATRIGEN DMA Trigger Enable Register 0x00000240 32 read-write 0x00000000 0x00000003 DFIFOFULL Trigger DMA upon FIFO 100 percent Full [1:1] read-write DFIFO75 Trigger DMA upon FIFO 75 percent Full [0:0] read-write DMATRIGSTAT DMA Trigger Status Register 0x00000244 32 read-write 0x00000000 0x00000003 DFULLSTAT Triggered DMA from FIFO 100 percent Full [1:1] read-write D75STAT Triggered DMA from FIFO 75 percent Full [0:0] read-write DMACFG DMA Configuration Register 0x00000280 32 read-write 0x00000000 0x00070305 DPWROFF Power Off the ADC System upon DMACPL. [18:18] read-write DMAMSK Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory [17:17] read-write DIS FIFO Contents are copied directly to memory without modification. 0 EN Only the FIFODATA contents are copied to memory on DMA transfers. The SLOTNUM and FIFOCNT contents are cleared to zero. 1 DMAHONSTAT Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared. [16:16] read-write DIS ADC conversions will continue regardless of DMA status register 0 EN ADC conversions will not progress if DMAERR or DMACPL bits in DMA status register are set. 1 DMADYNPRI Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used. [9:9] read-write DIS Disable dynamic priority (use DMAPRI setting only) 0 EN Enable dynamic priority 1 DMAPRI Sets the Priority of the DMA request [8:8] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 DMADIR Direction [2:2] read-write P2M Peripheral to Memory (SRAM) transaction 0 M2P Memory to Peripheral transaction 1 DMAEN DMA Enable [0:0] read-write DIS Disable DMA Function 0 EN Enable DMA Function 1 DMATOTCOUNT DMA Total Transfer Count 0x00000288 32 read-write 0x00000000 0x0003FFFC TOTCOUNT Total Transfer Count [17:2] read-write DMATARGADDR DMA Target Address Register 0x0000028C 32 read-write 0x20000000 0xFFFFFFFF UTARGADDR SRAM Target [31:19] read-write LTARGADDR DMA Target Address [18:0] read-write DMASTAT DMA Status Register 0x00000290 32 read-write 0x00000000 0x00000007 DMAERR DMA Error [2:2] read-write DMACPL DMA Transfer Complete [1:1] read-write DMATIP DMA Transfer In Progress [0:0] read-write APBDMA 1.0 APB DMA Register Interfaces 0x40011000 32 read-write 0 0x00000044 registers BBVALUE Control Register 0x00000000 32 read-write 0x00000000 0x00FF00FF PIN PIO values [23:16] read-write DATAOUT Data Output Values [7:0] read-write BBSETCLEAR Set/Clear Register 0x00000004 32 read-write 0x00000000 0x00FF00FF CLEAR Write 1 to Clear PIO value [23:16] read-write SET Write 1 to Set PIO value (set hier priority than clear if both bit set) [7:0] read-write BBINPUT PIO Input Values 0x00000008 32 read-write 0x00000000 0x000000FF DATAIN PIO values [7:0] read-write DEBUGDATA PIO Input Values 0x00000020 32 read-write 0x00000000 0xFFFFFFFF DEBUGDATA Debug Data [31:0] read-write DEBUG PIO Input Values 0x00000040 32 read-write 0x00000000 0x0000000F DEBUGEN Debug Enable [3:0] read-write OFF Debug Disabled 0 ARB Debug Arb values 1 BLEIF 1.0 BLE Interface 0x5000C000 32 read-write 0 0x00000414 registers BLE 12 FIFO FIFO Access Port 0x00000000 32 read-write 0x00000000 0xFFFFFFFF FIFO FIFO direct access. Only locations 0 - 3F will return valid information. [31:0] read-write FIFOPTR FIFO size and remaining slots open values 0x00000100 32 read-write 0x00000000 0xFFFFFFFF FIFO1REM The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU) [31:24] read-write FIFO1SIZ The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU) [23:16] read-write FIFO0REM The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface) [15:8] read-write FIFO0SIZ The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface) [7:0] read-write FIFOTHR FIFO Threshold Configuration 0x00000104 32 read-write 0x00000000 0x00003F3F FIFOWTHR FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations. [13:8] read-write FIFORTHR FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations. [5:0] read-write FIFOPOP FIFO POP register 0x00000108 32 read-write 0x00000000 0xFFFFFFFF FIFODOUT This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word. [31:0] read-write FIFOPUSH FIFO PUSH register 0x0000010C 32 read-write 0x00000000 0xFFFFFFFF FIFODIN This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes). [31:0] read-write FIFOCTRL FIFO Control Register 0x00000110 32 read-write 0x00000002 0x00000003 FIFORSTN Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset. [1:1] read-write POPWR Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode. [0:0] read-write FIFOLOC FIFO Pointers 0x00000114 32 read-write 0x00000000 0x00000F0F FIFORPTR Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation. [11:8] read-write FIFOWPTR Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices. [3:0] read-write CLKCFG I/O Clock Configuration 0x00000200 32 read-write 0x00000000 0x00001F01 DIV3 Enable of the divide by 3 of the source IOCLK. [12:12] read-write CLK32KEN Enable for the 32Khz clock to the BLE module [11:11] read-write FSEL Select the input clock frequency. [10:8] read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOM is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 IOCLKEN Enable for the interface clock. Must be enabled prior to executing any IO operations. [0:0] read-write CMD Command and offset Register 0x0000020C 32 read-write 0x00000000 0xFF3FFFFF OFFSETLO This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first. [31:24] read-write CMDSEL Command Specific selection information [21:20] read-write TSIZE Defines the transaction size in bytes. The offset transfer is not included in this size. [19:8] read-write CONT Contine to hold the bus after the current transaction if set to a 1 with a new command issued. [7:7] read-write OFFSETCNT Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If offsetcnt == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration. [6:5] read-write CMD Command for submodule. [4:0] read-write WRITE Write command using count of offset bytes specified in the OFFSETCNT field 1 READ Read command using count of offset bytes specified in the OFFSETCNT field 2 CMDRPT Command Repeat Register 0x00000210 32 read-write 0x00000000 0x0000001F CMDRPT Count of number of times to repeat the next command. [4:0] read-write OFFSETHI High order offset bytes 0x00000214 32 read-write 0x00000000 0x0000FFFF OFFSETHI Holds the high order bytes of the 2 or 3 byte offset phase of a transaction. [15:0] read-write CMDSTAT Command status 0x00000218 32 read-write 0x00000000 0x000FFFFF CTSIZE The current number of bytes still to be transferred with this command. This field will count down to zero. [19:8] read-write CMDSTAT The current status of the command execution. [7:5] read-write ERR Error encountered with command 1 ACTIVE Actively processing command 2 IDLE Idle state, no active command, no error 4 WAIT Command in progress, but waiting on data from host 6 CCMD current command that is being executed [4:0] read-write INTEN IO Master Interrupts: Enable 0x00000220 32 read-write 0x00000000 0x0001FFFF B2MSHUTDN Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0) [16:16] read-write B2MACTIVE Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0) [15:15] read-write B2MSLEEP The B2M_STATE from the BLE Core transitioned into the sleep state [14:14] read-write CQERR Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions [13:13] read-write CQUPD Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [12:12] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [11:11] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [10:10] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [9:9] read-write BLECSSTAT BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high. [8:8] read-write BLECIRQ BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write B2MST B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write INTSTAT IO Master Interrupts: Status 0x00000224 32 read-write 0x00000000 0x0001FFFF B2MSHUTDN Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0) [16:16] read-write B2MACTIVE Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0) [15:15] read-write B2MSLEEP The B2M_STATE from the BLE Core transitioned into the sleep state [14:14] read-write CQERR Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions [13:13] read-write CQUPD Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [12:12] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [11:11] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [10:10] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [9:9] read-write BLECSSTAT BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high. [8:8] read-write BLECIRQ BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write B2MST B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write INTCLR IO Master Interrupts: Clear 0x00000228 32 read-write 0x00000000 0x0001FFFF B2MSHUTDN Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0) [16:16] read-write B2MACTIVE Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0) [15:15] read-write B2MSLEEP The B2M_STATE from the BLE Core transitioned into the sleep state [14:14] read-write CQERR Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions [13:13] read-write CQUPD Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [12:12] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [11:11] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [10:10] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [9:9] read-write BLECSSTAT BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high. [8:8] read-write BLECIRQ BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write B2MST B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write INTSET IO Master Interrupts: Set 0x0000022C 32 read-write 0x00000000 0x0001FFFF B2MSHUTDN Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0) [16:16] read-write B2MACTIVE Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0) [15:15] read-write B2MSLEEP The B2M_STATE from the BLE Core transitioned into the sleep state [14:14] read-write CQERR Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions [13:13] read-write CQUPD Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [12:12] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [11:11] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [10:10] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [9:9] read-write BLECSSTAT BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high. [8:8] read-write BLECIRQ BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write B2MST B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write DMATRIGEN DMA Trigger Enable Register 0x00000230 32 read-write 0x00000000 0x00000003 DTHREN Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the commmand. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete. [1:1] read-write DCMDCMPEN Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed. [0:0] read-write DMATRIGSTAT DMA Trigger Status Register 0x00000234 32 read-write 0x00000000 0x00000007 DTOTCMP DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation. [2:2] read-write DTHR Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA. [1:1] read-write DCMDCMP Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA. [0:0] read-write DMACFG DMA Configuration Register 0x00000238 32 read-write 0x00000000 0x00000303 DPWROFF Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed. [9:9] read-write DIS Power off disabled 0 EN Power off enabled 1 DMAPRI Sets the Priority of the DMA request [8:8] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 DMADIR Direction [1:1] read-write P2M Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices. 0 M2P Memory to Peripheral transaction. To be set when doing IOM write operations, ie writing data to external devices. 1 DMAEN DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command [0:0] read-write DIS Disable DMA Function 0 EN Enable DMA Function 1 DMATOTCOUNT DMA Total Transfer Count 0x0000023C 32 read-write 0x00000000 0x00000FFF TOTCOUNT Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA. [11:0] read-write DMATARGADDR DMA Target Address Register 0x00000240 32 read-write 0x00000000 0x100FFFFF TARGADDR28 Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash [28:28] read-write TARGADDR Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. [19:0] read-write DMASTAT DMA Status Register 0x00000244 32 read-write 0x00000000 0x00000007 DMAERR DMA Error. This active high bit signals that an error was encountered during the DMA operation. [2:2] read-write DMACPL DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0. [1:1] read-write DMATIP DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only. [0:0] read-write CQCFG Command Queue Configuration Register 0x00000248 32 read-write 0x00000000 0x00000003 CQPRI Sets the Priority of the command queue dma request. [1:1] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 CQEN Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well. [0:0] read-write DIS Disable CQ Function 0 EN Enable CQ Function 1 CQADDR CQ Target Read Address Register 0x0000024C 32 read-write 0x00000000 0x100FFFFC CQADDR28 Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access [28:28] read-write CQADDR Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary [19:2] read-write CQSTAT Command Queue Status Register 0x00000250 32 read-write 0x00000000 0x00000007 CQERR Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation. [2:2] read-write CQPAUSED Command queue operation is currently paused. [1:1] read-write CQTIP Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event. [0:0] read-write CQFLAGS Command Queue Flag Register 0x00000254 32 read-write 0x00000000 0xFFFFFFFF CQIRQMASK Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE [31:16] read-write CQFLAGS Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status. [15:0] read-write CQSETCLEAR Command Queue Flag Set/Clear Register 0x00000258 32 read-write 0x00000000 0x00FFFFFF CQFCLR Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field [23:16] read-write CQFTGL Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field [15:8] read-write CQFSET Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field [7:0] read-write CQPAUSEEN Command Queue Pause Enable Register 0x0000025C 32 read-write 0x00000000 0x0000FFFF CQPEN Enables the specified event to pause command processing when active [15:0] read-write CNTEQ Pauses command queue processing when HWCNT matches SWCNT 32768 BLEXOREN Pause command queue when input BLE bit XORed with SWFLAG4 is '1' 16384 IOMXOREN Pause command queue when input IOM bit XORed with SWFLAG3 is '1' 8192 GPIOXOREN Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1' 4096 MSPI1XNOREN Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1' 2048 MSPI0XNOREN Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1' 1024 MSPI1XOREN Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1' 512 MSPI0XOREN Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1' 256 SWFLAGEN7 Pause the command queue when software flag bit 7 is '1'. 128 SWFLAGEN6 Pause the command queue when software flag bit 7 is '1' 64 SWFLAGEN5 Pause the command queue when software flag bit 7 is '1' 32 SWFLAGEN4 Pause the command queue when software flag bit 7 is '1' 16 SWFLAGEN3 Pause the command queue when software flag bit 7 is '1' 8 SWFLAGEN2 Pause the command queue when software flag bit 7 is '1' 4 SWFLAGEN1 Pause the command queue when software flag bit 7 is '1' 2 SWFLGEN0 Pause the command queue when software flag bit 7 is '1' 1 CQCURIDX IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue 0x00000260 32 read-write 0x00000000 0x000000FF CQCURIDX Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN. [7:0] read-write CQENDIDX IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue 0x00000264 32 read-write 0x00000000 0x000000FF CQENDIDX Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN. [7:0] read-write STATUS IOM Module Status Register 0x00000268 32 read-write 0x00000000 0x00000007 IDLEST indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers. [2:2] read-write IDLE The I/O state machine is in the idle state. 1 CMDACT Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized. [1:1] read-write ACTIVE An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed. 1 ERR Bit has been deprecated. Please refer to the other error indicators. This will always return 0. [0:0] read-write ERROR Bit has been deprecated and will always return 0. 1 MSPICFG SPI module master configuration 0x00000300 32 read-write 0x40000000 0x7FE30007 MSPIRST Bit is deprecated. setting it will have no effect. [30:30] read-write DOUTDLY Delay tap to use for the output signal (MOSI). This give more hold time on the output data. [29:27] read-write DINDLY Delay tap to use for the input signal (MISO). This gives more hold time on the input data. [26:24] read-write SPILSB Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first. [23:23] read-write MSB Send and receive MSB bit first 0 LSB Send and receive LSB bit first 1 RDFCPOL Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted. [22:22] read-write NORMAL SPI_STATUS signal from BLE Core high(1) creates flow control and new read spi transactions will not be started until the signal goes low.(default) 0 INVERTED SPI_STATUS signal from BLE Core low(0) creates flow control and new read spi transactions will not be started until the signal goes high. 1 WTFCPOL Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers). [21:21] read-write NORMAL SPI_STATUS signal from BLE Core high(1) creates flow control and new write spi transactions will not be started until the signal goes low.(default) 0 INVERTED SPI_STATUS signal from BLE Core high(1) creates low(0) control and new write spi transactions will not be started until the signal goes high. 1 RDFC Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core. [17:17] read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 WTFC Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core. [16:16] read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 FULLDUP Full Duplex mode. Capture read data during writes operations [2:2] read-write SPHA Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock. [1:1] read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge, rising or falling dependant on the value of SPOL 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge, rising of falling dependant on the value of SPOL 1 SPOL This bit selects SPI polarity. [0:0] read-write CLK_BASE_0 The initial value of the clock is 0. 0 CLK_BASE_1 The initial value of the clock is 1. 1 BLECFG BLE Core Control 0x00000304 32 read-write 0x00000000 0x0000FFFF SPIISOCTL Configuration of BLEH isolation controls for SPI related signals. [15:14] read-write ON SPI signals from BLE Core to/from MCU Core are isolated. 3 OFF SPI signals from BLE Core to/from MCU Core are not isolated. 2 AUTO SPI signals from BLE Core to/from MCU Core are automatically isolated by the logic 0 PWRISOCTL Configuration of BLEH isolation control for power related signals. [13:12] read-write ON BLEH power signal isolation to on (isolated). 3 OFF BLEH power signal isolation to off (not isolated). 2 AUTO BLEH Power signal isolation is controlled automatically through the interface logic 0 STAYASLEEP Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state. [11:11] read-write FRCCLK Force the clock in the BLEIF to be always running [10:10] read-write MCUFRCSLP Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine. [9:9] read-write WT4ACTOFF Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for dcdc req from BLE Core. [8:8] read-write BLEHREQCTL BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic. [7:6] read-write ON BLEH Power-on reg signal is set to on (1). 3 OFF BLEH Power-on signal is set to off (0). 2 AUTO BLEH Power-on signal is controlled by the PWRSM logic and automatically controlled 0 DCDCFLGCTL DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic. [5:4] read-write ON DCDC Flag signal is set to on (1). 3 OFF DCDC Flag signal is set to off (0). 2 AUTO DCDC Flag signal is controlled by the PWRSM logic and automatically controlled 0 WAKEUPCTL WAKE signal override. Controls the source of the WAKE signal to the BLE Core. [3:2] read-write ON Wake signal is set to on (1). 3 OFF Wake signal is set to off (0). 2 AUTO Wake signal is controlled by the PWRSM logic and automatically controlled 0 BLERSTN Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core. [1:1] read-write ACTIVE The reset signal is active (0) 1 INACTIVE The reset signal is inactive (1) 0 PWRSMEN Enable the power state machine for automatic sequencing and control of power states of the BLE Core module. [0:0] read-write ON Internal power state machine is enabled and will sequence the BLEH power domain as indicated in the design document. Overrides for the power signals are not enabled. 1 OFF Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals 0 PWRCMD BLE Power command interface 0x00000308 32 read-write 0x00000000 0x00000003 RESTART Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state. [1:1] read-write WAKEREQ Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state [0:0] read-write BSTATUS BLE Core status 0x0000030C 32 read-write 0x00000000 0x00001FFF BLEHREQ Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use. [12:12] read-write BLEHACK Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use. [11:11] read-write PWRST Current status of the power state machine [10:8] read-write OFF Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals 0 INIT Initialization state. BLEH not powered 1 PWRON Waiting for the powerup of the BLEH 2 ACTIVE The BLE Core is powered and active 3 SLEEP The BLE Core has entered sleep mode and the power request is inactive 6 SHUTDOWN The BLE Core is in shutdown mode 4 BLEIRQ Status of the BLEIRQ signal from the BLE Core. A value of 1 idicates that read data is available in the core and a read operation needs to be performed. [7:7] read-write WAKEUP Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state. [6:6] read-write DCDCFLAG Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH ppower is active. [5:5] read-write DCDCREQ Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1. [4:4] read-write SPISTATUS Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active. [3:3] read-write B2MSTATE State of the BLE Core logic. [2:0] read-write RESET Reset State 0 Sleep Sleep state. 1 Standby Standby State 2 Idle Idle state 3 Active Active state. 4 BLEDBG BLEIF Master Debug Register 0x00000410 32 read-write 0x00000000 0xFFFFFFFF DBGDATA Debug data [31:3] read-write APBCLKON APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed. [2:2] read-write IOCLKON IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed. [1:1] read-write DBGEN Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings [0:0] read-write CACHECTRL 1.0 Flash Cache Controller 0x40018000 32 read-write 0 0x00000240 registers CACHECFG Flash Cache Control Register 0x00000000 32 read-write 0x00100C50 0x01100FFF ENABLE_MONITOR Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments. [24:24] read-write DATA_CLKGATE Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency. [20:20] read-write CACHE_LS Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage. [11:11] read-write CACHE_CLKGATE Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency. [10:10] read-write DCACHE_ENABLE Enable Flash Data Caching. [9:9] read-write ICACHE_ENABLE Enable Flash Instruction Caching [8:8] read-write CONFIG Sets the cache configuration [7:4] read-write W1_128B_512E Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) 4 W2_128B_512E Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active) 5 W1_128B_1024E Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active) 8 ENABLE_NC1 Enable Non-cacheable region 1. See NCR1 registers to define the region. [3:3] read-write ENABLE_NC0 Enable Non-cacheable region 0. See NCR0 registers to define the region. [2:2] read-write LRU Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM. [1:1] read-write ENABLE Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access. [0:0] read-write FLASHCFG Flash Control Register 0x00000004 32 read-write 0x00000873 0x00003F7F LPMMODE Controls flash low power modes (control of LPM pin). [13:12] read-write NEVER High power mode (LPM not used). 0 STANDBY Fast Standby mode. LPM deasserted for read operations, but asserted while flash IDLE. 1 ALWAYS Low Power mode. LPM always asserted for reads. LPM_RD_WAIT must be programmed to accomodate longer read access times. 2 LPM_RD_WAIT Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only) [11:8] read-write SEDELAY Sets SE delay (flash address setup). A value of 5 is recommended. [6:4] read-write RD_WAIT Sets read waitstates for normal (fast) operation. A value of 1 is recommended. [3:0] read-write CTRL Cache Control 0x00000008 32 read-write 0x00000000 0x00000777 FLASH1_SLM_ENABLE Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned. [10:10] read-write FLASH1_SLM_DISABLE Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it). [9:9] read-write FLASH1_SLM_STATUS Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode. [8:8] read-write FLASH0_SLM_ENABLE Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned. [6:6] read-write FLASH0_SLM_DISABLE Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it). [5:5] read-write FLASH0_SLM_STATUS Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode. [4:4] read-write CACHE_READY Cache Ready Status (enabled and not processing an invalidate operation) [2:2] read-write RESET_STAT Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set. [1:1] read-write CLEAR Clear Cache Stats 1 INVALIDATE Writing a 1 to this bitfield invalidates the flash cache contents. [0:0] read-write NCR0START Flash Cache Noncachable Region 0 Start 0x00000010 32 read-write 0x00000000 0x07FFFFF0 ADDR Start address for non-cacheable region 0 [26:4] read-write NCR0END Flash Cache Noncachable Region 0 End 0x00000014 32 read-write 0x00000000 0x07FFFFF0 ADDR End address for non-cacheable region 0 [26:4] read-write NCR1START Flash Cache Noncachable Region 1 Start 0x00000018 32 read-write 0x00000000 0x07FFFFF0 ADDR Start address for non-cacheable region 1 [26:4] read-write NCR1END Flash Cache Noncachable Region 1 End 0x0000001C 32 read-write 0x00000000 0x07FFFFF0 ADDR End address for non-cacheable region 1 [26:4] read-write DMON0 Data Cache Total Accesses 0x00000040 32 read-write 0x00000000 0xFFFFFFFF DACCESS_COUNT Total accesses to data cache. All performance metrics should be relative to the number of accesses performed. [31:0] read-write DMON1 Data Cache Tag Lookups 0x00000044 32 read-write 0x00000000 0xFFFFFFFF DLOOKUP_COUNT Total tag lookups from data cache. [31:0] read-write DMON2 Data Cache Hits 0x00000048 32 read-write 0x00000000 0xFFFFFFFF DHIT_COUNT Cache hits from lookup operations. [31:0] read-write DMON3 Data Cache Line Hits 0x0000004C 32 read-write 0x00000000 0xFFFFFFFF DLINE_COUNT Cache hits from line cache [31:0] read-write IMON0 Instruction Cache Total Accesses 0x00000050 32 read-write 0x00000000 0xFFFFFFFF IACCESS_COUNT Total accesses to Instruction cache [31:0] read-write IMON1 Instruction Cache Tag Lookups 0x00000054 32 read-write 0x00000000 0xFFFFFFFF ILOOKUP_COUNT Total tag lookups from Instruction cache [31:0] read-write IMON2 Instruction Cache Hits 0x00000058 32 read-write 0x00000000 0xFFFFFFFF IHIT_COUNT Cache hits from lookup operations [31:0] read-write IMON3 Instruction Cache Line Hits 0x0000005C 32 read-write 0x00000000 0xFFFFFFFF ILINE_COUNT Cache hits from line cache [31:0] read-write CLKGEN 1.0 Clock Generator 0x40004000 32 read-write 0 0x00000110 registers CLKGEN 31 CALXT XT Oscillator Control 0x00000000 32 read-write 0x00000000 0x000007FF CALXT XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023. [10:0] read-write CALRC RC Oscillator Control 0x00000004 32 read-write 0x00000000 0x0003FFFF CALRC LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjuction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock. [17:0] read-write ACALCTR Autocalibration Counter 0x00000008 32 read-write 0x00000000 0x00FFFFFF ACALCTR Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC. [23:0] read-write OCTRL Oscillator Control 0x0000000C 32 read-write 0x00000000 0x000007C3 ACAL Autocalibration control. This selects the source to be used in the autocalibration flow. This flow can also be used to measure an internal clock against an external clock source, with the external clock normally used as the reference. [10:8] read-write DIS Disable Autocalibration 0 1024SEC Autocalibrate every 1024 seconds. Once autocalibration is done, an interrupt will be triggered at the end of 1024 seconds. 2 512SEC Autocalibrate every 512 seconds. Once autocalibration is done, an interrupt will be trigged at the end of 512 seconds. 3 XTFREQ Frequency measurement using XT. The XT clock is normally considered much more accurate than the LFRC clock source. 6 EXTFREQ Frequency measurement using external clock. 7 OSEL Selects the RTC oscillator (1 => LFRC, 0 => XT) [7:7] read-write RTC_XT RTC uses the XT 0 RTC_LFRC RTC uses the LFRC 1 FOS Oscillator switch on failure function. If this is set, then LFRC clock source will switch from XT to RC. [6:6] read-write DIS Disable the oscillator switch on failure function. 0 EN Enable the oscillator switch on failure function. 1 STOPRC Stop the LFRC Oscillator to the RTC [1:1] read-write EN Enable the LFRC Oscillator to drive the RTC 0 STOP Stop the LFRC Oscillator when driving the RTC 1 STOPXT Stop the XT Oscillator to the RTC [0:0] read-write EN Enable the XT Oscillator to drive the RTC 0 STOP Stop the XT Oscillator when driving the RTC 1 CLKOUT CLKOUT Frequency Select 0x00000010 32 read-write 0x00000000 0x000000BF CKEN Enable the CLKOUT signal [7:7] read-write DIS Disable CLKOUT 0 EN Enable CLKOUT 1 CKSEL CLKOUT signal select [5:0] read-write LFRC LFRC 0 XT_DIV2 XT / 2 1 XT_DIV4 XT / 4 2 XT_DIV8 XT / 8 3 XT_DIV16 XT / 16 4 XT_DIV32 XT / 32 5 RTC_1Hz 1 Hz as selected in RTC 16 XT_DIV2M XT / 2^21 22 XT XT 23 CG_100Hz 100 Hz as selected in CLKGEN 24 HFRC HFRC 25 HFRC_DIV4 HFRC / 4 26 HFRC_DIV8 HFRC / 8 27 HFRC_DIV16 HFRC / 16 28 HFRC_DIV64 HFRC / 64 29 HFRC_DIV128 HFRC / 128 30 HFRC_DIV256 HFRC / 256 31 HFRC_DIV512 HFRC / 512 32 FLASH_CLK Flash Clock 34 LFRC_DIV2 LFRC / 2 35 LFRC_DIV32 LFRC / 32 36 LFRC_DIV512 LFRC / 512 37 LFRC_DIV32K LFRC / 32768 38 XT_DIV256 XT / 256 39 XT_DIV8K XT / 8192 40 XT_DIV64K XT / 2^16 41 ULFRC_DIV16 Uncal LFRC / 16 42 ULFRC_DIV128 Uncal LFRC / 128 43 ULFRC_1Hz Uncal LFRC / 1024 44 ULFRC_DIV4K Uncal LFRC / 4096 45 ULFRC_DIV1M Uncal LFRC / 2^20 46 HFRC_DIV64K HFRC / 2^16 47 HFRC_DIV16M HFRC / 2^24 48 LFRC_DIV1M LFRC / 2^20 49 HFRCNE HFRC (not autoenabled) 50 HFRCNE_DIV8 HFRC / 8 (not autoenabled) 51 XTNE XT (not autoenabled) 53 XTNE_DIV16 XT / 16 (not autoenabled) 54 LFRCNE_DIV32 LFRC / 32 (not autoenabled) 55 LFRCNE LFRC (not autoenabled) - Default for undefined values 57 CLKKEY Key Register for Clock Control Register 0x00000014 32 read-write 0x00000000 0xFFFFFFFF CLKKEY Key register value. [31:0] read-write Key Key 71 CCTRL HFRC Clock Control 0x00000018 32 read-write 0x00000001 0x00000001 CORESEL Core Clock divisor [0:0] read-write HFRC Core Clock is HFRC 0 HFRC_DIV2 Core Clock is HFRC / 2 1 STATUS Clock Generator Status 0x0000001C 32 read-write 0x00000000 0x00000003 OSCF XT Oscillator is enabled but not oscillating [1:1] read-write OMODE Current RTC oscillator (1 => LFRC, 0 => XT). After an RTC oscillator change, it may take up to 2 seconds for this field to reflect the new oscillator. [0:0] read-write HFADJ HFRC Adjustment 0x00000020 32 read-write 0x0025B800 0x00FFFF0F HFADJGAIN Gain control for HFRC adjustment [23:21] read-write Gain_of_1 HF Adjust with Gain of 1 0 Gain_of_1_in_2 HF Adjust with Gain of 0.5 1 Gain_of_1_in_4 HF Adjust with Gain of 0.25 2 Gain_of_1_in_8 HF Adjust with Gain of 0.125 3 Gain_of_1_in_16 HF Adjust with Gain of 0.0625 4 Gain_of_1_in_32 HF Adjust with Gain of 0.03125 5 HFWARMUP XT warmup period for HFRC adjustment [20:20] read-write 1SEC Autoadjust XT warmup period = 1-2 seconds 0 2SEC Autoadjust XT warmup period = 2-4 seconds 1 HFXTADJ Target HFRC adjustment value. [19:8] read-write HFADJCK Repeat period for HFRC adjustment [3:1] read-write 4SEC Autoadjust repeat period = 4 seconds 0 16SEC Autoadjust repeat period = 16 seconds 1 32SEC Autoadjust repeat period = 32 seconds 2 64SEC Autoadjust repeat period = 64 seconds 3 128SEC Autoadjust repeat period = 128 seconds 4 256SEC Autoadjust repeat period = 256 seconds 5 512SEC Autoadjust repeat period = 512 seconds 6 1024SEC Autoadjust repeat period = 1024 seconds 7 HFADJEN HFRC adjustment control [0:0] read-write DIS Disable the HFRC adjustment 0 EN Enable the HFRC adjustment 1 CLOCKENSTAT Clock Enable Status 0x00000028 32 read-write 0x00000000 0xFFFFFFFF CLOCKENSTAT Clock enable status [31:0] read-write ADC_CLKEN Clock enable for the ADC. 1 APBDMA_ACTIVITY_CLKEN Clock enable for the APBDMA ACTIVITY 2 APBDMA_AOH_CLKEN Clock enable for the APBDMA AOH DOMAIN 4 APBDMA_AOL_CLKEN Clock enable for the APBDMA AOL DOMAIN 8 APBDMA_APB_CLKEN Clock enable for the APBDMA_APB 16 APBDMA_BLEL_CLKEN Clock enable for the APBDMA_BLEL 32 APBDMA_HCPA_CLKEN Clock enable for the APBDMA_HCPA 64 APBDMA_HCPB_CLKEN Clock enable for the APBDMA_HCPB 128 APBDMA_HCPC_CLKEN Clock enable for the APBDMA_HCPC 256 APBDMA_MSPI_CLKEN Clock enable for the APBDMA_MSPI 512 APBDMA_PDM_CLKEN Clock enable for the APBDMA_PDM 1024 BLEIF_CLK_CLKEN Clock enable for the BLEIF 2048 BLEIF_CLK32K_CLKEN Clock enable for the BLEIF 32khZ CLOCK 4096 CTIMER_CLKEN Clock enable for the CTIMER BLOCK 8192 CTIMER0A_CLKEN Clock enable for the CTIMER0A 16384 CTIMER0B_CLKEN Clock enable for the CTIMER0B 32768 CTIMER1A_CLKEN Clock enable for the CTIMER1A 65536 CTIMER1B_CLKEN Clock enable for the CTIMER1B 131072 CTIMER2A_CLKEN Clock enable for the CTIMER2A 262144 CTIMER2B_CLKEN Clock enable for the CTIMER2B 524288 CTIMER3A_CLKEN Clock enable for the CTIMER3A 1048576 CTIMER3B_CLKEN Clock enable for the CTIMER3B 2097152 CTIMER4A_CLKEN Clock enable for the CTIMER4A 4194304 CTIMER4B_CLKEN Clock enable for the CTIMER4B 8388608 CTIMER5A_CLKEN Clock enable for the CTIMER5A 16777216 CTIMER5B_CLKEN Clock enable for the CTIMER5B 33554432 CTIMER6A_CLKEN Clock enable for the CTIMER6A 67108864 CTIMER6B_CLKEN Clock enable for the CTIMER6B 134217728 CTIMER7A_CLKEN Clock enable for the CTIMER7A 268435456 CTIMER7B_CLKEN Clock enable for the CTIMER7B 536870912 DAP_CLKEN Clock enable for the DAP 1073741824 IOMSTRIFC0_CLKEN Clock enable for the IOMSTRIFC0 2147483648 CLOCKEN2STAT Clock Enable Status 0x0000002C 32 read-write 0x00000000 0xFFFFFFFF CLOCKEN2STAT Clock enable status 2 [31:0] read-write IOMSTRIFC1_CLKEN Clock enable for the IO MASTER 1 IFC INTERFACE 1 IOMSTRIFC2_CLKEN Clock enable for the IO MASTER 2 IFC INTERFACE 2 IOMSTRIFC3_CLKEN Clock enable for the IO MASTER 3 IFC INTERFACE 4 IOMSTRIFC4_CLKEN Clock enable for the IO MASTER 4 IFC INTERFACE 8 IOMSTRIFC5_CLKEN Clock enable for the IO MASTER 5 IFC INTERFACE 16 PDM_CLKEN Clock enable for the PDM 32 PDMIFC_CLKEN Clock enable for the PDM INTERFACE 64 PWRCTRL_CLKEN Clock enable for the PWRCTRL 128 PWRCTRL_COUNT_CLKEN Clock enable for the PWRCTRL counter 256 RSTGEN_CLKEN Clock enable for the RSTGEN 512 SCARD_CLKEN Clock enable for the SCARD 1024 SCARD_ALTAPB_CLKEN Clock enable for the SCARD ALTAPB 2048 STIMER_CNT_CLKEN Clock enable for the STIMER_CNT_CLKEN 4096 TPIU_CLKEN Clock enable for the TPIU_CLKEN 8192 UART0HF_CLKEN Clock enable for the UART0 HF 16384 UART1HF_CLKEN Clock enable for the UART1 HF 32768 XT_32KHZ_EN Clock enable for the XT 32KHZ 1073741824 FORCEHFRC HFRC is forced on Status. 2147483648 CLOCKEN3STAT Clock Enable Status 0x00000030 32 read-write 0x00000000 0xFFFFFFFF CLOCKEN3STAT Clock enable status 3 [31:0] read-write DAP_enabled DAP clock is enabled [17] 131072 VCOMP_enabled VCOMP powerdown indicator [18] 262144 XTAL_enabled XTAL is enabled [24] 16777216 HFRC_enabled HFRC is enabled [25] 33554432 HFADJEN HFRC Adjust enabled [26] 67108864 HFRC_en_out HFRC Enabled out [27] 134217728 RTC_XT RTC use XT [28] 268435456 clkout_xtal_en XTAL clkout enabled [29] 536870912 clkout_hfrc_en HFRC clkout enabled [30] 1073741824 flashclk_en Flash clk is enabled [31] 2147483648 FREQCTRL HFRC Frequency Control register 0x00000034 32 read-write 0x00000000 0x00000007 BURSTSTATUS This represents frequency burst status. [2:2] read-write BURSTACK Frequency Burst Request Acknowledge. Frequency burst requested is always acknowledged whether burst is granted or not depending on feature enable. [1:1] read-write BURSTREQ Frequency Burst Enable Request [0:0] read-write DIS Frequency for ARM core stays at 48MHz 0 EN Frequency for ARM core is increased to 96MHz 1 BLEBUCKTONADJ BLE BUCK TON ADJUST 0x0000003C 32 read-write 0x00000000 0x0FFFFFFF ZEROLENDETECTEN BLEBUCK ZERO LENGTH DETECT ENABLE [27:27] read-write DIS Disable Zero Length Detect 0 EN Enable Zero Length Detect 1 ZEROLENDETECTTRIM BLEBUCK ZERO LENGTH DETECT TRIM [26:23] read-write SetF Indicator send when the BLE BUCK asserts blebuck_comp1 for about 81us (10 percent margin of error) or more 15 SetE Indicator send when the BLE BUCK asserts blebuck_comp1 for about 75.6us (10 percent margin of error) or more 14 SetD Indicator send when the BLE BUCK asserts blebuck_comp1 for about 70.2us (10 percent margin of error) or more 13 SetC Indicator send when the BLE BUCK asserts blebuck_comp1 for about 64.8us (10 percent margin of error) or more 12 SetB Indicator send when the BLE BUCK asserts blebuck_comp1 for about 59.4us (10 percent margin of error) or more 11 SetA Indicator send when the BLE BUCK asserts blebuck_comp1 for about 54.0us (10 percent margin of error) or more 10 Set9 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 48.6us (10 percent margin of error) or more 9 Set8 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 43.2us (10 percent margin of error) or more 8 Set7 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 37.8us (10 percent margin of error) or more 7 Set6 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 32.4us (10 percent margin of error) or more 6 Set5 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 27.0us (10 percent margin of error) or more 5 Set4 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 21.6us (10 percent margin of error) or more 4 Set3 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 16.2us (10 percent margin of error) or more 3 Set2 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 10.8us (10 percent margin of error) or more 2 Set1 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 5.4us (10 percent margin of error) or more 1 Set0 Indicator send when the BLE BUCK asserts blebuck_comp1 for about 2.0us (10 percent margin of error) or more 0 TONADJUSTEN TON ADJUST ENABLE [22:22] read-write DIS Disable Adjust for BLE BUCK TON trim 0 EN Enable Adjust for BLE BUCK TON trim 1 TONADJUSTPERIOD TON ADJUST PERIOD [21:20] read-write HFRC_3KHz Adjust done for every 1 3KHz period 3 HFRC_12KHz Adjust done for every 1 12KHz period 2 HFRC_47KHz Adjust done for every 1 47KHz period 1 HFRC_94KHz Adjust done for every 1 94KHz period 0 TONHIGHTHRESHOLD TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz) [19:10] read-write TONLOWTHRESHOLD TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz) [9:0] read-write INTRPTEN CLKGEN Interrupt Register: Enable 0x00000100 32 read-write 0x00000000 0x00000007 OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTRPTSTAT CLKGEN Interrupt Register: Status 0x00000104 32 read-write 0x00000000 0x00000007 OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTRPTCLR CLKGEN Interrupt Register: Clear 0x00000108 32 read-write 0x00000000 0x00000007 OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTRPTSET CLKGEN Interrupt Register: Set 0x0000010C 32 read-write 0x00000000 0x00000007 OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write CTIMER 1.0 Counter/Timer 0x40008000 32 read-write 0 0x00000310 registers CTIMER 14 STIMER 22 STIMER_CMPR0 23 STIMER_CMPR1 24 STIMER_CMPR2 25 STIMER_CMPR3 26 STIMER_CMPR4 27 STIMER_CMPR5 28 STIMER_CMPR6 29 STIMER_CMPR7 30 TMR0 Counter/Timer Register 0x00000000 32 read-write 0x00000000 0xFFFFFFFF CTTMRB0 Counter/Timer B0. [31:16] read-write CTTMRA0 Counter/Timer A0. [15:0] read-write CMPRA0 Counter/Timer A0 Compare Registers 0x00000004 32 read-write 0x00000000 0xFFFFFFFF CMPR1A0 Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A. [31:16] read-write CMPR0A0 Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A. [15:0] read-write CMPRB0 Counter/Timer B0 Compare Registers 0x00000008 32 read-write 0x00000000 0xFFFFFFFF CMPR1B0 Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B. [31:16] read-write CMPR0B0 Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B. [15:0] read-write CTRL0 Counter/Timer Control 0x0000000C 32 read-write 0x00000000 0x9FFF1FFF CTLINK0 Counter/Timer A0/B0 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A0/B0 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A0/B0 timers into a single 32-bit timer. 1 TMRB0POL Counter/Timer B0 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB0 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB0 pin is the inverse of the timer output. 1 TMRB0CLR Counter/Timer B0 Clear bit. [27:27] read-write RUN Allow counter/timer B0 to run 0 CLEAR Holds counter/timer B0 at 0x0000. 1 TMRB0IE1 Counter/Timer B0 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B0 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B0 to generate an interrupt based on COMPR1. 1 TMRB0IE0 Counter/Timer B0 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B0 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B0 to generate an interrupt based on COMPR0 1 TMRB0FN Counter/Timer B0 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B0, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB0CLK Counter/Timer B0 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA0 Clock source is CTIMERA0 OUT. 20 CTMRB1 Clock source is CTIMERB1 OUT. 21 CTMRA1 Clock source is CTIMERA1 OUT. 22 CTMRA2 Clock source is CTIMERA2 OUT. 23 CTMRB2 Clock source is CTIMERB2 OUT. 24 CTMRB3 Clock source is CTIMERB3 OUT. 25 CTMRB4 Clock source is CTIMERB4 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB0EN Counter/Timer B0 Enable bit. [16:16] read-write DIS Counter/Timer B0 Disable. 0 EN Counter/Timer B0 Enable. 1 TMRA0POL Counter/Timer A0 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA0 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA0 pin is the inverse of the timer output. 1 TMRA0CLR Counter/Timer A0 Clear bit. [11:11] read-write RUN Allow counter/timer A0 to run 0 CLEAR Holds counter/timer A0 at 0x0000. 1 TMRA0IE1 Counter/Timer A0 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A0 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A0 to generate an interrupt based on COMPR1. 1 TMRA0IE0 Counter/Timer A0 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A0 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A0 to generate an interrupt based on COMPR0. 1 TMRA0FN Counter/Timer A0 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A0, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1A0, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA0CLK Counter/Timer A0 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB0 Clock source is CTIMERB0 OUT. 20 CTMRA1 Clock source is CTIMERA1 OUT. 21 CTMRB1 Clock source is CTIMERB1 OUT. 22 CTMRA2 Clock source is CTIMERA2 OUT. 23 CTMRB2 Clock source is CTIMERB2 OUT. 24 CTMRB3 Clock source is CTIMERB3 OUT. 25 CTMRB4 Clock source is CTIMERB4 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA0EN Counter/Timer A0 Enable bit. [0:0] read-write DIS Counter/Timer A0 Disable. 0 EN Counter/Timer A0 Enable. 1 CMPRAUXA0 Counter/Timer A0 Compare Registers 0x00000014 32 read-write 0x00000000 0xFFFFFFFF CMPR3A0 Counter/Timer A0 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A0 Counter/Timer A0 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB0 Counter/Timer B0 Compare Registers 0x00000018 32 read-write 0x00000000 0xFFFFFFFF CMPR3B0 Counter/Timer B0 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B0 Counter/Timer B0 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX0 Counter/Timer Auxiliary 0x0000001C 32 read-write 0x00000000 0x7FBF7FFF TMRB0EN23 Counter/Timer B0 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB0POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB0TINV Counter/Timer B0 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB0NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB0TRIG Counter/Timer B0 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A0OUT Trigger source is CTIMERA0 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 B2OUT Trigger source is CTIMERB2 OUT. 4 B5OUT Trigger source is CTIMERB5 OUT. 5 A4OUT Trigger source is CTIMERA4 OUT. 6 B4OUT Trigger source is CTIMERB4 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 B7OUT2 Trigger source is CTIMERB7 OUT2. 10 A2OUT2 Trigger source is CTIMERA2 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B5OUT2DUAL Trigger source is CTIMERB5 OUT2, dual edge. 14 A5OUT2DUAL Trigger source is CTIMERA5 OUT2, dual edge. 15 TMRB0LMT Counter/Timer B0 Pattern Limit Count. [21:16] read-write TMRA0EN23 Counter/Timer A0 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA0POL23 Counter/Timer A0 Upper output polarity [13:13] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA0TINV Counter/Timer A0 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA0NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA0TRIG Counter/Timer A0 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 B0OUT Trigger source is CTIMERB0 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A1OUT Trigger source is CTIMERA1 OUT. 4 B1OUT Trigger source is CTIMERB1 OUT. 5 A5OUT Trigger source is CTIMERA5 OUT. 6 B5OUT Trigger source is CTIMERB5 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 B6OUT2 Trigger source is CTIMERB6 OUT2. 10 A2OUT2 Trigger source is CTIMERA2 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B4OUT2DUAL Trigger source is CTIMERB4 OUT2, dual edge. 14 A4OUT2DUAL Trigger source is CTIMERA4 OUT2, dual edge. 15 TMRA0LMT Counter/Timer A0 Pattern Limit Count. [6:0] read-write TMR1 Counter/Timer Register 0x00000020 32 read-write 0x00000000 0xFFFFFFFF CTTMRB1 Counter/Timer B1. [31:16] read-write CTTMRA1 Counter/Timer A1. [15:0] read-write CMPRA1 Counter/Timer A1 Compare Registers 0x00000024 32 read-write 0x00000000 0xFFFFFFFF CMPR1A1 Counter/Timer A1 Compare Register 1. [31:16] read-write CMPR0A1 Counter/Timer A1 Compare Register 0. [15:0] read-write CMPRB1 Counter/Timer B1 Compare Registers 0x00000028 32 read-write 0x00000000 0xFFFFFFFF CMPR1B1 Counter/Timer B1 Compare Register 1. [31:16] read-write CMPR0B1 Counter/Timer B1 Compare Register 0. [15:0] read-write CTRL1 Counter/Timer Control 0x0000002C 32 read-write 0x00000000 0x9FFF1FFF CTLINK1 Counter/Timer A1/B1 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A1/B1 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A1/B1 timers into a single 32-bit timer. 1 TMRB1POL Counter/Timer B1 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB1 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB1 pin is the inverse of the timer output. 1 TMRB1CLR Counter/Timer B1 Clear bit. [27:27] read-write RUN Allow counter/timer B1 to run 0 CLEAR Holds counter/timer B1 at 0x0000. 1 TMRB1IE1 Counter/Timer B1 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B1 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B1 to generate an interrupt based on COMPR1. 1 TMRB1IE0 Counter/Timer B1 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B1 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B1 to generate an interrupt based on COMPR0 1 TMRB1FN Counter/Timer B1 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B1, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B1, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB1CLK Counter/Timer B1 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA1 Clock source is CTIMERA1 OUT. 20 CTMRA0 Clock source is CTIMERA0 OUT. 21 CTMRB0 Clock source is CTIMERB0 OUT. 22 CTMRA2 Clock source is CTIMERA2 OUT. 23 CTMRB2 Clock source is CTIMERB2 OUT. 24 CTMRB3 Clock source is CTIMERB3 OUT. 25 CTMRB4 Clock source is CTIMERB4 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB1EN Counter/Timer B1 Enable bit. [16:16] read-write DIS Counter/Timer B1 Disable. 0 EN Counter/Timer B1 Enable. 1 TMRA1POL Counter/Timer A1 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA1 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA1 pin is the inverse of the timer output. 1 TMRA1CLR Counter/Timer A1 Clear bit. [11:11] read-write RUN Allow counter/timer A1 to run 0 CLEAR Holds counter/timer A1 at 0x0000. 1 TMRA1IE1 Counter/Timer A1 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A1 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A1 to generate an interrupt based on COMPR1. 1 TMRA1IE0 Counter/Timer A1 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A1 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A1 to generate an interrupt based on COMPR0. 1 TMRA1FN Counter/Timer A1 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A1, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1A1, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA1CLK Counter/Timer A1 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB1 Clock source is CTIMERB1 OUT. 20 CTMRA0 Clock source is CTIMERA0 OUT. 21 CTMRB0 Clock source is CTIMERB0 OUT. 22 CTMRA2 Clock source is CTIMERA2 OUT. 23 CTMRB2 Clock source is CTIMERB2 OUT. 24 CTMRB3 Clock source is CTIMERB3 OUT. 25 CTMRB4 Clock source is CTIMERB4 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA1EN Counter/Timer A1 Enable bit. [0:0] read-write DIS Counter/Timer A1 Disable. 0 EN Counter/Timer A1 Enable. 1 CMPRAUXA1 Counter/Timer A1 Compare Registers 0x00000034 32 read-write 0x00000000 0xFFFFFFFF CMPR3A1 Counter/Timer A1 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A1 Counter/Timer A1 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB1 Counter/Timer B1 Compare Registers 0x00000038 32 read-write 0x00000000 0xFFFFFFFF CMPR3B1 Counter/Timer B1 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B1 Counter/Timer B1 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX1 Counter/Timer Auxiliary 0x0000003C 32 read-write 0x00000000 0x7FBF7FFF TMRB1EN23 Counter/Timer B1 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB1POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB1TINV Counter/Timer B1 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB1NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB1TRIG Counter/Timer B1 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A1OUT Trigger source is CTIMERA1 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A6OUT Trigger source is CTIMERA6 OUT. 4 B6OUT Trigger source is CTIMERB6 OUT. 5 A0OUT Trigger source is CTIMERA0 OUT. 6 B0OUT Trigger source is CTIMERB0 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A4OUT2 Trigger source is CTIMERA4 OUT2. 10 B4OUT2 Trigger source is CTIMERB4 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B5OUT2DUAL Trigger source is CTIMERB5 OUT2, dual edge. 14 A5OUT2DUAL Trigger source is CTIMERA5 OUT2, dual edge. 15 TMRB1LMT Counter/Timer B1 Pattern Limit Count. [21:16] read-write TMRA1EN23 Counter/Timer A1 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA1POL23 Counter/Timer A1 Upper output polarity [13:13] read-write NORMAL Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA1TINV Counter/Timer A1 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA1NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA1TRIG Counter/Timer A1 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 B1OUT Trigger source is CTIMERB1 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A0OUT Trigger source is CTIMERA0 OUT. 4 B0OUT Trigger source is CTIMERB0 OUT. 5 A5OUT Trigger source is CTIMERA5 OUT. 6 B5OUT Trigger source is CTIMERB5 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A4OUT2 Trigger source is CTIMERA4 OUT2. 10 B4OUT2 Trigger source is CTIMERB4 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B5OUT2DUAL Trigger source is CTIMERB5 OUT2, dual edge. 14 A5OUT2DUAL Trigger source is CTIMERA5 OUT2, dual edge. 15 TMRA1LMT Counter/Timer A1 Pattern Limit Count. [6:0] read-write TMR2 Counter/Timer Register 0x00000040 32 read-write 0x00000000 0xFFFFFFFF CTTMRB2 Counter/Timer B2. [31:16] read-write CTTMRA2 Counter/Timer A2. [15:0] read-write CMPRA2 Counter/Timer A2 Compare Registers 0x00000044 32 read-write 0x00000000 0xFFFFFFFF CMPR1A2 Counter/Timer A2 Compare Register 1. [31:16] read-write CMPR0A2 Counter/Timer A2 Compare Register 0. [15:0] read-write CMPRB2 Counter/Timer B2 Compare Registers 0x00000048 32 read-write 0x00000000 0xFFFFFFFF CMPR1B2 Counter/Timer B2 Compare Register 1. [31:16] read-write CMPR0B2 Counter/Timer B2 Compare Register 0. [15:0] read-write CTRL2 Counter/Timer Control 0x0000004C 32 read-write 0x00000000 0x9FFF1FFF CTLINK2 Counter/Timer A2/B2 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A2/B2 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A2/B2 timers into a single 32-bit timer. 1 TMRB2POL Counter/Timer B2 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB2 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB2 pin is the inverse of the timer output. 1 TMRB2CLR Counter/Timer B2 Clear bit. [27:27] read-write RUN Allow counter/timer B2 to run 0 CLEAR Holds counter/timer B2 at 0x0000. 1 TMRB2IE1 Counter/Timer B2 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B2 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B2 to generate an interrupt based on COMPR1. 1 TMRB2IE0 Counter/Timer B2 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B2 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B2 to generate an interrupt based on COMPR0 1 TMRB2FN Counter/Timer B2 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B2, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB2CLK Counter/Timer B2 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA2 Clock source is CTIMERA2 OUT. 20 CTMRB3 Clock source is CTIMERA3 OUT. 21 CTMRA3 Clock source is CTIMERB3 OUT. 22 CTMRA4 Clock source is CTIMERA4 OUT. 23 CTMRB4 Clock source is CTIMERB4 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB1 Clock source is CTIMERB1 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB2EN Counter/Timer B2 Enable bit. [16:16] read-write DIS Counter/Timer B2 Disable. 0 EN Counter/Timer B2 Enable. 1 TMRA2POL Counter/Timer A2 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA2 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA2 pin is the inverse of the timer output. 1 TMRA2CLR Counter/Timer A2 Clear bit. [11:11] read-write RUN Allow counter/timer A2 to run 0 CLEAR Holds counter/timer A2 at 0x0000. 1 TMRA2IE1 Counter/Timer A2 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A2 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A2 to generate an interrupt based on COMPR1. 1 TMRA2IE0 Counter/Timer A2 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A2 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A2 to generate an interrupt based on COMPR0. 1 TMRA2FN Counter/Timer A2 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A2, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1A2, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA2CLK Counter/Timer A2 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB2 Clock source is CTIMERB2 OUT. 20 CTMRB3 Clock source is CTIMERA3 OUT. 21 CTMRA3 Clock source is CTIMERB3 OUT. 22 CTMRA4 Clock source is CTIMERA4 OUT. 23 CTMRB4 Clock source is CTIMERB4 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB1 Clock source is CTIMERB1 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA2EN Counter/Timer A2 Enable bit. [0:0] read-write DIS Counter/Timer A2 Disable. 0 EN Counter/Timer A2 Enable. 1 CMPRAUXA2 Counter/Timer A2 Compare Registers 0x00000054 32 read-write 0x00000000 0xFFFFFFFF CMPR3A2 Counter/Timer A2 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A2 Counter/Timer A2 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB2 Counter/Timer B2 Compare Registers 0x00000058 32 read-write 0x00000000 0xFFFFFFFF CMPR3B2 Counter/Timer B2 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B2 Counter/Timer B2 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX2 Counter/Timer Auxiliary 0x0000005C 32 read-write 0x00000000 0x7FBF7FFF TMRB2EN23 Counter/Timer B2 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB2POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB2TINV Counter/Timer B2 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB2NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB2TRIG Counter/Timer B2 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A2OUT Trigger source is CTIMERA2 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A1OUT Trigger source is CTIMERA1 OUT. 4 B1OUT Trigger source is CTIMERB1 OUT. 5 A4OUT Trigger source is CTIMERA4 OUT. 6 B4OUT Trigger source is CTIMERB4 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A5OUT2 Trigger source is CTIMERA5 OUT2. 10 B5OUT2 Trigger source is CTIMERB5 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B4OUT2DUAL Trigger source is CTIMERB4 OUT2, dual edge. 14 A4OUT2DUAL Trigger source is CTIMERA4 OUT2, dual edge. 15 TMRB2LMT Counter/Timer B2 Pattern Limit Count. [21:16] read-write TMRA2EN23 Counter/Timer A2 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA2POL23 Counter/Timer A2 Upper output polarity [13:13] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA2TINV Counter/Timer A2 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA2NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA2TRIG Counter/Timer A2 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 B2OUT Trigger source is CTIMERB2 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A0OUT Trigger source is CTIMERA0 OUT. 4 B0OUT Trigger source is CTIMERB0 OUT. 5 A4OUT Trigger source is CTIMERA4 OUT. 6 B4OUT Trigger source is CTIMERB4 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A5OUT2 Trigger source is CTIMERA5 OUT2. 10 B5OUT2 Trigger source is CTIMERB5 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B4OUT2DUAL Trigger source is CTIMERB4 OUT2, dual edge. 14 A4OUT2DUAL Trigger source is CTIMERA4 OUT2, dual edge. 15 TMRA2LMT Counter/Timer A2 Pattern Limit Count. [6:0] read-write TMR3 Counter/Timer Register 0x00000060 32 read-write 0x00000000 0xFFFFFFFF CTTMRB3 Counter/Timer B3. [31:16] read-write CTTMRA3 Counter/Timer A3. [15:0] read-write CMPRA3 Counter/Timer A3 Compare Registers 0x00000064 32 read-write 0x00000000 0xFFFFFFFF CMPR1A3 Counter/Timer A3 Compare Register 1. [31:16] read-write CMPR0A3 Counter/Timer A3 Compare Register 0. [15:0] read-write CMPRB3 Counter/Timer B3 Compare Registers 0x00000068 32 read-write 0x00000000 0xFFFFFFFF CMPR1B3 Counter/Timer B3 Compare Register 1. [31:16] read-write CMPR0B3 Counter/Timer B3 Compare Register 0. [15:0] read-write CTRL3 Counter/Timer Control 0x0000006C 32 read-write 0x00000000 0x9FFF9FFF CTLINK3 Counter/Timer A3/B3 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A3/B3 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A3/B3 timers into a single 32-bit timer. 1 TMRB3POL Counter/Timer B3 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB3 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB3 pin is the inverse of the timer output. 1 TMRB3CLR Counter/Timer B3 Clear bit. [27:27] read-write RUN Allow counter/timer B3 to run 0 CLEAR Holds counter/timer B3 at 0x0000. 1 TMRB3IE1 Counter/Timer B3 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B3 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B3 to generate an interrupt based on COMPR1. 1 TMRB3IE0 Counter/Timer B3 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B3 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B3 to generate an interrupt based on COMPR0 1 TMRB3FN Counter/Timer B3 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B3, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B3, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB3CLK Counter/Timer B3 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA3 Clock source is CTIMERA3 OUT. 20 CTMRA2 Clock source is CTIMERA2 OUT. 21 CTMRB2 Clock source is CTIMERB2 OUT. 22 CTMRA4 Clock source is CTIMERA4 OUT. 23 CTMRB4 Clock source is CTIMERB4 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB1 Clock source is CTIMERB1 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB3EN Counter/Timer B3 Enable bit. [16:16] read-write DIS Counter/Timer B3 Disable. 0 EN Counter/Timer B3 Enable. 1 ADCEN Special Timer A3 enable for ADC function. [15:15] read-write TMRA3POL Counter/Timer A3 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA3 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA3 pin is the inverse of the timer output. 1 TMRA3CLR Counter/Timer A3 Clear bit. [11:11] read-write RUN Allow counter/timer A3 to run 0 CLEAR Holds counter/timer A3 at 0x0000. 1 TMRA3IE1 Counter/Timer A3 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A3 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A3 to generate an interrupt based on COMPR1. 1 TMRA3IE0 Counter/Timer A3 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A3 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A3 to generate an interrupt based on COMPR0. 1 TMRA3FN Counter/Timer A3 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A3, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1A3, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA3CLK Counter/Timer A3 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB3 Clock source is CTIMERB3 OUT. 20 CTMRA2 Clock source is CTIMERA2 OUT. 21 CTMRB2 Clock source is CTIMERB2 OUT. 22 CTMRA4 Clock source is CTIMERA4 OUT. 23 CTMRB4 Clock source is CTIMERB4 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB1 Clock source is CTIMERB1 OUT. 26 CTMRB5 Clock source is CTIMERB5 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA3EN Counter/Timer A3 Enable bit. [0:0] read-write DIS Counter/Timer A3 Disable. 0 EN Counter/Timer A3 Enable. 1 CMPRAUXA3 Counter/Timer A3 Compare Registers 0x00000074 32 read-write 0x00000000 0xFFFFFFFF CMPR3A3 Counter/Timer A3 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A3 Counter/Timer A3 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB3 Counter/Timer B3 Compare Registers 0x00000078 32 read-write 0x00000000 0xFFFFFFFF CMPR3B3 Counter/Timer B3 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B3 Counter/Timer B3 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX3 Counter/Timer Auxiliary 0x0000007C 32 read-write 0x00000000 0x7FBF7FFF TMRB3EN23 Counter/Timer B3 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB3POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB3TINV Counter/Timer B3 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB3NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB3TRIG Counter/Timer B3 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A3OUT Trigger source is CTIMERA3 OUT. 1 B2OUT Trigger source is CTIMERB2 OUT. 2 A2OUT Trigger source is CTIMERA2 OUT. 3 A4OUT Trigger source is CTIMERA4 OUT. 4 B4OUT Trigger source is CTIMERB4 OUT. 5 A6OUT Trigger source is CTIMERA6 OUT. 6 B6OUT Trigger source is CTIMERB6 OUT. 7 B5OUT2 Trigger source is CTIMERB5 OUT2. 8 A5OUT2 Trigger source is CTIMERA5 OUT2. 9 A1OUT2 Trigger source is CTIMERA1 OUT2. 10 B1OUT2 Trigger source is CTIMERB1 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B2OUT2DUAL Trigger source is CTIMERB2 OUT2, dual edge. 14 A2OUT2DUAL Trigger source is CTIMERA2 OUT2, dual edge. 15 TMRB3LMT Counter/Timer B3 Pattern Limit Count. [21:16] read-write TMRA3EN23 Counter/Timer A3 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA3POL23 Counter/Timer A3 Upper output polarity [13:13] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA3TINV Counter/Timer A3 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA3NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA3TRIG Counter/Timer A3 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 B3OUT Trigger source is CTIMERB3 OUT. 1 B2OUT Trigger source is CTIMERB2 OUT. 2 A2OUT Trigger source is CTIMERA2 OUT. 3 A4OUT Trigger source is CTIMERA4 OUT. 4 B4OUT Trigger source is CTIMERB4 OUT. 5 A7OUT Trigger source is CTIMERA7 OUT. 6 B7OUT Trigger source is CTIMERB7 OUT. 7 B5OUT2 Trigger source is CTIMERB5 OUT2. 8 A5OUT2 Trigger source is CTIMERA5 OUT2. 9 A1OUT2 Trigger source is CTIMERA1 OUT2. 10 B1OUT2 Trigger source is CTIMERB1 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B2OUT2DUAL Trigger source is CTIMERB2 OUT2, dual edge. 14 A2OUT2DUAL Trigger source is CTIMERA2 OUT2, dual edge. 15 TMRA3LMT Counter/Timer A3 Pattern Limit Count. [6:0] read-write TMR4 Counter/Timer Register 0x00000080 32 read-write 0x00000000 0xFFFFFFFF CTTMRB4 Counter/Timer B4. [31:16] read-write CTTMRA4 Counter/Timer A4. [15:0] read-write CMPRA4 Counter/Timer A4 Compare Registers 0x00000084 32 read-write 0x00000000 0xFFFFFFFF CMPR1A4 Counter/Timer A4 Compare Register 1. Holds the upper limit for timer half A. [31:16] read-write CMPR0A4 Counter/Timer A4 Compare Register 0. Holds the lower limit for timer half A. [15:0] read-write CMPRB4 Counter/Timer B4 Compare Registers 0x00000088 32 read-write 0x00000000 0xFFFFFFFF CMPR1B4 Counter/Timer B4 Compare Register 1. Holds the upper limit for timer half B. [31:16] read-write CMPR0B4 Counter/Timer B4 Compare Register 0. Holds the lower limit for timer half B. [15:0] read-write CTRL4 Counter/Timer Control 0x0000008C 32 read-write 0x00000000 0x9FFF1FFF CTLINK4 Counter/Timer A4/B4 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A4/B4 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A4/B4 timers into a single 32-bit timer. 1 TMRB4POL Counter/Timer B4 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB4 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB4 pin is the inverse of the timer output. 1 TMRB4CLR Counter/Timer B4 Clear bit. [27:27] read-write RUN Allow counter/timer B4 to run 0 CLEAR Holds counter/timer B4 at 0x0000. 1 TMRB4IE1 Counter/Timer B4 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B4 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B4 to generate an interrupt based on COMPR1. 1 TMRB4IE0 Counter/Timer B4 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B4 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B4 to generate an interrupt based on COMPR0 1 TMRB4FN Counter/Timer B4 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B4, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B4, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B4, assert, count to CMPR1B4, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B4, assert, count to CMPR1B4, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB4CLK Counter/Timer B4 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA4 Clock source is CTIMERA4 OUT. 20 CTMRA1 Clock source is CTIMERA1 OUT. 21 CTMRB1 Clock source is CTIMERB1 OUT. 22 CTMRA5 Clock source is CTIMERA5 OUT. 23 CTMRB5 Clock source is CTIMERB5 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB2 Clock source is CTIMERB2 OUT. 26 CTMRB3 Clock source is CTIMERB3 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB4EN Counter/Timer B4 Enable bit. [16:16] read-write DIS Counter/Timer B4 Disable. 0 EN Counter/Timer B4 Enable. 1 TMRA4POL Counter/Timer A4 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA4 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA4 pin is the inverse of the timer output. 1 TMRA4CLR Counter/Timer A4 Clear bit. [11:11] read-write RUN Allow counter/timer A4 to run 0 CLEAR Holds counter/timer A4 at 0x0000. 1 TMRA4IE1 Counter/Timer A4 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A4 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A4 to generate an interrupt based on COMPR1. 1 TMRA4IE0 Counter/Timer A4 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A4 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A4 to generate an interrupt based on COMPR0. 1 TMRA4FN Counter/Timer A4 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A4, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A4, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A4, assert, count to CMPR1A4, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A4, assert, count to CMPR1A4, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA4CLK Counter/Timer A4 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4. (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB4 Clock source is CTIMERB4 OUT. 20 CTMRA1 Clock source is CTIMERA1 OUT. 21 CTMRB1 Clock source is CTIMERB1 OUT. 22 CTMRA5 Clock source is CTIMERA5 OUT. 23 CTMRB5 Clock source is CTIMERB5 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB2 Clock source is CTIMERB2 OUT. 26 CTMRB3 Clock source is CTIMERB3 OUT. 27 CTMRB6 Clock source is CTIMERB6 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA4EN Counter/Timer A4 Enable bit. [0:0] read-write DIS Counter/Timer A4 Disable. 0 EN Counter/Timer A4 Enable. 1 CMPRAUXA4 Counter/Timer A4 Compare Registers 0x00000094 32 read-write 0x00000000 0xFFFFFFFF CMPR3A4 Counter/Timer A4 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A4 Counter/Timer A4 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB4 Counter/Timer B4 Compare Registers 0x00000098 32 read-write 0x00000000 0xFFFFFFFF CMPR3B4 Counter/Timer B4 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B4 Counter/Timer B4 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX4 Counter/Timer Auxiliary 0x0000009C 32 read-write 0x00000000 0x7FBF7FFF TMRB4EN23 Counter/Timer B4 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB4POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB4TINV Counter/Timer B4 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB4NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB4TRIG Counter/Timer B4 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A4OUT Trigger source is CTIMERA4 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A7OUT Trigger source is CTIMERA7 OUT. 4 B7OUT Trigger source is CTIMERB7 OUT. 5 A1OUT Trigger source is CTIMERA1 OUT. 6 B1OUT Trigger source is CTIMERB1 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A1OUT2 Trigger source is CTIMERA1 OUT2. 10 B1OUT2 Trigger source is CTIMERB1 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B5OUT2DUAL Trigger source is CTIMERB5 OUT2, dual edge. 14 A5OUT2DUAL Trigger source is CTIMERA5 OUT2, dual edge. 15 TMRB4LMT Counter/Timer B4 Pattern Limit Count. [21:16] read-write TMRA4EN23 Counter/Timer A4 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA4POL23 Counter/Timer A4 Upper output polarity [13:13] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA4TINV Counter/Timer A4 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA4NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA4TRIG Counter/Timer A4 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 STIMER Trigger source is STimer Interrupt. Only Active When CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER interrupt 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A6OUT Trigger source is CTIMERA6 OUT. 4 B6OUT Trigger source is CTIMERB6 OUT. 5 A2OUT Trigger source is CTIMERA2 OUT. 6 B2OUT Trigger source is CTIMERB2 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A1OUT2 Trigger source is CTIMERA1 OUT2. 10 B1OUT2 Trigger source is CTIMERB1 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B5OUT2DUAL Trigger source is CTIMERB5 OUT2, dual edge. 14 A5OUT2DUAL Trigger source is CTIMERA5 OUT2, dual edge. 15 TMRA4LMT Counter/Timer A4 Pattern Limit Count. [6:0] read-write TMR5 Counter/Timer Register 0x000000A0 32 read-write 0x00000000 0xFFFFFFFF CTTMRB5 Counter/Timer B5. [31:16] read-write CTTMRA5 Counter/Timer A5. [15:0] read-write CMPRA5 Counter/Timer A5 Compare Registers 0x000000A4 32 read-write 0x00000000 0xFFFFFFFF CMPR1A5 Counter/Timer A5 Compare Register 1. [31:16] read-write CMPR0A5 Counter/Timer A5 Compare Register 0. [15:0] read-write CMPRB5 Counter/Timer B5 Compare Registers 0x000000A8 32 read-write 0x00000000 0xFFFFFFFF CMPR1B5 Counter/Timer B5 Compare Register 1. [31:16] read-write CMPR0B5 Counter/Timer B5 Compare Register 0. [15:0] read-write CTRL5 Counter/Timer Control 0x000000AC 32 read-write 0x00000000 0x9FFF1FFF CTLINK5 Counter/Timer A5/B5 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A5/B5 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A5/B5 timers into a single 32-bit timer. 1 TMRB5POL Counter/Timer B5 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB5 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB5 pin is the inverse of the timer output. 1 TMRB5CLR Counter/Timer B5 Clear bit. [27:27] read-write RUN Allow counter/timer B5 to run 0 CLEAR Holds counter/timer B5 at 0x0000. 1 TMRB5IE1 Counter/Timer B5 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B5 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B5 to generate an interrupt based on COMPR1. 1 TMRB5IE0 Counter/Timer B5 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B5 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B5 to generate an interrupt based on COMPR0 1 TMRB5FN Counter/Timer B5 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B5, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B5, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B5, assert, count to CMPR1B5, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B5, assert, count to CMPR1B5, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB5CLK Counter/Timer B5 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA5 Clock source is CTIMERA5 OUT. 20 CTMRA0 Clock source is CTIMERA0 OUT. 21 CTMRB0 Clock source is CTIMERB0 OUT. 22 CTMRA6 Clock source is CTIMERA6 OUT. 23 CTMRB6 Clock source is CTIMERB6 OUT. 24 CTMRB1 Clock source is CTIMERB1 OUT. 25 CTMRB2 Clock source is CTIMERB2 OUT. 26 CTMRB3 Clock source is CTIMERB3 OUT. 27 CTMRB4 Clock source is CTIMERB4 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB5EN Counter/Timer B5 Enable bit. [16:16] read-write DIS Counter/Timer B5 Disable. 0 EN Counter/Timer B5 Enable. 1 TMRA5POL Counter/Timer A5 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA5 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA5 pin is the inverse of the timer output. 1 TMRA5CLR Counter/Timer A5 Clear bit. [11:11] read-write RUN Allow counter/timer A5 to run 0 CLEAR Holds counter/timer A5 at 0x0000. 1 TMRA5IE1 Counter/Timer A5 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A5 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A5 to generate an interrupt based on COMPR1. 1 TMRA5IE0 Counter/Timer A5 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A5 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A5 to generate an interrupt based on COMPR0. 1 TMRA5FN Counter/Timer A5 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A5, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A5, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A5, assert, count to CMPR1A5, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A5, assert, count to CMPR1A5, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA5CLK Counter/Timer A5 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB5 Clock source is CTIMERB5 OUT. 20 CTMRA0 Clock source is CTIMERA0 OUT. 21 CTMRB0 Clock source is CTIMERB0 OUT. 22 CTMRA6 Clock source is CTIMERA6 OUT. 23 CTMRB6 Clock source is CTIMERB6 OUT. 24 CTMRB1 Clock source is CTIMERB1 OUT. 25 CTMRB2 Clock source is CTIMERB2 OUT. 26 CTMRB3 Clock source is CTIMERB3 OUT. 27 CTMRB4 Clock source is CTIMERB4 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA5EN Counter/Timer A5 Enable bit. [0:0] read-write DIS Counter/Timer A5 Disable. 0 EN Counter/Timer A5 Enable. 1 CMPRAUXA5 Counter/Timer A5 Compare Registers 0x000000B4 32 read-write 0x00000000 0xFFFFFFFF CMPR3A5 Counter/Timer A5 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A5 Counter/Timer A5 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB5 Counter/Timer B5 Compare Registers 0x000000B8 32 read-write 0x00000000 0xFFFFFFFF CMPR3B5 Counter/Timer B5 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B5 Counter/Timer B5 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX5 Counter/Timer Auxiliary 0x000000BC 32 read-write 0x00000000 0x7FBF7FFF TMRB5EN23 Counter/Timer B5 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB5POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB5TINV Counter/Timer B5 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB5NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB5TRIG Counter/Timer B5 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A5OUT Trigger source is CTIMERA5 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A6OUT Trigger source is CTIMERA6 OUT. 4 B6OUT Trigger source is CTIMERB6 OUT. 5 A1OUT Trigger source is CTIMERA1 OUT. 6 B1OUT Trigger source is CTIMERB1 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A0OUT2 Trigger source is CTIMERA0 OUT2. 10 B0OUT2 Trigger source is CTIMERB0 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B4OUT2DUAL Trigger source is CTIMERB4 OUT2, dual edge. 14 A4OUT2DUAL Trigger source is CTIMERA4 OUT2, dual edge. 15 TMRB5LMT Counter/Timer B5 Pattern Limit Count. [21:16] read-write TMRA5EN23 Counter/Timer A5 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA5POL23 Counter/Timer A5 Upper output polarity [13:13] read-write NORMAL Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA5TINV Counter/Timer A5 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA5NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA5TRIG Counter/Timer A5 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 STIMER Trigger source is STimer Interrupt. Only Active When CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER interrupt 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A4OUT Trigger source is CTIMERA4 OUT. 4 B4OUT Trigger source is CTIMERB4 OUT. 5 A2OUT Trigger source is CTIMERA2 OUT. 6 B2OUT Trigger source is CTIMERB2 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A0OUT2 Trigger source is CTIMERA0 OUT2. 10 B0OUT2 Trigger source is CTIMERB0 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B4OUT2DUAL Trigger source is CTIMERB4 OUT2, dual edge. 14 A4OUT2DUAL Trigger source is CTIMERA4 OUT2, dual edge. 15 TMRA5LMT Counter/Timer A5 Pattern Limit Count. [6:0] read-write TMR6 Counter/Timer Register 0x000000C0 32 read-write 0x00000000 0xFFFFFFFF CTTMRB6 Counter/Timer B6. [31:16] read-write CTTMRA6 Counter/Timer A6. [15:0] read-write CMPRA6 Counter/Timer A6 Compare Registers 0x000000C4 32 read-write 0x00000000 0xFFFFFFFF CMPR1A6 Counter/Timer A6 Compare Register 1. [31:16] read-write CMPR0A6 Counter/Timer A6 Compare Register 0. [15:0] read-write CMPRB6 Counter/Timer B6 Compare Registers 0x000000C8 32 read-write 0x00000000 0xFFFFFFFF CMPR1B6 Counter/Timer B6 Compare Register 1. [31:16] read-write CMPR0B6 Counter/Timer B6 Compare Register 0. [15:0] read-write CTRL6 Counter/Timer Control 0x000000CC 32 read-write 0x00000000 0x9FFF1FFF CTLINK6 Counter/Timer A6/B6 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A6/B6 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A6/B6 timers into a single 32-bit timer. 1 TMRB6POL Counter/Timer B6 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB6 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB6 pin is the inverse of the timer output. 1 TMRB6CLR Counter/Timer B6 Clear bit. [27:27] read-write RUN Allow counter/timer B6 to run 0 CLEAR Holds counter/timer B6 at 0x0000. 1 TMRB6IE1 Counter/Timer B6 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B6 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B6 to generate an interrupt based on COMPR1. 1 TMRB6IE0 Counter/Timer B6 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B6 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B6 to generate an interrupt based on COMPR0 1 TMRB6FN Counter/Timer B6 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B6, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B6, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B6, assert, count to CMPR1B6, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B6, assert, count to CMPR1B6, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB6CLK Counter/Timer B6 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA6 Clock source is CTIMERA6 OUT. 20 CTMRA3 Clock source is CTIMERA3 OUT. 21 CTMRB3 Clock source is CTIMERB3 OUT. 22 CTMRA7 Clock source is CTIMERA7 OUT. 23 CTMRB7 Clock source is CTIMERB7 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB1 Clock source is CTIMERB1 OUT. 26 CTMRB2 Clock source is CTIMERB2 OUT. 27 CTMRB4 Clock source is CTIMERB4 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB6EN Counter/Timer B6 Enable bit. [16:16] read-write DIS Counter/Timer B6 Disable. 0 EN Counter/Timer B6 Enable. 1 TMRA6POL Counter/Timer A6 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA6 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA6 pin is the inverse of the timer output. 1 TMRA6CLR Counter/Timer A6 Clear bit. [11:11] read-write RUN Allow counter/timer A6 to run 0 CLEAR Holds counter/timer A6 at 0x0000. 1 TMRA6IE1 Counter/Timer A6 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A6 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A6 to generate an interrupt based on COMPR1. 1 TMRA6IE0 Counter/Timer A6 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A6 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A6 to generate an interrupt based on COMPR0. 1 TMRA6FN Counter/Timer A6 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A6, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A6, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A6, assert, count to CMPR1A6, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A6, assert, count to CMPR1A6, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA6CLK Counter/Timer A6 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB6 Clock source is CTIMERB6 OUT. 20 CTMRA3 Clock source is CTIMERA3 OUT. 21 CTMRB3 Clock source is CTIMERB3 OUT. 22 CTMRA7 Clock source is CTIMERA7 OUT. 23 CTMRB7 Clock source is CTIMERB7 OUT. 24 CTMRB0 Clock source is CTIMERB0 OUT. 25 CTMRB1 Clock source is CTIMERB1 OUT. 26 CTMRB2 Clock source is CTIMERB2 OUT. 27 CTMRB4 Clock source is CTIMERB4 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA6EN Counter/Timer A6 Enable bit. [0:0] read-write DIS Counter/Timer A6 Disable. 0 EN Counter/Timer A6 Enable. 1 CMPRAUXA6 Counter/Timer A6 Compare Registers 0x000000D4 32 read-write 0x00000000 0xFFFFFFFF CMPR3A6 Counter/Timer A6 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A6 Counter/Timer A6 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB6 Counter/Timer B6 Compare Registers 0x000000D8 32 read-write 0x00000000 0xFFFFFFFF CMPR3B6 Counter/Timer B6 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B6 Counter/Timer B6 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX6 Counter/Timer Auxiliary 0x000000DC 32 read-write 0x00000000 0x7FBF7FFF TMRB6EN23 Counter/Timer B6 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB6POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB6TINV Counter/Timer B6 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB6NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB6TRIG Counter/Timer B6 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A6OUT Trigger source is CTIMERA6 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A4OUT Trigger source is CTIMERA4 OUT. 4 B4OUT Trigger source is CTIMERB4 OUT. 5 A1OUT Trigger source is CTIMERA1 OUT. 6 B1OUT Trigger source is CTIMERB1 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A2OUT2 Trigger source is CTIMERA2 OUT2. 10 B2OUT2 Trigger source is CTIMERB2 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B0OUT2DUAL Trigger source is CTIMERB0 OUT2, dual edge. 14 A0OUT2DUAL Trigger source is CTIMERA0 OUT2, dual edge. 15 TMRB6LMT Counter/Timer B6 Pattern Limit Count. [21:16] read-write TMRA6EN23 Counter/Timer A6 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA6POL23 Counter/Timer A6 Upper output polarity [13:13] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA6TINV Counter/Timer A6 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA6NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA6TRIG Counter/Timer A6 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 B6OUT Trigger source is CTIMERB6 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A5OUT Trigger source is CTIMERA5 OUT. 4 B5OUT Trigger source is CTIMERB5 OUT. 5 A1OUT Trigger source is CTIMERA1 OUT. 6 B1OUT Trigger source is CTIMERB1 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A2OUT2 Trigger source is CTIMERA2 OUT2. 10 B2OUT2 Trigger source is CTIMERBb OUT2. 11 A5OUT2DUAL Trigger source is CTIMERA5 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B0OUT2DUAL Trigger source is CTIMERB0 OUT2, dual edge. 14 A0OUT2DUAL Trigger source is CTIMERA0 OUT2, dual edge. 15 TMRA6LMT Counter/Timer A6 Pattern Limit Count. [6:0] read-write TMR7 Counter/Timer Register 0x000000E0 32 read-write 0x00000000 0xFFFFFFFF CTTMRB7 Counter/Timer B7. [31:16] read-write CTTMRA7 Counter/Timer A7. [15:0] read-write CMPRA7 Counter/Timer A7 Compare Registers 0x000000E4 32 read-write 0x00000000 0xFFFFFFFF CMPR1A7 Counter/Timer A7 Compare Register 1. [31:16] read-write CMPR0A7 Counter/Timer A7 Compare Register 0. [15:0] read-write CMPRB7 Counter/Timer B7 Compare Registers 0x000000E8 32 read-write 0x00000000 0xFFFFFFFF CMPR1B7 Counter/Timer B3 Compare Register 1. [31:16] read-write CMPR0B7 Counter/Timer B3 Compare Register 0. [15:0] read-write CTRL7 Counter/Timer Control 0x000000EC 32 read-write 0x00000000 0x9FFF1FFF CTLINK7 Counter/Timer A7/B7 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A7/B7 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A7/B7 timers into a single 32-bit timer. 1 TMRB7POL Counter/Timer B7 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB7 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB7 pin is the inverse of the timer output. 1 TMRB7CLR Counter/Timer B7 Clear bit. [27:27] read-write RUN Allow counter/timer B7 to run 0 CLEAR Holds counter/timer B7 at 0x0000. 1 TMRB7IE1 Counter/Timer B7 Interrupt Enable bit for COMPR1. [26:26] read-write DIS Disable counter/timer B7 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B7 to generate an interrupt based on COMPR1. 1 TMRB7IE0 Counter/Timer B7 Interrupt Enable bit for COMPR0. [25:25] read-write DIS Disable counter/timer B7 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B7 to generate an interrupt based on COMPR0 1 TMRB7FN Counter/Timer B7 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B7, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B7, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B7, assert, count to CMPR1B7, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B7, assert, count to CMPR1B7, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRB7CLK Counter/Timer B7 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRA7 Clock source is CTIMERA7 OUT. 20 CTMRA2 Clock source is CTIMERA2 OUT. 21 CTMRB2 Clock source is CTIMERB2 OUT. 22 CTMRA0 Clock source is CTIMERA0 OUT. 23 CTMRB0 Clock source is CTIMERB0 OUT. 24 CTMRB1 Clock source is CTIMERB1 OUT. 25 CTMRB3 Clock source is CTIMERB3 OUT. 26 CTMRB4 Clock source is CTIMERB4 OUT. 27 CTMRB5 Clock source is CTIMERB5 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRB7EN Counter/Timer B7 Enable bit. [16:16] read-write DIS Counter/Timer B7 Disable. 0 EN Counter/Timer B7 Enable. 1 TMRA7POL Counter/Timer A7 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA7 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA7 pin is the inverse of the timer output. 1 TMRA7CLR Counter/Timer A7 Clear bit. [11:11] read-write RUN Allow counter/timer A7 to run 0 CLEAR Holds counter/timer A7 at 0x0000. 1 TMRA7IE1 Counter/Timer A7 Interrupt Enable bit based on COMPR1. [10:10] read-write DIS Disable counter/timer A7 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A7 to generate an interrupt based on COMPR1. 1 TMRA7IE0 Counter/Timer A7 Interrupt Enable bit based on COMPR0. [9:9] read-write DIS Disable counter/timer A7 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A7 to generate an interrupt based on COMPR0. 1 TMRA7FN Counter/Timer A7 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A7, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A7, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A7, assert, count to CMPR1A7, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A7, assert, count to CMPR1A7, deassert, restart. 3 SINGLEPATTERN Single pattern. 4 REPEATPATTERN Repeated pattern. 5 CONTINUOUS Continuous run (aka Free Run). Count continuously. 6 ALTPWN Alternate PWM 7 TMRA7CLK Counter/Timer A7 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is the HFRC / 4 1 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV128 Clock source is XT / 128 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) 15 XT_DIV4 Clock source is XT / 4 16 XT_DIV8 Clock source is XT / 8 17 XT_DIV32 Clock source is XT / 32 18 CTMRB7 Clock source is CTIMERB7 OUT. 20 CTMRA2 Clock source is CTIMERA2 OUT. 21 CTMRB2 Clock source is CTIMERB2 OUT. 22 CTMRA0 Clock source is CTIMERA0 OUT. 23 CTMRB0 Clock source is CTIMERB0 OUT. 24 CTMRB1 Clock source is CTIMERB1 OUT. 25 CTMRB3 Clock source is CTIMERB3 OUT. 26 CTMRB4 Clock source is CTIMERB4 OUT. 27 CTMRB5 Clock source is CTIMERB5 OUT. 28 BUCKBLE Clock source is BLE buck converter TON pulses. 29 BUCKB Clock source is Memory buck converter TON pulses. 30 BUCKA Clock source is CPU buck converter TON pulses. 31 TMRA7EN Counter/Timer A7 Enable bit. [0:0] read-write DIS Counter/Timer A7 Disable. 0 EN Counter/Timer A7 Enable. 1 CMPRAUXA7 Counter/Timer A7 Compare Registers 0x000000F4 32 read-write 0x00000000 0xFFFFFFFF CMPR3A7 Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half A. [31:16] read-write CMPR2A7 Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A. [15:0] read-write CMPRAUXB7 Counter/Timer B7 Compare Registers 0x000000F8 32 read-write 0x00000000 0xFFFFFFFF CMPR3B7 Counter/Timer B7 Compare Register 3. Holds the upper limit for timer half B. [31:16] read-write CMPR2B7 Counter/Timer B7 Compare Register 2. Holds the lower limit for timer half B. [15:0] read-write AUX7 Counter/Timer Auxiliary 0x000000FC 32 read-write 0x00000000 0x7FBF7FFF TMRB7EN23 Counter/Timer B7 Upper compare enable. [30:30] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRB7POL23 Upper output polarity [29:29] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRB7TINV Counter/Timer B7 Invert on trigger. [28:28] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRB7NOSYNC Source clock synchronization control. [27:27] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRB7TRIG Counter/Timer B7 Trigger Select. [26:23] read-write DIS Trigger source is disabled. 0 A7OUT Trigger source is CTIMERA7 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A5OUT Trigger source is CTIMERA5 OUT. 4 B5OUT Trigger source is CTIMERB5 OUT. 5 A2OUT Trigger source is CTIMERA2 OUT. 6 B2OUT Trigger source is CTIMERB2 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A2OUT2 Trigger source is CTIMERA2 OUT2. 10 B2OUT2 Trigger source is CTIMERB2 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A7OUT2DUAL Trigger source is CTIMERA7 OUT2, dual edge. 13 B1OUT2DUAL Trigger source is CTIMERB1 OUT2, dual edge. 14 A1OUT2DUAL Trigger source is CTIMERA1 OUT2, dual edge. 15 TMRB7LMT Counter/Timer B7 Pattern Limit Count. [21:16] read-write TMRA7EN23 Counter/Timer A7 Upper compare enable. [14:14] read-write DIS Disable enhanced functions. 1 EN Enable enhanced functions. 0 TMRA7POL23 Counter/Timer A7 Upper output polarity [13:13] read-write NORM Upper output normal polarity 0 INV Upper output inverted polarity. 1 TMRA7TINV Counter/Timer A7 Invert on trigger. [12:12] read-write DIS Disable invert on trigger 0 EN Enable invert on trigger 1 TMRA7NOSYNC Source clock synchronization control. [11:11] read-write DIS Synchronization on source clock 0 NOSYNC No synchronization on source clock 1 TMRA7TRIG Counter/Timer A7 Trigger Select. [10:7] read-write DIS Trigger source is disabled. 0 B7OUT Trigger source is CTIMERB7 OUT. 1 B3OUT Trigger source is CTIMERB3 OUT. 2 A3OUT Trigger source is CTIMERA3 OUT. 3 A1OUT Trigger source is CTIMERA1 OUT. 4 B1OUT Trigger source is CTIMERB1 OUT. 5 A4OUT Trigger source is CTIMERA4 OUT. 6 B4OUT Trigger source is CTIMERB4 OUT. 7 B3OUT2 Trigger source is CTIMERB3 OUT2. 8 A3OUT2 Trigger source is CTIMERA3 OUT2. 9 A2OUT2 Trigger source is CTIMERA2 OUT2. 10 B2OUT2 Trigger source is CTIMERB2 OUT2. 11 A6OUT2DUAL Trigger source is CTIMERA6 OUT2, dual edge. 12 A5OUT2DUAL Trigger source is CTIMERA5 OUT2, dual edge. 13 B4OUT2DUAL Trigger source is CTIMERB4 OUT2, dual edge. 14 A4OUT2DUAL Trigger source is CTIMERA4 OUT2, dual edge. 15 TMRA7LMT Counter/Timer A7 Pattern Limit Count. [6:0] read-write GLOBEN Counter/Timer Global Enable 0x00000100 32 read-write 0x0000FFFF 0x0000FFFF ENB7 Alternate enable for B7. [15:15] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA7 Alternate enable for A7 [14:14] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENB6 Alternate enable for B6 [13:13] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA6 Alternate enable for A6 [12:12] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENB5 Alternate enable for B5 [11:11] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA5 Alternate enable for A5 [10:10] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENB4 Alternate enable for B4 [9:9] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA4 Alternate enable for A4 [8:8] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENB3 Alternate enable for B3. [7:7] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA3 Alternate enable for A3 [6:6] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENB2 Alternate enable for B2 [5:5] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA2 Alternate enable for A2 [4:4] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENB1 Alternate enable for B1 [3:3] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA1 Alternate enable for A1 [2:2] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENB0 Alternate enable for B0 [1:1] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 ENA0 Alternate enable for A0 [0:0] read-write LCO Use local enable. 1 DIS Disable CTIMER. 0 OUTCFG0 Counter/Timer Output Config 0 0x00000104 32 read-write 0x24922292 0x7FFF7FFF CFG9 Pad output 9 configuration [30:28] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B0OUT Output is B0OUT. 5 A4OUT Output is A4OUT. 4 A2OUT Output is A2OUT. 3 A2OUT2 Output is A2OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG8 Pad output 8 configuration [27:25] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B6OUT Output is B6OUT. 5 A4OUT2 Output is A4OUT2. 4 A3OUT2 Output is A3OUT. 3 A2OUT Output is A2OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG7 Pad output 7 configuration [24:22] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A7OUT Output is A7OUT. 5 B5OUT Output is B5OUT. 4 B1OUT Output is B1OUT. 3 B1OUT2 Output is B1OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG6 Pad output 6 configuration [21:19] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B7OUT Output is B7OUT. 5 B5OUT2 Output is B5OUT2. 4 A1OUT Output is A1OUT. 3 B1OUT Output is B1OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG5 Pad output 5 configuration [18:16] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A7OUT Output is A7OUT. 5 B6OUT Output is A5OUT. 4 A1OUT Output is A1OUT. 3 A1OUT2 Output is A1OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG4 Pad output 4 configuration [14:12] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B5OUT Output is B5OUT. 5 A5OUT2 Output is A5OUT2. 4 A2OUT2 Output is A2OUT2. 3 A1OUT Output is A1OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG3 Pad output 3 configuration [11:9] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A6OUT Output is A6OUT. 5 A1OUT Output is A1OUT. 4 B0OUT Output is B0OUT. 3 B0OUT2 Output is B0OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG2 Pad output 2 configuration [8:6] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A7OUT Output is A7OUT. 5 B6OUT2 Output is B6OUT2. 4 B1OUT2 Output is B1OUT2. 3 B0OUT Output is B0OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG1 Pad output 1 configuration [5:3] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B7OUT2 Output is B7OUT2. 5 A5OUT Output is A5OUT. 4 A0OUT Output is A0OUT. 3 A0OUT2 Output is A0OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG0 Pad output 0 configuration [2:0] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A6OUT Output is A6OUT. 5 A5OUT2 Output is A5OUT2. 4 B2OUT2 Output is B2OUT2. 3 A0OUT Output is A0OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 OUTCFG1 Counter/Timer Output Config 1 0x00000108 32 read-write 0x24922292 0x7FFF7FFF CFG19 Pad output 19 configuration [30:28] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B1OUT2 Output is B1OUT2. 5 B4OUT Output is B4OUT. 4 A2OUT Output is A2OUT. 3 B4OUT2 Output is B4OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG18 Pad output 18 configuration [27:25] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A3OUT2 Output is A3OUT2. 5 A0OUT Output is A0OUT. 4 B0OUT Output is B0OUT. 3 B4OUT Output is B4OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG17 Pad output 17 configuration [24:22] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A1OUT2 Output is A1OUT2. 5 A4OUT Output is A4OUT. 4 B7OUT Output is B7OUT. 3 A4OUT2 Output is A4OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG16 Pad output 16 configuration [21:19] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B3OUT2 Output is B3OUT2. 5 A0OUT2 Output is A0OUT2. 4 A0OUT Output is A0OUT. 3 A4OUT Output is A4OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG15 Pad output 15 configuration [18:16] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A4OUT2 Output is A4OUT2. 5 A7OUT Output is A7OUT. 4 B3OUT Output is B3OUT. 3 B3OUT2 Output is B3OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG14 Pad output 14 configuration [14:12] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A7OUT Output is A7OUT. 5 B7OUT2 Output is B7OUT2. 4 B1OUT Output is B1OUT. 3 B3OUT Output is B3OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG13 Pad output 13 configuration [11:9] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B4OUT2 Output is B4OUT2. 5 A6OUT Output is A6OUT. 4 A3OUT Output is A3OUT. 3 A3OUT2 Output is A3OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG12 Pad output 12 configuration [8:6] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B6OUT2 Output is B6OUT2. 5 B0OUT2 Output is B0OUT2. 4 B1OUT Output is B1OUT. 3 A3OUT Output is A3OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG11 Pad output 11 configuration [5:3] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B5OUT2 Output is B5OUT2. 5 B4OUT Output is B4OUT. 4 B2OUT Output is B2OUT. 3 B2OUT2 Output is B2OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG10 Pad output 10 configuration [2:0] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A6OUT Output is A6OUT. 5 B4OUT2 Output is B4OUT2. 4 B3OUT2 Output is B3OUT2. 3 B2OUT Output is B2OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 OUTCFG2 Counter/Timer Output Config 2 0x0000010C 32 read-write 0x24922292 0x7FFF7FFF CFG29 Pad output 29 configuration [30:28] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A3OUT2 Output is A3OUT2. 5 A7OUT Output is A7OUT. 4 A1OUT Output is A1OUT. 3 B5OUT2 Output is B5OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG28 Pad output 28 configuration [27:25] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B0OUT2 Output is B0OUT2. 5 A5OUT2 Output is A5OUT2. 4 A3OUT Output is A3OUT. 3 A7OUT Output is A7OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG27 Pad output 27 configuration [24:22] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B2OUT2 Output is B2OUT2. 5 B6OUT Output is B6OUT. 4 A1OUT Output is A1OUT. 3 B6OUT2 Output is B6OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG26 Pad output 26 configuration [21:19] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A1OUT2 Output is A1OUT2. 5 A5OUT Output is A5OUT. 4 B2OUT Output is B2OUT. 3 B6OUT Output is B6OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG25 Pad output 25 configuration [18:16] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A2OUT2 Output is A2OUT2. 5 A6OUT Output is A6OUT. 4 B2OUT Output is B2OUT. 3 B4OUT2 Output is B4OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG24 Pad output 24 configuration [14:12] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B1OUT2 Output is B1OUT2. 5 A1OUT Output is A1OUT. 4 A2OUT Output is A2OUT. 3 A6OUT Output is A6OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG23 Pad output 23 configuration [11:9] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B0OUT2 Output is B0OUT2. 5 A5OUT Output is A5OUT. 4 A7OUT Output is A7OUT. 3 B5OUT2 Output is B5OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG22 Pad output 22 configuration [8:6] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A2OUT2 Output is A2OUT2. 5 A1OUT Output is A1OUT. 4 A6OUT Output is A6OUT. 3 B5OUT Output is B5OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG21 Pad output 21 configuration [5:3] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A0OUT2 Output is A0OUT2. 5 B5OUT Output is B5OUT. 4 A1OUT Output is A1OUT. 3 A5OUT2 Output is A5OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG20 Pad output 20 configuration [2:0] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B2OUT2 Output is B2OUT2. 5 A1OUT2 Output is A1OUT2. 4 A1OUT Output is A1OUT. 3 A5OUT Output is A5OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 OUTCFG3 Counter/Timer Output Config 3 0x00000114 32 read-write 0x00000012 0x0000003F CFG31 Pad output 31 configuration [5:3] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 B3OUT2 Output is B3OUT2. 5 B7OUT Output is B7OUT. 4 A6OUT Output is A6OUT. 3 B7OUT2 Output is B7OUT2 2 ONE Force output to 1. 1 ZERO Force output to 0 0 CFG30 Pad output 30 configuration [2:0] read-write A7OUT2 Output is A7OUT2. 7 A6OUT2 Output is A6OUT2. 6 A0OUT2 Output is A0OUT2. 5 A4OUT2 Output is A4OUT2. 4 B3OUT Output is B3OUT. 3 B7OUT Output is B7OUT 2 ONE Force output to 1. 1 ZERO Force output to 0 0 INCFG Counter/Timer Input Config 0x00000118 32 read-write 0x00000000 0x0000FFFF CFGB7 CTIMER B7 input configuration [15:15] read-write CT31 Input is CT31 1 CT30 Input is CT30 0 CFGA7 CTIMER A7 input configuration [14:14] read-write CT29 Input is CT29 1 CT28 Input is CT28 0 CFGB6 CTIMER B6 input configuration [13:13] read-write CT27 Input is CT27 1 CT26 Input is CT26 0 CFGA6 CTIMER A6 input configuration [12:12] read-write CT25 Input is CT25 1 CT24 Input is CT24 0 CFGB5 CTIMER B5 input configuration [11:11] read-write CT23 Input is CT23 1 CT22 Input is CT22 0 CFGA5 CTIMER A5 input configuration [10:10] read-write CT21 Input is CT21 1 CT20 Input is CT20 0 CFGB4 CTIMER B4 input configuration [9:9] read-write CT19 Input is CT19 1 CT18 Input is CT18 0 CFGA4 CTIMER A4 input configuration [8:8] read-write CT17 Input is CT17 1 CT16 Input is CT16 0 CFGB3 CTIMER B3 input configuration [7:7] read-write CT15 Input is CT15 1 CT14 Input is CT14 0 CFGA3 CTIMER A3 input configuration [6:6] read-write CT13 Input is CT13 1 CT12 Input is CT12 0 CFGB2 CTIMER B2 input configuration [5:5] read-write CT11 Input is CT11 1 CT10 Input is CT10 0 CFGA2 CTIMER A2 input configuration [4:4] read-write CT9 Input is CT9 1 CT8 Input is CT8 0 CFGB1 CTIMER B1 input configuration [3:3] read-write CT7 Input is CT7 1 CT6 Input is CT6 0 CFGA1 CTIMER A1 input configuration [2:2] read-write CT5 Input is CT5 1 CT4 Input is CT4 0 CFGB0 CTIMER B0 input configuration [1:1] read-write CT3 Input is CT3 1 CT2 Input is CT2 0 CFGA0 CTIMER A0 input configuration [0:0] read-write CT1 Input is CT1 1 CT0 Input is CT0 0 STCFG Configuration Register 0x00000140 32 read-write 0x80000000 0xC000FF0F FREEZE Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume. [31:31] read-write THAW Let the COUNTER register run on its input clock. 0 FREEZE Stop the COUNTER register for loading. 1 CLEAR Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running. [30:30] read-write RUN Let the COUNTER register run on its input clock. 0 CLEAR Stop the COUNTER register for loading. 1 COMPARE_H_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [15:15] read-write DISABLE Compare H disabled. 0 ENABLE Compare H enabled. 1 COMPARE_G_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [14:14] read-write DISABLE Compare G disabled. 0 ENABLE Compare G enabled. 1 COMPARE_F_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [13:13] read-write DISABLE Compare F disabled. 0 ENABLE Compare F enabled. 1 COMPARE_E_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [12:12] read-write DISABLE Compare E disabled. 0 ENABLE Compare E enabled. 1 COMPARE_D_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [11:11] read-write DISABLE Compare D disabled. 0 ENABLE Compare D enabled. 1 COMPARE_C_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [10:10] read-write DISABLE Compare C disabled. 0 ENABLE Compare C enabled. 1 COMPARE_B_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [9:9] read-write DISABLE Compare B disabled. 0 ENABLE Compare B enabled. 1 COMPARE_A_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. [8:8] read-write DISABLE Compare A disabled. 0 ENABLE Compare A enabled. 1 CLKSEL Selects an appropriate clock source and divider to use for the System Timer clock. [3:0] read-write NOCLK No clock enabled. 0 HFRC_DIV16 3MHz from the HFRC clock divider. 1 HFRC_DIV256 187.5KHz from the HFRC clock divider. 2 XTAL_DIV1 32768Hz from the crystal oscillator. 3 XTAL_DIV2 16384Hz from the crystal oscillator. 4 XTAL_DIV32 1024Hz from the crystal oscillator. 5 LFRC_DIV1 Approximately 1KHz from the LFRC oscillator (uncalibrated). 6 CTIMER0A Use CTIMER 0 section A as a prescaler for the clock source. 7 CTIMER0B Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source. 8 STTMR System Timer Count Register (Real Time Counter) 0x00000144 32 read-write 0x00000000 0xFFFFFFFF STTMR Value of the 32-bit counter as it ticks over. [31:0] read-write CAPTURECONTROL Capture Control Register 0x00000148 32 read-write 0x00000000 0x0000000F CAPTURE3 Selects whether capture is enabled for the specified capture register. [3:3] read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 CAPTURE2 Selects whether capture is enabled for the specified capture register. [2:2] read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 CAPTURE1 Selects whether capture is enabled for the specified capture register. [1:1] read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 CAPTURE0 Selects whether capture is enabled for the specified capture register. [0:0] read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 SCMPR0 Compare Register A 0x00000150 32 read-write 0x00000000 0xFFFFFFFF SCMPR0 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCMPR1 Compare Register B 0x00000154 32 read-write 0x00000000 0xFFFFFFFF SCMPR1 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCMPR2 Compare Register C 0x00000158 32 read-write 0x00000000 0xFFFFFFFF SCMPR2 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCMPR3 Compare Register D 0x0000015C 32 read-write 0x00000000 0xFFFFFFFF SCMPR3 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCMPR4 Compare Register E 0x00000160 32 read-write 0x00000000 0xFFFFFFFF SCMPR4 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCMPR5 Compare Register F 0x00000164 32 read-write 0x00000000 0xFFFFFFFF SCMPR5 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCMPR6 Compare Register G 0x00000168 32 read-write 0x00000000 0xFFFFFFFF SCMPR6 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCMPR7 Compare Register H 0x0000016C 32 read-write 0x00000000 0xFFFFFFFF SCMPR7 Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register. [31:0] read-write SCAPT0 Capture Register A 0x000001E0 32 read-write 0x00000000 0xFFFFFFFF SCAPT0 Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. [31:0] read-write SCAPT1 Capture Register B 0x000001E4 32 read-write 0x00000000 0xFFFFFFFF SCAPT1 Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. [31:0] read-write SCAPT2 Capture Register C 0x000001E8 32 read-write 0x00000000 0xFFFFFFFF SCAPT2 Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. [31:0] read-write SCAPT3 Capture Register D 0x000001EC 32 read-write 0x00000000 0xFFFFFFFF SCAPT3 Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. [31:0] read-write SNVR0 System Timer NVRAM_A Register 0x000001F0 32 read-write 0x00000000 0xFFFFFFFF SNVR0 Value of the 32-bit counter as it ticks over. [31:0] read-write SNVR1 System Timer NVRAM_B Register 0x000001F4 32 read-write 0x00000000 0xFFFFFFFF SNVR1 Value of the 32-bit counter as it ticks over. [31:0] read-write SNVR2 System Timer NVRAM_C Register 0x000001F8 32 read-write 0x00000000 0xFFFFFFFF SNVR2 Value of the 32-bit counter as it ticks over. [31:0] read-write SNVR3 System Timer NVRAM_D Register 0x000001FC 32 read-write 0x00000000 0xFFFFFFFF SNVR3 Value of the 32-bit counter as it ticks over. [31:0] read-write INTEN Counter/Timer Interrupts: Enable 0x00000200 32 read-write 0x00000000 0xFFFFFFFF CTMRB7C1INT Counter/Timer B7 interrupt based on COMPR1. [31:31] read-write CTMRA7C1INT Counter/Timer A7 interrupt based on COMPR1. [30:30] read-write CTMRB6C1INT Counter/Timer B6 interrupt based on COMPR1. [29:29] read-write CTMRA6C1INT Counter/Timer A6 interrupt based on COMPR1. [28:28] read-write CTMRB5C1INT Counter/Timer B5 interrupt based on COMPR1. [27:27] read-write CTMRA5C1INT Counter/Timer A5 interrupt based on COMPR1. [26:26] read-write CTMRB4C1INT Counter/Timer B4 interrupt based on COMPR1. [25:25] read-write CTMRA4C1INT Counter/Timer A4 interrupt based on COMPR1. [24:24] read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. [23:23] read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. [22:22] read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. [21:21] read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. [20:20] read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. [19:19] read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. [18:18] read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. [17:17] read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. [16:16] read-write CTMRB7C0INT Counter/Timer B7 interrupt based on COMPR0. [15:15] read-write CTMRA7C0INT Counter/Timer A7 interrupt based on COMPR0. [14:14] read-write CTMRB6C0INT Counter/Timer B6 interrupt based on COMPR0. [13:13] read-write CTMRA6C0INT Counter/Timer A6 interrupt based on COMPR0. [12:12] read-write CTMRB5C0INT Counter/Timer B5 interrupt based on COMPR0. [11:11] read-write CTMRA5C0INT Counter/Timer A5 interrupt based on COMPR0. [10:10] read-write CTMRB4C0INT Counter/Timer B4 interrupt based on COMPR0. [9:9] read-write CTMRA4C0INT Counter/Timer A4 interrupt based on COMPR0. [8:8] read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. [7:7] read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. [6:6] read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. [5:5] read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. [4:4] read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. [3:3] read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. [2:2] read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. [1:1] read-write CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. [0:0] read-write INTSTAT Counter/Timer Interrupts: Status 0x00000204 32 read-write 0x00000000 0xFFFFFFFF CTMRB7C1INT Counter/Timer B7 interrupt based on COMPR1. [31:31] read-write CTMRA7C1INT Counter/Timer A7 interrupt based on COMPR1. [30:30] read-write CTMRB6C1INT Counter/Timer B6 interrupt based on COMPR1. [29:29] read-write CTMRA6C1INT Counter/Timer A6 interrupt based on COMPR1. [28:28] read-write CTMRB5C1INT Counter/Timer B5 interrupt based on COMPR1. [27:27] read-write CTMRA5C1INT Counter/Timer A5 interrupt based on COMPR1. [26:26] read-write CTMRB4C1INT Counter/Timer B4 interrupt based on COMPR1. [25:25] read-write CTMRA4C1INT Counter/Timer A4 interrupt based on COMPR1. [24:24] read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. [23:23] read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. [22:22] read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. [21:21] read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. [20:20] read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. [19:19] read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. [18:18] read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. [17:17] read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. [16:16] read-write CTMRB7C0INT Counter/Timer B7 interrupt based on COMPR0. [15:15] read-write CTMRA7C0INT Counter/Timer A7 interrupt based on COMPR0. [14:14] read-write CTMRB6C0INT Counter/Timer B6 interrupt based on COMPR0. [13:13] read-write CTMRA6C0INT Counter/Timer A6 interrupt based on COMPR0. [12:12] read-write CTMRB5C0INT Counter/Timer B5 interrupt based on COMPR0. [11:11] read-write CTMRA5C0INT Counter/Timer A5 interrupt based on COMPR0. [10:10] read-write CTMRB4C0INT Counter/Timer B4 interrupt based on COMPR0. [9:9] read-write CTMRA4C0INT Counter/Timer A4 interrupt based on COMPR0. [8:8] read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. [7:7] read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. [6:6] read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. [5:5] read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. [4:4] read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. [3:3] read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. [2:2] read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. [1:1] read-write CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. [0:0] read-write INTCLR Counter/Timer Interrupts: Clear 0x00000208 32 read-write 0x00000000 0xFFFFFFFF CTMRB7C1INT Counter/Timer B7 interrupt based on COMPR1. [31:31] read-write CTMRA7C1INT Counter/Timer A7 interrupt based on COMPR1. [30:30] read-write CTMRB6C1INT Counter/Timer B6 interrupt based on COMPR1. [29:29] read-write CTMRA6C1INT Counter/Timer A6 interrupt based on COMPR1. [28:28] read-write CTMRB5C1INT Counter/Timer B5 interrupt based on COMPR1. [27:27] read-write CTMRA5C1INT Counter/Timer A5 interrupt based on COMPR1. [26:26] read-write CTMRB4C1INT Counter/Timer B4 interrupt based on COMPR1. [25:25] read-write CTMRA4C1INT Counter/Timer A4 interrupt based on COMPR1. [24:24] read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. [23:23] read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. [22:22] read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. [21:21] read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. [20:20] read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. [19:19] read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. [18:18] read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. [17:17] read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. [16:16] read-write CTMRB7C0INT Counter/Timer B7 interrupt based on COMPR0. [15:15] read-write CTMRA7C0INT Counter/Timer A7 interrupt based on COMPR0. [14:14] read-write CTMRB6C0INT Counter/Timer B6 interrupt based on COMPR0. [13:13] read-write CTMRA6C0INT Counter/Timer A6 interrupt based on COMPR0. [12:12] read-write CTMRB5C0INT Counter/Timer B5 interrupt based on COMPR0. [11:11] read-write CTMRA5C0INT Counter/Timer A5 interrupt based on COMPR0. [10:10] read-write CTMRB4C0INT Counter/Timer B4 interrupt based on COMPR0. [9:9] read-write CTMRA4C0INT Counter/Timer A4 interrupt based on COMPR0. [8:8] read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. [7:7] read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. [6:6] read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. [5:5] read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. [4:4] read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. [3:3] read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. [2:2] read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. [1:1] read-write CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. [0:0] read-write INTSET Counter/Timer Interrupts: Set 0x0000020C 32 read-write 0x00000000 0xFFFFFFFF CTMRB7C1INT Counter/Timer B7 interrupt based on COMPR1. [31:31] read-write CTMRA7C1INT Counter/Timer A7 interrupt based on COMPR1. [30:30] read-write CTMRB6C1INT Counter/Timer B6 interrupt based on COMPR1. [29:29] read-write CTMRA6C1INT Counter/Timer A6 interrupt based on COMPR1. [28:28] read-write CTMRB5C1INT Counter/Timer B5 interrupt based on COMPR1. [27:27] read-write CTMRA5C1INT Counter/Timer A5 interrupt based on COMPR1. [26:26] read-write CTMRB4C1INT Counter/Timer B4 interrupt based on COMPR1. [25:25] read-write CTMRA4C1INT Counter/Timer A4 interrupt based on COMPR1. [24:24] read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. [23:23] read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. [22:22] read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. [21:21] read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. [20:20] read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. [19:19] read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. [18:18] read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. [17:17] read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. [16:16] read-write CTMRB7C0INT Counter/Timer B7 interrupt based on COMPR0. [15:15] read-write CTMRA7C0INT Counter/Timer A7 interrupt based on COMPR0. [14:14] read-write CTMRB6C0INT Counter/Timer B6 interrupt based on COMPR0. [13:13] read-write CTMRA6C0INT Counter/Timer A6 interrupt based on COMPR0. [12:12] read-write CTMRB5C0INT Counter/Timer B5 interrupt based on COMPR0. [11:11] read-write CTMRA5C0INT Counter/Timer A5 interrupt based on COMPR0. [10:10] read-write CTMRB4C0INT Counter/Timer B4 interrupt based on COMPR0. [9:9] read-write CTMRA4C0INT Counter/Timer A4 interrupt based on COMPR0. [8:8] read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. [7:7] read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. [6:6] read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. [5:5] read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. [4:4] read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. [3:3] read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. [2:2] read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. [1:1] read-write CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. [0:0] read-write STMINTEN STIMER Interrupt registers: Enable 0x00000300 32 read-write 0x00000000 0x00001FFF CAPTURED CAPTURE register D has grabbed the value in the counter [12:12] read-write CAPD_INT Capture D interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter [11:11] read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter [10:10] read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREA CAPTURE register A has grabbed the value in the counter [9:9] read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. [8:8] read-write OFLOW_INT Overflow interrupt status bit was set. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. [7:7] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. [6:6] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. [5:5] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. [4:4] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. [3:3] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. [2:2] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. [1:1] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. [0:0] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 STMINTSTAT STIMER Interrupt registers: Status 0x00000304 32 read-write 0x00000000 0x00001FFF CAPTURED CAPTURE register D has grabbed the value in the counter [12:12] read-write CAPD_INT Capture D interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter [11:11] read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter [10:10] read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREA CAPTURE register A has grabbed the value in the counter [9:9] read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. [8:8] read-write OFLOW_INT Overflow interrupt status bit was set. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. [7:7] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. [6:6] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. [5:5] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. [4:4] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. [3:3] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. [2:2] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. [1:1] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. [0:0] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 STMINTCLR STIMER Interrupt registers: Clear 0x00000308 32 read-write 0x00000000 0x00001FFF CAPTURED CAPTURE register D has grabbed the value in the counter [12:12] read-write CAPD_INT Capture D interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter [11:11] read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter [10:10] read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREA CAPTURE register A has grabbed the value in the counter [9:9] read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. [8:8] read-write OFLOW_INT Overflow interrupt status bit was set. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. [7:7] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. [6:6] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. [5:5] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. [4:4] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. [3:3] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. [2:2] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. [1:1] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. [0:0] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 STMINTSET STIMER Interrupt registers: Set 0x0000030C 32 read-write 0x00000000 0x00001FFF CAPTURED CAPTURE register D has grabbed the value in the counter [12:12] read-write CAPD_INT Capture D interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter [11:11] read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter [10:10] read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREA CAPTURE register A has grabbed the value in the counter [9:9] read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. [8:8] read-write OFLOW_INT Overflow interrupt status bit was set. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. [7:7] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. [6:6] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. [5:5] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. [4:4] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. [3:3] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. [2:2] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. [1:1] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. [0:0] read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 GPIO 1.0 General Purpose IO 0x40010000 32 read-write 0 0x00000220 registers GPIO 13 PADREGA Pad Configuration Register A (Pads 3-0) 0x00000000 32 read-write 0x18181818 0x7F3FFFFF PAD3PWRUP Pad 3 VDD power switch enable [30:30] read-write DIS Power switch disabled 0 EN Power switch enabled (switched to VDD) 1 PAD3FNCSEL Pad 3 function select [29:27] read-write UA0RTS Configure as the UART0 RTS output 0 SLnCE Configure as the IOSLAVE SPI nCE signal 1 NCE3 IOM/MSPI nCE group 3 2 GPIO3 Configure as GPIO3 3 MSPI7 MSPI data connection 7 5 TRIG1 Configure as the ADC Trigger 1 signal 6 I2S_WCLK Configure as the PDM I2S Word Clock input 7 PAD3STRNG Pad 3 drive strength. [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD3INPEN Pad 3 input enable. [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD3PULL Pad 3 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD2FNCSEL Pad 2 function select [21:19] read-write UART1RX Configure as the UART1 RX input. 0 SLMISO Configure as the IOSLAVE SPI MISO signal. 1 UART0RX Configure as the UART0 RX input. 2 GPIO2 Configure as GPIO2. 3 MSPI6 MSPI data connection 6. 5 NCE2 IOM/MSPI nCE group 2 7 PAD2STRNG Pad 2 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD2INPEN Pad 2 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD2PULL Pad 2 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD1RSEL Pad 1 pullup resistor selection. [15:14] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD1FNCSEL Pad 1 function select [13:11] read-write SLSDAWIR3 Configure as the IOSLAVE I2C SDA or SPI WIR3 signal 0 SLMOSI Configure as the IOSLAVE SPI MOSI signal 1 UART0TX Configure as the UART0 TX output signal 2 GPIO1 Configure as GPIO1 3 MSPI5 MSPI data connection 5 5 NCE1 IOM/MSPI nCE group 1 7 PAD1STRNG Pad 1 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD1INPEN Pad 1 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD1PULL Pad 1 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD0RSEL Pad 0 pullup resistor selection. [7:6] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD0FNCSEL Pad 0 function select [5:3] read-write SLSCL Configure as the IOSLAVE I2C SCL signal 0 SLSCK Configure as the IOSLAVE SPI SCK signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO0 Configure as GPIO0 3 MSPI4 MSPI data connection 4 5 NCE0 IOM/MSPI nCE group 0 7 PAD0STRNG Pad 0 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD0INPEN Pad 0 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD0PULL Pad 0 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGB Pad Configuration Register B (Pads 7-4) 0x00000004 32 read-write 0x18181818 0x3FFFFF3F PAD7FNCSEL Pad 7 function select [29:27] read-write NCE7 IOM/MSPI nCE group 7 0 M0MOSI Configure as the IOMSTR0 SPI MOSI signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO7 Configure as GPIO7 3 TRIG0 Configure as the ADC Trigger 0 signal 4 UART0TX Configure as the UART0 TX output signal 5 CT19 CTIMER connection 19 7 PAD7STRNG Pad 7 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD7INPEN Pad 7 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD7PULL Pad 7 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD6RSEL Pad 6 pullup resistor selection. [23:22] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD6FNCSEL Pad 6 function select [21:19] read-write M0SDAWIR3 Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal 0 M0MISO Configure as the IOMSTR0 SPI MISO signal 1 UA0CTS Configure as the UART0 CTS input signal 2 GPIO6 Configure as GPIO6 3 CT10 CTIMER connection 10 5 I2S_DAT Configure as the PDM I2S Data output signal 7 PAD6STRNG Pad 6 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD6INPEN Pad 6 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD6PULL Pad 6 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD5RSEL Pad 5 pullup resistor selection. [15:14] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD5FNCSEL Pad 5 function select [13:11] read-write M0SCL Configure as the IOMSTR0 I2C SCL signal 0 M0SCK Configure as the IOMSTR0 SPI SCK signal 1 UA0RTS Configure as the UART0 RTS signal output 2 GPIO5 Configure as GPIO5 3 EXTHFA Configure as the External HFA input clock 5 CT8 CTIMER connection 8 7 PAD5STRNG Pad 5 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD5INPEN Pad 5 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD5PULL Pad 5 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD4FNCSEL Pad 4 function select [5:3] read-write UA0CTS Configure as the UART0 CTS input signal 0 SLINT Configure as the IOSLAVE interrupt out signal 1 NCE4 IOM/SPI nCE group 4 2 GPIO4 Configure as GPIO4 3 UART0RX Configure as the UART0 RX input 5 CT17 CTIMER connection 17 6 MSPI2 MSPI data connection 2 7 PAD4STRNG Pad 4 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD4INPEN Pad 4 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD4PULL Pad 4 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGC Pad Configuration Register C (Pads 11-8) 0x00000008 32 read-write 0x18181818 0x3F3FFFFF PAD11FNCSEL Pad 11 function select [29:27] read-write ADCSE2 Configure as the analog input for ADC single ended input 2 0 NCE11 IOM/MSPI nCE group 11 1 CT31 CTIMER connection 31 2 GPIO11 Configure as GPIO11 3 SLINT Configure as the IOSLAVE interrupt out signal 4 UA1CTS Configure as the UART1 CTS input signal 5 UART0RX Configure as the UART0 RX input signal 6 PDM_DATA Configure as the PDM Data input signal 7 PAD11STRNG Pad 11 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD11INPEN Pad 11 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD11PULL Pad 11 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD10FNCSEL Pad 10 function select [21:19] read-write M1MOSI Configure as the IOMSTR1 SPI MOSI signal 1 NCE10 IOM/MSPI nCE group 10 2 GPIO10 Configure as GPIO10 3 PDMCLK PDM serial clock out 4 UA1RTS Configure as the UART1 RTS output signal 5 PAD10STRNG Pad 10 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD10INPEN Pad 10 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD10PULL Pad 10 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD9RSEL Pad 9 pullup resistor selection [15:14] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD9FNCSEL Pad 9 function select [13:11] read-write M1SDAWIR3 Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal 0 M1MISO Configure as the IOMSTR1 SPI MISO signal 1 NCE9 IOM/MSPI nCE group 9 2 GPIO9 Configure as GPIO9 3 SCCIO SCARD data I/O connection 4 UART1RX Configure as UART1 RX input signal 6 PAD9STRNG Pad 9 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD9INPEN Pad 9 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD9PULL Pad 9 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD8RSEL Pad 8 pullup resistor selection. [7:6] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD8FNCSEL Pad 8 function select [5:3] read-write M1SCL Configure as the IOMSTR1 I2C SCL signal 0 M1SCK Configure as the IOMSTR1 SPI SCK signal 1 NCE8 IOM/MSPI nCE group 8 2 GPIO8 Configure as GPIO8 3 SCCLK SCARD serial clock output 4 UART1TX Configure as the UART1 TX output signal 6 PAD8STRNG Pad 8 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD8INPEN Pad 8 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD8PULL Pad 8 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGD Pad Configuration Register D (Pads 15-12) 0x0000000C 32 read-write 0x18181818 0x3F3F3F3F PAD15FNCSEL Pad 15 function select [29:27] read-write ADCD1N Configure as the analog ADC differential pair 1 N input signal 0 NCE15 IOM/MSPI nCE group 15 1 UART1RX Configure as the UART1 RX signal 2 GPIO15 Configure as GPIO15 3 PDMDATA PDM serial data input 4 EXTXT Configure as the external XTAL oscillator input 5 SWDIO Configure as an alternate port for the SWDIO I/O signal 6 SWO Configure as an SWO (Serial Wire Trace output) 7 PAD15STRNG Pad 15 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD15INPEN Pad 15 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD15PULL Pad 15 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD14FNCSEL Pad 14 function select [21:19] read-write ADCD1P Configure as the analog ADC differential pair 1 P input signal 0 NCE14 IOM/MSPI nCE group 14 1 UART1TX Configure as the UART1 TX output signal 2 GPIO14 Configure as GPIO14 3 PDMCLK PDM serial clock output 4 EXTHFS Configure as the External HFRC oscillator input select 5 SWDCK Configure as the alternate input for the SWDCK input signal 6 32kHzXT Configure as the 32kHz crystal output signal 7 PAD14STRNG Pad 14 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD14INPEN Pad 14 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD14PULL Pad 14 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD13FNCSEL Pad 13 function select [13:11] read-write ADCD0PSE8 Configure as the ADC Differential pair 0 P, or Single Ended input 8 analog input signal. Determination of the D0P vs SE8 usage is done when the particular channel is selected within the ADC module 0 NCE13 IOM/MSPI nCE group 13 1 CT2 CTIMER connection 2 2 GPIO13 Configure as GPIO13 3 I2SBCLK I2C interface bit clock 4 EXTHFB Configure as the external HFRC oscillator input 5 UA0RTS Configure as the UART0 RTS signal output 6 UART1RX Configure as the UART1 RX input signal 7 PAD13STRNG Pad 13 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD13INPEN Pad 13 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD13PULL Pad 13 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD12FNCSEL Pad 12 function select [5:3] read-write ADCD0NSE9 Configure as the ADC Differential pair 0 N, or Single Ended input 9 analog input signal. Determination of the D0N vs SE9 usage is done when the particular channel is selected within the ADC module 0 NCE12 IOM/MSPI nCE group 12 1 CT0 CTIMER connection 0 2 GPIO12 Configure as GPIO12 3 PDMCLK PDM serial clock output 5 UA0CTS Configure as the UART0 CTS input signal 6 UART1TX Configure as the UART1 TX output signal 7 PAD12STRNG Pad 12 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD12INPEN Pad 12 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD12PULL Pad 12 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGE Pad Configuration Register E (Pads 19-16) 0x00000010 32 read-write 0x18181818 0x3F3F3F3F PAD19FNCSEL Pad 19 function select [29:27] read-write CMPRF0 Configure as the analog comparator reference 0 signal 0 NCE19 IOM/MSPI nCE group 19 1 CT6 CTIMER conenction 6 2 GPIO19 Configure as GPIO19 3 SCCLK SCARD serial clock 4 ANATEST1 Configure as the ANATEST1 I/O signal 5 UART1RX Configure as the UART1 RX input signal 6 I2SBCLK Configure as the PDM I2S bit clock input signal 7 PAD19STRNG Pad 19 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD19INPEN Pad 19 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD19PULL Pad 19 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD18FNCSEL Pad 18 function select [21:19] read-write CMPIN1 Configure as the analog comparator input 1 signal 0 NCE18 IOM/MSPI nCE group 18 1 CT4 CTIMER connection 4 2 GPIO18 Configure as GPIO18 3 UA0RTS Configure as UART0 RTS output signal 4 ANATEST2 Configure as ANATEST2 I/O signal 5 UART1TX Configure as UART1 TX output signal 6 SCCIO SCARD data input/output connectin 7 PAD18STRNG Pad 18 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD18INPEN Pad 18 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD18PULL Pad 18 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD17FNCSEL Pad 17 function select [13:11] read-write CMPRF1 Configure as the analog comparator reference signal 1 input signal 0 NCE17 IOM/MSPI nCE group 17 1 TRIG1 Configure as the ADC Trigger 1 signal 2 GPIO17 Configure as GPIO17 3 SCCCLK SCARD serial clock output 4 UART0RX Configure as UART0 RX input signal 6 UA1CTS Configure as UART1 CTS input signal 7 PAD17STRNG Pad 17 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD17INPEN Pad 17 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD17PULL Pad 17 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD16FNCSEL Pad 16 function select [5:3] read-write ADCSE0 Configure as the analog ADC single ended port 0 input signal 0 NCE16 IOM/MSPI nCE group 16 1 TRIG0 Configure as the ADC Trigger 0 signal 2 GPIO16 Configure as GPIO16 3 SCCRST SCARD reset output 4 CMPIN0 Configure as comparator input 0 signal 5 UART0TX Configure as UART0 TX output signal 6 UA1RTS Configure as UART1 RTS output signal 7 PAD16STRNG Pad 16 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD16INPEN Pad 16 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD16PULL Pad 16 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGF Pad Configuration Register F (Pads 23-20) 0x00000014 32 read-write 0x18180202 0x3F3F3F3F PAD23FNCSEL Pad 23 function select [29:27] read-write UART0RX Configure as the UART0 RX signal 0 NCE23 IOM/MSPI nCE group 23 1 CT14 CTIMER connection 14 2 GPIO23 Configure as GPIO23 3 I2SWCLK I2S word clock input 4 CMPOUT Configure as voltage comparitor output 5 MSPI3 MSPI data connection 3 6 EXTXT External XTAL osacillatgor input 7 PAD23STRNG Pad 23 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD23INPEN Pad 23 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD23PULL Pad 23 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD22FNCSEL Pad 22 function select [21:19] read-write UART0TX Configure as the UART0 TX signal 0 NCE22 IOM/MSPI nCE group 22 1 CT12 CTIMER connection 12 2 GPIO22 Configure as GPIO22 3 PDM_CLK Configure as the PDM CLK output 4 EXTLF External LFRC input 5 MSPI0 MSPI data connection 0 6 SWO Configure as the serial trace data output signal 7 PAD22STRNG Pad 22 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD22INPEN Pad 22 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD22PULL Pad 22 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD21FNCSEL Pad 21 function select [13:11] read-write SWDIO Configure as the serial wire debug data signal 0 NCE21 IOM/MSPI nCE group 21 1 GPIO21 Configure as GPIO21 3 UART0RX Configure as UART0 RX input signal 4 UART1RX Configure as UART1 RX input signal 5 I2SBCLK I2S byte clock input 6 UA1CTS Configure as UART1 CTS input signal 7 PAD21STRNG Pad 21 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD21INPEN Pad 21 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD21PULL Pad 21 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD20FNCSEL Pad 20 function select [5:3] read-write SWDCK Configure as the serial wire debug clock signal 0 NCE20 IOM/MSPI nCE group 20 1 GPIO20 Configure as GPIO20 3 UART0TX Configure as UART0 TX output signal 4 UART1TX Configure as UART1 TX output signal 5 I2SBCLK I2S byte clock input 6 UA1RTS Configure as UART1 RTS output signal 7 PAD20STRNG Pad 20 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD20INPEN Pad 20 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD20PULL Pad 20 pulldown enable [0:0] read-write DIS Pulldown disabled 0 EN Pulldown enabled 1 PADREGG Pad Configuration Register G (Pads 27-24) 0x00000018 32 read-write 0x18181818 0xFF3FFF3F PAD27RSEL Pad 27 pullup resistor selection. [31:30] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD27FNCSEL Pad 27 function select [29:27] read-write UART0RX Configure as UART0 RX input signal 0 NCE27 IOM/MSPI nCE group 27 1 CT5 CTIMER connection 5 2 GPIO27 Configure as GPIO27 3 M2SCL Configure as I2C clock I/O signal from IOMSTR2 4 M2SCK Configure as SPI clock output signal from IOMSTR2 5 PAD27STRNG Pad 27 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD27INPEN Pad 27 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD27PULL Pad 27 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD26FNCSEL Pad 26 function select [21:19] read-write EXTHF Configure as the external HFRC oscillator input 0 NCE26 IOM/MSPI nCE group 26 1 CT3 CTIMER connection 3 2 GPIO26 Configure as GPIO26 3 SCCRST SCARD reset output 4 MSPI1 MSPI data connection 1 5 UART0TX Configure as UART0 TX output signal 6 UA1CTS Configure as UART1 CTS input signal 7 PAD26STRNG Pad 26 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD26INPEN Pad 26 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD26PULL Pad 26 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD25RSEL Pad 25 pullup resistor selection. [15:14] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD25FNCSEL Pad 25 function select [13:11] read-write UART1RX Configure as UART1 RX input signal 0 NCE25 IOM/MSPI nCE group 25 1 CT1 CTIMER connection 1 2 GPIO25 Configure as GPIO25 3 M2SDAWIR3 Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal 4 M2MISO Configure as the IOMSTR2 SPI MISO input signal 5 PAD25STRNG Pad 25 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD25INPEN Pad 25 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD25PULL Pad 25 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD24FNCSEL Pad 24 function select [5:3] read-write UART1TX Configure as UART1 TX output signal 0 NCE24 IOM/MSPI nCE group 24 1 MSPI8 MSPI data connection 8 2 GPIO24 Configure as GPIO24 3 UA0CTS Configure as UART0 CTS input signal 4 CT21 CTIMER connection 21 5 32kHzXT Configure as the 32kHz crystal output signal 6 SWO Configure as the serial trace data output signal 7 PAD24STRNG Pad 24 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD24INPEN Pad 24 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD24PULL Pad 24 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGH Pad Configuration Register H (Pads 31-28) 0x0000001C 32 read-write 0x18181818 0x3F3F3F3F PAD31FNCSEL Pad 31 function select [29:27] read-write ADCSE3 Configure as the analog input for ADC single ended input 3 0 NCE31 IOM/MSPI nCE group 31 1 CT13 CTIMER connection 13 2 GPIO31 Configure as GPIO31 3 UART0RX Configure as the UART0 RX input signal 4 SCCCLK SCARD serial clock output 5 UA1RTS Configure as UART1 RTS output signal 7 PAD31STRNG Pad 31 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD31INPEN Pad 31 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD31PULL Pad 31 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD30FNCSEL Pad 30 function select [21:19] read-write ANATEST1 Configure as the ANATEST1 I/O signal 0 NCE30 IOM/MSPI nCE group 30 1 CT11 CTIMER connection 11 2 GPIO30 Configure as GPIO30 3 UART0TX Configure as UART0 TX output signal 4 UA1RTS Configure as UART1 RTS output signal 5 I2S_DAT Configure as the PDM I2S Data output signal 7 PAD30STRNG Pad 30 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD30INPEN Pad 30 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD30PULL Pad 30 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD29FNCSEL Pad 29 function select [13:11] read-write ADCSE1 Configure as the analog input for ADC single ended input 1 0 NCE29 IOM/MSPI nCE group 29 1 CT9 CTIMER connection 9 2 GPIO29 Configure as GPIO29 3 UA0CTS Configure as the UART0 CTS input signal 4 UA1CTS Configure as the UART1 CTS input signal 5 UART0RX Configure as the UART0 RX input signal 6 PDM_DATA Configure as PDM DATA input 7 PAD29STRNG Pad 29 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD29INPEN Pad 29 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD29PULL Pad 29 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD28FNCSEL Pad 28 function select [5:3] read-write I2S_WCLK Configure as the PDM I2S Word Clock input 0 NCE28 IOM/MSPI nCE group 28 1 CT7 CTIMER connection 7 2 GPIO28 Configure as GPIO28 3 M2MOSI Configure as the IOMSTR2 SPI MOSI output signal 5 UART0TX Configure as the UART0 TX output signal 6 PAD28STRNG Pad 28 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD28INPEN Pad 28 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD28PULL Pad 28 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGI Pad Configuration Register I (Pads 35-32) 0x00000020 32 read-write 0x18181818 0x3F3F3F3F PAD35FNCSEL Pad 35 function select [29:27] read-write ADCSE7 Configure as the analog input for ADC single ended input 7 0 NCE35 IOM/MSPI nCE group 35 1 UART1TX Configure as the UART1 TX signal 2 GPIO35 Configure as GPIO35 3 I2SDAT I2S serial data output 4 CT27 CTIMER connection 27 5 UA0RTS Configure as the UART0 RTS output 6 PAD35STRNG Pad 35 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD35INPEN Pad 35 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD35PULL Pad 35 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD34FNCSEL Pad 34 function select [21:19] read-write ADCSE6 Configure as the analog input for ADC single ended input 6 0 NCE34 IOM/MSPI nCE group 34 1 UA1RTS Configure as the UART1 RTS output 2 GPIO34 Configure as GPIO34 3 CMPRF2 Configure as the analog comparator reference 2 signal 4 UA0RTS Configure as the UART0 RTS output 5 UART0RX Configure as the UART0 RX input 6 PDMDATA PDM serial data input 7 PAD34STRNG Pad 34 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD34INPEN Pad 34 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD34PULL Pad 34 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD33FNCSEL Pad 33 function select [13:11] read-write ADCSE5 Configure as the analog ADC single ended port 5 input signal 0 NCE33 IOM/MSPI nCE group 33 1 32kHzXT Configure as the 32kHz crystal output signal 2 GPIO33 Configure as GPIO33 3 UA0CTS Configure as the UART0 CTS input 5 CT23 CTIMER connection 23 6 SWO Configure as the serial trace data output signal 7 PAD33STRNG Pad 33 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD33INPEN Pad 33 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD33PULL Pad 33 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD32FNCSEL Pad 32 function select [5:3] read-write ADCSE4 Configure as the analog input for ADC single ended input 4 0 NCE32 IOM/MSPI nCE group 32 1 CT15 CTIMER connection 15 2 GPIO32 Configure as GPIO32 3 SCCIO SCARD serial data input/output 4 EXTLF External input to the LFRC oscillator 5 UA1CTS Configure as the UART1 CTS input 7 PAD32STRNG Pad 32 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD32INPEN Pad 32 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD32PULL Pad 32 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGJ Pad Configuration Register J (Pads 39-36) 0x00000024 32 read-write 0x18181818 0xFF3FBF7F PAD39RSEL Pad 39 pullup resistor selection. [31:30] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD39FNCSEL Pad 39 function select [29:27] read-write UART0TX Configure as the UART0 TX output signal 0 UART1TX Configure as the UART1 TX output signal 1 CT25 CTIMER connection 25 2 GPIO39 Configure as GPIO39 3 M4SCL Configure as the IOMSTR4 I2C SCL signal 4 M4SCK Configure as the IOMSTR4 SPI SCK signal 5 PAD39STRNG Pad 39 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD39INPEN Pad 39 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD39PULL Pad 39 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD38FNCSEL Pad 38 function select [21:19] read-write TRIG3 Configure as the ADC Trigger 3 signal 0 NCE38 IOM/MSPI nCE group 38 1 UA0CTS Configure as the UART0 CTS signal 2 GPIO38 Configure as GPIO38 3 M3MOSI Configure as the IOMSTR3 SPI MOSI output signal 5 UART1RX Configure as the UART1 RX input signal 6 PAD38STRNG Pad 38 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD38INPEN Pad 38 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD38PULL Pad 38 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD37PWRDN Pad 37 VSS power switch enable [15:15] read-write DIS Power switch disabled 0 EN Power switch enabled (switch to GND) 1 PAD37FNCSEL Pad 37 function select [13:11] read-write TRIG2 Configure as the ADC Trigger 2 signal 0 NCE37 IOM/MSPI nCE group 37 1 UA0RTS Configure as the UART0 RTS output signal 2 GPIO37 Configure as GPIO37 3 SCCIO SCARD serial data input/output 4 UART1TX Configure as the UART1 TX output signal 5 PDMCLK Configure as the PDM CLK output signal 6 CT29 CTIMER connection 29 7 PAD37STRNG Pad 37 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD37INPEN Pad 37 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD37PULL Pad 37 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD36PWRUP Pad 36 VDD power switch enable [6:6] read-write DIS Power switch disabled 0 EN Power switch enabled (switched to VDD) 1 PAD36FNCSEL Pad 36 function select [5:3] read-write TRIG1 Configure as the ADC Trigger 1 signal 0 NCE36 IOM/MSPI nCE group 36 1 UART1RX Configure as the UART1 RX input signal 2 GPIO36 Configure as GPIO36 3 32kHzXT Configure as the 32kHz output clock from the crystal 4 UA1CTS Configure as the UART1 CTS input signal 5 UA0CTS Configure as the UART0 CTS input signal 6 PDMDATA PDM serial data input 7 PAD36STRNG Pad 36 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD36INPEN Pad 36 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD36PULL Pad 36 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGK Pad Configuration Register K (Pads 43-40) 0x00000028 32 read-write 0x18181818 0xFFFFBFFF PAD43RSEL Pad 43 pullup resistor selection. [31:30] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD43FNCSEL Pad 43 function select [29:27] read-write UART1RX Configure as the UART1 RX input signal 0 NCE43 IOM/MSPI nCE group 43 1 CT18 CTIMER connection 18 2 GPIO43 Configure as GPIO43 3 M3SDAWIR3 Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal 4 M3MISO Configure as the IOMSTR3 SPI MISO signal 5 PAD43STRNG Pad 43 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD43INPEN Pad 43 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD43PULL Pad 43 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD42RSEL Pad 42 pullup resistor selection. [23:22] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD42FNCSEL Pad 42 function select [21:19] read-write UART1TX Configure as the UART1 TX output signal 0 NCE42 IOM/MSPI nCE group 42 1 CT16 CTIMER connection 16 2 GPIO42 Configure as GPIO42 3 M3SCL Configure as the IOMSTR3 I2C SCL clock I/O signal 4 M3SCK Configure as the IOMSTR3 SPI SCK output 5 PAD42STRNG Pad 42 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD42INPEN Pad 42 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD42PULL Pad 42 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD41PWRDN Pad 41 power switch enable [15:15] read-write DIS Power switch disabled 0 EN Power switch enabled (Switch pad to VSS) 1 PAD41FNCSEL Pad 41 function select [13:11] read-write NCE41 IOM/MSPI nCE group 41 0 SWO Configure as the serial wire debug SWO signal 2 GPIO41 Configure as GPIO41 3 I2SWCLK I2S word clock input 4 UA1RTS Configure as the UART1 RTS output signal 5 UART0TX Configure as the UART0 TX output signal 6 UA0RTS Configure as the UART0 RTS output signal 7 PAD41STRNG Pad 41 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD41INPEN Pad 41 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD41PULL Pad 41 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD40RSEL Pad 40 pullup resistor selection. [7:6] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD40FNCSEL Pad 40 function select [5:3] read-write UART0RX Configure as the UART0 RX input signal 0 UART1RX Configure as the UART1 RX input signal 1 TRIG0 Configure as the ADC Trigger 0 signal 2 GPIO40 Configure as GPIO40 3 M4SDAWIR3 Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal 4 M4MISO Configure as the IOMSTR4 SPI MISO input signal 5 PAD40STRNG Pad 40 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD40INPEN Pad 40 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD40PULL Pad 40 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGL Pad Configuration Register L (Pads 47-44) 0x0000002C 32 read-write 0x18181818 0x3F3F3F3F PAD47FNCSEL Pad 47 function select [29:27] read-write 32kHzXT Configure as the 32kHz output clock from the crystal 0 NCE47 IOM/MSPI nCE group 47 1 CT26 CTIMER connection 26 2 GPIO47 Configure as GPIO47 3 M5MOSI Configure as the IOMSTR5 SPI MOSI output signal 5 UART1RX Configure as the UART1 RX input signal 6 PAD47STRNG Pad 47 drive strength [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD47INPEN Pad 47 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD47PULL Pad 47 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD46FNCSEL Pad 46 function select [21:19] read-write 32khz_XT Configure as the 32kHz output clock from the crystal 0 NCE46 IOM/MSPI nCE group 46 1 CT24 CTIMER connection 24 2 GPIO46 Configure as GPIO46 3 SCCRST SCARD reset output 4 PDMCLK PDM serial clock output 5 UART1TX Configure as the UART1 TX output signal 6 SWO Configure as the serial wire debug SWO signal 7 PAD46STRNG Pad 46 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD46INPEN Pad 46 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD46PULL Pad 46 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD45FNCSEL Pad 45 function select [13:11] read-write UA1CTS Configure as the UART1 CTS input signal 0 NCE45 IOM/MSPI nCE group 45 1 CT22 CTIMER connection 22 2 GPIO45 Configure as GPIO45 3 I2SDAT I2S serial data output 4 PDMDATA PDM serial data input 5 UART0RX Configure as the SPI channel 5 nCE signal from IOMSTR5 6 SWO Configure as the serial wire debug SWO signal 7 PAD45STRNG Pad 45 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD45INPEN Pad 45 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD45PULL Pad 45 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD44FNCSEL Pad 44 function select [5:3] read-write UA1RTS Configure as the UART1 RTS output signal 0 NCE44 IOM/MSPI nCE group 44 1 CT20 CTIMER connection 20 2 GPIO44 Configure as GPIO44 3 M4MOSI Configure as the IOMSTR4 SPI MOSI signal 5 M5nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR5 6 PAD44STRNG Pad 44 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD44INPEN Pad 44 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD44PULL Pad 44 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGM Pad Configuration Register M (Pads 49-48) 0x00000030 32 read-write 0x00001818 0x0000FFFF PAD49RSEL Pad 49 pullup resistor selection. [15:14] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD49FNCSEL Pad 49 function select [13:11] read-write UART0RX Configure as the UART0 RX input signal 0 NCE49 IOM/MSPPI nCE group 49 1 CT30 CTIMER connection 30 2 GPIO49 Configure as GPIO49 3 M5SDAWIR3 Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal 4 M5MISO Configure as the IOMSTR5 SPI MISO input signal 5 PAD49STRNG Pad 49 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD49INPEN Pad 49 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD49PULL Pad 49 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD48RSEL Pad 48 pullup resistor selection. [7:6] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD48FNCSEL Pad 48 function select [5:3] read-write UART0TX Configure as the UART0 TX output signal 0 NCE48 IOM/MSPI nCE group 48 1 CT28 CTIMER conenction 28 2 GPIO48 Configure as GPIO48 3 M5SCL Configure as the IOMSTR5 I2C SCL clock I/O signal 4 M5SCK Configure as the IOMSTR5 SPI SCK output 5 PAD48STRNG Pad 48 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD48INPEN Pad 48 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD48PULL Pad 48 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 CFGA GPIO Configuration Register A (Pads 7-0) 0x00000040 32 read-write 0x00000000 0xFFFFFFFF GPIO7INTD GPIO7 interrupt direction, nCE polarity. [31:31] read-write nCELOW FNCSEL = 0x0 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x0 - nCE polarity active high 1 GPIO7OUTCFG GPIO7 output configuration. [30:29] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO7INCFG GPIO7 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO6INTD GPIO6 interrupt direction. [27:27] read-write INTDIS INCFG = 1 - No interrupt on GPIO transition 0 INTBOTH INCFG = 1 - Interrupt on either low to high or high to low GPIO transition 1 GPIO6OUTCFG GPIO6 output configuration. [26:25] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO6INCFG GPIO6 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO5INTD GPIO5 interrupt direction. [23:23] read-write INTDIS INCFG = 1 - No interrupt on GPIO transition 0 INTBOTH INCFG = 1 - Interrupt on either low to high or high to low GPIO transition 1 GPIO5OUTCFG GPIO5 output configuration. [22:21] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO5INCFG GPIO5 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO4INTD GPIO4 interrupt direction. [19:19] read-write nCELOW FNCSEL = 0x2 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x2 - nCE polarity active high 1 GPIO4OUTCFG GPIO4 output configuration. [18:17] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO4INCFG GPIO4 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO3INTD GPIO3 interrupt direction. [15:15] read-write nCELOW FNCSEL = 0x2 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x2 - nCE polarity active high 1 GPIO3OUTCFG GPIO3 output configuration. [14:13] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO3INCFG GPIO3 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO2INTD GPIO2 interrupt direction. [11:11] read-write nCELOW FNCSEL = 0x7 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x7 - nCE polarity active high 1 GPIO2OUTCFG GPIO2 output configuration. [10:9] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO2INCFG GPIO2 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO1INTD GPIO1 interrupt direction. [7:7] read-write nCELOW FNCSEL = 0x7 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x7 - nCE polarity active high 1 GPIO1OUTCFG GPIO1 output configuration. [6:5] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO1INCFG GPIO1 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO0INTD GPIO0 interrupt direction. [3:3] read-write nCELOW FNCSEL = 0x7 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x7 - nCE polarity active high 1 GPIO0OUTCFG GPIO0 output configuration. [2:1] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO0INCFG GPIO0 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 CFGB GPIO Configuration Register B (Pads 15-8) 0x00000044 32 read-write 0x00000000 0xFFFFFFFF GPIO15INTD GPIO15 interrupt direction. [31:31] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO15OUTCFG GPIO15 output configuration. [30:29] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO15INCFG GPIO15 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO14INTD GPIO14 interrupt direction. [27:27] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO14OUTCFG GPIO14 output configuration. [26:25] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO14INCFG GPIO14 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO13INTD GPIO13 interrupt direction. [23:23] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO13OUTCFG GPIO13 output configuration. [22:21] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO13INCFG GPIO13 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO12INTD GPIO12 interrupt direction. [19:19] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO12OUTCFG GPIO12 output configuration. [18:17] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO12INCFG GPIO12 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO11INTD GPIO11 interrupt direction. [15:15] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO11OUTCFG GPIO11 output configuration. [14:13] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO11INCFG GPIO11 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO10INTD GPIO10 interrupt direction. [11:11] read-write nCELOW FNCSEL = 0x2 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x2 - nCE polarity active high 1 GPIO10OUTCFG GPIO10 output configuration. [10:9] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO10INCFG GPIO10 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO9INTD GPIO9 interrupt direction. [7:7] read-write nCELOW FNCSEL = 0x2 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x2 - nCE polarity active high 1 GPIO9OUTCFG GPIO9 output configuration. [6:5] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO9INCFG GPIO9 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO8INTD GPIO8 interrupt direction. [3:3] read-write nCELOW FNCSEL = 0x2 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x2 - nCE polarity active high 1 GPIO8OUTCFG GPIO8 output configuration. [2:1] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO8INCFG GPIO8 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 CFGC GPIO Configuration Register C (Pads 23-16) 0x00000048 32 read-write 0x00110000 0xFFFFFFFF GPIO23INTD GPIO23 interrupt direction. [31:31] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO23OUTCFG GPIO23 output configuration. [30:29] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO23INCFG GPIO23 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO22INTD GPIO22 interrupt direction. [27:27] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO22OUTCFG GPIO22 output configuration. [26:25] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO22INCFG GPIO22 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO21INTD GPIO21 interrupt direction. [23:23] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO21OUTCFG GPIO21 output configuration. [22:21] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO21INCFG GPIO21 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO20INTD GPIO20 interrupt direction. [19:19] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO20OUTCFG GPIO20 output configuration. [18:17] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO20INCFG GPIO20 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO19INTD GPIO19 interrupt direction. [15:15] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO19OUTCFG GPIO19 output configuration. [14:13] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO19INCFG GPIO19 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO18INTD GPIO18 interrupt direction. [11:11] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO18OUTCFG GPIO18 output configuration. [10:9] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO18INCFG GPIO18 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO17INTD GPIO17 interrupt direction. [7:7] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO17OUTCFG GPIO17 output configuration. [6:5] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO17INCFG GPIO17 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO16INTD GPIO16 interrupt direction. [3:3] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO16OUTCFG GPIO16 output configuration. [2:1] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO16INCFG GPIO16 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 CFGD GPIO Configuration Register D (Pads 31-24) 0x0000004C 32 read-write 0x00000000 0xFFFFFFFF GPIO31INTD GPIO31 interrupt direction. [31:31] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO31OUTCFG GPIO31 output configuration. [30:29] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO31INCFG GPIO31 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO30INTD GPIO30 interrupt direction. [27:27] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO30OUTCFG GPIO30 output configuration. [26:25] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO30INCFG GPIO30 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO29INTD GPIO29 interrupt direction. [23:23] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO29OUTCFG GPIO29 output configuration. [22:21] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO29INCFG GPIO29 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO28INTD GPIO28 interrupt direction. [19:19] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO28OUTCFG GPIO28 output configuration. [18:17] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO28INCFG GPIO28 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO27INTD GPIO27 interrupt direction. [15:15] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO27OUTCFG GPIO27 output configuration. [14:13] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO27INCFG GPIO27 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO26INTD GPIO26 interrupt direction. [11:11] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO26OUTCFG GPIO26 output configuration. [10:9] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO26INCFG GPIO26 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO25INTD GPIO25 interrupt direction. [7:7] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO25OUTCFG GPIO25 output configuration. [6:5] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO25INCFG GPIO25 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO24INTD GPIO24 interrupt direction. [3:3] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO24OUTCFG GPIO24 output configuration. [2:1] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO24INCFG GPIO24 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 CFGE GPIO Configuration Register E (Pads 39-32) 0x00000050 32 read-write 0x00000000 0xFFFFFFFF GPIO39INTD GPIO39 interrupt direction. [31:31] read-write INTDIS INCFG = 1 - No interrupt on GPIO transition 0 INTBOTH INCFG = 1 - Interrupt on either low to high or high to low GPIO transition 1 GPIO39OUTCFG GPIO39 output configuration. [30:29] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO39INCFG GPIO39 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO38INTD GPIO38 interrupt direction. [27:27] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO38OUTCFG GPIO38 output configuration. [26:25] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO38INCFG GPIO38 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO37INTD GPIO37 interrupt direction. [23:23] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO37OUTCFG GPIO37 output configuration. [22:21] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO37INCFG GPIO37 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO36INTD GPIO36 interrupt direction. [19:19] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO36OUTCFG GPIO36 output configuration. [18:17] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO36INCFG GPIO36 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO35INTD GPIO35 interrupt direction. [15:15] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO35OUTCFG GPIO35 output configuration. [14:13] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO35INCFG GPIO35 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO34INTD GPIO34 interrupt direction. [11:11] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO34OUTCFG GPIO34 output configuration. [10:9] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO34INCFG GPIO34 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO33INTD GPIO33 interrupt direction. [7:7] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO33OUTCFG GPIO33 output configuration. [6:5] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO33INCFG GPIO33 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO32INTD GPIO32 interrupt direction. [3:3] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO32OUTCFG GPIO32 output configuration. [2:1] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO32INCFG GPIO32 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 CFGF GPIO Configuration Register F (Pads 47-40) 0x00000054 32 read-write 0x00000000 0xFFFFFFFF GPIO47INTD GPIO47 interrupt direction. [31:31] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO47OUTCFG GPIO47 output configuration. [30:29] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO47INCFG GPIO47 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO46INTD GPIO46 interrupt direction. [27:27] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO46OUTCFG GPIO46 output configuration. [26:25] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO46INCFG GPIO46 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO45INTD GPIO45 interrupt direction. [23:23] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO45OUTCFG GPIO45 output configuration. [22:21] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO45INCFG GPIO45 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO44INTD GPIO44 interrupt direction. [19:19] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO44OUTCFG GPIO44 output configuration. [18:17] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO44INCFG GPIO44 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO43INTD GPIO43 interrupt direction. [15:15] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO43OUTCFG GPIO43 output configuration. [14:13] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO43INCFG GPIO43 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO42INTD GPIO42 interrupt direction. [11:11] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO42OUTCFG GPIO42 output configuration. [10:9] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO42INCFG GPIO42 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO41INTD GPIO41 interrupt direction. [7:7] read-write nCELOW FNCSEL = 0x0 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x0 - nCE polarity active high 1 GPIO41OUTCFG GPIO41 output configuration. [6:5] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO41INCFG GPIO41 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO40INTD GPIO40 interrupt direction. [3:3] read-write INTDIS INCFG = 1 - No interrupt on GPIO transition 0 INTBOTH INCFG = 1 - Interrupt on either low to high or high to low GPIO transition 1 GPIO40OUTCFG GPIO40 output configuration. [2:1] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO40INCFG GPIO40 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 CFGG GPIO Configuration Register G (Pads 49-48) 0x00000058 32 read-write 0x00000000 0x000000FF GPIO49INTD GPIO49 interrupt direction. [7:7] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO49OUTCFG GPIO49 output configuration. [6:5] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO49INCFG GPIO49 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 GPIO48INTD GPIO48 interrupt direction. [3:3] read-write nCELOW FNCSEL = 0x1 - nCE polarity active low 0 nCEHIGH FNCSEL = 0x1 - nCE polarity active high 1 GPIO48OUTCFG GPIO48 output configuration. [2:1] read-write DIS FNCSEL = 0x3 - Output disabled 0 PUSHPULL FNCSEL = 0x3 - Output is push-pull 1 OD FNCSEL = 0x3 - Output is open drain 2 TS FNCSEL = 0x3 - Output is tri-state 3 GPIO48INCFG GPIO48 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO INTD = 0 - Readback will always be zero 1 PADKEY Key Register for all pad configuration registers 0x00000060 32 read-write 0x00000000 0xFFFFFFFF PADKEY Key register value. [31:0] read-write Key Key 115 RDA GPIO Input Register A 0x00000080 32 read-write 0x00000000 0xFFFFFFFF RDA GPIO31-0 read data. [31:0] read-write RDB GPIO Input Register B 0x00000084 32 read-write 0x00000000 0x0003FFFF RDB GPIO49-32 read data. [17:0] read-write WTA GPIO Output Register A 0x00000088 32 read-write 0x00000000 0xFFFFFFFF WTA GPIO31-0 write data. [31:0] read-write WTB GPIO Output Register B 0x0000008C 32 read-write 0x00000000 0x0003FFFF WTB GPIO49-32 write data. [17:0] read-write WTSA GPIO Output Register A Set 0x00000090 32 read-write 0x00000000 0xFFFFFFFF WTSA Set the GPIO31-0 write data. [31:0] read-write WTSB GPIO Output Register B Set 0x00000094 32 read-write 0x00000000 0x0003FFFF WTSB Set the GPIO49-32 write data. [17:0] read-write WTCA GPIO Output Register A Clear 0x00000098 32 read-write 0x00000000 0xFFFFFFFF WTCA Clear the GPIO31-0 write data. [31:0] read-write WTCB GPIO Output Register B Clear 0x0000009C 32 read-write 0x00000000 0x0003FFFF WTCB Clear the GPIO49-32 write data. [17:0] read-write ENA GPIO Enable Register A 0x000000A0 32 read-write 0x00000000 0xFFFFFFFF ENA GPIO31-0 output enables [31:0] read-write ENB GPIO Enable Register B 0x000000A4 32 read-write 0x00000000 0x0003FFFF ENB GPIO49-32 output enables [17:0] read-write ENSA GPIO Enable Register A Set 0x000000A8 32 read-write 0x00000000 0xFFFFFFFF ENSA Set the GPIO31-0 output enables [31:0] read-write ENSB GPIO Enable Register B Set 0x000000AC 32 read-write 0x00000000 0x0003FFFF ENSB Set the GPIO49-32 output enables [17:0] read-write ENCA GPIO Enable Register A Clear 0x000000B4 32 read-write 0x00000000 0xFFFFFFFF ENCA Clear the GPIO31-0 output enables [31:0] read-write ENCB GPIO Enable Register B Clear 0x000000B8 32 read-write 0x00000000 0x0003FFFF ENCB Clear the GPIO49-32 output enables [17:0] read-write STMRCAP STIMER Capture Control 0x000000BC 32 read-write 0x3F3F3F3F 0x7F7F7F7F STPOL3 STIMER Capture 3 Polarity. [30:30] read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STSEL3 STIMER Capture 3 Select. [29:24] read-write STPOL2 STIMER Capture 2 Polarity. [22:22] read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STSEL2 STIMER Capture 2 Select. [21:16] read-write STPOL1 STIMER Capture 1 Polarity. [14:14] read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STSEL1 STIMER Capture 1 Select. [13:8] read-write STPOL0 STIMER Capture 0 Polarity. [6:6] read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STSEL0 STIMER Capture 0 Select. [5:0] read-write IOM0IRQ IOM0 Flow Control IRQ Select 0x000000C0 32 read-write 0x0000003F 0x0000003F IOM0IRQ IOMSTR0 IRQ pad select. [5:0] read-write IOM1IRQ IOM1 Flow Control IRQ Select 0x000000C4 32 read-write 0x0000003F 0x0000003F IOM1IRQ IOMSTR1 IRQ pad select. [5:0] read-write IOM2IRQ IOM2 Flow Control IRQ Select 0x000000C8 32 read-write 0x0000003F 0x0000003F IOM2IRQ IOMSTR2 IRQ pad select. [5:0] read-write IOM3IRQ IOM3 Flow Control IRQ Select 0x000000CC 32 read-write 0x0000003F 0x0000003F IOM3IRQ IOMSTR3 IRQ pad select. [5:0] read-write IOM4IRQ IOM4 Flow Control IRQ Select 0x000000D0 32 read-write 0x0000003F 0x0000003F IOM4IRQ IOMSTR4 IRQ pad select. [5:0] read-write IOM5IRQ IOM5 Flow Control IRQ Select 0x000000D4 32 read-write 0x0000003F 0x0000003F IOM5IRQ IOMSTR5 IRQ pad select. [5:0] read-write BLEIFIRQ BLEIF Flow Control IRQ Select 0x000000D8 32 read-write 0x0000003F 0x0000003F BLEIFIRQ BLEIF IRQ pad select. [5:0] read-write GPIOOBS GPIO Observation Mode Sample register 0x000000DC 32 read-write 0x00000000 0x0000FFFF OBS_DATA Sample of the data output on the GPIO observation port. May have async sampling issues, as the data is not synronized to the read operation. Intended for debug purposes only [15:0] read-write ALTPADCFGA Alternate Pad Configuration reg0 (Pads 0-3) 0x000000E0 32 read-write 0x00000000 0x11111111 PAD3_SR Pad 3 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD3_DS1 Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength. [24:24] read-write PAD2_SR Pad 2 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD2_DS1 Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength. [16:16] read-write PAD1_SR Pad 1 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD1_DS1 Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength. [8:8] read-write PAD0_SR Pad 0 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD0_DS1 Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGB Alternate Pad Configuration reg1 (Pads 4-7) 0x000000E4 32 read-write 0x00000000 0x11111111 PAD7_SR Pad 7 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD7_DS1 Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength. [24:24] read-write PAD6_SR Pad 6 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD6_DS1 Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength. [16:16] read-write PAD5_SR Pad 5 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD5_DS1 Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength. [8:8] read-write PAD4_SR Pad 4 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD4_DS1 Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGC Alternate Pad Configuration reg2 (Pads 8-11) 0x000000E8 32 read-write 0x00000000 0x11111111 PAD11_SR Pad 11 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD11_DS1 Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength. [24:24] read-write PAD10_SR Pad 10 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD10_DS1 Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength. [16:16] read-write PAD9_SR Pad 9 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD9_DS1 Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength. [8:8] read-write PAD8_SR Pad 8 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD8_DS1 Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGD Alternate Pad Configuration reg3 (Pads 12-15) 0x000000EC 32 read-write 0x00000000 0x11111111 PAD15_SR Pad 15 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD15_DS1 Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength. [24:24] read-write PAD14_SR Pad 14 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD14_DS1 Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength. [16:16] read-write PAD13_SR Pad 13 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD13_DS1 Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength. [8:8] read-write PAD12_SR Pad 12 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD12_DS1 Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGE Alternate Pad Configuration reg4 (Pads 16-19) 0x000000F0 32 read-write 0x00000000 0x11111111 PAD19_SR Pad 19 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD19_DS1 Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength. [24:24] read-write PAD18_SR Pad 18 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD18_DS1 Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength. [16:16] read-write PAD17_SR Pad 17 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD17_DS1 Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength. [8:8] read-write PAD16_SR Pad 16 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD16_DS1 Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGF Alternate Pad Configuration reg5 (Pads 20-23) 0x000000F4 32 read-write 0x00000000 0x11111111 PAD23_SR Pad 23 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD23_DS1 Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength. [24:24] read-write PAD22_SR Pad 22 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD22_DS1 Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength. [16:16] read-write PAD21_SR Pad 21 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD21_DS1 Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength. [8:8] read-write PAD20_SR Pad 20 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD20_DS1 Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGG Alternate Pad Configuration reg6 (Pads 24-27) 0x000000F8 32 read-write 0x00000000 0x11111111 PAD27_SR Pad 27 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD27_DS1 Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength. [24:24] read-write PAD26_SR Pad 26 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD26_DS1 Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength. [16:16] read-write PAD25_SR Pad 25 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD25_DS1 Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength. [8:8] read-write PAD24_SR Pad 24 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD24_DS1 Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGH Alternate Pad Configuration reg7 (Pads 28-31) 0x000000FC 32 read-write 0x00000000 0x11111111 PAD31_SR Pad 31 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD31_DS1 Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength. [24:24] read-write PAD30_SR Pad 30 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD30_DS1 Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength. [16:16] read-write PAD29_SR Pad 29 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD29_DS1 Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength. [8:8] read-write PAD28_SR Pad 28 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD28_DS1 Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGI Alternate Pad Configuration reg8 (Pads 32-35) 0x00000100 32 read-write 0x00000000 0x11111111 PAD35_SR Pad 35 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD35_DS1 Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength. [24:24] read-write PAD34_SR Pad 34 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD34_DS1 Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength. [16:16] read-write PAD33_SR Pad 33 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD33_DS1 Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength. [8:8] read-write PAD32_SR Pad 32 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD32_DS1 Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGJ Alternate Pad Configuration reg9 (Pads 36-39) 0x00000104 32 read-write 0x00000000 0x11111111 PAD39_SR Pad 39 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD39_DS1 Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength. [24:24] read-write PAD38_SR Pad 38 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD38_DS1 Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength. [16:16] read-write PAD37_SR Pad 37 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD37_DS1 Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength. [8:8] read-write PAD36_SR Pad 36 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD36_DS1 Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGK Alternate Pad Configuration reg10 (Pads 40-43) 0x00000108 32 read-write 0x00000000 0x11111111 PAD43_SR Pad 43 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD43_DS1 Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength. [24:24] read-write PAD42_SR Pad 42 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD42_DS1 Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength. [16:16] read-write PAD41_SR Pad 41 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD41_DS1 Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength. [8:8] read-write PAD40_SR Pad 40 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD40_DS1 Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGL Alternate Pad Configuration reg11 (Pads 44-47) 0x0000010C 32 read-write 0x00000000 0x11111111 PAD47_SR Pad 47 slew rate selection. [28:28] read-write SR_EN Enables Slew rate control on pad 1 PAD47_DS1 Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength. [24:24] read-write PAD46_SR Pad 46 slew rate selection. [20:20] read-write SR_EN Enables Slew rate control on pad 1 PAD46_DS1 Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength. [16:16] read-write PAD45_SR Pad 45 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD45_DS1 Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength. [8:8] read-write PAD44_SR Pad 44 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD44_DS1 Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength. [0:0] read-write ALTPADCFGM Alternate Pad Configuration reg12 (Pads 48-49) 0x00000110 32 read-write 0x00000000 0x00001111 PAD49_SR Pad 49 slew rate selection. [12:12] read-write SR_EN Enables Slew rate control on pad 1 PAD49_DS1 Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength. [8:8] read-write PAD48_SR Pad 48 slew rate selection. [4:4] read-write SR_EN Enables Slew rate control on pad 1 PAD48_DS1 Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength. [0:0] read-write SCDET SCARD Card Detect select 0x00000114 32 read-write 0x0000003F 0x0000003F SCDET SCARD card detect pad select. [5:0] read-write CTENCFG Counter/Timer Enable Config 0x00000118 32 read-write 0xFFFFFFFF 0xFFFFFFFF EN31 CT31 Enable [31:31] read-write DIS Disable CT31 for output 1 EN Enable CT31 for output 0 EN30 CT30 Enable [30:30] read-write DIS Disable CT30 for output 1 EN Enable CT30 for output 0 EN29 CT29 Enable [29:29] read-write DIS Disable CT29 for output 1 EN Enable CT29 for output 0 EN28 CT28 Enable [28:28] read-write DIS Disable CT28 for output 1 EN Enable CT28 for output 0 EN27 CT27 Enable [27:27] read-write DIS Disable CT27 for output 1 EN Enable CT27 for output 0 EN26 CT26 Enable [26:26] read-write DIS Disable CT26 for output 1 EN Enable CT26 for output 0 EN25 CT25 Enable [25:25] read-write DIS Disable CT25 for output 1 EN Enable CT25 for output 0 EN24 CT24 Enable [24:24] read-write DIS Disable CT24 for output 1 EN Enable CT24 for output 0 EN23 CT23 Enable [23:23] read-write DIS Disable CT23 for output 1 EN Enable CT23 for output 0 EN22 CT22 Enable [22:22] read-write DIS Disable CT22 for output 1 EN Enable CT22 for output 0 EN21 CT21 Enable [21:21] read-write DIS Disable CT21 for output 1 EN Enable CT21 for output 0 EN20 CT20 Enable [20:20] read-write DIS Disable CT20 for output 1 EN Enable CT20 for output 0 EN19 CT19 Enable [19:19] read-write DIS Disable CT19 for output 1 EN Enable CT19 for output 0 EN18 CT18 Enable [18:18] read-write DIS Disable CT18 for output 1 EN Enable CT18 for output 0 EN17 CT17 Enable [17:17] read-write DIS Disable CT17 for output 1 EN Enable CT17 for output 0 EN16 CT16 Enable [16:16] read-write DIS Disable CT16 for output 1 EN Enable CT16 for output 0 EN15 CT15 Enable [15:15] read-write DIS Disable CT15 for output 1 EN Enable CT15 for output 0 EN14 CT14 Enable [14:14] read-write DIS Disable CT14 for output 1 EN Enable CT14 for output 0 EN13 CT13 Enable [13:13] read-write DIS Disable CT13 for output 1 EN Enable CT13 for output 0 EN12 CT12 Enable [12:12] read-write DIS Disable CT12 for output 1 EN Enable CT12 for output 0 EN11 CT11 Enable [11:11] read-write DIS Disable CT11 for output 1 EN Enable CT11 for output 0 EN10 CT10 Enable [10:10] read-write DIS Disable CT10 for output 1 EN Enable CT10 for output 0 EN9 CT9 Enable [9:9] read-write DIS Disable CT9 for output 0 EN8 CT8 Enable [8:8] read-write DIS Disable CT8 for output 1 EN Enable CT8 for output 0 EN7 CT7 Enable [7:7] read-write DIS Disable CT7 for output 1 EN Enable CT7 for output 0 EN6 CT6 Enable [6:6] read-write DIS Disable CT6 for output 1 EN Enable CT6 for output 0 EN5 CT5 Enable [5:5] read-write DIS Disable CT5 for output 1 EN Enable CT5 for output 0 EN4 CT4 Enable [4:4] read-write DIS Disable CT4 for output 1 EN Enable CT4 for output 0 EN3 CT3 Enable [3:3] read-write DIS Disable CT3 for output 1 EN Enable CT3 for output 0 EN2 CT2 Enable [2:2] read-write DIS Disable CT2 for output 1 EN Enable CT2 for output 0 EN1 CT1 Enable [1:1] read-write DIS Disable CT1 for output 1 EN Enable CT1 for output 0 EN0 CT0 Enable [0:0] read-write DIS Disable CT0 for output 1 EN Enable CT0 for output 0 INT0EN GPIO Interrupt Registers 31-0: Enable 0x00000200 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT0STAT GPIO Interrupt Registers 31-0: Status 0x00000204 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT0CLR GPIO Interrupt Registers 31-0: Clear 0x00000208 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT0SET GPIO Interrupt Registers 31-0: Set 0x0000020C 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT1EN GPIO Interrupt Registers 49-32: Enable 0x00000210 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write INT1STAT GPIO Interrupt Registers 49-32: Status 0x00000214 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write INT1CLR GPIO Interrupt Registers 49-32: Clear 0x00000218 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write INT1SET GPIO Interrupt Registers 49-32: Set 0x0000021C 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write IOM0 1.0 IO Peripheral Master 0x50004000 32 read-write 0 0x00000414 registers IOMSTR0 6 FIFO FIFO Access Port 0x00000000 32 read-write 0x00000000 0xFFFFFFFF FIFO FIFO direct access. Only locations 0 - 3F will return valid information. [31:0] read-write FIFOPTR FIFO size and remaining slots open values 0x00000100 32 read-write 0x00000000 0xFFFFFFFF FIFO1REM The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU) [31:24] read-write FIFO1SIZ The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU) [23:16] read-write FIFO0REM The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface) [15:8] read-write FIFO0SIZ The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface) [7:0] read-write FIFOTHR FIFO Threshold Configuration 0x00000104 32 read-write 0x00000000 0x00003F3F FIFOWTHR FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations. [13:8] read-write FIFORTHR FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations. [5:0] read-write FIFOPOP FIFO POP register 0x00000108 32 read-write 0x00000000 0xFFFFFFFF FIFODOUT This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word. [31:0] read-write FIFOPUSH FIFO PUSH register 0x0000010C 32 read-write 0x00000000 0xFFFFFFFF FIFODIN This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes). [31:0] read-write FIFOCTRL FIFO Control Register 0x00000110 32 read-write 0x00000002 0x00000003 FIFORSTN Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset. [1:1] read-write POPWR Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode. [0:0] read-write FIFOLOC FIFO Pointers 0x00000114 32 read-write 0x00000000 0x00000F0F FIFORPTR Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation. [11:8] read-write FIFOWPTR Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices. [3:0] read-write INTEN IO Master Interrupts: Enable 0x00000200 32 read-write 0x00000000 0x00007FFF CQERR Error during command queue operations [14:14] read-write CQUPD CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [13:13] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [12:12] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [11:11] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [10:10] read-write ARB Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. [9:9] read-write STOP STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. [8:8] read-write START START command interrupt. Asserted when another master on the bus has signaled a START command. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write NAK I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write INTSTAT IO Master Interrupts: Status 0x00000204 32 read-write 0x00000000 0x00007FFF CQERR Error during command queue operations [14:14] read-write CQUPD CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [13:13] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [12:12] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [11:11] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [10:10] read-write ARB Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. [9:9] read-write STOP STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. [8:8] read-write START START command interrupt. Asserted when another master on the bus has signaled a START command. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write NAK I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write INTCLR IO Master Interrupts: Clear 0x00000208 32 read-write 0x00000000 0x00007FFF CQERR Error during command queue operations [14:14] read-write CQUPD CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [13:13] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [12:12] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [11:11] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [10:10] read-write ARB Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. [9:9] read-write STOP STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. [8:8] read-write START START command interrupt. Asserted when another master on the bus has signaled a START command. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write NAK I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write INTSET IO Master Interrupts: Set 0x0000020C 32 read-write 0x00000000 0x00007FFF CQERR Error during command queue operations [14:14] read-write CQUPD CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. [13:13] read-write CQPAUSED Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. [12:12] read-write DERR DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. [11:11] read-write DCMP DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state [10:10] read-write ARB Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. [9:9] read-write STOP STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. [8:8] read-write START START command interrupt. Asserted when another master on the bus has signaled a START command. [7:7] read-write ICMD illegal command interrupt. Asserted when a command is written when an active command is in progress. [6:6] read-write IACC illegal FIFO access interrupt. Asserted when there is a overflow or underflow event [5:5] read-write NAK I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. [4:4] read-write FOVFL Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. [3:3] read-write FUNDFL Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. [2:2] read-write THR FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. [1:1] read-write CMDCMP Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. [0:0] read-write CLKCFG I/O Clock Configuration 0x00000210 32 read-write 0x00000000 0xFFFF1F01 TOTPER Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The source clock is selected by FSEL. Only applicable when DIVEN = 1. [31:24] read-write LOWPER Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1. Only applicable when DIVEN = 1. [23:16] read-write DIVEN Enable clock division by TOTPER and LOWPER [12:12] read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 DIV3 Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider, and if enabled will provide the divided by 3 clock as the source to the programmable divider. [11:11] read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 FSEL Select the input clock frequency. [10:8] read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOM is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 IOCLKEN Enable for the interface clock. Must be enabled prior to executing any IO operations. [0:0] read-write SUBMODCTRL Submodule control 0x00000214 32 read-write 0x00000020 0x000000FF SMOD1TYPE Submodule 0 module type. This is the I2C Master interface [7:5] read-write MSPI SPI Master submodule 0 I2C_MASTER MI2C submodule 1 SSPI SPI Slave submodule 2 SI2C I2C Slave submodule 3 NA NOT INSTALLED 7 SMOD1EN Submodule 1 enable (1) or disable (0) [4:4] read-write SMOD0TYPE Submodule 0 module type. This is the SPI Master interface. [3:1] read-write SPI_MASTER MSPI submodule 0 I2C_MASTER I2C Master submodule 1 SSPI SPI Slave submodule 2 SI2C I2C Slave submodule 3 NA NOT INSTALLED 7 SMOD0EN Submodule 0 enable (1) or disable (0) [0:0] read-write CMD Command and offset Register 0x00000218 32 read-write 0x00000000 0xFF3FFFFF OFFSETLO This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. [31:24] read-write CMDSEL Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions [21:20] read-write TSIZE Defines the transaction size in bytes. The offset transfer is not included in this size. [19:8] read-write CONT Contine to hold the bus after the current transaction if set to a 1 with a new command issued. [7:7] read-write OFFSETCNT Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If offsetcnt == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration. [6:5] read-write CMD Command for submodule. [4:0] read-write WRITE Write command using count of offset bytes specified in the OFFSETCNT field 1 READ Read command using count of offset bytes specified in the OFFSETCNT field 2 TMW SPI only. Test mode to do constant write operations. Useful for debug and power measurements. Will continually send data in OFFSET field 3 TMR SPI Only. Test mode to do constant read operations. Useful for debug and power measurements. Will continually read data from external input 4 DCX DCX Control Register 0x0000021C 32 read-write 0x00000000 0x0000001F DCXEN Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte, and high during transmission of data bytes. [4:4] read-write EN Enable DCX. 1 DIS Disable DCX. 0 CE3OUT Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output. [3:3] read-write CE2OUT Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output. [2:2] read-write CE1OUT Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output. [1:1] read-write CE0OUT Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output. [0:0] read-write OFFSETHI High order 2 bytes of 3 byte offset for IO transaction 0x00000220 32 read-write 0x00000000 0x0000FFFF OFFSETHI Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register [15:0] read-write CMDSTAT Command status 0x00000224 32 read-write 0x00000000 0x000FFFFF CTSIZE The current number of bytes still to be transferred with this command. This field will count down to zero. [19:8] read-write CMDSTAT The current status of the command execution. [7:5] read-write ERR Error encountered with command 1 ACTIVE Actively processing command 2 IDLE Idle state, no active command, no error 4 WAIT Command in progress, but waiting on data from host 6 CCMD current command that is being executed [4:0] read-write DMATRIGEN DMA Trigger Enable Register 0x00000240 32 read-write 0x00000000 0x00000003 DTHREN Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, the CMDCMP trigger must also be enabled to transfer the remaining read FIFO data to SRAM. [1:1] read-write DCMDCMPEN Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or [0:0] read-write DMATRIGSTAT DMA Trigger Status Register 0x00000244 32 read-write 0x00000000 0x00000007 DTOTCMP DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation. [2:2] read-write DTHR Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA. [1:1] read-write DCMDCMP Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA. [0:0] read-write DMACFG DMA Configuration Register 0x00000280 32 read-write 0x00000000 0x00000303 DPWROFF Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed. [9:9] read-write DIS Power off disabled 0 EN Power off enabled 1 DMAPRI Sets the Priority of the DMA request [8:8] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 DMADIR Direction [1:1] read-write P2M Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices. 0 M2P Memory to Peripheral transaction. To be set when doing IOM write operations, ie writing data to external devices. 1 DMAEN DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command [0:0] read-write DIS Disable DMA Function 0 EN Enable DMA Function 1 DMATOTCOUNT DMA Total Transfer Count 0x00000288 32 read-write 0x00000000 0x00000FFF TOTCOUNT Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA. [11:0] read-write DMATARGADDR DMA Target Address Register 0x0000028C 32 read-write 0x00000000 0x100FFFFF TARGADDR28 Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash [28:28] read-write TARGADDR Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. [19:0] read-write DMASTAT DMA Status Register 0x00000290 32 read-write 0x00000000 0x00000007 DMAERR DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set, this bit will remain set until cleared by software. [2:2] read-write DMACPL DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0, and will also be cleared when a new DMA is started. [1:1] read-write DMATIP DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only. [0:0] read-write CQCFG Command Queue Configuration Register 0x00000294 32 read-write 0x00000000 0x00000003 CQPRI Sets the Priority of the command queue dma request [1:1] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 CQEN Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well. [0:0] read-write DIS Disable CQ Function 0 EN Enable CQ Function 1 CQADDR CQ Target Read Address Register 0x00000298 32 read-write 0x00000000 0x100FFFFC CQADDR28 Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access [28:28] read-write CQADDR Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary [19:2] read-write CQSTAT Command Queue Status Register 0x0000029C 32 read-write 0x00000000 0x00000007 CQERR Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation. [2:2] read-write CQPAUSED Command queue operation is currently paused. [1:1] read-write CQTIP Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event. [0:0] read-write CQFLAGS Command Queue Flag Register 0x000002A0 32 read-write 0x00000000 0xFFFFFFFF CQIRQMASK Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE [31:16] read-write CQFLAGS Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status. [15:0] read-write CQSETCLEAR Command Queue Flag Set/Clear Register 0x000002A4 32 read-write 0x00000000 0x00FFFFFF CQFCLR Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field [23:16] read-write CQFTGL Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field [15:8] read-write CQFSET Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field [7:0] read-write CQPAUSEEN Command Queue Pause Enable Register 0x000002A8 32 read-write 0x00000000 0x0000FFFF CQPEN Enables the specified event to pause command processing when active [15:0] read-write IDXEQ Pauses the command queue when the current index matches the last index 32768 BLEXOREN Pause command queue when input BLE bit XORed with SWFLAG4 is '1' 16384 IOMXOREN Pause command queue when input IOM bit XORed with SWFLAG3 is '1' 8192 GPIOXOREN Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1' 4096 MSPI1XNOREN Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1' 2048 MSPI0XNOREN Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1' 1024 MSPI1XOREN Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1' 512 MSPI0XOREN Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1' 256 SWFLAGEN7 Pause the command queue when software flag bit 7 is '1'. 128 SWFLAGEN6 Pause the command queue when software flag bit 6 is '1' 64 SWFLAGEN5 Pause the command queue when software flag bit 5 is '1' 32 SWFLAGEN4 Pause the command queue when software flag bit 4 is '1' 16 SWFLAGEN3 Pause the command queue when software flag bit 3 is '1' 8 SWFLAGEN2 Pause the command queue when software flag bit 2 is '1' 4 SWFLAGEN1 Pause the command queue when software flag bit 1 is '1' 2 SWFLAGEN0 Pause the command queue when software flag bit 0 is '1' 1 CQCURIDX IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue 0x000002AC 32 read-write 0x00000000 0x000000FF CQCURIDX Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN. [7:0] read-write CQENDIDX IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue 0x000002B0 32 read-write 0x00000000 0x000000FF CQENDIDX Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN. [7:0] read-write STATUS IOM Module Status Register 0x000002B4 32 read-write 0x00000000 0x00000007 IDLEST indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers. [2:2] read-write IDLE The I/O state machine is in the idle state. 1 CMDACT Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized. [1:1] read-write ACTIVE An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed. 1 ERR Bit has been deprecated. Please refer to the other error indicators. This will always return 0. [0:0] read-write ERROR Bit has been deprecated and will always return 0. 1 MSPICFG SPI module master configuration 0x00000300 32 read-write 0x00200000 0x7FF70007 MSPIRST Not used. To reset the module, toggle the SMOD_EN for the module [30:30] read-write DOUTDLY Delay tap to use for the output signal (MOSI). This give more hold time on the output data [29:27] read-write DINDLY Delay tap to use for the input signal (MISO). This gives more hold time on the input data. [26:24] read-write SPILSB Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first. [23:23] read-write MSB Send and receive MSB bit first 0 LSB Send and receive LSB bit first 1 RDFCPOL selects the read flow control signal polarity. [22:22] read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 WTFCPOL selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers). [21:21] read-write HIGH Flow control signal high(1) creates flow control and byte transfers will stop until the flow control signal goes low. 0 LOW Flow control signal low(0) creates flow control and byte transfers will stop until the flow control signal goes high(1). 1 WTFCIRQ selects the write mode flow control signal. [20:20] read-write MISO MISO is used as the write mode flow control signal. 0 IRQ IRQ is used as the write mode flow control signal. 1 MOSIINV inverts MOSI when flow control is enabled. [18:18] read-write NORMAL MOSI is set to 0 in read mode and 1 in write mode. 0 INVERT MOSI is set to 1 in read mode and 0 in write mode. 1 RDFC enables read mode flow control. [17:17] read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 WTFC enables write mode flow control. [16:16] read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 FULLDUP Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo [2:2] read-write SPHA selects SPI phase. [1:1] read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL selects SPI polarity. [0:0] read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 MI2CCFG I2C Master configuration 0x00000400 32 read-write 0x00000000 0x01FFFF77 STRDIS Disable detection of clock stretch events smaller than 1 cycle [24:24] read-write SMPCNT Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured [23:16] read-write SDAENDLY Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock [15:12] read-write SCLENDLY Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping. [11:8] read-write MI2CRST Not used. To reset the module, toggle the SMOD_EN for the module [6:6] read-write SDADLY Delay to enable on the SDA output. Values are 0x0-0x3. [5:4] read-write ARBEN Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master, this function can be disabled to save clock cycles on I2C transactions [2:2] read-write ARBEN Enable multi-master bus arbitration support for this i2c master 1 ARBDIS Disable multi-master bus arbitration support for this i2c master 0 I2CLSB Direction of data transmit and receive, MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data, and read data will be bit [1:1] read-write MSBFIRST Byte data is transmitted MSB first onto the bus/read from the bus 0 LSBFIRST Byte data is transmitted LSB first onto the bus/read from the bus 1 ADDRSZ Sets the I2C master device address size to either 7b (0) or 10b (1). [0:0] read-write ADDRSZ7 Use 7b addressing for I2C master transactions 0 ADDRSZ10 Use 10b addressing for I2C master transactions 1 DEVCFG I2C Device Configuration register 0x00000404 32 read-write 0x00000000 0x000003FF DEVADDR I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address. [9:0] read-write IOMDBG IOM Debug Register 0x00000410 32 read-write 0x00000000 0xFFFFFFFF DBGDATA Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers. [31:3] read-write APBCLKON APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed. [2:2] read-write IOCLKON IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed. [1:1] read-write DBGEN Debug Enable. Setting bit will enable the update of data within this register, otherwise it is clock gated for power savings [0:0] read-write IOM1 0x50005000 IOMSTR1 7 IOM2 0x50006000 IOMSTR2 8 IOM3 0x50007000 IOMSTR3 9 IOM4 0x50008000 IOMSTR4 10 IOM5 0x50009000 IOMSTR5 11 IOSLAVE 1.0 I2C/SPI Slave 0x50000000 32 read-write 0 0x00000220 registers IOSLAVE 4 IOSLAVEACC 5 FIFOPTR Current FIFO Pointer 0x00000100 32 read-write 0x00000000 0x0000FFFF FIFOSIZ The number of bytes currently in the hardware FIFO. [15:8] read-write FIFOPTR Current FIFO pointer. [7:0] read-write FIFOCFG FIFO Configuration 0x00000104 32 read-write 0x20000000 0x3F003F1F ROBASE Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1) [29:24] read-write FIFOMAX These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F. [13:8] read-write FIFOBASE These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1). [4:0] read-write FIFOTHR FIFO Threshold Configuration 0x00000108 32 read-write 0x00000000 0x000000FF FIFOTHR FIFO size interrupt threshold. [7:0] read-write FUPD FIFO Update Status 0x0000010C 32 read-write 0x00000000 0x00000003 IOREAD This bitfield indicates an IO read is active. [1:1] read-write FIFOUPD This bit indicates that a FIFO update is underway. [0:0] read-write FIFOCTR Overall FIFO Counter 0x00000110 32 read-write 0x00000000 0x000003FF FIFOCTR Virtual FIFO byte count [9:0] read-write FIFOINC Overall FIFO Counter Increment 0x00000114 32 read-write 0x00000000 0x000003FF FIFOINC Increment the Overall FIFO Counter by this value on a write [9:0] read-write CFG I/O Slave Configuration 0x00000118 32 read-write 0x00000000 0x800FFF17 IFCEN IOSLAVE interface enable. [31:31] read-write DIS Disable the IOSLAVE 0 EN Enable the IOSLAVE 1 I2CADDR 7-bit or 10-bit I2C device address. [19:8] read-write STARTRD This bit holds the cycle to initiate an I/O RAM read. [4:4] read-write LATE Initiate I/O RAM read late in each transferred byte. 0 EARLY Initiate I/O RAM read early in each transferred byte. 1 LSB This bit selects the transfer bit ordering. [2:2] read-write MSB_FIRST Data is assumed to be sent and received with MSB first. 0 LSB_FIRST Data is assumed to be sent and received with LSB first. 1 SPOL This bit selects SPI polarity. [1:1] read-write SPI_MODES_0_3 Polarity 0, handles SPI modes 0 and 3. 0 SPI_MODES_1_2 Polarity 1, handles SPI modes 1 and 2. 1 IFCSEL This bit selects the I/O interface. [0:0] read-write I2C Selects I2C interface for the IO Slave. 0 SPI Selects SPI interface for the IO Slave. 1 PRENC I/O Slave Interrupt Priority Encode 0x0000011C 32 read-write 0x00000000 0x0000001F PRENC These bits hold the priority encode of the REGACC interrupts. [4:0] read-write IOINTCTL I/O Interrupt Control 0x00000120 32 read-write 0x00000000 0xFF01FFFF IOINTSET These bits set the IOINT interrupts when written with a 1. [31:24] read-write IOINTCLR This bit clears all of the IOINT interrupts when written with a 1. [16:16] read-write IOINT These bits read the IOINT interrupts. [15:8] read-write IOINTEN These read-only bits indicate whether the IOINT interrupts are enabled. [7:0] read-write GENADD General Address Data 0x00000124 32 read-write 0x00000000 0x000000FF GADATA The data supplied on the last General Address reference. [7:0] read-write INTEN IO Slave Interrupts: Enable 0x00000200 32 read-write 0x00000000 0x000003FF XCMPWR Transfer complete interrupt, write to register space. [9:9] read-write XCMPWF Transfer complete interrupt, write to FIFO space. [8:8] read-write XCMPRR Transfer complete interrupt, read from register space. [7:7] read-write XCMPRF Transfer complete interrupt, read from FIFO space. [6:6] read-write IOINTW IO Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write INTSTAT IO Slave Interrupts: Status 0x00000204 32 read-write 0x00000000 0x000003FF XCMPWR Transfer complete interrupt, write to register space. [9:9] read-write XCMPWF Transfer complete interrupt, write to FIFO space. [8:8] read-write XCMPRR Transfer complete interrupt, read from register space. [7:7] read-write XCMPRF Transfer complete interrupt, read from FIFO space. [6:6] read-write IOINTW IO Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write INTCLR IO Slave Interrupts: Clear 0x00000208 32 read-write 0x00000000 0x000003FF XCMPWR Transfer complete interrupt, write to register space. [9:9] read-write XCMPWF Transfer complete interrupt, write to FIFO space. [8:8] read-write XCMPRR Transfer complete interrupt, read from register space. [7:7] read-write XCMPRF Transfer complete interrupt, read from FIFO space. [6:6] read-write IOINTW IO Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write INTSET IO Slave Interrupts: Set 0x0000020C 32 read-write 0x00000000 0x000003FF XCMPWR Transfer complete interrupt, write to register space. [9:9] read-write XCMPWF Transfer complete interrupt, write to FIFO space. [8:8] read-write XCMPRR Transfer complete interrupt, read from register space. [7:7] read-write XCMPRF Transfer complete interrupt, read from FIFO space. [6:6] read-write IOINTW IO Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write REGACCINTEN Register Access Interrupts: Enable 0x00000210 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write REGACCINTSTAT Register Access Interrupts: Status 0x00000214 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write REGACCINTCLR Register Access Interrupts: Clear 0x00000218 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write REGACCINTSET Register Access Interrupts: Set 0x0000021C 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write MCUCTRL 1.0 MCU Miscellaneous Control Logic 0x40020000 32 read-write 0 0x000003D8 registers BROWNOUT 0 CHIPPN Chip Information Register 0x00000000 32 read-write 0x04000000 0xFFFFFFFF PARTNUM BCD part number. [31:0] read-write APOLLO3 Apollo3 Blue part number is 0x06xxxxxx. 100663296 APOLLO2 Apollo2 part number is 0x03xxxxxx. 50331648 APOLLO Apollo part number is 0x01xxxxxx. 16777216 PN_M Mask for the part number field. 4278190080 PN_S Bit position for the part number field. 24 FLASHSIZE_M Mask for the FLASH_SIZE field. Values: 0: 16KB 1: 32KB 2: 64KB 3: 128KB 4: 256KB 5: 512KB 6: 1MB 7: 2MB 15728640 FLASHSIZE_S Bit position for the FLASH_SIZE field. 20 SRAMSIZE_M Mask for the SRAM_SIZE field. Values: 0: 16KB 1: 32KB 2: 64KB 3: 128KB 4: 256KB 5: 512KB 6: 1MB 7: 384KB 8: 768KB 983040 SRAMSIZE_S Bit position for the SRAM_SIZE field. 16 REV_M Mask for the revision field. Bits [15:12] are major rev, [11:8] are minor rev. Values: 0: Major Rev A, Minor Rev 0 1: Major Rev B, Minor Rev 1 65280 REV_S Bit position for the revision field. 8 PKG_M Mask for the package field. Values: 0: SIP 1: QFN 2: BGA 3: CSP 192 PKG_S Bit position for the package field. 6 PINS_M Mask for the pins field. Values: 0: 25 pins 1: 49 pins 2: 64 pins 3: 81 pins 4: 104 pins 56 PINS_S Bit position for the pins field. 3 TEMP_S Bit position for the temperature field. 1 QUAL_S Bit position for the qualified field. 0 CHIPID0 Unique Chip ID 0 0x00000004 32 read-write 0x00000000 0xFFFFFFFF CHIPID0 Unique chip ID 0. [31:0] read-write APOLLO3 Apollo3 Blue Plus CHIPID0. 0 CHIPID1 Unique Chip ID 1 0x00000008 32 read-write 0x00000000 0xFFFFFFFF CHIPID1 Unique chip ID 1. [31:0] read-write APOLLO3 Apollo3 Blue Plus CHIPID1. 0 CHIPREV Chip Revision 0x0000000C 32 read-write 0x00000001 0x000FFFFF SIPART Silicon Part ID [19:8] read-write REVMAJ Major Revision ID. [7:4] read-write B Apollo3 Blue revision B 2 A Apollo3 Blue revision A 1 REVMIN Minor Revision ID. [3:0] read-write REV1 Apollo3 Blue minor rev 1. 2 REV0 Apollo3 Blue minor rev 0. Minor revision value, succeeding minor revisions will increment from this value. 1 VENDORID Unique Vendor ID 0x00000010 32 read-write 0x00000000 0xFFFFFFFF VENDORID Unique Vendor ID [31:0] read-write AMBIQ Ambiq Vendor ID 'AMBQ' 1095582289 SKU Unique Chip SKU 0x00000014 32 read-write 0x00000000 0x00000007 SECBOOT Secure boot feature allowed [2:2] read-write ALLOWBLE Allow BLE feature [1:1] read-write ALLOWBURST Allow Burst feature [0:0] read-write FEATUREENABLE Feature Enable on Burst and BLE 0x00000018 32 read-write 0x00000001 0x00000077 BURSTAVAIL Availability of Burst functionality [6:6] read-write AVAIL Burst functionality available 1 NOTAVAIL Burst functionality not available 0 BURSTACK ACK for BURSTREQ [5:5] read-write BURSTREQ Controls the Burst functionality [4:4] read-write EN Enable the Burst functionality 1 DIS Disable the Burst functionality 0 BLEAVAIL AVAILABILITY of the BLE functionality [2:2] read-write AVAIL BLE functionality available 1 NOTAVAIL BLE functionality not available 0 BLEACK ACK for BLEREQ [1:1] read-write BLEREQ Controls the BLE functionality [0:0] read-write EN Enable the BLE functionality 1 DIS Disable the BLE functionality 0 DEBUGGER Debugger Control 0x00000020 32 read-write 0x00000000 0x00000001 LOCKOUT Lockout of debugger (SWD). [0:0] read-write BODCTRL BOD control Register 0x00000100 32 read-write 0x00000000 0x0000003F BODHVREFSEL BODH External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect. [5:5] read-write BODLVREFSEL BODL External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect. [4:4] read-write BODFPWD BODF Power Down. [3:3] read-write BODCPWD BODC Power Down. [2:2] read-write BODHPWD BODH Power Down. [1:1] read-write BODLPWD BODL Power Down. [0:0] read-write ADCPWRDLY ADC Power Up Delay Control 0x00000104 32 read-write 0x00000000 0x0000FFFF ADCPWR1 ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2. [15:8] read-write ADCPWR0 ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2. [7:0] read-write ADCCAL ADC Calibration Control 0x0000010C 32 read-write 0x00000001 0x00000003 ADCCALIBRATED Status for ADC Calibration [1:1] read-write FALSE ADC is not calibrated 0 TRUE ADC is calibrated 1 CALONPWRUP Run ADC Calibration on initial power up sequence [0:0] read-write DIS Disable automatic calibration on initial power up 0 EN Enable automatic calibration on initial power up 1 ADCBATTLOAD ADC Battery Load Enable 0x00000110 32 read-write 0x00000000 0x00000001 BATTLOAD Enable the ADC battery load resistor [0:0] read-write DIS Battery load is disconnected 0 EN Battery load is enabled 1 ADCTRIM ADC Trims 0x00000118 32 read-write 0x00000200 0x00001FC3 ADCRFBUFIBTRIM ADC reference buffer input bias trim [12:11] read-write ADCREFBUFTRIM ADC Reference buffer trim [10:6] read-write ADCREFKEEPIBTRIM ADC Reference Ibias trim [1:0] read-write ADCREFCOMP ADC Reference Keeper and Comparator Control 0x0000011C 32 read-write 0x00000000 0x00011F01 ADCRFCMPEN ADC Reference comparator power down [16:16] read-write ADCREFKEEPTRIM ADC Reference Keeper Trim [12:8] read-write ADC_REFCOMP_OUT Output of the ADC reference comparator [0:0] read-write XTALCTRL XTAL Oscillator Control 0x00000120 32 read-write 0x00000358 0x000003FF XTALICOMPTRIM XTAL ICOMP trim [9:8] read-write XTALIBUFTRIM XTAL IBUFF trim [7:6] read-write PWDBODXTAL XTAL Power down on brown out. [5:5] read-write PWRUPBOD Power up XTAL on BOD. 0 PWRDNBOD Power down XTAL on BOD. 1 PDNBCMPRXTAL XTAL Oscillator Power Down Comparator. [4:4] read-write PWRUPCOMP Power up XTAL oscillator comparator. 1 PWRDNCOMP Power down XTAL oscillator comparator. 0 PDNBCOREXTAL XTAL Oscillator Power Down Core. [3:3] read-write PWRUPCORE Power up XTAL oscillator core. 1 PWRDNCORE Power down XTAL oscillator core. 0 BYPCMPRXTAL XTAL Oscillator Bypass Comparator. [2:2] read-write USECOMP Use the XTAL oscillator comparator. 0 BYPCOMP Bypass the XTAL oscillator comparator. 1 FDBKDSBLXTAL XTAL Oscillator Disable Feedback. [1:1] read-write EN Enable XTAL oscillator comparator. 0 DIS Disable XTAL oscillator comparator. 1 XTALSWE XTAL Software Override Enable. [0:0] read-write OVERRIDE_DIS XTAL Software Override Disable. 0 OVERRIDE_EN XTAL Software Override Enable. 1 XTALGENCTRL XTAL Oscillator General Control 0x00000124 32 read-write 0x00000100 0x00003FFF XTALKSBIASTRIM XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock. [13:8] read-write XTALBIASTRIM XTAL BIAS trim [7:2] read-write ACWARMUP Auto-calibration delay control [1:0] read-write SEC1 Warm-up period of 1-2 seconds 0 SEC2 Warm-up period of 2-4 seconds 1 SEC4 Warm-up period of 4-8 seconds 2 SEC8 Warm-up period of 8-16 seconds 3 MISCCTRL Miscellaneous control register. 0x00000198 32 read-write 0x00000000 0x0000003F BLE_RESETN BLE reset signal. [5:5] read-write RESERVED_RW_0 Reserved bits, always leave unchanged. The MISCCTRL register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior. [4:0] read-write BOOTLOADER Bootloader and secure boot functions 0x000001A0 32 read-write 0x00000007 0xFC000007 SECBOOTONRST Indicates whether the secure boot on warm reset is enabled [31:30] read-write DISABLED Secure boot disabled 0 ENABLED Secure boot enabled 1 ERROR Error in secure boot configuration 2 SECBOOT Indicates whether the secure boot on cold reset is enabled [29:28] read-write DISABLED Secure boot disabled 0 ENABLED Secure boot enabled 1 ERROR Error in secure boot configuration 2 SECBOOTFEATURE Indicates whether the secure boot feature is enabled. [27:26] read-write DISABLED Secure boot disabled 0 ENABLED Secure boot enabled 1 ERROR Error in secure boot configuration 2 PROTLOCK Flash protection lock. Always resets to 1, write 1 to clear. Enables writes to flash protection register set. [2:2] read-write LOCK Enable the secure boot lock 1 SBLOCK Secure boot lock. Always resets to 1, write 1 to clear. Enables system visibility to bootloader until set. [1:1] read-write LOCK Enable the secure boot lock 1 BOOTLOADERLOW Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1, write 1 to clear. [0:0] read-write ADDR0 Bootloader code at 0x00000000. 1 SHADOWVALID Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space. 0x000001A4 32 read-write 0x00000007 0x00000007 INFO0_VALID Indicates whether INFO0 contains valid data [2:2] read-write VALID Flash INFO0 (customer) space contains valid data. 1 BLDSLEEP Indicates whether the bootloader should sleep or deep sleep if no image loaded. [1:1] read-write DEEPSLEEP Bootloader will go to deep sleep if no flash image loaded 1 VALID Indicates whether the shadow registers contain valid data from the Flash Information Space. [0:0] read-write VALID Flash information space contains valid data. 1 SCRATCH0 Scratch register that is not reset by any reset 0x000001B0 32 read-write 0x00000000 0xFFFFFFFF SCRATCH0 Scratch register 0. [31:0] read-write SCRATCH1 Scratch register that is not reset by any reset 0x000001B4 32 read-write 0x00000000 0xFFFFFFFF SCRATCH1 Scratch register 1. [31:0] read-write ICODEFAULTADDR ICODE bus address which was present when a bus fault occurred. 0x000001C0 32 read-write 0x00000000 0xFFFFFFFF ICODEFAULTADDR The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. [31:0] read-write DCODEFAULTADDR DCODE bus address which was present when a bus fault occurred. 0x000001C4 32 read-write 0x00000000 0xFFFFFFFF DCODEFAULTADDR The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. [31:0] read-write SYSFAULTADDR System bus address which was present when a bus fault occurred. 0x000001C8 32 read-write 0x00000000 0xFFFFFFFF SYSFAULTADDR SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. [31:0] read-write FAULTSTATUS Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register. 0x000001CC 32 read-write 0x00000000 0x00000007 SYSFAULT SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault. [2:2] read-write NOFAULT No bus fault has been detected. 0 FAULT Bus fault detected. 1 DCODEFAULT DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault. [1:1] read-write NOFAULT No DCODE fault has been detected. 0 FAULT DCODE fault detected. 1 ICODEFAULT The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault. [0:0] read-write NOFAULT No ICODE fault has been detected. 0 FAULT ICODE fault detected. 1 FAULTCAPTUREEN Enable the fault capture registers 0x000001D0 32 read-write 0x00000000 0x00000001 FAULTCAPTUREEN Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers. [0:0] read-write DIS Disable fault capture. 0 EN Enable fault capture. 1 DBGR1 Read-only debug register 1 0x00000200 32 read-write 0x12345678 0xFFFFFFFF ONETO8 Read-only register for communication validation [31:0] read-write DBGR2 Read-only debug register 2 0x00000204 32 read-write 0xC001C0DE 0xFFFFFFFF COOLCODE Read-only register for communication validation [31:0] read-write PMUENABLE Control bit to enable/disable the PMU 0x00000220 32 read-write 0x00000001 0x00000001 ENABLE PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode. [0:0] read-write DIS Disable MCU power management. 0 EN Enable MCU power management. 1 TPIUCTRL TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface. 0x00000250 32 read-write 0x00000000 0x00000701 CLKSEL This field selects the frequency of the ARM M4 TPIU port. [10:8] read-write LOWPWR Low power state. 0 HFRCDIV2 Selects HFRC divided by 2 as the source TPIU clock 1 HFRCDIV8 Selects HFRC divided by 8 as the source TPIU clock 2 HFRCDIV16 Selects HFRC divided by 16 as the source TPIU clock 3 HFRCDIV32 Selects HFRC divided by 32 as the source TPIU clock 4 ENABLE TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules. [0:0] read-write DIS Disable the TPIU. 0 EN Enable the TPIU. 1 OTAPOINTER OTA (Over the Air) Update Pointer/Status. Reset only by POA 0x00000264 32 read-write 0x00000000 0xFFFFFFFF OTAPOINTER Flash page pointer with updated OTA image [31:2] read-write OTASBLUPDATE Indicates that the sbl_init has been updated [1:1] read-write OTAVALID Indicates that an OTA update is valid [0:0] read-write APBDMACTRL DMA Control Register. Determines misc settings for DMA operation 0x00000280 32 read-write 0x00000203 0x0000FF03 HYSTERESIS This field determines how long the DMA will remain active during deep sleep before shutting down and returning the system to full deep sleep. Values are based on a 94KHz clock and are roughly 10 us increments for a range of ~10 us to 2.55 ms [15:8] read-write DECODEABORT APB Decode Abort. When set, the APB bridge will issue a data abort (bus fault) on transactions to peripherals that are powered down. When set to 0, writes are quietly discarded and reads return 0. [1:1] read-write DISABLE Bus operations to powered down peripherals are quietly discarded 0 ENABLE Bus operations to powered down peripherals result in a bus fault. 1 DMA_ENABLE Enable the DMA controller. When disabled, DMA requests will be ignored by the controller [0:0] read-write DISABLE DMA operations disabled 0 ENABLE DMA operations enabled 1 SRAMMODE SRAM Controller mode bits 0x00000284 32 read-write 0x00000000 0x00000033 DPREFETCH_CACHE Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires DPREFETCH to be set). [5:5] read-write DPREFETCH When set, data bus accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Use of this mode bit is only recommended if the work flow has a large number of sequential accesses. [4:4] read-write IPREFETCH_CACHE Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires IPREFETCH to be set). [1:1] read-write IPREFETCH When set, instruction accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Generally, this mode bit should be set for improved performance when executing instructions from SRAM. [0:0] read-write KEXTCLKSEL Key Register to enable the use of external clock selects via the EXTCLKSEL reg 0x00000348 32 read-write 0x00000000 0xFFFFFFFF KEXTCLKSEL Key register value. [31:0] read-write Key Key 83 SIMOBUCK2 SIMO Buck Control Reg 2 0x00000354 32 read-write 0x00AA0000 0xFFFFFFFF RESERVED_RW_24 Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior. [31:24] read-write SIMOBUCKCORELPLOWTONTRIM simobuck_core_lp_low_ton_trim [23:20] read-write SIMOBUCKCORELPHIGHTONTRIM simobuck_core_lp_high_ton_trim [19:16] read-write RESERVED_RW_0 Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior. [15:0] read-write SIMOBUCK3 SIMO Buck Control Reg 3 0x00000358 32 read-write 0x5000AAAA 0xFFFFFFFF RESERVED_RW_31 Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior. [31:31] read-write SIMOBUCKMEMLPHIGHTONTRIM simobuck_mem_lp_high_ton_trim [30:27] read-write RESERVED_RW_16 Reserved bits, always leave unchanged. The SIMOBUCK3 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior. [26:16] read-write SIMOBUCKMEMLPLOWTOFFTRIM simobuck_mem_lp_low_toff_trim [15:12] read-write SIMOBUCKMEMLPHIGHTOFFTRIM simobuck_mem_lp_high_toff_trim [11:8] read-write SIMOBUCKCORELPLOWTOFFTRIM simobuck_core_lp_low_toff_trim [7:4] read-write SIMOBUCKCORELPHIGHTOFFTRIM simobuck_core_lp_high_toff_trim [3:0] read-write SIMOBUCK4 SIMO Buck Control Reg 4 0x0000035C 32 read-write 0x3C8D80AA 0x0160000F SIMOBUCKCOMP2TIMEOUTEN simobuck_comp2_timeout_en [24:24] read-write SIMOBUCKCLKDIVSEL simobuck_clkdiv_sel [22:21] read-write SIMOBUCKMEMLPLOWTONTRIM simobuck_mem_lp_low_ton_trim [3:0] read-write BLEBUCK2 BLEBUCK2 Control Reg 0x00000368 32 read-write 0x0000004E 0x0003FFFF BLEBUCKTOND2ATRIM blebuck_ton_trim [17:12] read-write BLEBUCKTONHITRIM blebuck_ton_hi_trim [11:6] read-write BLEBUCKTONLOWTRIM blebuck_ton_low_trim [5:0] read-write FLASHWPROT0 Flash Write Protection Bits 0x000003A0 32 read-write 0x00000000 0xFFFFFFFF FW0BITS Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset) [31:0] read-write FLASHWPROT1 Flash Write Protection Bits 0x000003A4 32 read-write 0x00000000 0xFFFFFFFF FW1BITS Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset) [31:0] read-write FLASHRPROT0 Flash Read Protection Bits 0x000003B0 32 read-write 0x00000000 0xFFFFFFFF FR0BITS Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset) [31:0] read-write FLASHRPROT1 Flash Read Protection Bits 0x000003B4 32 read-write 0x00000000 0xFFFFFFFF FR1BITS Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset) [31:0] read-write DMASRAMWRITEPROTECT0 SRAM write-protection bits. 0x000003C0 32 read-write 0x00000000 0xFFFFFFFF DMA_WPROT0 Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region. [31:0] read-write DMASRAMWRITEPROTECT1 SRAM write-protection bits. 0x000003C4 32 read-write 0x00000000 0x0000FFFF DMA_WPROT1 Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region. [15:0] read-write DMASRAMREADPROTECT0 SRAM read-protection bits. 0x000003D0 32 read-write 0x00000000 0xFFFFFFFF DMA_RPROT0 Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region. [31:0] read-write DMASRAMREADPROTECT1 SRAM read-protection bits. 0x000003D4 32 read-write 0x00000000 0x0000FFFF DMA_RPROT1 Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region. [15:0] read-write MSPI 1.0 Multi-bit SPI Master 0x50014000 32 read-write 0 0x000002C8 registers MSPI0 20 CTRL MSPI PIO Transfer Control/Status 0x00000000 32 read-write 0x00000000 0xFFFF0FCF XFERBYTES Number of bytes to transmit or receive (based on TXRX bit) [31:16] read-write PIOSCRAMBLE Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device. [11:11] read-write TXRX 1 Indicates a TX operation, 0 indicates an RX operation of XFERBYTES [10:10] read-write SENDI Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register) [9:9] read-write SENDA Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register) [8:8] read-write ENTURN Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register). [7:7] read-write BIGENDIAN 1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default, LSB first). [6:6] read-write QUADCMD Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers). [3:3] read-write BUSY Command status: 1 indicates controller is busy (command in progress) [2:2] read-write STATUS Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer. [1:1] read-write START Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set). [0:0] read-write CFG MSPI Transfer Configuration 0x00000004 32 read-write 0x00000001 0x00033FFF CPOL Serial clock polarity. [17:17] read-write LOW Clock inactive state is low. 0 HIGH Clock inactive state is high. 1 CPHA Serial clock phase. [16:16] read-write MIDDLE Clock toggles in middle of data bit. 0 START Clock toggles at start of data bit. 1 TURNAROUND Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field. [13:8] read-write SEPIO Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins. [7:7] read-write ISIZE Instruction Size enum name = I8 value = 0x0 desc = Instruction is 1 byte enum name = I16 value = 0x1 desc = Instruction is 2 bytes [6:6] read-write ASIZE Address Size. Address bytes to send from ADDR register [5:4] read-write A1 Send one address byte 0 A2 Send two address bytes 1 A3 Send three address bytes 2 A4 Send four address bytes 3 DEVCFG Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format). [3:0] read-write SERIAL0 Single bit SPI flash on chip select 0 1 SERIAL1 Single bit SPI flash on chip select 1 2 DUAL0 Dual SPI flash on chip select 0 5 DUAL1 Dual bit SPI flash on chip select 1 6 QUAD0 Quad SPI flash on chip select 0 9 QUAD1 Quad SPI flash on chip select 1 10 OCTAL0 Octal SPI flash on chip select 0 13 OCTAL1 Octal SPI flash on chip select 1 14 QUADPAIRED Dual Quad SPI flash on chip selects 0/1. 15 QUADPAIRED_SERIAL Dual Quad SPI flash on chip selects 0/1, but transmit in serial mode for initialization operations 3 ADDR MSPI Transfer Address 0x00000008 32 read-write 0x00000000 0xFFFFFFFF ADDR Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR. [31:0] read-write INSTR MSPI Transfer Instruction 0x0000000C 32 read-write 0x00000000 0x0000FFFF INSTR Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE [15:0] read-write TXFIFO TX Data FIFO 0x00000010 32 read-write 0x00000000 0xFFFFFFFF TXFIFO Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set. [31:0] read-write RXFIFO RX Data FIFO 0x00000014 32 read-write 0x00000000 0xFFFFFFFF RXFIFO Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set. [31:0] read-write TXENTRIES TX FIFO Entries 0x00000018 32 read-write 0x00000000 0x0000001F TXENTRIES Number of 32-bit words/entries in TX FIFO [4:0] read-write RXENTRIES RX FIFO Entries 0x0000001C 32 read-write 0x00000000 0x0000001F RXENTRIES Number of 32-bit words/entries in RX FIFO [4:0] read-write THRESHOLD TX/RX FIFO Threshold Levels 0x00000020 32 read-write 0x00000000 0x00001F1F RXTHRESH Number of entries in TX FIFO that cause RXE interrupt [12:8] read-write TXTHRESH Number of entries in TX FIFO that cause TXF interrupt [4:0] read-write MSPICFG MSPI Module Configuration 0x00000100 32 read-write 0xC0000200 0xE0003F7F PRSTN Peripheral reset. Master reset to the entire MSPI module (DMA, XIP, and transfer state machines). 1=normal operation, 0=in reset. [31:31] read-write IPRSTN IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus. [30:30] read-write FIFORESET Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal operation. May be used to manually flush the FIFO in error handling. [29:29] read-write CLKDIV Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency, but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock pulse (to allow longer round-trip for read data). [13:8] read-write CLK48 48 MHz MSPI clock 1 CLK24 24 MHz MSPI clock 2 CLK12 12 MHz MSPI clock 4 CLK6 6 MHz MSPI clock 8 CLK3 3 MHz MSPI clock 16 CLK1_5 1.5 MHz MSPI clock 32 IOMSEL Selects which IOM is selected for CQ handshake status. [6:4] read-write IOM0 IOM0 0 IOM1 IOM1 1 IOM2 IOM2 2 IOM3 IOM3 3 IOM4 IOM4 4 IOM5 IOM5 5 DISABLED No IOM selected. Signals always zero. 7 TXNEG Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL). [3:3] read-write NORMAL TX launched from posedge internal clock 0 NEGEDGE TX data launched from negedge of internal clock 1 RXNEG Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation, it is expected that RXNEG will be set to 0. [2:2] read-write NORMAL RX data sampled on posedge of internal clock 0 NEGEDGE RX data sampled on negedge of internal clock 1 RXCAP Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However, to accommodate chip/pad/board delays, a setting of RXCAP of 1 is expected to be used to align the capture point with the return data window. This bit is used in conjunction with RXNEG to provide 4 unique capture points, all about 10 ns apart. [1:1] read-write NORMAL RX Capture phase aligns with CPHA setting 0 DELAY RX Capture phase is delayed from CPHA setting by one clock edge 1 APBCLK Enable continuous APB clock. For power-efficient operation, APBCLK should be set to 0. [0:0] read-write DIS Disable continuous clock. 0 EN Enable continuous clock. 1 PADCFG MSPI Output Pad Configuration 0x00000104 32 read-write 0x00000000 0x003F001F REVCS Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines [21:21] read-write IN3 Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7] [20:20] read-write IN2 Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6] [19:19] read-write IN1 Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5] [18:18] read-write IN0 Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5] [17:16] read-write OUT7 Output pad 7 configuration. 0=data[7] 1=data[3] [4:4] read-write OUT6 Output pad 6 configuration. 0=data[6] 1=data[2] [3:3] read-write OUT5 Output pad 5 configuration. 0=data[5] 1=data[1] [2:2] read-write OUT4 Output pad 4 configuration. 0=data[4] 1=data[0] [1:1] read-write OUT3 Output pad 3 configuration. 0=data[3] 1=CLK [0:0] read-write PADOUTEN MSPI Output Enable Pad Configuration 0x00000108 32 read-write 0x00000000 0x000001FF OUTEN Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data, [7:4] are Quad1 data, and [8] is clock. [8:0] read-write QUAD0 Quad0 (4 data + 1 clock) 271 QUAD1 Quad1 (4 data + 1 clock) 496 OCTAL Octal (8 data + 1 clock) 511 SERIAL0 Serial (2 data + 1 clock) 259 FLASH Configuration for XIP/DMA support of SPI flash modules. 0x0000010C 32 read-write 0x0B060000 0xFFFF07FD READINSTR Read command sent to flash for DMA/XIP operations [31:24] read-write WRITEINSTR Write command sent for DMA operations [23:16] read-write XIPMIXED Reserved. Set to 0x0 [10:8] read-write XIPSENDI Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG) [7:7] read-write XIPSENDA Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG) [6:6] read-write XIPENTURN Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles [5:5] read-write XIPBIGENDIAN Indicates whether XIP/AUTO DMA data transfers are in big or little endian format [4:4] read-write XIPACK Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only) [3:2] read-write NOACK No acknowledgment sent. Data IOs are tri-stated the first turnaround cycle 0 ACK Positive acknowledgment sent. Data IOs are driven to 0 the first turnaround cycle to acknowledge XIP mode 2 TERMINATE Negative acknowledgment sent. Data IOs are driven to 1 the first turnaround cycle to terminate XIP mode. XIPSENDI should be re-enabled for the next transfer 3 XIPEN Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF. [0:0] read-write SCRAMBLING External Flash Scrambling Controls 0x00000120 32 read-write 0x00000000 0x83FF03FF SCRENABLE Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0, data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range. [31:31] read-write SCREND Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range. [25:16] read-write SCRSTART Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range. [9:0] read-write INTEN MSPI Master Interrupts: Enable 0x00000200 32 read-write 0x00000000 0x00001FFF SCRERR Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address. [12:12] read-write CQERR Command Queue Error Interrupt [11:11] read-write CQPAUSED Command Queue is Paused. [10:10] read-write CQUPD Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts. [9:9] read-write CQCMP Command Queue Complete Interrupt [8:8] read-write DERR DMA Error Interrupt [7:7] read-write DCMP DMA Complete Interrupt [6:6] read-write RXF Receive FIFO full [5:5] read-write RXO Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall) [4:4] read-write RXU Receive FIFO underflow (only occurs when SW reads from an empty FIFO) [3:3] read-write TXO Transmit FIFO Overflow (only occurs when SW writes to a full FIFO). [2:2] read-write TXE Transmit FIFO empty. [1:1] read-write CMDCMP Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. [0:0] read-write INTSTAT MSPI Master Interrupts: Status 0x00000204 32 read-write 0x00000000 0x00001FFF SCRERR Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address. [12:12] read-write CQERR Command Queue Error Interrupt [11:11] read-write CQPAUSED Command Queue is Paused. [10:10] read-write CQUPD Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts. [9:9] read-write CQCMP Command Queue Complete Interrupt [8:8] read-write DERR DMA Error Interrupt [7:7] read-write DCMP DMA Complete Interrupt [6:6] read-write RXF Receive FIFO full [5:5] read-write RXO Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall) [4:4] read-write RXU Receive FIFO underflow (only occurs when SW reads from an empty FIFO) [3:3] read-write TXO Transmit FIFO Overflow (only occurs when SW writes to a full FIFO). [2:2] read-write TXE Transmit FIFO empty. [1:1] read-write CMDCMP Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. [0:0] read-write INTCLR MSPI Master Interrupts: Clear 0x00000208 32 read-write 0x00000000 0x00001FFF SCRERR Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address. [12:12] read-write CQERR Command Queue Error Interrupt [11:11] read-write CQPAUSED Command Queue is Paused. [10:10] read-write CQUPD Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts. [9:9] read-write CQCMP Command Queue Complete Interrupt [8:8] read-write DERR DMA Error Interrupt [7:7] read-write DCMP DMA Complete Interrupt [6:6] read-write RXF Receive FIFO full [5:5] read-write RXO Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall) [4:4] read-write RXU Receive FIFO underflow (only occurs when SW reads from an empty FIFO) [3:3] read-write TXO Transmit FIFO Overflow (only occurs when SW writes to a full FIFO). [2:2] read-write TXE Transmit FIFO empty. [1:1] read-write CMDCMP Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. [0:0] read-write INTSET MSPI Master Interrupts: Set 0x0000020C 32 read-write 0x00000000 0x00001FFF SCRERR Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address. [12:12] read-write CQERR Command Queue Error Interrupt [11:11] read-write CQPAUSED Command Queue is Paused. [10:10] read-write CQUPD Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts. [9:9] read-write CQCMP Command Queue Complete Interrupt [8:8] read-write DERR DMA Error Interrupt [7:7] read-write DCMP DMA Complete Interrupt [6:6] read-write RXF Receive FIFO full [5:5] read-write RXO Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall) [4:4] read-write RXU Receive FIFO underflow (only occurs when SW reads from an empty FIFO) [3:3] read-write TXO Transmit FIFO Overflow (only occurs when SW writes to a full FIFO). [2:2] read-write TXE Transmit FIFO empty. [1:1] read-write CMDCMP Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. [0:0] read-write DMACFG DMA Configuration 0x00000250 32 read-write 0x00000000 0x0004001F DMAPWROFF Power off MSPI domain upon completion of DMA operation. [18:18] read-write DMAPRI Sets the Priority of the DMA request [4:3] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 AUTO Auto Priority (priority raised once TX FIFO empties or RX FIFO fills) 2 DMADIR Direction [2:2] read-write P2M Peripheral to Memory (SRAM) transaction 0 M2P Memory to Peripheral transaction 1 DMAEN DMA Enable. Setting this bit to EN will start the DMA operation [1:0] read-write DIS Disable DMA Function 0 EN Enable HW controlled DMA Function to manage DMA to flash devices. HW will automatically handle issuance of instruction/address bytes based on settings in the FLASH register. 3 DMASTAT DMA Status 0x00000254 32 read-write 0x00000000 0x0000000F SCRERR Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR. [3:3] read-write DMAERR DMA Error. This active high bit signals that an error was encountered during the DMA operation. [2:2] read-write DMACPL DMA Transfer Complete. This signals the end of the DMA operation. [1:1] read-write DMATIP DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. [0:0] read-write DMATARGADDR DMA Target Address 0x00000258 32 read-write 0x00000000 0xFFFFFFFF TARGADDR Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. [31:0] read-write DMADEVADDR DMA Device Address 0x0000025C 32 read-write 0x00000000 0xFFFFFFFF DEVADDR SPI Device address for automated DMA transactions (both read and write). [31:0] read-write DMATOTCOUNT DMA Total Transfer Count 0x00000260 32 read-write 0x00000000 0x0000FFFF TOTCOUNT Total Transfer Count in bytes. [15:0] read-write DMABCOUNT DMA BYTE Transfer Count 0x00000264 32 read-write 0x00000000 0x000000FF BCOUNT Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended values are 16 or 32. [7:0] read-write DMATHRESH DMA Transmit Trigger Threshold 0x00000278 32 read-write 0x00000008 0x0000000F DMATHRESH DMA transfer FIFO level trigger. For read operations, DMA is triggered when the FIFO level is greater than this value. For write operations, DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT bytes. [3:0] read-write CQCFG Command Queue Configuration 0x000002A0 32 read-write 0x00000000 0x0000000F CQAUTOCLEARMASK Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ. [3:3] read-write CQPWROFF Power off MSPI domain upon completion of DMA operation. [2:2] read-write CQPRI Sets the Priority of the command queue DMA request [1:1] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 CQEN Command queue enable. When set, will enable the processing of the command queue [0:0] read-write DIS Disable CQ Function 0 EN Enable CQ Function 1 CQADDR CQ Target Read Address 0x000002A8 32 read-write 0x00000000 0x1FFFFFFF CQADDR Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary. [28:0] read-write CQSTAT Command Queue Status 0x000002AC 32 read-write 0x00000000 0x0000000F CQPAUSED Command queue is currently paused status. [3:3] read-write CQERR Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation. [2:2] read-write CQCPL Command queue operation Complete. This signals the end of the command queue operation. [1:1] read-write CQTIP Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event. [0:0] read-write CQFLAGS Command Queue Flags 0x000002B0 32 read-write 0x00000000 0x0000FFFF CQFLAGS Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status. [15:0] read-write STOP CQ Stop Flag. When set, CQ processing will complete. 32768 CQIDX CQ Index Pointers (CURIDX/ENDIDX) match. 16384 DMACPL DMA Complete Status (hardwired DMACPL bit in DMASTAT) 2048 CMDCPL PIO Operation completed (STATUS bit in CTRL register) 1024 IOM1READY IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer. 512 IOM0READY IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer. 256 SWFLAG7 Software flag 7. Can be used by software to start/pause operations. 128 SWFLAG6 Software flag 6. Can be used by software to start/pause operations. 64 SWFLAG5 Software flag 5. Can be used by software to start/pause operations. 32 SWFLAG4 Software flag 4. Can be used by software to start/pause operations. 16 SWFLAG3 Software flag 3. Can be used by software to start/pause operations. 8 SWFLAG2 Software flag 2. Can be used by software to start/pause operations. 4 SWFLAG1 Software flag 1. Can be used by software to start/pause operations. 2 SWFLAG0 Software flag 0. Can be used by software to start/pause operations. 1 CQSETCLEAR Command Queue Flag Set/Clear 0x000002B4 32 read-write 0x00000000 0x00FFFFFF CQFCLR Clear CQFlag status bits. [23:16] read-write CQFTOGGLE Toggle CQFlag status bits [15:8] read-write CQFSET Set CQFlag status bits. Set has priority over clear if both are high. [7:0] read-write CQPAUSE Command Queue Pause Mask 0x000002B8 32 read-write 0x00000000 0x0000FFFF CQMASK CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK. [15:0] read-write STOP CQ Stop Flag. When set, CQ processing will complete. 32768 CQIDX CQ Index Pointers (CURIDX/ENDIDX) match. 16384 DMACPL DMA Complete Status (hardwired DMACPL bit in DMASTAT) 2048 CMDCPL PIO Operation completed (STATUS bit in CTRL register) 1024 IOM1READY IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer. 512 IOM0READY IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer. 256 SWFLAG7 Software flag 7. Can be used by software to start/pause operations. 128 SWFLAG6 Software flag 6. Can be used by software to start/pause operations. 64 SWFLAG5 Software flag 5. Can be used by software to start/pause operations. 32 SWFLAG4 Software flag 4. Can be used by software to start/pause operations. 16 SWFLAG3 Software flag 3. Can be used by software to start/pause operations. 8 SWFLAG2 Software flag 2. Can be used by software to start/pause operations. 4 SWFLAG1 Software flag 1. Can be used by software to start/pause operations. 2 SWFLAG0 Software flag 0. Can be used by software to start/pause operations. 1 CQCURIDX Command Queue Current Index 0x000002C0 32 read-write 0x00000000 0x000000FF CQCURIDX Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal, allowing SW to pause the CQ processing until the end index is updated. [7:0] read-write CQENDIDX Command Queue End Index 0x000002C4 32 read-write 0x00000000 0x000000FF CQENDIDX Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer. [7:0] read-write PDM 1.0 PDM Audio 0x50011000 32 read-write 0 0x00000294 registers PDM 19 PCFG PDM Configuration Register 0x00000000 32 read-write 0x0000C365 0xFFE7FFFF LRSWAP Left/right channel swap. [31:31] read-write EN Swap left and right channels (FIFO Read RIGHT_LEFT). 1 NOSWAP No channel swapping (IFO Read LEFT_RIGHT). 0 PGARIGHT Right channel PGA gain. [30:26] read-write P405DB 40.5 db gain. 31 P390DB 39.0 db gain. 30 P375DB 37.5 db gain. 29 P360DB 36.0 db gain. 28 P345DB 34.5 db gain. 27 P330DB 33.0 db gain. 26 P315DB 31.5 db gain. 25 P300DB 30.0 db gain. 24 P285DB 28.5 db gain. 23 P270DB 27.0 db gain. 22 P255DB 25.5 db gain. 21 P240DB 24.0 db gain. 20 P225DB 22.5 db gain. 19 P210DB 21.0 db gain. 18 P195DB 19.5 db gain. 17 P180DB 18.0 db gain. 16 P165DB 16.5 db gain. 15 P150DB 15.0 db gain. 14 P135DB 13.5 db gain. 13 P120DB 12.0 db gain. 12 P105DB 10.5 db gain. 11 P90DB 9.0 db gain. 10 P75DB 7.5 db gain. 9 P60DB 6.0 db gain. 8 P45DB 4.5 db gain. 7 P30DB 3.0 db gain. 6 P15DB 1.5 db gain. 5 0DB 0.0 db gain. 4 M15DB -1.5 db gain. 3 M300DB -3.0 db gain. 2 M45DB -4.5 db gain. 1 M60DB -6.0 db gain. 0 PGALEFT Left channel PGA gain. [25:21] read-write P405DB 40.5 db gain. 31 P390DB 39.0 db gain. 30 P375DB 37.5 db gain. 29 P360DB 36.0 db gain. 28 P345DB 34.5 db gain. 27 P330DB 33.0 db gain. 26 P315DB 31.5 db gain. 25 P300DB 30.0 db gain. 24 P285DB 28.5 db gain. 23 P270DB 27.0 db gain. 22 P255DB 25.5 db gain. 21 P240DB 24.0 db gain. 20 P225DB 22.5 db gain. 19 P210DB 21.0 db gain. 18 P195DB 19.5 db gain. 17 P180DB 18.0 db gain. 16 P165DB 16.5 db gain. 15 P150DB 15.0 db gain. 14 P135DB 13.5 db gain. 13 P120DB 12.0 db gain. 12 P105DB 10.5 db gain. 11 P90DB 9.0 db gain. 10 P75DB 7.5 db gain. 9 P60DB 6.0 db gain. 8 P45DB 4.5 db gain. 7 P30DB 3.0 db gain. 6 P15DB 1.5 db gain. 5 0DB 0.0 db gain. 4 M15DB -1.5 db gain. 3 M300DB -3.0 db gain. 2 M45DB -4.5 db gain. 1 M60DB -6.0 db gain. 0 MCLKDIV PDM_CLK frequency divisor. [18:17] read-write MCKDIV4 Divide input clock by 4 3 MCKDIV3 Divide input clock by 3 2 MCKDIV2 Divide input clock by 2 1 MCKDIV1 Divide input clock by 1 0 SINCRATE SINC decimation rate. [16:10] read-write ADCHPD High pass filter control. [9:9] read-write EN Enable high pass filter. 0 DIS Disable high pass filter. 1 HPCUTOFF High pass filter coefficients. [8:5] read-write CYCLES Number of clocks during gain-setting changes. [4:2] read-write SOFTMUTE Soft mute control. [1:1] read-write EN Enable Soft Mute. 1 DIS Disable Soft Mute. 0 PDMCOREEN Data Streaming Control. [0:0] read-write EN Enable Data Streaming. 1 DIS Disable Data Streaming. 0 VCFG Voice Configuration Register 0x00000004 32 read-write 0x00000008 0xFC1B0118 IOCLKEN Enable the IO clock. [31:31] read-write DIS Disable FIFO read. 0 EN Enable FIFO read. 1 RSTB Reset the IP core. [30:30] read-write RESET Reset the core. 0 NORM Enable the core. 1 PDMCLKSEL Select the PDM input clock. [29:27] read-write DISABLE Static value. 0 12MHz PDM clock is 12 MHz. 1 6MHz PDM clock is 6 MHz. 2 3MHz PDM clock is 3 MHz. 3 1_5MHz PDM clock is 1.5 MHz. 4 750KHz PDM clock is 750 KHz. 5 375KHz PDM clock is 375 KHz. 6 187KHz PDM clock is 187.5 KHz. 7 PDMCLKEN Enable the serial clock. [26:26] read-write DIS Disable serial clock. 0 EN Enable serial clock. 1 I2SEN I2S interface enable. [20:20] read-write DIS Disable I2S interface. 0 EN Enable I2S interface. 1 BCLKINV I2S BCLK input inversion. [19:19] read-write INV BCLK inverted. 0 NORM BCLK not inverted. 1 DMICKDEL PDM clock sampling delay. [17:17] read-write 0CYC No delay. 0 1CYC 1 cycle delay. 1 SELAP Select PDM input clock source. [16:16] read-write I2S Clock source from I2S BCLK. 1 INTERNAL Clock source from internal clock generator. 0 PCMPACK PCM data packing enable. [8:8] read-write DIS Disable PCM packing. 0 EN Enable PCM packing. 1 CHSET Set PCM channels. [4:3] read-write DIS Channel disabled. 0 LEFT Mono left channel. 1 RIGHT Mono right channel. 2 STEREO Stereo channels. 3 VOICESTAT Voice Status Register 0x00000008 32 read-write 0x00000000 0x0000003F FIFOCNT Valid 32-bit entries currently in the FIFO. [5:0] read-write FIFOREAD FIFO Read 0x0000000C 32 read-write 0x00000000 0xFFFFFFFF FIFOREAD FIFO read data. [31:0] read-write FIFOFLUSH FIFO Flush 0x00000010 32 read-write 0x00000000 0x00000001 FIFOFLUSH FIFO FLUSH. [0:0] read-write FIFOTHR FIFO Threshold 0x00000014 32 read-write 0x00000010 0x0000001F FIFOTHR FIFO Threshold value. When the FIFO count is equal to, or larger than this value (in words), a THR interrupt is generated (if enabled) [4:0] read-write INTEN IO Master Interrupts: Enable 0x00000200 32 read-write 0x00000000 0x0000001F DERR DMA Error receieved [4:4] read-write DCMP DMA completed a transfer [3:3] read-write UNDFL This is the FIFO underflow interrupt. [2:2] read-write OVF This is the FIFO overflow interrupt. [1:1] read-write THR This is the FIFO threshold interrupt. [0:0] read-write INTSTAT IO Master Interrupts: Status 0x00000204 32 read-write 0x00000000 0x0000001F DERR DMA Error receieved [4:4] read-write DCMP DMA completed a transfer [3:3] read-write UNDFL This is the FIFO underflow interrupt. [2:2] read-write OVF This is the FIFO overflow interrupt. [1:1] read-write THR This is the FIFO threshold interrupt. [0:0] read-write INTCLR IO Master Interrupts: Clear 0x00000208 32 read-write 0x00000000 0x0000001F DERR DMA Error receieved [4:4] read-write DCMP DMA completed a transfer [3:3] read-write UNDFL This is the FIFO underflow interrupt. [2:2] read-write OVF This is the FIFO overflow interrupt. [1:1] read-write THR This is the FIFO threshold interrupt. [0:0] read-write INTSET IO Master Interrupts: Set 0x0000020C 32 read-write 0x00000000 0x0000001F DERR DMA Error receieved [4:4] read-write DCMP DMA completed a transfer [3:3] read-write UNDFL This is the FIFO underflow interrupt. [2:2] read-write OVF This is the FIFO overflow interrupt. [1:1] read-write THR This is the FIFO threshold interrupt. [0:0] read-write DMATRIGEN DMA Trigger Enable Register 0x00000240 32 read-write 0x00000000 0x00000003 DTHR90 Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function [1:1] read-write DTHR Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD,at granularity of 16 bytes only [0:0] read-write DMATRIGSTAT DMA Trigger Status Register 0x00000244 32 read-write 0x00000000 0x00000003 DTHR90STAT Triggered DMA from FIFO reaching 90 percent full [1:1] read-write DTHRSTAT Triggered DMA from FIFO reaching threshold [0:0] read-write DMACFG DMA Configuration Register 0x00000280 32 read-write 0x00000000 0x00000705 DPWROFF Power Off the ADC System upon DMACPL. [10:10] read-write DAUTOHIP Raise priority to high on fifo full, and DMAPRI set to low [9:9] read-write DMAPRI Sets the Priority of the DMA request [8:8] read-write LOW Low Priority (service as best effort) 0 HIGH High Priority (service immediately) 1 DMADIR Direction [2:2] read-write P2M Peripheral to Memory (SRAM) transaction. THe PDM module will only DMA to memory. 0 M2P Memory to Peripheral transaction. Not available for PDM module 1 DMAEN DMA Enable [0:0] read-write DIS Disable DMA Function 0 EN Enable DMA Function 1 DMATOTCOUNT DMA Total Transfer Count 0x00000288 32 read-write 0x00000000 0x000FFFFF TOTCOUNT Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns. [19:0] read-write DMATARGADDR DMA Target Address Register 0x0000028C 32 read-write 0x10000000 0xFFFFFFFF UTARGADDR SRAM Target [31:20] read-write LTARGADDR DMA Target Address. This register is not updated with the current address of the DMA, but will remain static with the original address during the DMA transfer. [19:0] read-write DMASTAT DMA Status Register 0x00000290 32 read-write 0x00000000 0x00000007 DMAERR DMA Error [2:2] read-write DMACPL DMA Transfer Complete [1:1] read-write DMATIP DMA Transfer In Progress [0:0] read-write PWRCTRL 1.0 PWR Controller Register Bank 0x40021000 32 read-write 0 0x00000030 registers SUPPLYSRC Voltage Regulator Select Register 0x00000000 32 read-write 0x00000000 0x00000001 BLEBUCKEN Enables and Selects the BLE Buck as the supply for the BLE power domain or for Burst LDO. It takes the initial value from Customer INFO space. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed. [0:0] read-write EN Enable the BLE Buck. 1 DIS Disable the BLE Buck. 0 SUPPLYSTATUS Voltage Regulators status 0x00000004 32 read-write 0x00000000 0x00000003 BLEBUCKON Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate reature is allowed. [1:1] read-write LDO Indicates the the LDO is supplying the BLE/Burst power domain 0 BUCK Indicates the the Buck is supplying the BLE/Burst power domain 1 SIMOBUCKON Indicates whether the Core/Mem low-voltage domains are supplied from the LDO or the Buck. [0:0] read-write OFF Indicates the the SIMO Buck is OFF. 0 ON Indicates the the SIMO Buck is ON. 1 DEVPWREN Device Power Enables 0x00000008 32 read-write 0x00000000 0x00003FFF PWRBLEL Power up BLE controller [13:13] read-write EN Power up BLE controller 1 DIS Power down BLE controller 0 PWRPDM Power up PDM block [12:12] read-write EN Power up PDM 1 DIS Power down PDM 0 PWRMSPI Power up MSPI Controller [11:11] read-write EN Power up MSPI 1 DIS Power down MSPI 0 PWRSCARD Power up SCARD Controller [10:10] read-write EN Power up SCARD 1 DIS Power down SCARD 0 PWRADC Power up ADC Digital Controller [9:9] read-write EN Power up ADC 1 DIS Power Down ADC 0 PWRUART1 Power up UART Controller 1 [8:8] read-write EN Power up UART 1 1 DIS Power down UART 1 0 PWRUART0 Power up UART Controller 0 [7:7] read-write EN Power up UART 0 1 DIS Power down UART 0 0 PWRIOM5 Power up IO Master 5 [6:6] read-write EN Power up IO Master 5 1 DIS Power down IO Master 5 0 PWRIOM4 Power up IO Master 4 [5:5] read-write EN Power up IO Master 4 1 DIS Power down IO Master 4 0 PWRIOM3 Power up IO Master 3 [4:4] read-write EN Power up IO Master 3 1 DIS Power down IO Master 3 0 PWRIOM2 Power up IO Master 2 [3:3] read-write EN Power up IO Master 2 1 DIS Power down IO Master 2 0 PWRIOM1 Power up IO Master 1 [2:2] read-write EN Power up IO Master 1 1 DIS Power down IO Master 1 0 PWRIOM0 Power up IO Master 0 [1:1] read-write EN Power up IO Master 0 1 DIS Power down IO Master 0 0 PWRIOS Power up IO Slave [0:0] read-write EN Power up IO slave 1 DIS Power down IO slave 0 MEMPWDINSLEEP Powerdown SRAM banks in Deep Sleep mode 0x0000000C 32 read-write 0x00006000 0x80007FFF CACHEPWDSLP power down cache in deep sleep [31:31] read-write EN Power down cache in deep sleep 1 DIS Retain cache in deep sleep 0 FLASH1PWDSLP Powerdown flash1 in deep sleep [14:14] read-write EN Flash1 is powered down during deepsleep 1 DIS Flash1 is kept powered on during deepsleep 0 FLASH0PWDSLP Powerdown flash0 in deep sleep [13:13] read-write EN Flash0 is powered down during deepsleep 1 DIS Flash0 is kept powered on during deepsleep 0 SRAMPWDSLP Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost. [12:3] read-write NONE All banks retained 0 GROUP0 SRAM GROUP0 powered down (64KB-96KB) 1 GROUP1 SRAM GROUP1 powered down (96KB-128KB) 2 GROUP2 SRAM GROUP2 powered down (128KB-160KB) 4 GROUP3 SRAM GROUP3 powered down (160KB-192KB) 8 GROUP4 SRAM GROUP4 powered down (192KB-224KB) 16 GROUP5 SRAM GROUP5 powered down (224KB-256KB) 32 GROUP6 SRAM GROUP6 powered down (256KB-288KB) 64 GROUP7 SRAM GROUP7 powered down (288KB-320KB) 128 GROUP8 SRAM GROUP8 powered down (320KB-352KB) 256 GROUP9 SRAM GROUP9 powered down (352KB-384KB) 512 SRAM64K Powerdown lower 64k SRAM (64KB-128KB) 3 SRAM128K Powerdown lower 128k SRAM (64KB-192KB) 15 ALLBUTLOWER32K All SRAM banks but lower 32k powered down (96KB-384KB). 1022 ALLBUTLOWER64K All banks but lower 64k powered down. 1020 ALLBUTLOWER128K All banks but lower 128k powered down. 1008 ALL All banks powered down. 1023 DTCMPWDSLP power down DTCM in deep sleep [2:0] read-write NONE All DTCM retained 0 GROUP0DTCM0 Group0_DTCM0 powered down in deep sleep (0KB-8KB) 1 GROUP0DTCM1 Group0_DTCM1 powered down in deep sleep (8KB-32KB) 2 GROUP0 Both DTCMs in group0 are powered down in deep sleep (0KB-32KB) 3 ALLBUTGROUP0DTCM0 Group1 and Group0_DTCM1 are powered down in deep sleep (8KB-64KB) 6 GROUP1 Group1 DTCM powered down in deep sleep (32KB-64KB) 4 ALL All DTCMs powered down in deep sleep (0KB-64KB) 7 MEMPWREN Enables individual banks of the MEMORY array 0x00000010 32 read-write 0xC0007FFF 0xC0007FFF CACHEB2 Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank2, cache has to be enabled and this bit has to be set. [31:31] read-write EN Power up Cache Bank 2 1 DIS Power down Cache Bank 2 0 CACHEB0 Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank0, cache has to be enabled and this bit has to be set. [30:30] read-write EN Power up Cache Bank 0 1 DIS Power down Cache Bank 0 0 FLASH1 Power up Flash1 [14:14] read-write EN Power up Flash1 1 DIS Power down Flash1 0 FLASH0 Power up Flash0 [13:13] read-write EN Power up Flash0 1 DIS Power down Flash0 0 SRAM Power up SRAM groups [12:3] read-write NONE Do not power ON any of the SRAM banks 0 GROUP0 Power ON only SRAM group0 (0KB-32KB) 1 GROUP1 Power ON only SRAM group1 (32KB-64KB) 2 GROUP2 Power ON only SRAM group2 (64KB-96KB) 4 GROUP3 Power ON only SRAM group3 (96KB-128KB) 8 GROUP4 Power ON only SRAM group4 (128KB-160KB) 16 GROUP5 Power ON only SRAM group5 (160KB-192KB) 32 GROUP6 Power ON only SRAM group6 (192KB-224KB) 64 GROUP7 Power ON only SRAM group7 (224KB-256KB) 128 GROUP8 Power ON only SRAM group8 (256KB-288KB) 256 GROUP9 Power ON only SRAM group9 (288KB-320KB) 512 SRAM64K Power ON only lower 64k 3 SRAM128K Power ON only lower 128k 15 SRAM256K Power ON only lower 256k 255 ALL All SRAM banks (320K) powered ON 1023 DTCM Power up DTCM [2:0] read-write NONE Do not enable power to any DTCMs 0 GROUP0DTCM0 Power ON only GROUP0_DTCM0 1 GROUP0DTCM1 Power ON only GROUP0_DTCM1 2 GROUP0 Power ON only DTCMs in group0 3 GROUP1 Power ON only DTCMs in group1 4 ALL Power ON all DTCMs 7 MEMPWRSTATUS Mem Power ON Status 0x00000014 32 read-write 0x00007FFF 0x0001FFFF CACHEB2 This bit is 1 if power is supplied to Cache Bank 2 [16:16] read-write CACHEB0 This bit is 1 if power is supplied to Cache Bank 0 [15:15] read-write FLASH1 This bit is 1 if power is supplied to FLASH 1 [14:14] read-write FLASH0 This bit is 1 if power is supplied to FLASH 0 [13:13] read-write SRAM9 This bit is 1 if power is supplied to SRAM GROUP9 [12:12] read-write SRAM8 This bit is 1 if power is supplied to SRAM GROUP8 [11:11] read-write SRAM7 This bit is 1 if power is supplied to SRAM GROUP7 [10:10] read-write SRAM6 This bit is 1 if power is supplied to SRAM GROUP6 [9:9] read-write SRAM5 This bit is 1 if power is supplied to SRAM GROUP5 [8:8] read-write SRAM4 This bit is 1 if power is supplied to SRAM GROUP4 [7:7] read-write SRAM3 This bit is 1 if power is supplied to SRAM GROUP3 [6:6] read-write SRAM2 This bit is 1 if power is supplied to SRAM GROUP2 [5:5] read-write SRAM1 This bit is 1 if power is supplied to SRAM GROUP1 [4:4] read-write SRAM0 This bit is 1 if power is supplied to SRAM GROUP0 [3:3] read-write DTCM1 This bit is 1 if power is supplied to DTCM GROUP1 [2:2] read-write DTCM01 This bit is 1 if power is supplied to DTCM GROUP0_1 [1:1] read-write DTCM00 This bit is 1 if power is supplied to DTCM GROUP0_0 [0:0] read-write DEVPWRSTATUS Device Power ON Status 0x00000018 32 read-write 0x00000003 0x000003FF BLEH This bit is 1 if power is supplied to BLEH [9:9] read-write BLEL This bit is 1 if power is supplied to BLEL [8:8] read-write PWRPDM This bit is 1 if power is supplied to PDM [7:7] read-write PWRMSPI This bit is 1 if power is supplied to MSPI [6:6] read-write PWRADC This bit is 1 if power is supplied to ADC [5:5] read-write HCPC This bit is 1 if power is supplied to HCPC domain (IO MASTER4, 5, 6) [4:4] read-write HCPB This bit is 1 if power is supplied to HCPB domain (IO MASTER 0, 1, 2) [3:3] read-write HCPA This bit is 1 if power is supplied to HCPA domain (IO SLAVE, UART0, UART1, SCARD) [2:2] read-write MCUH This bit is 1 if power is supplied to MCUH [1:1] read-write MCUL This bit is 1 if power is supplied to MCUL [0:0] read-write SRAMCTRL SRAM Control register 0x0000001C 32 read-write 0x00000000 0x000FFF06 SRAMLIGHTSLEEP Light Sleep enable for each TCM/SRAM bank. When 1, corresponding bank will be put into light sleep. For optimal power, banks should be put into light sleep while the system is active but the bank has minimal or no accesses. [19:8] read-write ALL Enable LIGHT SLEEP for ALL SRAMs 255 DIS Disables LIGHT SLEEP for ALL SRAMs 0 SRAMMASTERCLKGATE This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block) [2:2] read-write EN Enable Master SRAM Clock Gate 1 DIS Disables Master SRAM Clock Gating 0 SRAMCLKGATE This bit is 1 if clock gating is allowed for individual system SRAMs [1:1] read-write EN Enable Individual SRAM Clock Gating 1 DIS Disables Individual SRAM Clock Gating 0 ADCSTATUS Power Status Register for ADC Block 0x00000020 32 read-write 0x0000003F 0x0000003F REFBUFPWD This bit indicates that the ADC REFBUF is powered down [5:5] read-write REFKEEPPWD This bit indicates that the ADC REFKEEP is powered down [4:4] read-write VBATPWD This bit indicates that the ADC VBAT resistor divider is powered down [3:3] read-write VPTATPWD This bit indicates that the ADC temperature sensor input buffer is powered down [2:2] read-write BGTPWD This bit indicates that the ADC Band Gap is powered down [1:1] read-write ADCPWD This bit indicates that the ADC is powered down [0:0] read-write MISC Power Optimization Control Bits 0x00000024 32 read-write 0x00000000 0x00000048 MEMVRLPBLE Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or BLEH is powered on given none of the other domains require it. [6:6] read-write EN Mem VR can go to lp mode even when BLE is powered on. 1 DIS Mem VR will stay in active mode when BLE is powered on. 0 FORCEMEMVRLPTIMERS Control Bit to force Mem VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running. [3:3] read-write DEVPWREVENTEN Event enable register to control which DEVPWRSTATUS bits are routed to event input of CPU. 0x00000028 32 read-write 0x00000000 0xE00001FF BURSTEVEN Control BURST status event [31:31] read-write EN Enable BURST status event 1 DIS Disable BURST status event 0 BURSTFEATUREEVEN Control BURSTFEATURE status event [30:30] read-write EN Enable BURSTFEATURE status event 1 DIS Disable BURSTFEATURE status event 0 BLEFEATUREEVEN Control BLEFEATURE status event [29:29] read-write EN Enable BLEFEATURE status event 1 DIS Disable BLEFEATURE status event 0 BLELEVEN Control BLE power-on status event [8:8] read-write EN Enable BLE power-on status event 1 DIS Disable BLE power-on status event 0 PDMEVEN Control PDM power-on status event [7:7] read-write EN Enable PDM power-on status event 1 DIS Disable PDM power-on status event 0 MSPIEVEN Control MSPI power-on status event [6:6] read-write EN Enable MSPI power-on status event 1 DIS Disable MSPI power-on status event 0 ADCEVEN Control ADC power-on status event [5:5] read-write EN Enable ADC power-on status event 1 DIS Disable ADC power-on status event 0 HCPCEVEN Control HCPC power-on status event [4:4] read-write EN Enable HCPC power-on status event 1 DIS Disable HCPC power-on status event 0 HCPBEVEN Control HCPB power-on status event [3:3] read-write EN Enable HCPB power-on status event 1 DIS Disable HCPB power-on status event 0 HCPAEVEN Control HCPA power-on status event [2:2] read-write EN Enable HCPA power-on status event 1 DIS Disable HCPA power-on status event 0 MCUHEVEN Control MCUH power-on status event [1:1] read-write EN Enable MCHU power-on status event 1 DIS Disable MCUH power-on status event 0 MCULEVEN Control MCUL power-on status event [0:0] read-write EN Enable MCUL power-on status event 1 DIS Disable MCUL power-on status event 0 MEMPWREVENTEN Event enable register to control which MEMPWRSTATUS bits are routed to event input of CPU. 0x0000002C 32 read-write 0x00000000 0xC0007FFF CACHEB2EN Control CACHEB2 power-on status event [31:31] read-write EN Enable CACHE BANK 2 status event 1 DIS Disable CACHE BANK 2 status event 0 CACHEB0EN Control CACHE BANK 0 power-on status event [30:30] read-write EN Enable CACHE BANK 0 status event 1 DIS Disable CACHE BANK 0 status event 0 FLASH1EN Control Flash power-on status event [14:14] read-write EN Enable FLASH status event 1 DIS Disables FLASH status event 0 FLASH0EN Control Flash power-on status event [13:13] read-write EN Enable FLASH status event 1 DIS Disables FLASH status event 0 SRAMEN Control SRAM power-on status event [12:3] read-write NONE Disable SRAM power-on status event 0 GROUP0EN Enable SRAM group0 (0KB-32KB) power on status event 1 GROUP1EN Enable SRAM group1 (32KB-64KB) power on status event 2 GROUP2EN Enable SRAM group2 (64KB-96KB) power on status event 4 GROUP3EN Enable SRAM group3 (96KB-128KB) power on status event 8 GROUP4EN Enable SRAM group4 (128KB-160KB) power on status event 16 GROUP5EN Enable SRAM group5 (160KB-192KB) power on status event 32 GROUP6EN Enable SRAM group6 (192KB-224KB) power on status event 64 GROUP7EN Enable SRAM group7 (224KB-256KB) power on status event 128 GROUP8EN Enable SRAM group8 (256KB-288KB) power on status event 256 GROUP9EN Enable SRAM group9 (288KB-320KB) power on status event 512 DTCMEN Enable DTCM power-on status event [2:0] read-write NONE Do not enable DTCM power-on status event 0 GROUP0DTCM0EN Enable GROUP0_DTCM0 power on status event 1 GROUP0DTCM1EN Enable GROUP0_DTCM1 power on status event 2 GROUP0EN Enable DTCMs in group0 power on status event 3 GROUP1EN Enable DTCMs in group1 power on status event 4 ALL Enable all DTCM power on status event 7 RSTGEN 1.0 MCU Reset Generator 0x40000000 32 read-write 0 0x0FFFF004 registers CFG Configuration Register 0x00000000 32 read-write 0x00000000 0x00000003 WDREN Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset. This includes enabling the RESEN bit in WDTCFG register in Watch dog timer block. [1:1] read-write BODHREN Brown out high (2.1v) reset enable. [0:0] read-write SWPOI Software POI Reset 0x00000004 32 read-write 0x00000000 0x000000FF SWPOIKEY 0x1B generates a software POI reset. This is a write-only register. Reading from this register will yield only all 0s. [7:0] read-write KEYVALUE Writing 0x1B key value generates a software POI reset. 27 SWPOR Software POR Reset 0x00000008 32 read-write 0x00000000 0x000000FF SWPORKEY 0xD4 generates a software POR reset. [7:0] read-write KEYVALUE Writing 0xD4 key value generates a software POR reset. 212 TPIURST TPIU reset 0x00000014 32 read-write 0x00000000 0x00000001 TPIURST Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset. [0:0] read-write INTEN Reset Interrupt register: Enable 0x00000200 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write INTSTAT Reset Interrupt register: Status 0x00000204 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write INTCLR Reset Interrupt register: Clear 0x00000208 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write INTSET Reset Interrupt register: Set 0x0000020C 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write STAT Status Register (SBL) 0x0FFFF000 32 read-write 0x00000000 0xC00007FF SBOOT Set when booting securely (SBL). [31:31] read-write FBOOT Set if current boot was initiated by soft reset and resulted in Fast Boot (SBL). [30:30] read-write BOBSTAT A BLE/Burst Regulator Brownout Event occurred (SBL). [10:10] read-write BOFSTAT A Memory Regulator Brownout Event occurred (SBL). [9:9] read-write BOCSTAT A Core Regulator Brownout Event occurred (SBL). [8:8] read-write BOUSTAT An Unregulated Supply Brownout Event occurred (SBL). [7:7] read-write WDRSTAT Reset was initiated by a Watchdog Timer Reset (SBL). [6:6] read-write DBGRSTAT Reset was a initiated by Debugger Reset (SBL). [5:5] read-write POIRSTAT Reset was a initiated by Software POI Reset (SBL). [4:4] read-write SWRSTAT Reset was a initiated by SW POR or AIRCR Reset (SBL). [3:3] read-write BORSTAT Reset was initiated by a Brown-Out Reset (SBL). [2:2] read-write PORSTAT Reset was initiated by a Power-On Reset (SBL). [1:1] read-write EXRSTAT Reset was initiated by an External Reset (SBL). [0:0] read-write RTC 1.0 Real Time Clock 0x40004200 32 read-write 0 0x00000110 registers RTC 2 CTRLOW RTC Counters Lower 0x00000040 32 read-write 0x01000000 0x3F7F7FFF CTRHR Hours Counter [29:24] read-write CTRMIN Minutes Counter [22:16] read-write CTRSEC Seconds Counter [14:8] read-write CTR100 100ths of a second Counter [7:0] read-write CTRUP RTC Counters Upper 0x00000044 32 read-write 0x00000000 0x9FFF1F3F CTERR Counter read error status. Error is triggered when software reads the lower word of the counters, and fails to read the upper counter within 1/100 second. This is because when the lower counter is read, the upper counter is held off from incrementing until it is read so that the full time stamp can be read. [31:31] read-write NOERR No read error occurred 0 RDERR Read error occurred 1 CEB Century enable [28:28] read-write DIS Disable the Century bit from changing 0 EN Enable the Century bit to change 1 CB Century [27:27] read-write 2000 Century is 2000s 0 1900_2100 Century is 1900s/2100s 1 CTRWKDY Weekdays Counter [26:24] read-write CTRYR Years Counter [23:16] read-write CTRMO Months Counter [12:8] read-write CTRDATE Date Counter [5:0] read-write ALMLOW RTC Alarms Lower 0x00000048 32 read-write 0x00000000 0x3F7F7FFF ALMHR Hours Alarm [29:24] read-write ALMMIN Minutes Alarm [22:16] read-write ALMSEC Seconds Alarm [14:8] read-write ALM100 100ths of a second Alarm [7:0] read-write ALMUP RTC Alarms Upper 0x0000004C 32 read-write 0x00000000 0x00071F3F ALMWKDY Weekdays Alarm [18:16] read-write ALMMO Months Alarm [12:8] read-write ALMDATE Date Alarm [5:0] read-write RTCCTL RTC Control Register 0x00000050 32 read-write 0x00000000 0x0000003F HR1224 Hours Counter mode [5:5] read-write 24HR Hours in 24 hour mode 0 12HR Hours in 12 hour mode 1 RSTOP RTC input clock control [4:4] read-write RUN Allow the RTC input clock to run 0 STOP Stop the RTC input clock 1 RPT Alarm repeat interval [3:1] read-write DIS Alarm interrupt disabled 0 YEAR Interrupt every year 1 MONTH Interrupt every month 2 WEEK Interrupt every week 3 DAY Interrupt every day 4 HR Interrupt every hour 5 MIN Interrupt every minute 6 SEC Interrupt every second/10th/100th 7 WRTC Counter write control [0:0] read-write DIS Counter writes are disabled 0 EN Counter writes are enabled 1 INTEN RTC Interrupt Register: Enable 0x00000100 32 read-write 0x00000000 0x00000001 ALM RTC Alarm interrupt [0:0] read-write INTSTAT RTC Interrupt Register: Status 0x00000104 32 read-write 0x00000000 0x00000001 ALM RTC Alarm interrupt [0:0] read-write INTCLR RTC Interrupt Register: Clear 0x00000108 32 read-write 0x00000000 0x00000001 ALM RTC Alarm interrupt [0:0] read-write INTSET RTC Interrupt Register: Set 0x0000010C 32 read-write 0x00000000 0x00000001 ALM RTC Alarm interrupt [0:0] read-write SCARD 1.0 Serial ISO7816 0x40080000 32 read-write 0 0x00000104 registers SCARD 17 SR ISO7816 interrupt status 0x00000000 32 read-write 0x00000000 0x0000007F FHF FIFO Half Full. [6:6] read-write HALFFULL FIFO is half full. 1 FT2REND TX to RX finished. [5:5] read-write CMPL TX to RX completed. 1 NOTCMPL TX to RX not completed. 0 PE Parity Error. [4:4] read-write PEERR Parity error. 1 PENONE No parity error. 0 OVR RX FIFO overflow. [3:3] read-write RXOVR RX FIFO overflow. 1 RXOVRNONE RX FIFO no overflow. 0 FER Framing error. [2:2] read-write FRAMINGERR Framing error. 1 NOFRAMINGERR No framing error detected. 0 TBERBF FIFO empty (transmit) or full (receive). [1:1] read-write TXFIFOEMPTY Transmit: FIFO empty. 1 TXFIFONOTEMPTY Transmit: FIFO not empty. 0 FNE RX FIFO not empty. [0:0] read-write NOTEMPTY RX FIFO not empty. 1 EMPTY RX FIFO empty. 0 IER ISO7816 interrupt enable 0x00000004 32 read-write 0x00000000 0x0000007F FHFEN FIFO Half Full interrupt enable. [6:6] read-write FT2RENDEN TX to RX finished interrupt enable. [5:5] read-write PEEN Parity Error interrupt enable. [4:4] read-write OVREN RX FIFOI overflow interrupt enable. [3:3] read-write FEREN Framing error interrupt enable. [2:2] read-write TBERBFEN FIFO empty (transmit) or full (receive) interrupt enable. [1:1] read-write FNEEN RX FIFO not empty interrupt enable. [0:0] read-write TCR ISO7816 transmit control 0x00000008 32 read-write 0x00000002 0x000000FF DMAMD DMA direction. [7:7] read-write FIP Parity select. [6:6] read-write AUTOCONV Automatic conversion. [5:5] read-write PROT PROT control. [4:4] read-write TR Transmit/receive mode. [3:3] read-write LCT Fast TX to RX. [2:2] read-write SS Use first byte to configure conversion. [1:1] read-write CONV Conversion inversion control. [0:0] read-write UCR ISO7816 user control 0x0000000C 32 read-write 0x00000008 0x0000000F RETXEN Enable TX/RX time configuration. [3:3] read-write RSTIN Reset polarity. [2:2] read-write RIU ISO7816 reset. This bit is write-only. [1:1] read-write CST Clock control. [0:0] read-write DR ISO7816 data 0x00000010 32 read-write 0x00000000 0x000000FF DR Data register. [7:0] read-write BPRL ISO7816 baud rate low 0x00000014 32 read-write 0x00000074 0x000000FF BPRL Baud rate low [7:0] read-write BPRH ISO7816 baud rate high 0x00000018 32 read-write 0x00000001 0x0000000F BPRH Baud rate high [3:0] read-write UCR1 ISO7816 user control 1 0x0000001C 32 read-write 0x00000030 0x0000003D ENLASTB Enable last byte function. [5:5] read-write CLKIOV Output clock level. [4:4] read-write T1PAREN Parity check control. [3:3] read-write STSP ETU counter control. This bit is write-only. [2:2] read-write PR Query Card Detect. [0:0] read-write SR1 ISO7816 interrupt status 1 0x00000020 32 read-write 0x00000008 0x0000000F IDLE ISO7816 idle. [3:3] read-write IDLE ISO7816 idle. 1 ACTIVE ISO7816 active. 0 SYNCEND Write complete synchronization. [2:2] read-write CMPL Synchronization complete. 1 INCMPL Incomplete. 0 PRL Card insert/remove. [1:1] read-write INSREM Card inserted/removed. 1 ECNTOVER ETU counter overflow. [0:0] read-write OVR ETU overflow. 1 IER1 ISO7816 interrupt enable 1 0x00000024 32 read-write 0x00000000 0x00000007 SYNCENDEN Write complete synchronization interrupt enable. [2:2] read-write PRLEN Card insert/remove interrupt enable. [1:1] read-write ECNTOVEREN ETU counter overflow interrupt enable. [0:0] read-write ECNTL ETU counter low 0x00000028 32 read-write 0x00000000 0x000000FF ECNTL ETU counter low register. [7:0] read-write ECNTH ETU counter high 0x0000002C 32 read-write 0x00000000 0x000000FF ECNTH ETU counter high register. [7:0] read-write GTR ISO7816 guard time configuration 0x00000030 32 read-write 0x000000FF 0x000000FF GTR Guard time configuration register. [7:0] read-write RETXCNT ISO7816 resend count 0x00000034 32 read-write 0x00000004 0x0000000F RETXCNT Resend count register. [3:0] read-write RETXCNTRMI ISO7816 resent count inquiry 0x00000038 32 read-write 0x00000000 0x0000000F RETXCNTRMI Resent count inquiry register. [3:0] read-write CLKCTRL Clock Control 0x00000100 32 read-write 0x00000000 0x00000003 APBCLKEN Enable the SCARD APB clock to run continuously. [1:1] read-write CLKEN Enable the serial source clock for SCARD. [0:0] read-write SECURITY 1.0 Security Interfaces 0x40030000 32 read-write 0 0x00000090 registers CTRL Control Register 0x00000000 32 read-write 0x00000000 0x800000F1 CRCERROR CRC Error Status - Set to 1 if an error occurs during a CRC operation. Cleared when CTRL register is written (with any value). Usually indicates an invalid address range. [31:31] read-write FUNCTION Function Select [7:4] read-write CRC32 Perform CRC32 operation 0 ENABLE Function Enable. Software should set the ENABLE bit to initiate a CRC operation. Hardware will clear the ENABLE bit upon completion. [0:0] read-write SRCADDR Source Addresss 0x00000010 32 read-write 0x00000000 0xFFFFFFFF ADDR Source Buffer Address. Address may be byte aligned, but the length must be a multiple of 4 bits. [31:0] read-write LEN Length 0x00000020 32 read-write 0x00000000 0x000FFFFC LEN Buffer size (bottom two bits assumed to be zero to ensure a multiple of 4 bytes) [19:2] read-write RESULT CRC Seed/Result Register 0x00000030 32 read-write 0x00000000 0xFFFFFFFF CRC CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF before starting a CRC operation (unless the CRC is continued from a previous operation). [31:0] read-write LOCKCTRL LOCK Control Register 0x00000078 32 read-write 0x00000000 0x000000FF SELECT LOCK Function Select register. [7:0] read-write CUSTOMER_KEY Unlock Customer Key (access to top half of info0) 1 NONE Lock Control should be set to NONE when not in use. 0 LOCKSTAT LOCK Status Register 0x0000007C 32 read-write 0x00000000 0xFFFFFFFF STATUS LOCK Status register. This register is a bitmask for which resources are currently unlocked. These bits are one-hot per resource. [31:0] read-write CUSTOMER_KEY Customer Key is unlocked (access is granted to top half of info0) 1 NONE No resources are unlocked 0 KEY0 Key0 Register 0x00000080 32 read-write 0x00000000 0xFFFFFFFF KEY0 Bits [31:0] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000. [31:0] read-write KEY1 Key1 Register 0x00000084 32 read-write 0x00000000 0xFFFFFFFF KEY1 Bits [63:32] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000. [31:0] read-write KEY2 Key2 Register 0x00000088 32 read-write 0x00000000 0xFFFFFFFF KEY2 Bits [95:64] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000. [31:0] read-write KEY3 Key3 Register 0x0000008C 32 read-write 0x00000000 0xFFFFFFFF KEY3 Bits [127:96] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000. [31:0] read-write UART0 1.0 Serial UART 0x4001C000 32 read-write 0 0x00000048 registers UART0 15 DR UART Data Register 0x00000000 32 read-write 0x00000000 0x00000FFF OEDATA This is the overrun error indicator. [11:11] read-write NOERR No error on UART OEDATA, overrun error indicator. 0 ERR Error on UART OEDATA, overrun error indicator. 1 BEDATA This is the break error indicator. [10:10] read-write NOERR No error on UART BEDATA, break error indicator. 0 ERR Error on UART BEDATA, break error indicator. 1 PEDATA This is the parity error indicator. [9:9] read-write NOERR No error on UART PEDATA, parity error indicator. 0 ERR Error on UART PEDATA, parity error indicator. 1 FEDATA This is the framing error indicator. [8:8] read-write NOERR No error on UART FEDATA, framing error indicator. 0 ERR Error on UART FEDATA, framing error indicator. 1 DATA This is the UART data port. [7:0] read-write RSR UART Status Register 0x00000004 32 read-write 0x00000000 0x0000000F OESTAT This is the overrun error indicator. [3:3] read-write NOERR No error on UART OESTAT, overrun error indicator. 0 ERR Error on UART OESTAT, overrun error indicator. 1 BESTAT This is the break error indicator. [2:2] read-write NOERR No error on UART BESTAT, break error indicator. 0 ERR Error on UART BESTAT, break error indicator. 1 PESTAT This is the parity error indicator. [1:1] read-write NOERR No error on UART PESTAT, parity error indicator. 0 ERR Error on UART PESTAT, parity error indicator. 1 FESTAT This is the framing error indicator. [0:0] read-write NOERR No error on UART FESTAT, framing error indicator. 0 ERR Error on UART FESTAT, framing error indicator. 1 FR Flag Register 0x00000018 32 read-write 0x00000000 0x000001FF TXBUSY This bit holds the transmit BUSY indicator. [8:8] read-write TXFE This bit holds the transmit FIFO empty indicator. [7:7] read-write XMTFIFO_EMPTY Transmit fifo is empty. 1 RXFF This bit holds the receive FIFO full indicator. [6:6] read-write RCVFIFO_FULL Receive fifo is full. 1 TXFF This bit holds the transmit FIFO full indicator. [5:5] read-write XMTFIFO_FULL Transmit fifo is full. 1 RXFE This bit holds the receive FIFO empty indicator. [4:4] read-write RCVFIFO_EMPTY Receive fifo is empty. 1 BUSY This bit holds the busy indicator. [3:3] read-write BUSY UART busy indicator. 1 DCD This bit holds the data carrier detect indicator. [2:2] read-write DETECTED Data carrier detect detected. 1 DSR This bit holds the data set ready indicator. [1:1] read-write READY Data set ready. 1 CTS This bit holds the clear to send indicator. [0:0] read-write CLEARTOSEND Clear to send is indicated. 1 ILPR IrDA Counter 0x00000020 32 read-write 0x00000000 0x000000FF ILPDVSR These bits hold the IrDA counter divisor. [7:0] read-write IBRD Integer Baud Rate Divisor 0x00000024 32 read-write 0x00000000 0x0000FFFF DIVINT These bits hold the baud integer divisor. [15:0] read-write FBRD Fractional Baud Rate Divisor 0x00000028 32 read-write 0x00000000 0x0000003F DIVFRAC These bits hold the baud fractional divisor. [5:0] read-write LCRH Line Control High 0x0000002C 32 read-write 0x00000000 0x000000FF SPS This bit holds the stick parity select. [7:7] read-write WLEN These bits hold the write length. [6:5] read-write FEN This bit holds the FIFO enable. [4:4] read-write STP2 This bit holds the two stop bits select. [3:3] read-write EPS This bit holds the even parity select. [2:2] read-write PEN This bit holds the parity enable. [1:1] read-write BRK This bit holds the break set. [0:0] read-write CR Control Register 0x00000030 32 read-write 0x00000300 0x0000FFFF CTSEN This bit enables CTS hardware flow control. [15:15] read-write RTSEN This bit enables RTS hardware flow control. [14:14] read-write OUT2 This bit holds modem Out2. [13:13] read-write OUT1 This bit holds modem Out1. [12:12] read-write RTS This bit enables request to send. [11:11] read-write DTR This bit enables data transmit ready. [10:10] read-write RXE This bit is the receive enable. [9:9] read-write TXE This bit is the transmit enable. [8:8] read-write LBE This bit is the loopback enable. [7:7] read-write CLKSEL This bitfield is the UART clock select. [6:4] read-write NOCLK No UART clock. This is the low power default. 0 24MHZ 24 MHz clock. 1 12MHZ 12 MHz clock. 2 6MHZ 6 MHz clock. 3 3MHZ 3 MHz clock. 4 CLKEN This bit is the UART clock enable. [3:3] read-write SIRLP This bit is the SIR low power select. [2:2] read-write SIREN This bit is the SIR ENDEC enable. [1:1] read-write UARTEN This bit is the UART enable. [0:0] read-write IFLS FIFO Interrupt Level Select 0x00000034 32 read-write 0x00000012 0x0000003F RXIFLSEL These bits hold the receive FIFO interrupt level. [5:3] read-write TXIFLSEL These bits hold the transmit FIFO interrupt level. [2:0] read-write IER Interrupt Enable 0x00000038 32 read-write 0x00000000 0x000007FF OEIM This bit holds the overflow interrupt enable. [10:10] read-write BEIM This bit holds the break error interrupt enable. [9:9] read-write PEIM This bit holds the parity error interrupt enable. [8:8] read-write FEIM This bit holds the framing error interrupt enable. [7:7] read-write RTIM This bit holds the receive timeout interrupt enable. [6:6] read-write TXIM This bit holds the transmit interrupt enable. [5:5] read-write RXIM This bit holds the receive interrupt enable. [4:4] read-write DSRMIM This bit holds the modem DSR interrupt enable. [3:3] read-write DCDMIM This bit holds the modem DCD interrupt enable. [2:2] read-write CTSMIM This bit holds the modem CTS interrupt enable. [1:1] read-write TXCMPMIM This bit holds the modem TXCMP interrupt enable. [0:0] read-write IES Interrupt Status 0x0000003C 32 read-write 0x00000000 0x000007FF OERIS This bit holds the overflow interrupt status. [10:10] read-write BERIS This bit holds the break error interrupt status. [9:9] read-write PERIS This bit holds the parity error interrupt status. [8:8] read-write FERIS This bit holds the framing error interrupt status. [7:7] read-write RTRIS This bit holds the receive timeout interrupt status. [6:6] read-write TXRIS This bit holds the transmit interrupt status. [5:5] read-write RXRIS This bit holds the receive interrupt status. [4:4] read-write DSRMRIS This bit holds the modem DSR interrupt status. [3:3] read-write DCDMRIS This bit holds the modem DCD interrupt status. [2:2] read-write CTSMRIS This bit holds the modem CTS interrupt status. [1:1] read-write TXCMPMRIS This bit holds the modem TXCMP interrupt status. [0:0] read-write MIS Masked Interrupt Status 0x00000040 32 read-write 0x00000000 0x000007FF OEMIS This bit holds the overflow interrupt status masked. [10:10] read-write BEMIS This bit holds the break error interrupt status masked. [9:9] read-write PEMIS This bit holds the parity error interrupt status masked. [8:8] read-write FEMIS This bit holds the framing error interrupt status masked. [7:7] read-write RTMIS This bit holds the receive timeout interrupt status masked. [6:6] read-write TXMIS This bit holds the transmit interrupt status masked. [5:5] read-write RXMIS This bit holds the receive interrupt status masked. [4:4] read-write DSRMMIS This bit holds the modem DSR interrupt status masked. [3:3] read-write DCDMMIS This bit holds the modem DCD interrupt status masked. [2:2] read-write CTSMMIS This bit holds the modem CTS interrupt status masked. [1:1] read-write TXCMPMMIS This bit holds the modem TXCMP interrupt status masked. [0:0] read-write IEC Interrupt Clear 0x00000044 32 read-write 0x00000000 0x000007FF OEIC This bit holds the overflow interrupt clear. [10:10] read-write BEIC This bit holds the break error interrupt clear. [9:9] read-write PEIC This bit holds the parity error interrupt clear. [8:8] read-write FEIC This bit holds the framing error interrupt clear. [7:7] read-write RTIC This bit holds the receive timeout interrupt clear. [6:6] read-write TXIC This bit holds the transmit interrupt clear. [5:5] read-write RXIC This bit holds the receive interrupt clear. [4:4] read-write DSRMIC This bit holds the modem DSR interrupt clear. [3:3] read-write DCDMIC This bit holds the modem DCD interrupt clear. [2:2] read-write CTSMIC This bit holds the modem CTS interrupt clear. [1:1] read-write TXCMPMIC This bit holds the modem TXCMP interrupt clear. [0:0] read-write UART1 0x4001D000 UART1 16 VCOMP 1.0 Voltage Comparator 0x4000C000 32 read-write 0 0x00000210 registers VCOMP 3 CFG Configuration Register 0x00000000 32 read-write 0x00000000 0x000F0303 LVLSEL When the reference input NSEL is set to NSEL_DAC, this bitfield selects the voltage level for the negative input to the comparator. [19:16] read-write 0P58V Set Reference input to 0.58 Volts. 0 0P77V Set Reference input to 0.77 Volts. 1 0P97V Set Reference input to 0.97 Volts. 2 1P16V Set Reference input to 1.16 Volts. 3 1P35V Set Reference input to 1.35 Volts. 4 1P55V Set Reference input to 1.55 Volts. 5 1P74V Set Reference input to 1.74 Volts. 6 1P93V Set Reference input to 1.93 Volts. 7 2P13V Set Reference input to 2.13 Volts. 8 2P32V Set Reference input to 2.32 Volts. 9 2P51V Set Reference input to 2.51 Volts. 10 2P71V Set Reference input to 2.71 Volts. 11 2P90V Set Reference input to 2.90 Volts. 12 3P09V Set Reference input to 3.09 Volts. 13 3P29V Set Reference input to 3.29 Volts. 14 3P48V Set Reference input to 3.48 Volts. 15 NSEL This bitfield selects the negative input to the comparator. [9:8] read-write VREFEXT1 Use external reference 1 for reference input. 0 VREFEXT2 Use external reference 2 for reference input. 1 VREFEXT3 Use external reference 3 for reference input. 2 DAC Use DAC output selected by LVLSEL for reference input. 3 PSEL This bitfield selects the positive input to the comparator. [1:0] read-write VDDADJ Use VDDADJ for the positive input. 0 VTEMP Use the temperature sensor output for the positive input. Note: If this channel is selected for PSEL, the bandap circuit required for temperature comparisons will automatically turn on. The bandgap circuit requires 11us to stabalize. 1 VEXT1 Use external voltage 0 for positive input. 2 VEXT2 Use external voltage 1 for positive input. 3 STAT Status Register 0x00000004 32 read-write 0x00000000 0x00000003 PWDSTAT This bit indicates the power down state of the voltage comparator. [1:1] read-write POWERED_DOWN The voltage comparator is powered down. 1 CMPOUT This bit is 1 if the positive input of the comparator is greater than the negative input. [0:0] read-write VOUT_LOW The negative input of the comparator is greater than the positive input. 0 VOUT_HIGH The positive input of the comparator is greater than the negative input. 1 PWDKEY Key Register for Powering Down the Voltage Comparator 0x00000008 32 read-write 0x00000000 0xFFFFFFFF PWDKEY Key register value. [31:0] read-write Key Key 55 INTEN Voltage Comparator Interrupt registers: Enable 0x00000200 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write INTSTAT Voltage Comparator Interrupt registers: Status 0x00000204 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write INTCLR Voltage Comparator Interrupt registers: Clear 0x00000208 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write INTSET Voltage Comparator Interrupt registers: Set 0x0000020C 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write WDT 1.0 Watchdog Timer 0x40024000 32 read-write 0 0x00000210 registers WDT 1 CFG Configuration Register 0x00000000 32 read-write 0x00FFFF00 0x07FFFF07 CLKSEL Select the frequency for the WDT. All values not enumerated below are undefined. [26:24] read-write OFF Low Power Mode. This setting disables the watch dog timer. 0 128HZ 128 Hz LFRC clock. 1 16HZ 16 Hz LFRC clock. 2 1HZ 1 Hz LFRC clock. 3 1_16HZ 1/16th Hz LFRC clock. 4 INTVAL This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt. [23:16] read-write RESVAL This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset. This will cause a software reset. [15:8] read-write RESEN This bitfield enables the WDT reset. This needs to be set together with the WDREN bit in REG_RSTGEN_CFG register (in reset gen) to trigger the reset. [2:2] read-write INTEN This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC. [1:1] read-write WDTEN This bitfield enables the WDT. [0:0] read-write RSTRT Restart the watchdog timer. 0x00000004 32 read-write 0x00000000 0x000000FF RSTRT Writing 0xB2 to WDTRSTRT restarts the watchdog timer. This is a write only register. Reading this register will only provide all 0. [7:0] read-write KEYVALUE This is the key value to write to WDTRSTRT to restart the WDT. This is a write only register. 178 LOCK Locks the WDT 0x00000008 32 read-write 0x00000000 0x000000FF LOCK Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set. [7:0] read-write KEYVALUE This is the key value to write to WDTLOCK to lock the WDT. 58 COUNT Current Counter Value for WDT 0x0000000C 32 read-write 0x00000000 0x000000FF COUNT Read-Only current value of the WDT counter [7:0] read-write INTEN WDT Interrupt register: Enable 0x00000200 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write INTSTAT WDT Interrupt register: Status 0x00000204 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write INTCLR WDT Interrupt register: Clear 0x00000208 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write INTSET WDT Interrupt register: Set 0x0000020C 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write