Ambiq Micro Ambiq apollo1 Apollo 1.0 Ultra-Low power ARM Cortex-M4 MCU from Ambiq Micro Copyright (c) 2019, Ambiq Micro\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\nthis list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\nnotice, this list of conditions and the following disclaimer in the\ndocumentation and/or other materials provided with the distribution.\n\n3. Neither the name of the copyright holder nor the names of its\ncontributors may be used to endorse or promote products derived from this\nsoftware without specific prior written permission.\n\nThird party software included in this distribution is subject to the\nadditional license terms as defined in the /docs/licenses directory.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n CM4 r1p0 little true true 3 false 8 32 32 read-write 0x00000000 0xFFFFFFFF ADC 1.0 Analog Digital Converter Control 0x50008000 32 read-write 0 0x00000210 registers ADC 8 CFG Configuration Register 0x00000000 32 read-write 0x00000000 0x071F03FF CLKSEL Select the source and frequency for the ADC clock. All values not enumerated below are undefined. [26:24] read-write OFF Low Power Mode. 0 12MHZ 12 MHz ADC clock. 1 6MHZ 6 MHz ADC clock. 2 3MHZ 12 MHz ADC clock. 3 1_5MHZ 1.5 MHz ADC clock. 4 TRIGPOL This bit selects the ADC trigger polarity for external off chip triggers. [20:20] read-write RISING_EDGE Trigger on rising edge. 0 FALLING_EDGE Trigger on falling edge. 1 TRIGSEL Select the ADC trigger source. [19:16] read-write EXT0 Off chip External Trigger0 (ADC_ET0) 0 EXT1 Off chip External Trigger1 (ADC_ET1) 1 EXT2 Off chip External Trigger2 (ADC_ET2) 2 EXT3 Off chip External Trigger3 (ADC_ET3) 3 EXT4 Off chip External Trigger4 (ADC_ET4) 4 EXT5 Off chip External Trigger5 (ADC_ET5) 5 EXT6 Off chip External Trigger6 (ADC_ET6) 6 EXT7 Off chip External Trigger7 (ADC_ET7) 7 SWT Software Trigger 8 REFSEL Select the ADC reference voltage. [9:8] read-write INTERNAL Internal Bandgap Reference Voltage 0 VDD Select VDD as the ADEC reference voltage. 1 ADCREF Off Chip Reference (ADC_REF) 2 UNDEFINED Reserved 3 BATTLOAD Control 500 Ohm battery load resistor. [7:7] read-write DIS Disable battery load. 0 EN Enable battery load. 1 OPMODE Select the sample rate mode. It adjusts the current in the ADC for higher sample rates. A 12MHz ADC clock can result in a sample rate up to 1Msps depending on the trigger or repeating mode rate. A 1.5MHz ADC clock can result in a sample rate up 125K sps. NOTE: All other values not specified below are undefined. [6:5] read-write SAMPLE_RATE_LE_125KSPS Sample Rate <= 125K sps 0 SAMPLE_RATE_125K_1MSPS Sample Rate 125K to 1M sps 2 LPMODE Select power mode to enter between active scans. [4:3] read-write MODE0 Low Power Mode 0 (2'b00). Leaves the ADC fully powered between scans with no latency between a trigger event and sample data collection. 0 MODE1 Low Power Mode 1 (2'b01). Enables a low power mode for the ADC between scans requiring 50us initialization time (latency) between a trigger event and the scan (assuming the HFRC remains running and the MCU is not in deepsleep mode in which case additional startup latency for HFRC startup is required). 1 MODE2 Low Power Mode 2 (2'b10). Disconnects power and clocks to the ADC effectively eliminating all active power associated with the ADC between scans. This mode requires 150us initialization (again, assuming the HFRC remains running and the MCU is not in deepsleep mode in which case additional startup latency for HFRC startup is required). 2 MODE_UNDEFINED Undefined Mode (2'b11) 3 RPTEN This bit enables Repeating Scan Mode. [2:2] read-write SINGLE_SCAN In Single Scan Mode, the ADC will complete a single scan upon each trigger event. 0 REPEATING_SCAN In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. 1 TMPSPWR This enables power to the temperature sensor module. After setting this bit, the temperature sensor will remain powered down while the ADC is power is disconnected (i.e, when the ADC PWDSTAT is 2'b10). [1:1] read-write DIS Power down the temperature sensor. 0 EN Enable the temperature sensor when the ADC is in it's active state. 1 ADCEN This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. [0:0] read-write DIS Disable the ADC module. 0 EN Enable the ADC module. 1 STAT ADC Power Status 0x00000004 32 read-write 0x00000000 0x00000003 PWDSTAT Indicates the power-status of the ADC. [1:0] read-write ON Powered on. 0 SWITCH_ON_SAR_OFF Power switch on, ADC Low Power Mode 1. 1 POWER_SWITCH_OFF Power switch off, ADC disabled. 2 SWT Software trigger 0x00000008 32 read-write 0x00000000 0x000000FF SWT Writing 0x37 to this register generates a software trigger. [7:0] read-write GEN_SW_TRIGGER Writing this value generates a software trigger. 55 SL0CFG Slot 0 Configuration Register 0x0000000C 32 read-write 0x00000000 0x07070F03 ADSEL0 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL0 Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL0 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN0 This bit enables the window compare function for slot 0. [1:1] read-write WCEN Enable the window compare for slot 0. 1 SLEN0 This bit enables slot 0 for ADC conversions. [0:0] read-write SLEN Enable slot 0 for ADC conversions. 1 SL1CFG Slot 1 Configuration Register 0x00000010 32 read-write 0x00000000 0x07070F03 ADSEL1 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL1 Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5 Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL1 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN1 This bit enables the window compare function for slot 1. [1:1] read-write WCEN Enable the window compare for slot 1. 1 SLEN1 This bit enables slot 1 for ADC conversions. [0:0] read-write SLEN Enable slot 1 for ADC conversions. 1 SL2CFG Slot 2 Configuration Register 0x00000014 32 read-write 0x00000000 0x07070F03 ADSEL2 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL2 Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL2 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN2 This bit enables the window compare function for slot 2. [1:1] read-write WCEN Enable the window compare for slot 2. 1 SLEN2 This bit enables slot 2 for ADC conversions. [0:0] read-write SLEN Enable slot 2 for ADC conversions. 1 SL3CFG Slot 3 Configuration Register 0x00000018 32 read-write 0x00000000 0x07070F03 ADSEL3 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL3 Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL3 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN3 This bit enables the window compare function for slot 3. [1:1] read-write WCEN Enable the window compare for slot 3. 1 SLEN3 This bit enables slot 3 for ADC conversions. [0:0] read-write SLEN Enable slot 3 for ADC conversions. 1 SL4CFG Slot 4 Configuration Register 0x0000001C 32 read-write 0x00000000 0x07070F03 ADSEL4 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL4 Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL4 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN4 This bit enables the window compare function for slot 4. [1:1] read-write WCEN Enable the window compare for slot 4. 1 SLEN4 This bit enables slot 4 for ADC conversions. [0:0] read-write SLEN Enable slot 4 for ADC conversions. 1 SL5CFG Slot 5 Configuration Register 0x00000020 32 read-write 0x00000000 0x07070F03 ADSEL5 Select number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL5 Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL5 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN5 This bit enables the window compare function for slot 5. [1:1] read-write WCEN Enable the window compare for slot 5. 1 SLEN5 This bit enables slot 5 for ADC conversions. [0:0] read-write SLEN Enable slot 5 for ADC conversions. 1 SL6CFG Slot 6 Configuration Register 0x00000024 32 read-write 0x00000000 0x07070F03 ADSEL6 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL6 Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL6 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN6 This bit enables the window compare function for slot 6. [1:1] read-write WCEN Enable the window compare for slot 6. 1 SLEN6 This bit enables slot 6 for ADC conversions. [0:0] read-write SLEN Enable slot 6 for ADC conversions. 1 SL7CFG Slot 7 Configuration Register 0x00000028 32 read-write 0x00000000 0x07070F03 ADSEL7 Select the number of measurements to average in the accumulate divide module for this slot. [26:24] read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 THSEL7 Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. [18:16] read-write 1_ADC_CLK 1 ADC clock cycle. 0 2_ADC_CLKS 2 ADC clock cycles. 1 4_ADC_CLKS 4 ADC clock cycles. 2 8_ADC_CLKS 8 ADC clock cycles. 3 16_ADC_CLKS 16 ADC clock cycles. 4 32_ADC_CLKS 32 ADC clock cycles. 5 64_ADC_CLKS 64 ADC clock cycles. 6 128_ADC_CLKS 128 ADC clock cycles. 7 CHSEL7 Select one of the 13 channel inputs for this slot. [11:8] read-write EXT0 ADC_EXT0 external GPIO pin connection. 0 EXT1 ADC_EXT1 external GPIO pin connection. 1 EXT2 ADC_EXT2 external GPIO pin connection. 2 EXT3 ADC_EXT3 external GPIO pin connection. 3 EXT4 ADC_EXT4 external GPIO pin connection. 4 EXT5 ADC_EXT5 external GPIO pin connection. 5 EXT6 ADC_EXT6 external GPIO pin connection. 6 EXT7 ADC_EXT7 external GPIO pin connection. 7 TEMP ADC_TEMP internal temperature sensor. 8 VDD ADC_VDD internal power rail connection. 9 VSS ADC_VSS internal ground connection. 10 VBATT ADC_VBATT internal voltage divide-by-3 connection to input power rail. 12 WCEN7 This bit enables the window compare function for slot 7. [1:1] read-write WCEN Enable the window compare for slot 7. 1 SLEN7 This bit enables slot 7 for ADC conversions. [0:0] read-write SLEN Enable slot 7 for ADC conversions. 1 WLIM Window Comparator Limits Register 0x0000002C 32 read-write 0x00000000 0xFFFFFFFF ULIM Sets the upper limit for the wondow comparator. [31:16] read-write LLIM Sets the lower limit for the wondow comparator. [15:0] read-write FIFO FIFO Data and Valid Count Register 0x00000030 32 read-write 0x00000000 0xFFFFFFFF RSVD_27 RESERVED. [31:27] read-write SLOTNUM Slot number associated with this FIFO data. [26:24] read-write RSVD_20 RESERVED. [23:20] read-write COUNT Number of valid entries in the ADC FIFO. [19:16] read-write DATA Oldest data in the FIFO. [15:0] read-write INTEN ADC Interrupt registers: Enable 0x00000200 32 read-write 0x00000000 0x0000003F WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 INTSTAT ADC Interrupt registers: Status 0x00000204 32 read-write 0x00000000 0x0000003F WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 INTCLR ADC Interrupt registers: Clear 0x00000208 32 read-write 0x00000000 0x0000003F WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 INTSET ADC Interrupt registers: Set 0x0000020C 32 read-write 0x00000000 0x0000003F WCINC Window comparator voltage incursion interrupt. [5:5] read-write WCINCINT Window comparitor voltage incursion interrupt. 1 WCEXC Window comparator voltage excursion interrupt. [4:4] read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. [3:3] read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. [2:2] read-write FIFO75INT FIFO 75 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. [1:1] read-write SCNCMPINT ADC scan complete interrupt. 1 CNVCMP ADC conversion complete interrupt. [0:0] read-write CNVCMPINT ADC conversion complete interrupt. 1 CLKGEN 1.0 Clock Generator 0x40004000 32 read-write 0 0x00000110 registers CLKGEN_RTC 2 CALXT XT Oscillator Control 0x00000000 32 read-write 0x00000000 0x000007FF CALXT XT Oscillator calibration value [10:0] read-write CALRC RC Oscillator Control 0x00000004 32 read-write 0x00000000 0x0003FFFF CALRC LFRC Oscillator calibration value [17:0] read-write ACALCTR Autocalibration Counter 0x00000008 32 read-write 0x00000000 0x00FFFFFF ACALCTR Autocalibration Counter result. [23:0] read-write OCTRL Oscillator Control 0x0000000C 32 read-write 0x00000000 0x000007C3 ACAL Autocalibration control [10:8] read-write DIS Disable Autocalibration 0 1024SEC Autocalibrate every 1024 seconds 2 512SEC Autocalibrate every 512 seconds 3 XTFREQ Frequency measurement using XT 6 EXTFREQ Frequency measurement using external clock 7 OSEL Selects the RTC oscillator (1 => LFRC, 0 => XT) [7:7] read-write RTC_XT RTC uses the XT 0 RTC_LFRC RTC uses the LFRC 1 FOS Oscillator switch on failure function [6:6] read-write DIS Disable the oscillator switch on failure function 0 EN Enable the oscillator switch on failure function 1 STOPRC Stop the LFRC Oscillator to the RTC [1:1] read-write EN Enable the LFRC Oscillator to drive the RTC 0 STOP Stop the LFRC Oscillator when driving the RTC 1 STOPXT Stop the XT Oscillator to the RTC [0:0] read-write EN Enable the XT Oscillator to drive the RTC 0 STOP Stop the XT Oscillator when driving the RTC 1 CLKOUT CLKOUT Frequency Select 0x00000010 32 read-write 0x00000000 0x000000BF CKEN Enable the CLKOUT signal [7:7] read-write DIS Disable CLKOUT 0 EN Enable CLKOUT 1 CKSEL CLKOUT signal select [5:0] read-write LFRC LFRC 0 XT_DIV2 XT / 2 1 XT_DIV4 XT / 4 2 XT_DIV8 XT / 8 3 XT_DIV16 XT / 16 4 XT_DIV32 XT / 32 5 RTC_1Hz 1 Hz as selected in RTC 16 XT_DIV2M XT / 2^21 22 XT XT 23 CG_100Hz 100 Hz as selected in CLKGEN 24 HFRC HFRC 25 HFRC_DIV2 HFRC / 2 26 HFRC_DIV4 HFRC / 4 27 HFRC_DIV8 HFRC / 8 28 HFRC_DIV32 HFRC / 32 29 HFRC_DIV64 HFRC / 64 30 HFRC_DIV128 HFRC / 128 31 HFRC_DIV256 HFRC / 256 32 FLASH_CLK Flash Clock 34 LFRC_DIV2 LFRC / 2 35 LFRC_DIV32 LFRC / 32 36 LFRC_DIV512 LFRC / 512 37 LFRC_DIV32K LFRC / 32768 38 XT_DIV256 XT / 256 39 XT_DIV8K XT / 8192 40 XT_DIV64K XT / 2^16 41 ULFRC_DIV16 Uncal LFRC / 16 42 ULFRC_DIV128 Uncal LFRC / 128 43 ULFRC_1Hz Uncal LFRC / 1024 44 ULFRC_DIV4K Uncal LFRC / 4096 45 ULFRC_DIV1M Uncal LFRC / 2^20 46 HFRC_DIV64K HFRC / 2^16 47 HFRC_DIV16M HFRC / 2^24 48 LFRC_DIV2M LFRC / 2^20 49 HFRCNE HFRC (not autoenabled) 50 HFRCNE_DIV8 HFRC / 8 (not autoenabled) 51 XTNE XT (not autoenabled) 53 XTNE_DIV16 XT / 16 (not autoenabled) 54 LFRCNE_DIV32 LFRC / 32 (not autoenabled) 55 LFRCNE LFRC (not autoenabled) - Default for undefined values 57 CLKKEY Key Register for Clock Control Register 0x00000014 32 read-write 0x00000000 0xFFFFFFFF CLKKEY Key register value. [31:0] read-write Key Key 71 CCTRL HFRC Clock Control 0x00000018 32 read-write 0x00000007 0x0000000F MEMSEL Flash Clock divisor [3:3] read-write HFRC_DIV25 Flash Clock is HFRC / 25 0 HFRC_DIV45 Flash Clock is HFRC / 45 1 CORESEL Core Clock divisor [2:0] read-write HFRC Core Clock is HFRC 0 HFRC_DIV2 Core Clock is HFRC / 2 1 HFRC_DIV3 Core Clock is HFRC / 3 2 HFRC_DIV4 Core Clock is HFRC / 4 3 HFRC_DIV5 Core Clock is HFRC / 5 4 HFRC_DIV6 Core Clock is HFRC / 6 5 HFRC_DIV7 Core Clock is HFRC / 7 6 HFRC_DIV8 Core Clock is HFRC / 8 7 STATUS Clock Generator Status 0x0000001C 32 read-write 0x00000000 0x00000003 OSCF XT Oscillator is enabled but not oscillating [1:1] read-write OMODE Current RTC oscillator (1 => LFRC, 0 => XT) [0:0] read-write HFADJ HFRC Adjustment 0x00000020 32 read-write 0x00000000 0x000FFF0F HFWARMUP XT warmup period for HFRC adjustment [19:19] read-write 1SEC Autoadjust XT warmup period = 1-2 seconds 0 2SEC Autoadjust XT warmup period = 2-4 seconds 1 HFXTADJ Target HFRC adjustment value. [18:8] read-write HFADJCK Repeat period for HFRC adjustment [3:1] read-write 4SEC Autoadjust repeat period = 4 seconds 0 16SEC Autoadjust repeat period = 16 seconds 1 32SEC Autoadjust repeat period = 32 seconds 2 64SEC Autoadjust repeat period = 64 seconds 3 128SEC Autoadjust repeat period = 128 seconds 4 256SEC Autoadjust repeat period = 256 seconds 5 512SEC Autoadjust repeat period = 512 seconds 6 1024SEC Autoadjust repeat period = 1024 seconds 7 HFADJEN HFRC adjustment control [0:0] read-write DIS Disable the HFRC adjustment 0 EN Enable the HFRC adjustment 1 HFVAL HFADJ readback 0x00000024 32 read-write 0x00000000 0x000007FF HFTUNERB Current HFTUNE value [10:0] read-write CLOCKEN Clock Enable Status 0x00000028 32 read-write 0x00000000 0xFFFFFFFF CLOCKEN Clock enable status [31:0] read-write UARTEN UART Enable 0x0000002C 32 read-write 0x00000000 0x00000001 UARTEN UART system clock control [0:0] read-write DIS Disable the UART system clock 0 EN Enable the UART system clock 1 INTEN CLKGEN Interrupt Register: Enable 0x00000100 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTSTAT CLKGEN Interrupt Register: Status 0x00000104 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTCLR CLKGEN Interrupt Register: Clear 0x00000108 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTSET CLKGEN Interrupt Register: Set 0x0000010C 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write CTIMER 1.0 Counter/Timer 0x40008000 32 read-write 0 0x00000210 registers CTIMER 10 TMR0 Counter/Timer Register 0x00000000 32 read-write 0x00000000 0xFFFFFFFF CTTMRB0 Counter/Timer B0. [31:16] read-write CTTMRA0 Counter/Timer A0. [15:0] read-write CMPRA0 Counter/Timer A0 Compare Registers 0x00000004 32 read-write 0x00000000 0xFFFFFFFF CMPR1A0 Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A. [31:16] read-write CMPR0A0 Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A. [15:0] read-write CMPRB0 Counter/Timer B0 Compare Registers 0x00000008 32 read-write 0x00000000 0xFFFFFFFF CMPR1B0 Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B. [31:16] read-write CMPR0B0 Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B. [15:0] read-write CTRL0 Counter/Timer Control 0x0000000C 32 read-write 0x00000000 0x9FFF1FFF CTLINK0 Counter/Timer A0/B0 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A0/B0 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A0/B0 timers into a single 32-bit timer. 1 TMRB0POL Counter/Timer B0 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB0 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB0 pin is the inverse of the timer output. 1 TMRB0CLR Counter/Timer B0 Clear bit. [27:27] read-write RUN Allow counter/timer B0 to run 0 CLEAR Holds counter/timer B0 at 0x0000. 1 TMRB0PE Counter/Timer B0 Output Enable bit. [26:26] read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB0POL. 0 EN Enable counter/timer B0 to generate a signal on TMRPINB. 1 TMRB0IE Counter/Timer B0 Interrupt Enable bit. [25:25] read-write DIS Disable counter/timer B0 from generating an interrupt. 0 EN Enable counter/timer B0 to generate an interrupt. 1 TMRB0FN Counter/Timer B0 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B0, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB0CLK Counter/Timer B0 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream B. 16 TMRB0EN Counter/Timer B0 Enable bit. [16:16] read-write DIS Counter/Timer B0 Disable. 0 EN Counter/Timer B0 Enable. 1 TMRA0POL Counter/Timer A0 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA0 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA0 pin is the inverse of the timer output. 1 TMRA0CLR Counter/Timer A0 Clear bit. [11:11] read-write RUN Allow counter/timer A0 to run 0 CLEAR Holds counter/timer A0 at 0x0000. 1 TMRA0PE Counter/Timer A0 Output Enable bit. [10:10] read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA0POL. 0 EN Enable counter/timer B0 to generate a signal on TMRPINB. 1 TMRA0IE Counter/Timer A0 Interrupt Enable bit. [9:9] read-write DIS Disable counter/timer A0 from generating an interrupt. 0 EN Enable counter/timer A0 to generate an interrupt. 1 TMRA0FN Counter/Timer A0 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A0, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA0CLK Counter/Timer A0 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKA Clock source is buck converter stream A. 16 TMRA0EN Counter/Timer A0 Enable bit. [0:0] read-write DIS Counter/Timer A0 Disable. 0 EN Counter/Timer A0 Enable. 1 TMR1 Counter/Timer Register 0x00000010 32 read-write 0x00000000 0xFFFFFFFF CTTMRB1 Counter/Timer B1. [31:16] read-write CTTMRA1 Counter/Timer A1. [15:0] read-write CMPRA1 Counter/Timer A1 Compare Registers 0x00000014 32 read-write 0x00000000 0xFFFFFFFF CMPR1A1 Counter/Timer A1 Compare Register 1. [31:16] read-write CMPR0A1 Counter/Timer A1 Compare Register 0. [15:0] read-write CMPRB1 Counter/Timer B1 Compare Registers 0x00000018 32 read-write 0x00000000 0xFFFFFFFF CMPR1B1 Counter/Timer B1 Compare Register 1. [31:16] read-write CMPR0B1 Counter/Timer B1 Compare Register 0. [15:0] read-write CTRL1 Counter/Timer Control 0x0000001C 32 read-write 0x00000000 0x9FFF1FFF CTLINK1 Counter/Timer A1/B1 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A0/B0 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A1/B1 timers into a single 32-bit timer. 1 TMRB1POL Counter/Timer B1 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB1 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB1 pin is the inverse of the timer output. 1 TMRB1CLR Counter/Timer B1 Clear bit. [27:27] read-write RUN Allow counter/timer B1 to run 0 CLEAR Holds counter/timer B1 at 0x0000. 1 TMRB1PE Counter/Timer B1 Output Enable bit. [26:26] read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB1POL. 0 EN Enable counter/timer B1 to generate a signal on TMRPINB. 1 TMRB1IE Counter/Timer B1 Interrupt Enable bit. [25:25] read-write DIS Disable counter/timer B1 from generating an interrupt. 0 EN Enable counter/timer B1 to generate an interrupt. 1 TMRB1FN Counter/Timer B1 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B1, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB1CLK Counter/Timer B1 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream B. 16 TMRB1EN Counter/Timer B1 Enable bit. [16:16] read-write DIS Counter/Timer B1 Disable. 0 EN Counter/Timer B1 Enable. 1 TMRA1POL Counter/Timer A1 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA1 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA1 pin is the inverse of the timer output. 1 TMRA1CLR Counter/Timer A1 Clear bit. [11:11] read-write RUN Allow counter/timer A1 to run 0 CLEAR Holds counter/timer A1 at 0x0000. 1 TMRA1PE Counter/Timer A1 Output Enable bit. [10:10] read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA1POL. 0 EN Enable counter/timer A1 to generate a signal on TMRPINA. 1 TMRA1IE Counter/Timer A1 Interrupt Enable bit. [9:9] read-write DIS Disable counter/timer A1 from generating an interrupt. 0 EN Enable counter/timer A1 to generate an interrupt. 1 TMRA1FN Counter/Timer A1 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A1, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA1CLK Counter/Timer A1 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is the HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKA Clock source is buck converter stream A. 16 TMRA1EN Counter/Timer A1 Enable bit. [0:0] read-write DIS Counter/Timer A1 Disable. 0 EN Counter/Timer A1 Enable. 1 TMR2 Counter/Timer Register 0x00000020 32 read-write 0x00000000 0xFFFFFFFF CTTMRB2 Counter/Timer B2. [31:16] read-write CTTMRA2 Counter/Timer A2. [15:0] read-write CMPRA2 Counter/Timer A2 Compare Registers 0x00000024 32 read-write 0x00000000 0xFFFFFFFF CMPR1A2 Counter/Timer A2 Compare Register 1. [31:16] read-write CMPR0A2 Counter/Timer A2 Compare Register 0. [15:0] read-write CMPRB2 Counter/Timer B2 Compare Registers 0x00000028 32 read-write 0x00000000 0xFFFFFFFF CMPR1B2 Counter/Timer B2 Compare Register 1. [31:16] read-write CMPR0B2 Counter/Timer B2 Compare Register 0. [15:0] read-write CTRL2 Counter/Timer Control 0x0000002C 32 read-write 0x00000000 0x9FFF1FFF CTLINK2 Counter/Timer A2/B2 Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A0/B0 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A2/B2 timers into a single 32-bit timer. 1 TMRB2POL Counter/Timer B2 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB2 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB2 pin is the inverse of the timer output. 1 TMRB2CLR Counter/Timer B2 Clear bit. [27:27] read-write RUN Allow counter/timer B2 to run 0 CLEAR Holds counter/timer B2 at 0x0000. 1 TMRB2PE Counter/Timer B2 Output Enable bit. [26:26] read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB2POL. 0 EN Enable counter/timer B2 to generate a signal on TMRPINB. 1 TMRB2IE Counter/Timer B2 Interrupt Enable bit. [25:25] read-write DIS Disable counter/timer B2 from generating an interrupt. 0 EN Enable counter/timer B2 to generate an interrupt. 1 TMRB2FN Counter/Timer B2 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B2, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB2CLK Counter/Timer B2 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKA Clock source is buck converter stream A. 16 TMRB2EN Counter/Timer B2 Enable bit. [16:16] read-write DIS Counter/Timer B2 Disable. 0 EN Counter/Timer B2 Enable. 1 TMRA2POL Counter/Timer A2 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA2 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA2 pin is the inverse of the timer output. 1 TMRA2CLR Counter/Timer A2 Clear bit. [11:11] read-write RUN Allow counter/timer A2 to run 0 CLEAR Holds counter/timer A2 at 0x0000. 1 TMRA2PE Counter/Timer A2 Output Enable bit. [10:10] read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA2POL. 0 EN Enable counter/timer A2 to generate a signal on TMRPINA. 1 TMRA2IE Counter/Timer A2 Interrupt Enable bit. [9:9] read-write DIS Disable counter/timer A2 from generating an interrupt. 0 EN Enable counter/timer A2 to generate an interrupt. 1 TMRA2FN Counter/Timer A2 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A2, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA2CLK Counter/Timer A2 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream B. 16 TMRA2EN Counter/Timer A2 Enable bit. [0:0] read-write DIS Counter/Timer A2 Disable. 0 EN Counter/Timer A2 Enable. 1 TMR3 Counter/Timer Register 0x00000030 32 read-write 0x00000000 0xFFFFFFFF CTTMRB3 Counter/Timer B3. [31:16] read-write CTTMRA3 Counter/Timer A3. [15:0] read-write CMPRA3 Counter/Timer A3 Compare Registers 0x00000034 32 read-write 0x00000000 0xFFFFFFFF CMPR1A3 Counter/Timer A3 Compare Register 1. [31:16] read-write CMPR0A3 Counter/Timer A3 Compare Register 0. [15:0] read-write CMPRB3 Counter/Timer B3 Compare Registers 0x00000038 32 read-write 0x00000000 0xFFFFFFFF CMPR1B3 Counter/Timer B3 Compare Register 1. [31:16] read-write CMPR0B3 Counter/Timer B3 Compare Register 0. [15:0] read-write CTRL3 Counter/Timer Control 0x0000003C 32 read-write 0x00000000 0x9FFF9FFF CTLINK3 Counter/Timer A/B Link bit. [31:31] read-write TWO_16BIT_TIMERS Use A0/B0 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A3/B3 timers into a single 32-bit timer. 1 TMRB3POL Counter/Timer B3 output polarity. [28:28] read-write NORMAL The polarity of the TMRPINB3 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB3 pin is the inverse of the timer output. 1 TMRB3CLR Counter/Timer B3 Clear bit. [27:27] read-write RUN Allow counter/timer B3 to run. 0 CLEAR Holds counter/timer B3 at 0x0000. 1 TMRB3PE Counter/Timer B3 Output Enable bit. [26:26] read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB3POL. 0 EN Enable counter/timer B3 to generate a signal on TMRPINB. 1 TMRB3IE Counter/Timer B3 Interrupt Enable bit. [25:25] read-write DIS Disable counter/timer B3 from generating an interrupt. 0 EN Enable counter/timer B3 to generate an interrupt. 1 TMRB3FN Counter/Timer B3 Function Select. [24:22] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B3, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB3CLK Counter/Timer B3 Clock Select. [21:17] read-write TMRPIN Clock source is TMRPINB. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKA Clock source is buck converter stream A. 16 TMRB3EN Counter/Timer B3 Enable bit. [16:16] read-write DIS Counter/Timer B3 Disable. 0 EN Counter/Timer B3 Enable. 1 ADCEN Special Timer A3 enable for ADC function. [15:15] read-write TMRA3POL Counter/Timer A3 output polarity. [12:12] read-write NORMAL The polarity of the TMRPINA3 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA3 pin is the inverse of the timer output. 1 TMRA3CLR Counter/Timer A3 Clear bit. [11:11] read-write CLEAR Holds counter/timer A3 at 0x0000. 1 TMRA3PE Counter/Timer A3 Output Enable bit. [10:10] read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA3POL. 0 EN Enable counter/timer A3 to generate a signal on TMRPINA. 1 TMRA3IE Counter/Timer A3 Interrupt Enable bit. [9:9] read-write DIS Disable counter/timer A3 from generating an interrupt. 0 EN Enable counter/timer A3 to generate an interrupt. 1 TMRA3FN Counter/Timer A3 Function Select. [8:6] read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A3, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1B, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA3CLK Counter/Timer A3 Clock Select. [5:1] read-write TMRPIN Clock source is TMRPINA. 0 HFRC Clock source is the HFRC 1 HFRC_DIV8 Clock source is HFRC / 8 2 HFRC_DIV128 Clock source is HFRC / 128 3 HFRC_DIV512 Clock source is HFRC / 512 4 HFRC_DIV2K Clock source is HFRC / 2048 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC / 16K 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream B. 16 TMRA3EN Counter/Timer A3 Enable bit. [0:0] read-write DIS Counter/Timer A3 Disable. 0 EN Counter/Timer A3 Enable. 1 INTEN Counter/Timer Interrupts: Enable 0x00000200 32 read-write 0x00000000 0x000000FF CTMRB3INT Counter/Timer B3 interrupt. [7:7] read-write CTMRA3INT Counter/Timer A3 interrupt. [6:6] read-write CTMRB2INT Counter/Timer B2 interrupt. [5:5] read-write CTMRA2INT Counter/Timer A2 interrupt. [4:4] read-write CTMRB1INT Counter/Timer B1 interrupt. [3:3] read-write CTMRA1INT Counter/Timer A1 interrupt. [2:2] read-write CTMRB0INT Counter/Timer B0 interrupt. [1:1] read-write CTMRA0INT Counter/Timer A0 interrupt. [0:0] read-write INTSTAT Counter/Timer Interrupts: Status 0x00000204 32 read-write 0x00000000 0x000000FF CTMRB3INT Counter/Timer B3 interrupt. [7:7] read-write CTMRA3INT Counter/Timer A3 interrupt. [6:6] read-write CTMRB2INT Counter/Timer B2 interrupt. [5:5] read-write CTMRA2INT Counter/Timer A2 interrupt. [4:4] read-write CTMRB1INT Counter/Timer B1 interrupt. [3:3] read-write CTMRA1INT Counter/Timer A1 interrupt. [2:2] read-write CTMRB0INT Counter/Timer B0 interrupt. [1:1] read-write CTMRA0INT Counter/Timer A0 interrupt. [0:0] read-write INTCLR Counter/Timer Interrupts: Clear 0x00000208 32 read-write 0x00000000 0x000000FF CTMRB3INT Counter/Timer B3 interrupt. [7:7] read-write CTMRA3INT Counter/Timer A3 interrupt. [6:6] read-write CTMRB2INT Counter/Timer B2 interrupt. [5:5] read-write CTMRA2INT Counter/Timer A2 interrupt. [4:4] read-write CTMRB1INT Counter/Timer B1 interrupt. [3:3] read-write CTMRA1INT Counter/Timer A1 interrupt. [2:2] read-write CTMRB0INT Counter/Timer B0 interrupt. [1:1] read-write CTMRA0INT Counter/Timer A0 interrupt. [0:0] read-write INTSET Counter/Timer Interrupts: Set 0x0000020C 32 read-write 0x00000000 0x000000FF CTMRB3INT Counter/Timer B3 interrupt. [7:7] read-write CTMRA3INT Counter/Timer A3 interrupt. [6:6] read-write CTMRB2INT Counter/Timer B2 interrupt. [5:5] read-write CTMRA2INT Counter/Timer A2 interrupt. [4:4] read-write CTMRB1INT Counter/Timer B1 interrupt. [3:3] read-write CTMRA1INT Counter/Timer A1 interrupt. [2:2] read-write CTMRB0INT Counter/Timer B0 interrupt. [1:1] read-write CTMRA0INT Counter/Timer A0 interrupt. [0:0] read-write GPIO 1.0 General Purpose IO 0x40010000 32 read-write 0 0x00000220 registers GPIO 9 PADREGA Pad Configuration Register A 0x00000000 32 read-write 0x18181818 0xBF3F3F3F PAD3PWRUP Pad 3 upper power switch enable [31:31] read-write DIS Power switch disabled 0 EN Power switch enabled 1 PAD3FNCSEL Pad 3 function select [29:27] read-write TRIG0 Configure as the ADC Trigger 0 signal 0 SLnCE Configure as the IOSLAVE SPI nCE signal 1 M1nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR1 2 GPIO3 Configure as GPIO3 3 M0nCE Configure as the IOSLAVE SPI nCE loopback signal from IOMSTR0 4 M1nCE Configure as the IOSLAVE SPI nCE loopback signal from IOMSTR1 5 DIS Pad disabled 6 PAD3STRNG Pad 3 drive strength. [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD3INPEN Pad 3 input enable. [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD3PULL Pad 3 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD2FNCSEL Pad 2 function select [21:19] read-write SLWIR3 Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal 0 SLMOSI Configure as the IOSLAVE SPI MOSI signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO2 Configure as GPIO2 3 M0MOSI Configure as the IOSLAVE SPI MOSI loopback signal from IOMSTR0 4 M1MOSI Configure as the IOSLAVE SPI MOSI loopback signal from IOMSTR1 5 M0WIR3 Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback signal from IOMSTR0 6 M1WIR3 Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback signal from IOMSTR1 7 PAD2STRNG Pad 2 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD2INPEN Pad 2 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD2PULL Pad 2 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD1FNCSEL Pad 1 function select [13:11] read-write SLSDA Configure as the IOSLAVE I2C SDA signal 0 SLMISO Configure as the IOSLAVE SPI MISO signal 1 UARTRX Configure as the UART RX signal 2 GPIO1 Configure as GPIO1 3 M0MISO Configure as the IOSLAVE SPI MISO loopback signal from IOMSTR0 4 M1MISO Configure as the IOSLAVE SPI MISO loopback signal from IOMSTR1 5 M0SDA Configure as the IOSLAVE I2C SDA loopback signal from IOMSTR0 6 M1SDA Configure as the IOSLAVE I2C SDA loopback signal from IOMSTR1 7 PAD1STRNG Pad 1 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD1INPEN Pad 1 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD1PULL Pad 1 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD0FNCSEL Pad 0 function select [5:3] read-write SLSCL Configure as the IOSLAVE I2C SCL signal 0 SLSCK Configure as the IOSLAVE SPI SCK signal 1 UARTTX Configure as the UART TX signal 2 GPIO0 Configure as GPIO0 3 M0SCK Configure as the IOSLAVE SPI SCK loopback signal from IOMSTR0 4 M1SCK Configure as the IOSLAVE SPI SCK loopback signal from IOMSTR1 5 M0SCL Configure as the IOSLAVE I2C SCL loopback signal from IOMSTR0 6 M1SCL Configure as the IOSLAVE I2C SCL loopback signal from IOMSTR1 7 PAD0STRNG Pad 0 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD0INPEN Pad 0 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD0PULL Pad 0 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGB Pad Configuration Register B 0x00000004 32 read-write 0x18181818 0x3FFFFFBF PAD7FNCSEL Pad 7 function select [29:27] read-write M0WIR3 Configure as the IOMSTR0 SPI 3-wire MOSI/MISO signal 0 M0MOSI Configure as the IOMSTR0 SPI MOSI signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO7 Configure as GPIO7 3 SLWIR3 Configure as the IOMSTR0 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 6 DIS Pad disabled 7 PAD7STRNG Pad 7 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD7INPEN Pad 7 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD7PULL Pad 7 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD6RSEL Pad 6 pullup resistor selection. [23:22] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD6FNCSEL Pad 6 function select [21:19] read-write M0SDA Configure as the IOMSTR0 I2C SDA signal 0 M0MISO Configure as the IOMSTR0 SPI MISO signal 1 UACTS Configure as the UART CTS signal 2 GPIO6 Configure as GPIO6 3 SLMISO Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE 4 SLSDA Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE 6 DIS Pad disabled 7 PAD6STRNG Pad 6 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD6INPEN Pad 6 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD6PULL Pad 6 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD5RSEL Pad 5 pullup resistor selection. [15:14] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD5FNCSEL Pad 5 function select [13:11] read-write M0SCL Configure as the IOMSTR0 I2C SCL signal 0 M0SCK Configure as the IOMSTR0 SPI SCK signal 1 UARTS Configure as the UART RTS signal 2 GPIO5 Configure as GPIO5 3 SLSCK Configure as the IOMSTR0 SPI SCK loopback signal from IOSLAVE 4 SLSCL Configure as the IOMSTR0 I2C SCL loopback signal from IOSLAVE 6 DIS Pad disabled 7 PAD5STRNG Pad 5 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD5INPEN Pad 5 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD5PULL Pad 5 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD4PWRUP Pad 4 upper power switch enable [7:7] read-write DIS Power switch disabled 0 EN Power switch enabled 1 PAD4FNCSEL Pad 4 function select [5:3] read-write TRIG1 Configure as the ADC Trigger 1 signal 0 SLINT Configure as the IOSLAVE interrupt out signal 1 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 2 GPIO4 Configure as GPIO4 3 SLINTGP Configure as the IOSLAVE interrupt loopback signal to GPIO4 4 SWO Configure as the serial wire debug SWO signal 5 CLKOUT Configure as the CLKOUT signal 6 DIS Pad disabled 7 PAD4STRNG Pad 4 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD4INPEN Pad 4 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD4PULL Pad 4 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGC Pad Configuration Register C 0x00000008 32 read-write 0x18181818 0x5F3FFFFF PAD11PWRDN Pad 11 lower power switch enable [30:30] read-write DIS Power switch disabled 0 EN Power switch enabled 1 PAD11FNCSEL Pad 11 function select [28:27] read-write ANATST Configure as the analog test output signal 0 M0nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR0 1 CLKOUT Configure as the CLKOUT signal 2 GPIO11 Configure as GPIO11 3 PAD11STRNG Pad 11 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD11INPEN Pad 11 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD11PULL Pad 11 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD10FNCSEL Pad 10 function select [21:19] read-write M1WIR3 Configure as the IOMSTR1 SPI 3-wire MOSI/MISO signal 0 M1MOSI Configure as the IOMSTR1 SPI MOSI signal 1 M0nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR0 2 GPIO10 Configure as GPIO10 3 EXTHFA Configure as the external HFRC A clock signal 5 DIS Pad disabled 6 SLWIR3 Configure as the IOMSTR1 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 7 PAD10STRNG Pad 10 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD10INPEN Pad 10 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD10PULL Pad 10 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD9RSEL Pad 9 pullup resistor selection [15:14] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD9FNCSEL Pad 9 function select [13:11] read-write M1SDA Configure as the IOMSTR1 I2C SDA signal 0 M1MISO Configure as the IOMSTR1 SPI MISO signal 1 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 2 GPIO9 Configure as GPIO9 3 SLMISO Configure as the IOMSTR1 SPI MISO loopback signal from IOSLAVE 5 DIS Pad disabled 6 SLSDA Configure as the IOMSTR1 I2C SDA loopback signal from IOSLAVE 7 PAD9STRNG Pad 9 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD9INPEN Pad 9 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD9PULL Pad 9 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD8RSEL Pad 8 pullup resistor selection. [7:6] read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD8FNCSEL Pad 8 function select [5:3] read-write M1SCL Configure as the IOMSTR1 I2C SCL signal 0 M1SCK Configure as the IOMSTR1 SPI SCK signal 1 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 2 GPIO8 Configure as GPIO8 3 SLSCK Configure as the IOMSTR1 SPI SCK loopback signal from IOSLAVE 5 DIS Pad disabled 6 SLSCL Configure as the IOMSTR1 I2C SCL loopback signal from IOSLAVE 7 PAD8STRNG Pad 8 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD8INPEN Pad 8 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD8PULL Pad 8 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGD Pad Configuration Register D 0x0000000C 32 read-write 0x18181818 0x3F3F3F1F PAD15FNCSEL Pad 15 function select [29:27] read-write ADC3 Configure as the analog ADC input 3 0 M1nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR1 1 UARTRX Configure as the UART RX signal 2 GPIO15 Configure as GPIO15 3 EXTXT Configure as the external XT clock signal 5 DIS Pad disabled 7 PAD15STRNG Pad 15 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD15INPEN Pad 15 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD15PULL Pad 15 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD14FNCSEL Pad 14 function select [21:19] read-write ADC2 Configure as the analog ADC input 2 0 M1nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR1 1 UARTTX Configure as the UART TX signal 2 GPIO14 Configure as GPIO14 3 EXTHFS Configure as the external HFRC select signal 5 DIS Pad disabled 7 PAD14STRNG Pad 14 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD14INPEN Pad 14 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD14PULL Pad 14 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD13FNCSEL Pad 13 function select [13:11] read-write ADC1 Configure as the analog ADC input 1 0 M1nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR1 1 TCTB0 Configure as the input/output signal from CTIMER B0 2 GPIO13 Configure as GPIO13 3 EXTHFA Configure as the external HFRC B clock signal 5 SWO Configure as the serial wire debug SWO signal 6 DIS Pad disabled 7 PAD13STRNG Pad 13 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD13INPEN Pad 13 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD13PULL Pad 13 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD12FNCSEL Pad 12 function select [4:3] read-write ADC0 Configure as the analog ADC input 0 0 M1nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR1 1 TCTA0 Configure as the input/output signal from CTIMER A0 2 GPIO12 Configure as GPIO12 3 PAD12STRNG Pad 12 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD12INPEN Pad 12 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD12PULL Pad 12 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGE Pad Configuration Register E 0x00000010 32 read-write 0x18181818 0x1F1F3F1F PAD19FNCSEL Pad 19 function select [28:27] read-write CMPRF Configure as the analog comparator reference signal 0 M0nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR0 1 TCTB1 Configure as the input/output signal from CTIMER B1 2 GPIO19 Configure as GPIO19 3 PAD19STRNG Pad 19 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD19INPEN Pad 19 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD19PULL Pad 19 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD18FNCSEL Pad 18 function select [20:19] read-write CMPIN1 Configure as the analog comparator input 1 signal 0 M0nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR0 1 TCTA1 Configure as the input/output signal from CTIMER A1 2 GPIO18 Configure as GPIO18 3 PAD18STRNG Pad 18 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD18INPEN Pad 18 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD18PULL Pad 18 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD17FNCSEL Pad 17 function select [13:11] read-write CMPIN0 Configure as the analog comparator input 0 signal 0 M0nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR0 1 TRIG3 Configure as the ADC Trigger 3 signal 2 GPIO17 Configure as GPIO17 3 EXTLF Configure as the external LFRC clock signal 5 DIS Pad disabled 7 PAD17STRNG Pad 17 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD17INPEN Pad 17 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD17PULL Pad 17 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD16FNCSEL Pad 16 function select [4:3] read-write ADCREF Configure as the analog ADC reference input signal 0 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 1 TRIG2 Configure as the ADC Trigger 2 signal 2 GPIO16 Configure as GPIO16 3 PAD16STRNG Pad 16 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD16INPEN Pad 16 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD16PULL Pad 16 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGF Pad Configuration Register F 0x00000014 32 read-write 0x18180202 0x1F1F1F1F PAD23FNCSEL Pad 23 function select [28:27] read-write UARTRX Configure as the UART RX signal 0 M0nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR0 1 TCTB3 Configure as the input/output signal from CTIMER B3 2 GPIO23 Configure as GPIO23 3 PAD23STRNG Pad 23 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD23INPEN Pad 23 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD23PULL Pad 23 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD22FNCSEL Pad 22 function select [20:19] read-write UARTTX Configure as the UART TX signal 0 M1nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR1 1 TCTA3 Configure as the input/output signal from CTIMER A3 2 GPIO22 Configure as GPIO22 3 PAD22STRNG Pad 22 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD22INPEN Pad 22 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD22PULL Pad 22 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD21FNCSEL Pad 21 function select [12:11] read-write SWDIO Configure as the serial wire debug data signal 0 M1nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR1 1 TCTB2 Configure as the input/output signal from CTIMER B2 2 GPIO21 Configure as GPIO21 3 PAD21STRNG Pad 21 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD21INPEN Pad 21 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD21PULL Pad 21 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD20FNCSEL Pad 20 function select [4:3] read-write SWDCK Configure as the serial wire debug clock signal 0 M1nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR1 1 TCTA2 Configure as the input/output signal from CTIMER A2 2 GPIO20 Configure as GPIO20 3 PAD20STRNG Pad 20 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD20INPEN Pad 20 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD20PULL Pad 20 pulldown enable [0:0] read-write DIS Pulldown disabled 0 EN Pulldown enabled 1 PADREGG Pad Configuration Register G 0x00000018 32 read-write 0x18181818 0x1F1F1F1F PAD27FNCSEL Pad 27 function select [28:27] read-write EXTHF Configure as the external HFRC clock signal 0 M1nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR1 1 TCTA1 Configure as the input/output signal from CTIMER A1 2 GPIO27 Configure as GPIO27 3 PAD27STRNG Pad 27 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD27INPEN Pad 27 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD27PULL Pad 27 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD26FNCSEL Pad 26 function select [20:19] read-write EXTLF Configure as the external LFRC clock signal 0 M0nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR0 1 TCTB0 Configure as the input/output signal from CTIMER B0 2 GPIO26 Configure as GPIO26 3 PAD26STRNG Pad 26 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD26INPEN Pad 26 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD26PULL Pad 26 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD25FNCSEL Pad 25 function select [12:11] read-write EXTXT Configure as the external XT clock signal 0 M0nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR0 1 TCTA0 Configure as the input/output signal from CTIMER A0 2 GPIO25 Configure as GPIO25 3 PAD25STRNG Pad 25 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD25INPEN Pad 25 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD25PULL Pad 25 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD24FNCSEL Pad 24 function select [4:3] read-write DIS Pad disabled 0 M0nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR0 1 CLKOUT Configure as the CLKOUT signal 2 GPIO24 Configure as GPIO24 3 PAD24STRNG Pad 24 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD24INPEN Pad 24 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD24PULL Pad 24 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGH Pad Configuration Register H 0x0000001C 32 read-write 0x18181818 0x1F1F1F1F PAD31FNCSEL Pad 31 function select [28:27] read-write ADC6 Configure as the analog ADC input 6 signal 0 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 1 TCTA3 Configure as the input/output signal from CTIMER A3 2 GPIO31 Configure as GPIO31 3 PAD31STRNG Pad 31 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD31INPEN Pad 31 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD31PULL Pad 31 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD30FNCSEL Pad 30 function select [20:19] read-write ADC5 Configure as the analog ADC input 5 signal 0 M1nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR1 1 TCTB2 Configure as the input/output signal from CTIMER B2 2 GPIO30 Configure as GPIO30 3 PAD30STRNG Pad 30 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD30INPEN Pad 30 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD30PULL Pad 30 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD29FNCSEL Pad 29 function select [12:11] read-write ADC4 Configure as the analog ADC input 4 signal 0 M1nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR1 1 TCTA2 Configure as the input/output signal from CTIMER A2 2 GPIO29 Configure as GPIO29 3 PAD29STRNG Pad 29 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD29INPEN Pad 29 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD29PULL Pad 29 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD28FNCSEL Pad 28 function select [4:3] read-write DIS Pad disabled 0 M1nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR1 1 TCTB1 Configure as the input/output signal from CTIMER B1 2 GPIO28 Configure as GPIO28 3 PAD28STRNG Pad 28 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD28INPEN Pad 28 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD28PULL Pad 28 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGI Pad Configuration Register I 0x00000020 32 read-write 0x18181818 0x1F1F1F1F PAD35FNCSEL Pad 35 function select [28:27] read-write DIS Pad disabled 0 M1nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR1 1 UARTTX Configure as the UART TX signal 2 GPIO35 Configure as GPIO35 3 PAD35STRNG Pad 35 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD35INPEN Pad 35 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD35PULL Pad 35 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD34FNCSEL Pad 34 function select [20:19] read-write CMPRF2 Configure as the analog comparator reference 2 signal 0 M0nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR0 1 DIS Pad disabled 2 GPIO34 Configure as GPIO34 3 PAD34STRNG Pad 34 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD34INPEN Pad 34 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD34PULL Pad 34 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD33FNCSEL Pad 33 function select [12:11] read-write CMPRF1 Configure as the analog comparator reference 1 signal 0 M0nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR0 1 DIS Pad disabled 2 GPIO33 Configure as GPIO33 3 PAD33STRNG Pad 33 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD33INPEN Pad 33 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD33PULL Pad 33 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD32FNCSEL Pad 32 function select [4:3] read-write ADC7 Configure as the analog ADC input 7 signal 0 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 1 TCTB3 Configure as the input/output signal from CTIMER B3 2 GPIO32 Configure as GPIO32 3 PAD32STRNG Pad 32 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD32INPEN Pad 32 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD32PULL Pad 32 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGJ Pad Configuration Register J 0x00000024 32 read-write 0x18181818 0x1F1F1F1F PAD39FNCSEL Pad 39 function select [28:27] read-write TRIG2 Configure as the ADC Trigger 2 signal 0 UARTTX Configure as the UART TX signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO39 Configure as GPIO39 3 PAD39STRNG Pad 39 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD39INPEN Pad 39 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD39PULL Pad 39 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD38FNCSEL Pad 38 function select [20:19] read-write TRIG1 Configure as the ADC Trigger 1 signal 0 M1nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR1 1 UACTS Configure as the UART CTS signal 2 GPIO38 Configure as GPIO38 3 PAD38STRNG Pad 38 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD38INPEN Pad 38 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD38PULL Pad 38 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD37FNCSEL Pad 37 function select [12:11] read-write TRIG0 Configure as the ADC Trigger 0 signal 0 M1nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR1 1 UARTS Configure as the UART RTS signal 2 GPIO37 Configure as GPIO37 3 PAD37STRNG Pad 37 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD37INPEN Pad 37 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD37PULL Pad 37 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD36FNCSEL Pad 36 function select [4:3] read-write DIS Pad disabled 0 M1nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR1 1 UARTRX Configure as the UART RX signal 2 GPIO36 Configure as GPIO36 3 PAD36STRNG Pad 36 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD36INPEN Pad 36 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD36PULL Pad 36 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGK Pad Configuration Register K 0x00000028 32 read-write 0x18181818 0x1F1F1F1F PAD43FNCSEL Pad 43 function select [28:27] read-write TRIG6 Configure as the ADC Trigger 6 signal 0 M0nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR0 1 TCTB0 Configure as the input/output signal from CTIMER B0 2 GPIO43 Configure as GPIO43 3 PAD43STRNG Pad 43 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD43INPEN Pad 43 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD43PULL Pad 43 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD42FNCSEL Pad 42 function select [20:19] read-write TRIG5 Configure as the ADC Trigger 5 signal 0 M0nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR0 1 TCTA0 Configure as the input/output signal from CTIMER A0 2 GPIO42 Configure as GPIO42 3 PAD42STRNG Pad 42 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD42INPEN Pad 42 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD42PULL Pad 42 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD41FNCSEL Pad 41 function select [12:11] read-write TRIG4 Configure as the ADC Trigger 4 signal 0 DIS Pad disabled 1 SWO Configure as the serial wire debug SWO signal 2 GPIO41 Configure as GPIO41 3 PAD41STRNG Pad 41 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD41INPEN Pad 41 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD41PULL Pad 41 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD40FNCSEL Pad 40 function select [4:3] read-write TRIG3 Configure as the ADC Trigger 3 signal 0 UARTRX Configure as the UART RX signal 1 DIS Pad disabled 2 GPIO40 Configure as GPIO40 3 PAD40STRNG Pad 40 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD40INPEN Pad 40 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD40PULL Pad 40 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGL Pad Configuration Register L 0x0000002C 32 read-write 0x18181818 0x1F1F1F1F PAD47FNCSEL Pad 47 function select [28:27] read-write DIS Pad disabled 0 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 1 TCTB2 Configure as the input/output signal from CTIMER B2 2 GPIO47 Configure as GPIO47 3 PAD47STRNG Pad 47 drive strentgh [26:26] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD47INPEN Pad 47 input enable [25:25] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD47PULL Pad 47 pullup enable [24:24] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD46FNCSEL Pad 46 function select [20:19] read-write DIS Pad disabled 0 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 1 TCTA2 Configure as the input/output signal from CTIMER A2 2 GPIO46 Configure as GPIO46 3 PAD46STRNG Pad 46 drive strength [18:18] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD46INPEN Pad 46 input enable [17:17] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD46PULL Pad 46 pullup enable [16:16] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD45FNCSEL Pad 45 function select [12:11] read-write DIS Pad disabled 0 M0nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR0 1 TCTB1 Configure as the input/output signal from CTIMER B1 2 GPIO45 Configure as GPIO45 3 PAD45STRNG Pad 45 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD45INPEN Pad 45 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD45PULL Pad 45 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD44FNCSEL Pad 44 function select [4:3] read-write TRIG7 Configure as the ADC Trigger 7 signal 0 M0nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR0 1 TCTA1 Configure as the input/output signal from CTIMER A1 2 GPIO44 Configure as GPIO44 3 PAD44STRNG Pad 44 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD44INPEN Pad 44 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD44PULL Pad 44 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PADREGM Pad Configuration Register M 0x00000030 32 read-write 0x00001818 0x00001F1F PAD49FNCSEL Pad 49 function select [12:11] read-write DIS Pad disabled 0 M0nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR0 1 TCTB3 Configure as the input/output signal from CTIMER B3 2 GPIO49 Configure as GPIO49 3 PAD49STRNG Pad 49 drive strength [10:10] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD49INPEN Pad 49 input enable [9:9] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD49PULL Pad 49 pullup enable [8:8] read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD48FNCSEL Pad 48 function select [4:3] read-write DIS Pad disabled 0 M0nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR0 1 TCTA3 Configure as the input/output signal from CTIMER A3 2 GPIO48 Configure as GPIO48 3 PAD48STRNG Pad 48 drive strength [2:2] read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD48INPEN Pad 48 input enable [1:1] read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD48PULL Pad 48 pullup enable [0:0] read-write DIS Pullup disabled 0 EN Pullup enabled 1 CFGA GPIO Configuration Register A 0x00000040 32 read-write 0x00000000 0xFFFFFFFF GPIO7INTD GPIO7 interrupt direction. [31:31] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO7OUTCFG GPIO7 output configuration. [30:29] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO7INCFG GPIO7 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO6INTD GPIO6 interrupt direction. [27:27] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO6OUTCFG GPIO6 output configuration. [26:25] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO6INCFG GPIO6 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO5INTD GPIO5 interrupt direction. [23:23] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO5OUTCFG GPIO5 output configuration. [22:21] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO5INCFG GPIO5 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO4INTD GPIO4 interrupt direction. [19:19] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO4OUTCFG GPIO4 output configuration. [18:17] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO4INCFG GPIO4 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO3INTD GPIO3 interrupt direction. [15:15] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO3OUTCFG GPIO3 output configuration. [14:13] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO3INCFG GPIO3 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO2INTD GPIO2 interrupt direction. [11:11] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO2OUTCFG GPIO2 output configuration. [10:9] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO2INCFG GPIO2 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO1INTD GPIO1 interrupt direction. [7:7] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO1OUTCFG GPIO1 output configuration. [6:5] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO1INCFG GPIO1 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO0INTD GPIO0 interrupt direction. [3:3] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO0OUTCFG GPIO0 output configuration. [2:1] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO0INCFG GPIO0 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 CFGB GPIO Configuration Register B 0x00000044 32 read-write 0x00000000 0xFFFFFFFF GPIO15INTD GPIO15 interrupt direction. [31:31] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO15OUTCFG GPIO15 output configuration. [30:29] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO15INCFG GPIO15 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO14INTD GPIO14 interrupt direction. [27:27] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO14OUTCFG GPIO14 output configuration. [26:25] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO14INCFG GPIO14 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO13INTD GPIO13 interrupt direction. [23:23] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO13OUTCFG GPIO13 output configuration. [22:21] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO13INCFG GPIO13 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO12INTD GPIO12 interrupt direction. [19:19] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO12OUTCFG GPIO12 output configuration. [18:17] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO12INCFG GPIO12 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO11INTD GPIO11 interrupt direction. [15:15] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO11OUTCFG GPIO11 output configuration. [14:13] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO11INCFG GPIO11 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO10INTD GPIO10 interrupt direction. [11:11] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO10OUTCFG GPIO10 output configuration. [10:9] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO10INCFG GPIO10 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO9INTD GPIO9 interrupt direction. [7:7] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO9OUTCFG GPIO9 output configuration. [6:5] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO9INCFG GPIO9 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO8INTD GPIO8 interrupt direction. [3:3] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO8OUTCFG GPIO8 output configuration. [2:1] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO8INCFG GPIO8 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 CFGC GPIO Configuration Register C 0x00000048 32 read-write 0x00110000 0xFFFFFFFF GPIO23INTD GPIO23 interrupt direction. [31:31] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO23OUTCFG GPIO23 output configuration. [30:29] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO23INCFG GPIO23 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO22INTD GPIO22 interrupt direction. [27:27] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO22OUTCFG GPIO22 output configuration. [26:25] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO22INCFG GPIO22 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO21INTD GPIO21 interrupt direction. [23:23] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO21OUTCFG GPIO21 output configuration. [22:21] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO21INCFG GPIO21 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO20INTD GPIO20 interrupt direction. [19:19] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO20OUTCFG GPIO20 output configuration. [18:17] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO20INCFG GPIO20 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO19INTD GPIO19 interrupt direction. [15:15] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO19OUTCFG GPIO19 output configuration. [14:13] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO19INCFG GPIO19 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO18INTD GPIO18 interrupt direction. [11:11] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO18OUTCFG GPIO18 output configuration. [10:9] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO18INCFG GPIO18 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO17INTD GPIO17 interrupt direction. [7:7] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO17OUTCFG GPIO17 output configuration. [6:5] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO17INCFG GPIO17 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO16INTD GPIO16 interrupt direction. [3:3] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO16OUTCFG GPIO16 output configuration. [2:1] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO16INCFG GPIO16 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 CFGD GPIO Configuration Register D 0x0000004C 32 read-write 0x00000000 0xFFFFFFFF GPIO31INTD GPIO31 interrupt direction. [31:31] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO31OUTCFG GPIO31 output configuration. [30:29] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO31INCFG GPIO31 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO30INTD GPIO30 interrupt direction. [27:27] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO30OUTCFG GPIO30 output configuration. [26:25] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO30INCFG GPIO30 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO29INTD GPIO29 interrupt direction. [23:23] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO29OUTCFG GPIO29 output configuration. [22:21] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO29INCFG GPIO29 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO28INTD GPIO28 interrupt direction. [19:19] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO28OUTCFG GPIO28 output configuration. [18:17] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO28INCFG GPIO28 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO27INTD GPIO27 interrupt direction. [15:15] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO27OUTCFG GPIO27 output configuration. [14:13] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO27INCFG GPIO27 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO26INTD GPIO26 interrupt direction. [11:11] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO26OUTCFG GPIO26 output configuration. [10:9] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO26INCFG GPIO26 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO25INTD GPIO25 interrupt direction. [7:7] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO25OUTCFG GPIO25 output configuration. [6:5] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO25INCFG GPIO25 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO24INTD GPIO24 interrupt direction. [3:3] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO24OUTCFG GPIO24 output configuration. [2:1] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO24INCFG GPIO24 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 CFGE GPIO Configuration Register E 0x00000050 32 read-write 0x00000000 0xFFFFFFFF GPIO39INTD GPIO39 interrupt direction. [31:31] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO39OUTCFG GPIO39 output configuration. [30:29] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO39INCFG GPIO39 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO38INTD GPIO38 interrupt direction. [27:27] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO38OUTCFG GPIO38 output configuration. [26:25] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO38INCFG GPIO38 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO37INTD GPIO37 interrupt direction. [23:23] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO37OUTCFG GPIO37 output configuration. [22:21] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO37INCFG GPIO37 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO36INTD GPIO36 interrupt direction. [19:19] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO36OUTCFG GPIO36 output configuration. [18:17] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO36INCFG GPIO36 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO35INTD GPIO35 interrupt direction. [15:15] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO35OUTCFG GPIO35 output configuration. [14:13] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO35INCFG GPIO35 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO34INTD GPIO34 interrupt direction. [11:11] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO34OUTCFG GPIO34 output configuration. [10:9] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO34INCFG GPIO34 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO33INTD GPIO33 interrupt direction. [7:7] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO33OUTCFG GPIO33 output configuration. [6:5] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO33INCFG GPIO33 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO32INTD GPIO32 interrupt direction. [3:3] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO32OUTCFG GPIO32 output configuration. [2:1] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO32INCFG GPIO32 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 CFGF GPIO Configuration Register F 0x00000054 32 read-write 0x00000000 0xFFFFFFFF GPIO47INTD GPIO47 interrupt direction. [31:31] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO47OUTCFG GPIO47 output configuration. [30:29] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO47INCFG GPIO47 input enable. [28:28] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO46INTD GPIO46 interrupt direction. [27:27] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO46OUTCFG GPIO46 output configuration. [26:25] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO46INCFG GPIO46 input enable. [24:24] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO45INTD GPIO45 interrupt direction. [23:23] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO45OUTCFG GPIO45 output configuration. [22:21] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO45INCFG GPIO45 input enable. [20:20] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO44INTD GPIO44 interrupt direction. [19:19] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO44OUTCFG GPIO44 output configuration. [18:17] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO44INCFG GPIO44 input enable. [16:16] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO43INTD GPIO43 interrupt direction. [15:15] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO43OUTCFG GPIO43 output configuration. [14:13] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO43INCFG GPIO43 input enable. [12:12] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO42INTD GPIO42 interrupt direction. [11:11] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO42OUTCFG GPIO42 output configuration. [10:9] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO42INCFG GPIO42 input enable. [8:8] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO41INTD GPIO41 interrupt direction. [7:7] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO41OUTCFG GPIO41 output configuration. [6:5] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO41INCFG GPIO41 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO40INTD GPIO40 interrupt direction. [3:3] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO40OUTCFG GPIO40 output configuration. [2:1] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO40INCFG GPIO40 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 CFGG GPIO Configuration Register G 0x00000058 32 read-write 0x00000000 0x000000FF GPIO49INTD GPIO49 interrupt direction. [7:7] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO49OUTCFG GPIO49 output configuration. [6:5] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO49INCFG GPIO49 input enable. [4:4] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO48INTD GPIO48 interrupt direction. [3:3] read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO48OUTCFG GPIO48 output configuration. [2:1] read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO48INCFG GPIO48 input enable. [0:0] read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 PADKEY Key Register for all pad configuration registers 0x00000060 32 read-write 0x00000000 0xFFFFFFFF PADKEY Key register value. [31:0] read-write Key Key 115 RDA GPIO Input Register A 0x00000080 32 read-write 0x00000000 0xFFFFFFFF RDA GPIO31-0 read data. [31:0] read-write RDB GPIO Input Register B 0x00000084 32 read-write 0x00000000 0x0003FFFF RDB GPIO49-32 read data. [17:0] read-write WTA GPIO Output Register A 0x00000088 32 read-write 0x00000000 0xFFFFFFFF WTA GPIO31-0 write data. [31:0] read-write WTB GPIO Output Register B 0x0000008C 32 read-write 0x00000000 0x0003FFFF WTB GPIO49-32 write data. [17:0] read-write WTSA GPIO Output Register A Set 0x00000090 32 read-write 0x00000000 0xFFFFFFFF WTSA Set the GPIO31-0 write data. [31:0] read-write WTSB GPIO Output Register B Set 0x00000094 32 read-write 0x00000000 0x0003FFFF WTSB Set the GPIO49-32 write data. [17:0] read-write WTCA GPIO Output Register A Clear 0x00000098 32 read-write 0x00000000 0xFFFFFFFF WTCA Clear the GPIO31-0 write data. [31:0] read-write WTCB GPIO Output Register B Clear 0x0000009C 32 read-write 0x00000000 0x0003FFFF WTCB Clear the GPIO49-32 write data. [17:0] read-write ENA GPIO Enable Register A 0x000000A0 32 read-write 0x00000000 0xFFFFFFFF ENA GPIO31-0 output enables [31:0] read-write ENB GPIO Enable Register B 0x000000A4 32 read-write 0x00000000 0x0003FFFF ENB GPIO49-32 output enables [17:0] read-write ENSA GPIO Enable Register A Set 0x000000A8 32 read-write 0x00000000 0xFFFFFFFF ENSA Set the GPIO31-0 output enables [31:0] read-write ENSB GPIO Enable Register B Set 0x000000AC 32 read-write 0x00000000 0x0003FFFF ENSB Set the GPIO49-32 output enables [17:0] read-write ENCA GPIO Enable Register A Clear 0x000000B4 32 read-write 0x00000000 0xFFFFFFFF ENCA Clear the GPIO31-0 output enables [31:0] read-write ENCB GPIO Enable Register B Clear 0x000000B8 32 read-write 0x00000000 0x0003FFFF ENCB Clear the GPIO49-32 output enables [17:0] read-write INT0EN GPIO Interrupt Registers 31-0: Enable 0x00000200 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT0STAT GPIO Interrupt Registers 31-0: Status 0x00000204 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT0CLR GPIO Interrupt Registers 31-0: Clear 0x00000208 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT0SET GPIO Interrupt Registers 31-0: Set 0x0000020C 32 read-write 0x00000000 0xFFFFFFFF GPIO31 GPIO31 interrupt. [31:31] read-write GPIO30 GPIO30 interrupt. [30:30] read-write GPIO29 GPIO29 interrupt. [29:29] read-write GPIO28 GPIO28 interrupt. [28:28] read-write GPIO27 GPIO27 interrupt. [27:27] read-write GPIO26 GPIO26 interrupt. [26:26] read-write GPIO25 GPIO25 interrupt. [25:25] read-write GPIO24 GPIO24 interrupt. [24:24] read-write GPIO23 GPIO23 interrupt. [23:23] read-write GPIO22 GPIO22 interrupt. [22:22] read-write GPIO21 GPIO21 interrupt. [21:21] read-write GPIO20 GPIO20 interrupt. [20:20] read-write GPIO19 GPIO19 interrupt. [19:19] read-write GPIO18 GPIO18interrupt. [18:18] read-write GPIO17 GPIO17 interrupt. [17:17] read-write GPIO16 GPIO16 interrupt. [16:16] read-write GPIO15 GPIO15 interrupt. [15:15] read-write GPIO14 GPIO14 interrupt. [14:14] read-write GPIO13 GPIO13 interrupt. [13:13] read-write GPIO12 GPIO12 interrupt. [12:12] read-write GPIO11 GPIO11 interrupt. [11:11] read-write GPIO10 GPIO10 interrupt. [10:10] read-write GPIO9 GPIO9 interrupt. [9:9] read-write GPIO8 GPIO8 interrupt. [8:8] read-write GPIO7 GPIO7 interrupt. [7:7] read-write GPIO6 GPIO6 interrupt. [6:6] read-write GPIO5 GPIO5 interrupt. [5:5] read-write GPIO4 GPIO4 interrupt. [4:4] read-write GPIO3 GPIO3 interrupt. [3:3] read-write GPIO2 GPIO2 interrupt. [2:2] read-write GPIO1 GPIO1 interrupt. [1:1] read-write GPIO0 GPIO0 interrupt. [0:0] read-write INT1EN GPIO Interrupt Registers 49-32: Enable 0x00000210 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write INT1STAT GPIO Interrupt Registers 49-32: Status 0x00000214 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write INT1CLR GPIO Interrupt Registers 49-32: Clear 0x00000218 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write INT1SET GPIO Interrupt Registers 49-32: Set 0x0000021C 32 read-write 0x00000000 0x0003FFFF GPIO49 GPIO49 interrupt. [17:17] read-write GPIO48 GPIO48 interrupt. [16:16] read-write GPIO47 GPIO47 interrupt. [15:15] read-write GPIO46 GPIO46 interrupt. [14:14] read-write GPIO45 GPIO45 interrupt. [13:13] read-write GPIO44 GPIO44 interrupt. [12:12] read-write GPIO43 GPIO43 interrupt. [11:11] read-write GPIO42 GPIO42 interrupt. [10:10] read-write GPIO41 GPIO41 interrupt. [9:9] read-write GPIO40 GPIO40 interrupt. [8:8] read-write GPIO39 GPIO39 interrupt. [7:7] read-write GPIO38 GPIO38 interrupt. [6:6] read-write GPIO37 GPIO37 interrupt. [5:5] read-write GPIO36 GPIO36 interrupt. [4:4] read-write GPIO35 GPIO35 interrupt. [3:3] read-write GPIO34 GPIO34 interrupt. [2:2] read-write GPIO33 GPIO33 interrupt. [1:1] read-write GPIO32 GPIO32 interrupt. [0:0] read-write IOMSTR0 1.0 I2C/SPI Master 0x50004000 32 read-write 0 0x00000210 registers IOMSTR0 6 FIFO FIFO Access Port 0x00000000 32 read-write 0x00000000 0xFFFFFFFF FIFO FIFO access port. [31:0] read-write FIFOPTR Current FIFO Pointers 0x00000100 32 read-write 0x00000000 0x007F007F FIFOREM The number of bytes remaining in the FIFO (i.e. 64-FIFOSIZ). [22:16] read-write FIFOSIZ The number of bytes currently in the FIFO. [6:0] read-write TLNGTH Transfer Length 0x00000104 32 read-write 0x00000000 0x00000FFF TLNGTH Remaining transfer length. [11:0] read-write FIFOTHR FIFO Threshold Configuration 0x00000108 32 read-write 0x00000000 0x00003F3F FIFOWTHR FIFO write threshold. [13:8] read-write FIFORTHR FIFO read threshold. [5:0] read-write CLKCFG I/O Clock Configuration 0x0000010C 32 read-write 0x00000000 0xFFFF1F00 TOTPER Clock total count minus 1. [31:24] read-write LOWPER Clock low count minus 1. [23:16] read-write DIVEN Enable clock division by TOTPER. [12:12] read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 DIV3 Enable divide by 3. [11:11] read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 FSEL Select the input clock frequency. [10:8] read-write HFRC_DIV64 Selects the HFRC / 64 as the input clock. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 CMD Command Register 0x00000110 32 read-write 0x00000000 0xFFFFFFFF CMD This register is the I/O Command. [31:0] read-write POS_LENGTH LSB bit position of the CMD LENGTH field. 0 POS_OFFSET LSB bit position of the CMD OFFSET field. 8 POS_ADDRESS LSB bit position of the I2C CMD ADDRESS field. 16 POS_UPLNGTH LSB bit position of the SPI CMD UPLNGTH field. 23 POS_10BIT LSB bit position of the I2C CMD 10-bit field. 26 POS_LSB LSB bit position of the CMD LSB-first field. 27 POS_CONT LSB bit position of the CMD CONTinue field. 28 POS_OPER LSB bit position of the CMD OPERation field. 29 MSK_LENGTH LSB bit mask of the CMD LENGTH field. 255 MSK_OFFSET LSB bit mask of the CMD OFFSET field. 65280 MSK_ADDRESS LSB bit mask of the I2C CMD ADDRESS field. 16711680 MSK_CHNL LSB bit mask of the SPI CMD CHANNEL field. 458752 MSK_UPLNGTH LSB bit mask of the SPI CMD UPLNGTH field. 125829120 MSK_10BIT LSB bit mask of the I2C CMD 10-bit field. 67108864 MSK_LSB LSB bit mask of the CMD LSB-first field. 134217728 MSK_CONT LSB bit mask of the CMD CONTinue field. 268435456 MSK_OPER LSB bit mask of the CMD OPERation field. 3758096384 CMDRPT Command Repeat Register 0x00000114 32 read-write 0x00000000 0x0000001F CMDRPT These bits hold the Command repeat count. [4:0] read-write STATUS Status Register 0x00000118 32 read-write 0x00000000 0x00000007 IDLEST This bit indicates if the I/O state machine is IDLE. [2:2] read-write IDLE The I/O state machine is in the idle state. 1 CMDACT This bit indicates if the I/O Command is active. [1:1] read-write ACTIVE An I/O command is active. 1 ERR This bit indicates if an error interrupt has occurred. [0:0] read-write ERROR An error has been indicated by the IOM. 1 CFG I/O Master Configuration 0x0000011C 32 read-write 0x00000000 0x80000007 IFCEN This bit enables the IO Master. [31:31] read-write DIS Disable the IO Master. 0 EN Enable the IO Master. 1 SPHA This bit selects SPI phase. [2:2] read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL This bit selects SPI polarity. [1:1] read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 IFCSEL This bit selects the I/O interface. [0:0] read-write I2C Selects I2C interface for the I/O Master. 0 SPI Selects SPI interface for the I/O Master. 1 INTEN IO Master Interrupts: Enable 0x00000200 32 read-write 0x00000000 0x000007FF ARB This is the arbitration loss interrupt. [10:10] read-write STOP This is the STOP command interrupt. [9:9] read-write START This is the START command interrupt. [8:8] read-write ICMD This is the illegal command interrupt. [7:7] read-write IACC This is the illegal FIFO access interrupt. [6:6] read-write WTLEN This is the write length mismatch interrupt. [5:5] read-write NAK This is the I2C NAK interrupt. [4:4] read-write FOVFL This is the Read FIFO Overflow interrupt. [3:3] read-write FUNDFL This is the Write FIFO Underflow interrupt. [2:2] read-write THR This is the FIFO Threshold interrupt. [1:1] read-write CMDCMP This is the Command Complete interrupt. [0:0] read-write INTSTAT IO Master Interrupts: Status 0x00000204 32 read-write 0x00000000 0x000007FF ARB This is the arbitration loss interrupt. [10:10] read-write STOP This is the STOP command interrupt. [9:9] read-write START This is the START command interrupt. [8:8] read-write ICMD This is the illegal command interrupt. [7:7] read-write IACC This is the illegal FIFO access interrupt. [6:6] read-write WTLEN This is the write length mismatch interrupt. [5:5] read-write NAK This is the I2C NAK interrupt. [4:4] read-write FOVFL This is the Read FIFO Overflow interrupt. [3:3] read-write FUNDFL This is the Write FIFO Underflow interrupt. [2:2] read-write THR This is the FIFO Threshold interrupt. [1:1] read-write CMDCMP This is the Command Complete interrupt. [0:0] read-write INTCLR IO Master Interrupts: Clear 0x00000208 32 read-write 0x00000000 0x000007FF ARB This is the arbitration loss interrupt. [10:10] read-write STOP This is the STOP command interrupt. [9:9] read-write START This is the START command interrupt. [8:8] read-write ICMD This is the illegal command interrupt. [7:7] read-write IACC This is the illegal FIFO access interrupt. [6:6] read-write WTLEN This is the write length mismatch interrupt. [5:5] read-write NAK This is the I2C NAK interrupt. [4:4] read-write FOVFL This is the Read FIFO Overflow interrupt. [3:3] read-write FUNDFL This is the Write FIFO Underflow interrupt. [2:2] read-write THR This is the FIFO Threshold interrupt. [1:1] read-write CMDCMP This is the Command Complete interrupt. [0:0] read-write INTSET IO Master Interrupts: Set 0x0000020C 32 read-write 0x00000000 0x000007FF ARB This is the arbitration loss interrupt. [10:10] read-write STOP This is the STOP command interrupt. [9:9] read-write START This is the START command interrupt. [8:8] read-write ICMD This is the illegal command interrupt. [7:7] read-write IACC This is the illegal FIFO access interrupt. [6:6] read-write WTLEN This is the write length mismatch interrupt. [5:5] read-write NAK This is the I2C NAK interrupt. [4:4] read-write FOVFL This is the Read FIFO Overflow interrupt. [3:3] read-write FUNDFL This is the Write FIFO Underflow interrupt. [2:2] read-write THR This is the FIFO Threshold interrupt. [1:1] read-write CMDCMP This is the Command Complete interrupt. [0:0] read-write IOMSTR1 0x50005000 IOMSTR1 7 IOSLAVE 1.0 I2C/SPI Slave 0x50000000 32 read-write 0 0x00000220 registers IOSLAVE 4 IOSLAVEACC 5 FIFOPTR Current FIFO Pointer 0x00000100 32 read-write 0x00000000 0x0000FFFF FIFOSIZ The number of bytes currently in the hardware FIFO. [15:8] read-write FIFOPTR Current FIFO pointer. [7:0] read-write FIFOCFG FIFO Configuration 0x00000104 32 read-write 0x20000000 0x3F003F1F ROBASE Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOOBASE*8-1) [29:24] read-write FIFOMAX These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F. [13:8] read-write FIFOBASE These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1). [4:0] read-write FIFOTHR FIFO Threshold Configuration 0x00000108 32 read-write 0x00000000 0x000000FF FIFOTHR FIFO size interrupt threshold. [7:0] read-write FUPD FIFO Update Status 0x0000010C 32 read-write 0x00000000 0x00000003 IOREAD This bitfield indicates an IO read is active. [1:1] read-write FIFOUPD This bit indicates that a FIFO update is underway. [0:0] read-write FIFOCTR Overall FIFO Counter 0x00000110 32 read-write 0x00000000 0x000003FF FIFOCTR Virtual FIFO byte count [9:0] read-write FIFOINC Overall FIFO Counter Increment 0x00000114 32 read-write 0x00000000 0x000003FF FIFOINC Increment the Overall FIFO Counter by this value on a write [9:0] read-write CFG I/O Slave Configuration 0x00000118 32 read-write 0x00000000 0x800FFF17 IFCEN IOSLAVE interface enable. [31:31] read-write DIS Disable the IOSLAVE 0 EN Enable the IOSLAVE 1 I2CADDR 7-bit or 10-bit I2C device address. [19:8] read-write STARTRD This bit holds the cycle to initiate an I/O RAM read. [4:4] read-write LATE Initiate I/O RAM read late in each transferred byte. 0 EARLY Initiate I/O RAM read early in each transferred byte. 1 LSB This bit selects the transfer bit ordering. [2:2] read-write MSB_FIRST Data is assumed to be sent and received with MSB first. 0 LSB_FIRST Data is assumed to be sent and received with LSB first. 1 SPOL This bit selects SPI polarity. [1:1] read-write SPI_MODES_0_3 Polarity 0, handles SPI modes 0 and 3. 0 SPI_MODES_1_2 Polarity 1, handles SPI modes 1 and 2. 1 IFCSEL This bit selects the I/O interface. [0:0] read-write I2C Selects I2C interface for the IO Slave. 0 SPI Selects SPI interface for the IO Slave. 1 PRENC I/O Slave Interrupt Priority Encode 0x0000011C 32 read-write 0x00000000 0x0000001F PRENC These bits hold the priority encode of the REGACC interrupts. [4:0] read-write IOINTCTL I/O Interrupt Control 0x00000120 32 read-write 0x00000000 0xFF01FFFF IOINTSET These bits set the IOINT interrupts when written with a 1. [31:24] read-write IOINTCLR This bit clears all of the IOINT interrupts when written with a 1. [16:16] read-write IOINT These bits read the IOINT interrupts. [15:8] read-write IOINTEN These bits setread the IOINT interrupt enables. [7:0] read-write GENADD General Address Data 0x00000124 32 read-write 0x00000000 0x000000FF GADATA The data supplied on the last General Address reference. [7:0] read-write INTEN IO Slave Interrupts: Enable 0x00000200 32 read-write 0x00000000 0x0000003F IOINTW I2C Interrupt Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write INTSTAT IO Slave Interrupts: Status 0x00000204 32 read-write 0x00000000 0x0000003F IOINTW I2C Interrupt Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write INTCLR IO Slave Interrupts: Clear 0x00000208 32 read-write 0x00000000 0x0000003F IOINTW I2C Interrupt Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write INTSET IO Slave Interrupts: Set 0x0000020C 32 read-write 0x00000000 0x0000003F IOINTW I2C Interrupt Write interrupt. [5:5] read-write GENAD I2C General Address interrupt. [4:4] read-write FRDERR FIFO Read Error interrupt. [3:3] read-write FUNDFL FIFO Underflow interrupt. [2:2] read-write FOVFL FIFO Overflow interrupt. [1:1] read-write FSIZE FIFO Size interrupt. [0:0] read-write REGACCINTEN Register Access Interrupts: Enable 0x00000210 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write REGACCINTSTAT Register Access Interrupts: Status 0x00000214 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write REGACCINTCLR Register Access Interrupts: Clear 0x00000218 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write REGACCINTSET Register Access Interrupts: Set 0x0000021C 32 read-write 0x00000000 0xFFFFFFFF REGACC Register access interrupts. [31:0] read-write MCUCTRL 1.0 MCU Miscellaneous Control Logic 0x40020000 32 read-write 0 0x00000254 registers BROWNOUT 0 CHIP_INFO Chip Information Register 0x00000000 32 read-write 0x0141114B 0xFFFFFFFF CLASS Device class. [31:24] read-write APOLLO APOLLO 1 FLASH Device flash size. [23:20] read-write 256K 256K of available flash. 3 512K 512K of available flash. 4 RAM Device RAM size. [19:16] read-write 32K 32K of available SRAM. 0 64K 64K of available SRAM. 1 MAJORREV Major device revision number. [15:12] read-write MINORREV Minor device revision number. [11:8] read-write PKG Device package type. [7:6] read-write BGA Ball grid array. 2 CSP Chip-scale package. 3 PINS Number of pins. [5:3] read-write 41PINS 41 package pins total. 1 TEMP Device temperature range. [2:1] read-write COMMERCIAL Commercial temperature range. 0 QUAL Device qualified. [0:0] read-write PROTOTYPE Prototype device. 0 QUALIFIED Fully qualified device. 1 CHIPID0 Unique Chip ID 0 0x00000004 32 read-write 0x00000000 0xFFFFFFFF VALUE Unique chip ID 0. [31:0] read-write APOLLO Apollo CHIPID0. 0 CHIPID1 Unique Chip ID 1 0x00000008 32 read-write 0x00000000 0xFFFFFFFF VALUE Unique chip ID 1. [31:0] read-write APOLLO Apollo CHIPID1. 0 CHIPREV Chip Revision 0x0000000C 32 read-write 0x00000000 0x000000FF REVISION Chip Revision Number. [7:0] read-write APOLLO Apollo CHIPREV. 0 SUPPLYSRC Memory and Core Voltage Supply Source Select Register 0x00000010 32 read-write 0x00000000 0x00000003 COREBUCKEN Enables and Selects the Core Buck as the supply for the low-voltage power domain. [1:1] read-write EN Enable the Core Buck for the low-voltage power domain. 1 MEMBUCKEN Enables and select the Memory Buck as the supply for the Flash and SRAM power domain. [0:0] read-write EN Enable the Memory Buck as the supply for flash and SRAM. 1 SUPPLYSTATUS Memory and Core Voltage Supply Source Status Register 0x00000014 32 read-write 0x00000000 0x00000003 COREBUCKON Indicates whether the Core low-voltage domain is supplied from the LDO or the Buck. [1:1] read-write LDO Indicates the the LDO is supplying the Core low-voltage. 0 BUCK Indicates the the Buck is supplying the Core low-voltage. 1 MEMBUCKON Indicate whether the Memory power domain is supplied from the LDO or the Buck. [0:0] read-write LDO Indicates the LDO is supplying the memory power domain. 0 BUCK Indicates the Buck is supplying the memory power domain. 1 BANDGAPEN Band Gap Enable 0x000000FC 32 read-write 0x00000000 0x00000001 BGPEN Bandgap Enable [0:0] read-write DIS Bandgap disable. 0 EN Bandgap enable. 1 SRAMPWDINSLEEP Powerdown an SRAM Bank in Deep Sleep mode 0x00000140 32 read-write 0x00000000 0x000000FF BANK7 Force SRAM Bank 7 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [7:7] read-write NORMAL SRAM Bank 7 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 7 deep sleep. 1 BANK6 Force SRAM Bank 6 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [6:6] read-write NORMAL SRAM Bank 6 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 6 deep sleep. 1 BANK5 Force SRAM Bank 5 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [5:5] read-write NORMAL SRAM Bank 5 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 5 deep sleep. 1 BANK4 Force SRAM Bank 4 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [4:4] read-write NORMAL SRAM Bank 4 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 4 deep sleep. 1 BANK3 Force SRAM Bank 3 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [3:3] read-write NORMAL SRAM Bank 3 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 3 deep sleep. 1 BANK2 Force SRAM Bank 2 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [2:2] read-write NORMAL SRAM Bank 2 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 2 deep sleep. 1 BANK1 Force SRAM Bank 1 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [1:1] read-write NORMAL SRAM Bank 1 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 1 deep sleep. 1 BANK0 Force SRAM Bank 0 to powerdown in deep sleep mode, causing the contents of the bank to be lost. [0:0] read-write NORMAL SRAM Bank 0 normal operation. 0 PWRDN_IN_DEEPSLEEP SRAM Bank 0 deep sleep. 1 SRAMPWRDIS Disables individual banks of the SRAM array 0x00000144 32 read-write 0x00000000 0x000000FF BANK7 Remove power from SRAM Bank 7 which will cause an access to its address space to generate a Hard Fault. [7:7] read-write DIS Disable SRAM Bank 7. 1 BANK6 Remove power from SRAM Bank 6 which will cause an access to its address space to generate a Hard Fault. [6:6] read-write DIS Disable SRAM Bank 6. 1 BANK5 Remove power from SRAM Bank 5 which will cause an access to its address space to generate a Hard Fault. [5:5] read-write DIS Disable SRAM Bank 5. 1 BANK4 Remove power from SRAM Bank 4 which will cause an access to its address space to generate a Hard Fault. [4:4] read-write DIS Disable SRAM Bank 4. 1 BANK3 Remove power from SRAM Bank 3 which will cause an access to its address space to generate a Hard Fault. [3:3] read-write DIS Disable SRAM Bank 3. 1 BANK2 Remove power from SRAM Bank 2 which will cause an access to its address space to generate a Hard Fault. [2:2] read-write DIS Disable SRAM Bank 2. 1 BANK1 Remove power from SRAM Bank 1 which will cause an access to its address space to generate a Hard Fault. [1:1] read-write DIS Disable SRAM Bank 1. 1 BANK0 Remove power from SRAM Bank 0 which will cause an access to its address space to generate a Hard Fault. [0:0] read-write DIS Disable SRAM Bank 0. 1 FLASHPWRDIS Disables individual banks of the Flash array 0x00000148 32 read-write 0x00000000 0x00000003 BANK1 Remove power from Flash Bank 1 which will cause an access to its address space to generate a Hard Fault. [1:1] read-write DIS Disable Flash instance 1. 1 BANK0 Remove power from Flash Bank 0 which will cause an access to its address space to generate a Hard Fault. [0:0] read-write DIS Disable Flash instance 0. 1 ICODEFAULTADDR ICODE bus address which was present when a bus fault occurred. 0x000001C0 32 read-write 0x00000000 0xFFFFFFFF ADDR The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. [31:0] read-write DCODEFAULTADDR DCODE bus address which was present when a bus fault occurred. 0x000001C4 32 read-write 0x00000000 0xFFFFFFFF ADDR The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. [31:0] read-write SYSFAULTADDR System bus address which was present when a bus fault occurred. 0x000001C8 32 read-write 0x00000000 0xFFFFFFFF ADDR SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. [31:0] read-write FAULTSTATUS Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register. 0x000001CC 32 read-write 0x00000000 0x00000007 SYS SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault. [2:2] read-write NOFAULT No bus fault has been detected. 0 FAULT Bus fault detected. 1 DCODE DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault. [1:1] read-write NOFAULT No DCODE fault has been detected. 0 FAULT DCODE fault detected. 1 ICODE The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault. [0:0] read-write NOFAULT No ICODE fault has been detected. 0 FAULT ICODE fault detected. 1 FAULTCAPTUREEN Enable the fault capture registers 0x000001D0 32 read-write 0x00000000 0x00000001 ENABLE Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers. [0:0] read-write DIS Disable fault capture. 0 EN Enable fault capture. 1 TPIUCTRL TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface. 0x00000250 32 read-write 0x00000000 0x00000301 CLKSEL This field selects the frequency of the ARM M4 TPIU port. [9:8] read-write LOW_PWR Low power state. 0 6MHZ Selects 6MHz frequency. 1 3MHZ Selects 3MHz frequency. 2 1_5MHZ Selects 1.5 MHz frequency. 3 ENABLE TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules. [0:0] read-write DIS Disable the TPIU. 0 EN Enable the TPIU. 1 RSTGEN 1.0 MCU Reset Generator 0x40000000 32 read-write 0 0x00000210 registers CFG Configuration Register 0x00000000 32 read-write 0x00000000 0x00000003 WDREN Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset. [1:1] read-write BODHREN Brown out high (2.1v) reset enable. [0:0] read-write SWPOI Software POI Reset 0x00000004 32 read-write 0x00000000 0x000000FF SWPOIKEY 0x1B generates a software POI reset. [7:0] read-write KEYVALUE Writing 0x1B key value generates a software POI reset. 27 SWPOR Software POR Reset 0x00000008 32 read-write 0x00000000 0x000000FF SWPORKEY 0xD4 generates a software POR reset. [7:0] read-write KEYVALUE Writing 0xD4 key value generates a software POR reset. 212 STAT Status Register 0x0000000C 32 read-write 0x00000000 0x0000007F WDRSTAT Reset was initiated by a Watchdog Timer Reset. [6:6] read-write DBGRSTAT Reset was a initiated by Debugger Reset. [5:5] read-write POIRSTAT Reset was a initiated by Software POI Reset. [4:4] read-write SWRSTAT Reset was a initiated by SW POR or AIRCR Reset. [3:3] read-write BORSTAT Reset was initiated by a Brown-Out Reset. [2:2] read-write PORSTAT Reset was initiated by a Power-On Reset. [1:1] read-write EXRSTAT Reset was initiated by an External Reset. [0:0] read-write CLRSTAT Clear the status register 0x00000010 32 read-write 0x00000000 0x00000001 CLRSTAT Writing a 1 to this bit clears all bits in the RST_STAT. [0:0] read-write INTEN Reset Interrupt register: Enable 0x00000200 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write INTSTAT Reset Interrupt register: Status 0x00000204 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write INTCLR Reset Interrupt register: Clear 0x00000208 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write INTSET Reset Interrupt register: Set 0x0000020C 32 read-write 0x00000000 0x00000001 BODH Enables an interrupt that triggers when VCC is below BODH level. [0:0] read-write RTC 1.0 Real Time Clock 0x40004040 32 read-write 0 0x000000D0 registers CTRLOW RTC Counters Lower 0x00000000 32 read-write 0x01000000 0x3F7F7FFF CTRHR Hours Counter [29:24] read-write CTRMIN Minutes Counter [22:16] read-write CTRSEC Seconds Counter [14:8] read-write CTR100 100ths of a second Counter [7:0] read-write CTRUP RTC Counters Upper 0x00000004 32 read-write 0x00000000 0x9FFF1F3F CTERR Counter read error status [31:31] read-write NOERR No read error occurred 0 RDERR Read error occurred 1 CEB Century enable [28:28] read-write DIS Disable the Century bit from changing 0 EN Enable the Century bit to change 1 CB Century [27:27] read-write 2000 Century is 2000s 0 1900_2100 Century is 1900s/2100s 1 CTRWKDY Weekdays Counter [26:24] read-write CTRYR Years Counter [23:16] read-write CTRMO Months Counter [12:8] read-write CTRDATE Date Counter [5:0] read-write ALMLOW RTC Alarms Lower 0x00000008 32 read-write 0x00000000 0x3F7F7FFF ALMHR Hours Alarm [29:24] read-write ALMMIN Minutes Alarm [22:16] read-write ALMSEC Seconds Alarm [14:8] read-write ALM100 100ths of a second Alarm [7:0] read-write ALMUP RTC Alarms Upper 0x0000000C 32 read-write 0x00000000 0x00071F3F ALMWKDY Weekdays Alarm [18:16] read-write ALMMO Months Alarm [12:8] read-write ALMDATE Date Alarm [5:0] read-write RTCCTL RTC Control Register 0x00000010 32 read-write 0x00000000 0x0000003F HR1224 Hours Counter mode [5:5] read-write 24HR Hours in 24 hour mode 0 12HR Hours in 12 hour mode 1 RSTOP RTC input clock control [4:4] read-write RUN Allow the RTC input clock to run 0 STOP Stop the RTC input clock 1 RPT Alarm repeat interval [3:1] read-write DIS Alarm interrupt disabled 0 YEAR Interrupt every year 1 MONTH Interrupt every month 2 WEEK Interrupt every week 3 DAY Interrupt every day 4 HR Interrupt every hour 5 MIN Interrupt every minute 6 SEC Interrupt every second/10th/100th 7 WRTC Counter write control [0:0] read-write DIS Counter writes are disabled 0 EN Counter writes are enabled 1 INTEN CLK_GEN Interrupt Register: Enable 0x000000C0 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTSTAT CLK_GEN Interrupt Register: Status 0x000000C4 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTCLR CLK_GEN Interrupt Register: Clear 0x000000C8 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write INTSET CLK_GEN Interrupt Register: Set 0x000000CC 32 read-write 0x00000000 0x0000000F ALM RTC Alarm interrupt [3:3] read-write OF XT Oscillator Fail interrupt [2:2] read-write ACC Autocalibration Complete interrupt [1:1] read-write ACF Autocalibration Fail interrupt [0:0] read-write UART 1.0 Serial UART 0x4001C000 32 read-write 0 0x00000048 registers UART 11 DR UART Data Register 0x00000000 32 read-write 0x00000000 0x00000FFF OEDATA This is the overrun error indicator. [11:11] read-write NOERR No error on UART OEDATA, overrun error indicator. 0 ERR Error on UART OEDATA, overrun error indicator. 1 BEDATA This is the break error indicator. [10:10] read-write NOERR No error on UART BEDATA, break error indicator. 0 ERR Error on UART BEDATA, break error indicator. 1 PEDATA This is the parity error indicator. [9:9] read-write NOERR No error on UART PEDATA, parity error indicator. 0 ERR Error on UART PEDATA, parity error indicator. 1 FEDATA This is the framing error indicator. [8:8] read-write NOERR No error on UART FEDATA, framing error indicator. 0 ERR Error on UART FEDATA, framing error indicator. 1 DATA This is the UART data port. [7:0] read-write RSR UART Status Register 0x00000004 32 read-write 0x00000000 0x0000000F OESTAT This is the overrun error indicator. [3:3] read-write NOERR No error on UART OESTAT, overrun error indicator. 0 ERR Error on UART OESTAT, overrun error indicator. 1 BESTAT This is the break error indicator. [2:2] read-write NOERR No error on UART BESTAT, break error indicator. 0 ERR Error on UART BESTAT, break error indicator. 1 PESTAT This is the parity error indicator. [1:1] read-write NOERR No error on UART PESTAT, parity error indicator. 0 ERR Error on UART PESTAT, parity error indicator. 1 FESTAT This is the framing error indicator. [0:0] read-write NOERR No error on UART FESTAT, framing error indicator. 0 ERR Error on UART FESTAT, framing error indicator. 1 FR Flag Register 0x00000018 32 read-write 0x00000000 0x000001FF RI This bit holds the ring indicator. [8:8] read-write TXFE This bit holds the transmit FIFO empty indicator. [7:7] read-write XMTFIFO_EMPTY Transmit fifo is empty. 1 RXFF This bit holds the receive FIFO full indicator. [6:6] read-write RCVFIFO_FULL Receive fifo is full. 1 TXFF This bit holds the transmit FIFO full indicator. [5:5] read-write XMTFIFO_FULL Transmit fifo is full. 1 RXFE This bit holds the receive FIFO empty indicator. [4:4] read-write RCVFIFO_EMPTY Receive fifo is empty. 1 BUSY This bit holds the busy indicator. [3:3] read-write BUSY UART busy indicator. 1 DCD This bit holds the data carrier detect indicator. [2:2] read-write DETECTED Data carrier detect detected. 1 DSR This bit holds the data set ready indicator. [1:1] read-write READY Data set ready. 1 CTS This bit holds the clear to send indicator. [0:0] read-write CLEARTOSEND Clear to send is indicated. 1 ILPR IrDA Counter 0x00000020 32 read-write 0x00000000 0x000000FF ILPDVSR These bits hold the IrDA counter divisor. [7:0] read-write IBRD Integer Baud Rate Divisor 0x00000024 32 read-write 0x00000000 0x0000FFFF DIVINT These bits hold the baud integer divisor. [15:0] read-write FBRD Fractional Baud Rate Divisor 0x00000028 32 read-write 0x00000000 0x0000003F DIVFRAC These bits hold the baud fractional divisor. [5:0] read-write LCRH Line Control High 0x0000002C 32 read-write 0x00000000 0x000000FF SPS This bit holds the stick parity select. [7:7] read-write WLEN These bits hold the write length. [6:5] read-write FEN This bit holds the FIFO enable. [4:4] read-write STP2 This bit holds the two stop bits select. [3:3] read-write EPS This bit holds the even parity select. [2:2] read-write PEN This bit holds the parity enable. [1:1] read-write BRK This bit holds the break set. [0:0] read-write CR Control Register 0x00000030 32 read-write 0x00000300 0x0000FFFF CTSEN This bit enables CTS hardware flow control. [15:15] read-write RTSEN This bit enables RTS hardware flow control. [14:14] read-write OUT2 This bit holds modem Out2. [13:13] read-write OUT1 This bit holds modem Out1. [12:12] read-write RTS This bit enables request to send. [11:11] read-write DTR This bit enables data transmit ready. [10:10] read-write RXE This bit is the receive enable. [9:9] read-write TXE This bit is the transmit enable. [8:8] read-write LBE This bit is the loopback enable. [7:7] read-write CLKSEL This bitfield is the UART clock select. [6:4] read-write NOCLK No UART clock. This is the low power default. 0 24MHZ 24 MHz clock. Must be used if CLKGEN CORESEL=0. 1 12MHZ 12 MHz clock. Must be used if CLKGEN CORESEL=1. Note that CORESEL=1 is unsupported by the IO Master. 2 6MHZ 6 MHz clock. Must be used if CLKGEN CORESEL=2, 3, or 4. Note that CORESEL=2 is unsupported. 3 3MHZ 3 MHz clock. Must be used if CLKGEN CORESEL=5, 6, or 7. 4 CLKEN This bit is the UART clock enable. [3:3] read-write SIRLP This bit is the SIR low power select. [2:2] read-write SIREN This bit is the SIR ENDEC enable. [1:1] read-write UARTEN This bit is the UART enable. [0:0] read-write IFLS FIFO Interrupt Level Select 0x00000034 32 read-write 0x00000012 0x0000003F RXIFLSEL These bits hold the receive FIFO interrupt level. [5:3] read-write TXIFLSEL These bits hold the transmit FIFO interrupt level. [2:0] read-write IER Interrupt Enable 0x00000038 32 read-write 0x00000000 0x000007FF OEIM This bit holds the overflow interrupt enable. [10:10] read-write BEIM This bit holds the break error interrupt enable. [9:9] read-write PEIM This bit holds the parity error interrupt enable. [8:8] read-write FEIM This bit holds the framing error interrupt enable. [7:7] read-write RTIM This bit holds the receive timeout interrupt enable. [6:6] read-write TXIM This bit holds the transmit interrupt enable. [5:5] read-write RXIM This bit holds the receive interrupt enable. [4:4] read-write DSRMIM This bit holds the modem DSR interrupt enable. [3:3] read-write DCDMIM This bit holds the modem DCD interrupt enable. [2:2] read-write CTSMIM This bit holds the modem CTS interrupt enable. [1:1] read-write RIMIM This bit holds the modem RI interrupt enable. [0:0] read-write IES Interrupt Status 0x0000003C 32 read-write 0x00000000 0x000007FF OERIS This bit holds the overflow interrupt status. [10:10] read-write BERIS This bit holds the break error interrupt status. [9:9] read-write PERIS This bit holds the parity error interrupt status. [8:8] read-write FERIS This bit holds the framing error interrupt status. [7:7] read-write RTRIS This bit holds the receive timeout interrupt status. [6:6] read-write TXRIS This bit holds the transmit interrupt status. [5:5] read-write RXRIS This bit holds the receive interrupt status. [4:4] read-write DSRMRIS This bit holds the modem DSR interrupt status. [3:3] read-write DCDMRIS This bit holds the modem DCD interrupt status. [2:2] read-write CTSMRIS This bit holds the modem CTS interrupt status. [1:1] read-write RIMRIS This bit holds the modem RI interrupt status. [0:0] read-write MIS Masked Interrupt Status 0x00000040 32 read-write 0x00000000 0x000007FF OEMIS This bit holds the overflow interrupt status masked. [10:10] read-write BEMIS This bit holds the break error interrupt status masked. [9:9] read-write PEMIS This bit holds the parity error interrupt status masked. [8:8] read-write FEMIS This bit holds the framing error interrupt status masked. [7:7] read-write RTMIS This bit holds the receive timeout interrupt status masked. [6:6] read-write TXMIS This bit holds the transmit interrupt status masked. [5:5] read-write RXMIS This bit holds the receive interrupt status masked. [4:4] read-write DSRMMIS This bit holds the modem DSR interrupt status masked. [3:3] read-write DCDMMIS This bit holds the modem DCD interrupt status masked. [2:2] read-write CTSMMIS This bit holds the modem CTS interrupt status masked. [1:1] read-write RIMMIS This bit holds the modem RI interrupt status masked. [0:0] read-write IEC Interrupt Clear 0x00000044 32 read-write 0x00000000 0x000007FF OEIC This bit holds the overflow interrupt clear. [10:10] read-write BEIC This bit holds the break error interrupt clear. [9:9] read-write PEIC This bit holds the parity error interrupt clear. [8:8] read-write FEIC This bit holds the framing error interrupt clear. [7:7] read-write RTIC This bit holds the receive timeout interrupt clear. [6:6] read-write TXIC This bit holds the transmit interrupt clear. [5:5] read-write RXIC This bit holds the receive interrupt clear. [4:4] read-write DSRMIC This bit holds the modem DSR interrupt clear. [3:3] read-write DCDMIC This bit holds the modem DCD interrupt clear. [2:2] read-write CTSMIC This bit holds the modem CTS interrupt clear. [1:1] read-write RIMIC This bit holds the modem RI interrupt clear. [0:0] read-write VCOMP 1.0 Voltage Comparator 0x4000C000 32 read-write 0 0x00000210 registers VCOMP 3 CFG Configuration Register 0x00000000 32 read-write 0x00000000 0x000F0303 LVLSEL When the reference input NSEL is set to NSEL_DAC, this bitfield selects the voltage level for the negative input to the comparator. [19:16] read-write 0P58V Set Reference input to 0.58 Volts. 0 0P77V Set Reference input to 0.77 Volts. 1 0P97V Set Reference input to 0.97 Volts. 2 1P16V Set Reference input to 1.16 Volts. 3 1P35V Set Reference input to 1.35 Volts. 4 1P55V Set Reference input to 1.55 Volts. 5 1P74V Set Reference input to 1.74 Volts. 6 1P93V Set Reference input to 1.93 Volts. 7 2P13V Set Reference input to 2.13 Volts. 8 2P32V Set Reference input to 2.32 Volts. 9 2P51V Set Reference input to 2.51 Volts. 10 2P71V Set Reference input to 2.71 Volts. 11 2P90V Set Reference input to 2.90 Volts. 12 3P09V Set Reference input to 3.09 Volts. 13 3P29V Set Reference input to 3.29 Volts. 14 3P48V Set Reference input to 3.48 Volts. 15 NSEL This bitfield selects the negative input to the comparator. [9:8] read-write VREFEXT1 Use external reference 1 for reference input. 0 VREFEXT2 Use external reference 2 for reference input. 1 VREFEXT3 Use external reference 3 for reference input. 3 PSEL This bitfield selects the positive input to the comparator. [1:0] read-write VDDADJ Use VDDADJ for the positive input. 0 VTEMP Use the temperature sensor output for the positive input. 1 VEXT1 Use external voltage 1 for positive input. 2 VEXT2 Use external voltage 1 for positive input. 3 STAT Status Register 0x00000004 32 read-write 0x00000000 0x00000003 PWDSTAT This bit indicates the power down state of the voltage comparator. [1:1] read-write POWERED_DOWN The voltage comparator is powered down. 1 CMPOUT This bit is 1 if the positive input of the comparator is greater than the negative input. [0:0] read-write VOUT_LOW The negative input of the comparator is greater than the positive input. 0 VOUT_HIGH The positive input of the comparator is greater than the negative input. 1 PWDKEY Key Register for Powering Down the Voltage Comparator 0x00000008 32 read-write 0x00000000 0xFFFFFFFF PWDKEY Key register value. [31:0] read-write Key Key 55 INTEN Voltage Comparator Interrupt registers: Enable 0x00000200 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write INTSTAT Voltage Comparator Interrupt registers: Status 0x00000204 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write INTCLR Voltage Comparator Interrupt registers: Clear 0x00000208 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write INTSET Voltage Comparator Interrupt registers: Set 0x0000020C 32 read-write 0x00000000 0x00000003 OUTHI This bit is the vcompout high interrupt. [1:1] read-write OUTLOW This bit is the vcompout low interrupt. [0:0] read-write WDT 1.0 Watchdog Timer 0x40024000 32 read-write 0 0x00000210 registers WDT 1 CFG Configuration Register 0x00000000 32 read-write 0x00000000 0x00FFFF07 INTVAL This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt. [23:16] read-write RESVAL This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset. [15:8] read-write RESEN This bitfield enables the WDT reset. [2:2] read-write INTEN This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC. [1:1] read-write WDTEN This bitfield enables the WDT. [0:0] read-write RSTRT Restart the watchdog timer 0x00000004 32 read-write 0x00000000 0x000000FF RSTRT Writing 0xB2 to WDTRSTRT restarts the watchdog timer. [7:0] read-write KEYVALUE This is the key value to write to WDTRSTRT to restart the WDT. 178 LOCK Locks the WDT 0x00000008 32 read-write 0x00000000 0x000000FF LOCK Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set. [7:0] read-write KEYVALUE This is the key value to write to WDTLOCK to lock the WDT. 58 INTEN WDT Interrupt register: Enable 0x00000200 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write INTSTAT WDT Interrupt register: Status 0x00000204 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write INTCLR WDT Interrupt register: Clear 0x00000208 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write INTSET WDT Interrupt register: Set 0x0000020C 32 read-write 0x00000000 0x00000001 WDTINT Watchdog Timer Interrupt. [0:0] read-write