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2022-10-23 23:45:43 -07:00
commit e190fa5193
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+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - FIFO Access Port"]
+    pub fifo: FIFO,
+    _reserved1: [u8; 0xfc],
+    #[doc = "0x100 - FIFO size and remaining slots open values"]
+    pub fifoptr: FIFOPTR,
+    #[doc = "0x104 - FIFO Threshold Configuration"]
+    pub fifothr: FIFOTHR,
+    #[doc = "0x108 - FIFO POP register"]
+    pub fifopop: FIFOPOP,
+    #[doc = "0x10c - FIFO PUSH register"]
+    pub fifopush: FIFOPUSH,
+    #[doc = "0x110 - FIFO Control Register"]
+    pub fifoctrl: FIFOCTRL,
+    #[doc = "0x114 - FIFO Pointers"]
+    pub fifoloc: FIFOLOC,
+    _reserved7: [u8; 0xe8],
+    #[doc = "0x200 - I/O Clock Configuration"]
+    pub clkcfg: CLKCFG,
+    _reserved8: [u8; 0x08],
+    #[doc = "0x20c - Command and offset Register"]
+    pub cmd: CMD,
+    #[doc = "0x210 - Command Repeat Register"]
+    pub cmdrpt: CMDRPT,
+    #[doc = "0x214 - High order offset bytes"]
+    pub offsethi: OFFSETHI,
+    #[doc = "0x218 - Command status"]
+    pub cmdstat: CMDSTAT,
+    _reserved12: [u8; 0x04],
+    #[doc = "0x220 - IO Master Interrupts: Enable"]
+    pub inten: INTEN,
+    #[doc = "0x224 - IO Master Interrupts: Status"]
+    pub intstat: INTSTAT,
+    #[doc = "0x228 - IO Master Interrupts: Clear"]
+    pub intclr: INTCLR,
+    #[doc = "0x22c - IO Master Interrupts: Set"]
+    pub intset: INTSET,
+    #[doc = "0x230 - DMA Trigger Enable Register"]
+    pub dmatrigen: DMATRIGEN,
+    #[doc = "0x234 - DMA Trigger Status Register"]
+    pub dmatrigstat: DMATRIGSTAT,
+    #[doc = "0x238 - DMA Configuration Register"]
+    pub dmacfg: DMACFG,
+    #[doc = "0x23c - DMA Total Transfer Count"]
+    pub dmatotcount: DMATOTCOUNT,
+    #[doc = "0x240 - DMA Target Address Register"]
+    pub dmatargaddr: DMATARGADDR,
+    #[doc = "0x244 - DMA Status Register"]
+    pub dmastat: DMASTAT,
+    #[doc = "0x248 - Command Queue Configuration Register"]
+    pub cqcfg: CQCFG,
+    #[doc = "0x24c - CQ Target Read Address Register"]
+    pub cqaddr: CQADDR,
+    #[doc = "0x250 - Command Queue Status Register"]
+    pub cqstat: CQSTAT,
+    #[doc = "0x254 - Command Queue Flag Register"]
+    pub cqflags: CQFLAGS,
+    #[doc = "0x258 - Command Queue Flag Set/Clear Register"]
+    pub cqsetclear: CQSETCLEAR,
+    #[doc = "0x25c - Command Queue Pause Enable Register"]
+    pub cqpauseen: CQPAUSEEN,
+    #[doc = "0x260 - IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue"]
+    pub cqcuridx: CQCURIDX,
+    #[doc = "0x264 - IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue"]
+    pub cqendidx: CQENDIDX,
+    #[doc = "0x268 - IOM Module Status Register"]
+    pub status: STATUS,
+    _reserved31: [u8; 0x94],
+    #[doc = "0x300 - SPI module master configuration"]
+    pub mspicfg: MSPICFG,
+    #[doc = "0x304 - BLE Core Control"]
+    pub blecfg: BLECFG,
+    #[doc = "0x308 - BLE Power command interface"]
+    pub pwrcmd: PWRCMD,
+    #[doc = "0x30c - BLE Core status"]
+    pub bstatus: BSTATUS,
+    _reserved35: [u8; 0x0100],
+    #[doc = "0x410 - BLEIF Master Debug Register"]
+    pub bledbg: BLEDBG,
+}
+#[doc = "FIFO (rw) register accessor: an alias for `Reg<FIFO_SPEC>`"]
+pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
+#[doc = "FIFO Access Port"]
+pub mod fifo;
+#[doc = "FIFOPTR (rw) register accessor: an alias for `Reg<FIFOPTR_SPEC>`"]
+pub type FIFOPTR = crate::Reg<fifoptr::FIFOPTR_SPEC>;
+#[doc = "FIFO size and remaining slots open values"]
+pub mod fifoptr;
+#[doc = "FIFOTHR (rw) register accessor: an alias for `Reg<FIFOTHR_SPEC>`"]
+pub type FIFOTHR = crate::Reg<fifothr::FIFOTHR_SPEC>;
+#[doc = "FIFO Threshold Configuration"]
+pub mod fifothr;
+#[doc = "FIFOPOP (rw) register accessor: an alias for `Reg<FIFOPOP_SPEC>`"]
+pub type FIFOPOP = crate::Reg<fifopop::FIFOPOP_SPEC>;
+#[doc = "FIFO POP register"]
+pub mod fifopop;
+#[doc = "FIFOPUSH (rw) register accessor: an alias for `Reg<FIFOPUSH_SPEC>`"]
+pub type FIFOPUSH = crate::Reg<fifopush::FIFOPUSH_SPEC>;
+#[doc = "FIFO PUSH register"]
+pub mod fifopush;
+#[doc = "FIFOCTRL (rw) register accessor: an alias for `Reg<FIFOCTRL_SPEC>`"]
+pub type FIFOCTRL = crate::Reg<fifoctrl::FIFOCTRL_SPEC>;
+#[doc = "FIFO Control Register"]
+pub mod fifoctrl;
+#[doc = "FIFOLOC (rw) register accessor: an alias for `Reg<FIFOLOC_SPEC>`"]
+pub type FIFOLOC = crate::Reg<fifoloc::FIFOLOC_SPEC>;
+#[doc = "FIFO Pointers"]
+pub mod fifoloc;
+#[doc = "CLKCFG (rw) register accessor: an alias for `Reg<CLKCFG_SPEC>`"]
+pub type CLKCFG = crate::Reg<clkcfg::CLKCFG_SPEC>;
+#[doc = "I/O Clock Configuration"]
+pub mod clkcfg;
+#[doc = "CMD (rw) register accessor: an alias for `Reg<CMD_SPEC>`"]
+pub type CMD = crate::Reg<cmd::CMD_SPEC>;
+#[doc = "Command and offset Register"]
+pub mod cmd;
+#[doc = "CMDRPT (rw) register accessor: an alias for `Reg<CMDRPT_SPEC>`"]
+pub type CMDRPT = crate::Reg<cmdrpt::CMDRPT_SPEC>;
+#[doc = "Command Repeat Register"]
+pub mod cmdrpt;
+#[doc = "OFFSETHI (rw) register accessor: an alias for `Reg<OFFSETHI_SPEC>`"]
+pub type OFFSETHI = crate::Reg<offsethi::OFFSETHI_SPEC>;
+#[doc = "High order offset bytes"]
+pub mod offsethi;
+#[doc = "CMDSTAT (rw) register accessor: an alias for `Reg<CMDSTAT_SPEC>`"]
+pub type CMDSTAT = crate::Reg<cmdstat::CMDSTAT_SPEC>;
+#[doc = "Command status"]
+pub mod cmdstat;
+#[doc = "INTEN (rw) register accessor: an alias for `Reg<INTEN_SPEC>`"]
+pub type INTEN = crate::Reg<inten::INTEN_SPEC>;
+#[doc = "IO Master Interrupts: Enable"]
+pub mod inten;
+#[doc = "INTSTAT (rw) register accessor: an alias for `Reg<INTSTAT_SPEC>`"]
+pub type INTSTAT = crate::Reg<intstat::INTSTAT_SPEC>;
+#[doc = "IO Master Interrupts: Status"]
+pub mod intstat;
+#[doc = "INTCLR (rw) register accessor: an alias for `Reg<INTCLR_SPEC>`"]
+pub type INTCLR = crate::Reg<intclr::INTCLR_SPEC>;
+#[doc = "IO Master Interrupts: Clear"]
+pub mod intclr;
+#[doc = "INTSET (rw) register accessor: an alias for `Reg<INTSET_SPEC>`"]
+pub type INTSET = crate::Reg<intset::INTSET_SPEC>;
+#[doc = "IO Master Interrupts: Set"]
+pub mod intset;
+#[doc = "DMATRIGEN (rw) register accessor: an alias for `Reg<DMATRIGEN_SPEC>`"]
+pub type DMATRIGEN = crate::Reg<dmatrigen::DMATRIGEN_SPEC>;
+#[doc = "DMA Trigger Enable Register"]
+pub mod dmatrigen;
+#[doc = "DMATRIGSTAT (rw) register accessor: an alias for `Reg<DMATRIGSTAT_SPEC>`"]
+pub type DMATRIGSTAT = crate::Reg<dmatrigstat::DMATRIGSTAT_SPEC>;
+#[doc = "DMA Trigger Status Register"]
+pub mod dmatrigstat;
+#[doc = "DMACFG (rw) register accessor: an alias for `Reg<DMACFG_SPEC>`"]
+pub type DMACFG = crate::Reg<dmacfg::DMACFG_SPEC>;
+#[doc = "DMA Configuration Register"]
+pub mod dmacfg;
+#[doc = "DMATOTCOUNT (rw) register accessor: an alias for `Reg<DMATOTCOUNT_SPEC>`"]
+pub type DMATOTCOUNT = crate::Reg<dmatotcount::DMATOTCOUNT_SPEC>;
+#[doc = "DMA Total Transfer Count"]
+pub mod dmatotcount;
+#[doc = "DMATARGADDR (rw) register accessor: an alias for `Reg<DMATARGADDR_SPEC>`"]
+pub type DMATARGADDR = crate::Reg<dmatargaddr::DMATARGADDR_SPEC>;
+#[doc = "DMA Target Address Register"]
+pub mod dmatargaddr;
+#[doc = "DMASTAT (rw) register accessor: an alias for `Reg<DMASTAT_SPEC>`"]
+pub type DMASTAT = crate::Reg<dmastat::DMASTAT_SPEC>;
+#[doc = "DMA Status Register"]
+pub mod dmastat;
+#[doc = "CQCFG (rw) register accessor: an alias for `Reg<CQCFG_SPEC>`"]
+pub type CQCFG = crate::Reg<cqcfg::CQCFG_SPEC>;
+#[doc = "Command Queue Configuration Register"]
+pub mod cqcfg;
+#[doc = "CQADDR (rw) register accessor: an alias for `Reg<CQADDR_SPEC>`"]
+pub type CQADDR = crate::Reg<cqaddr::CQADDR_SPEC>;
+#[doc = "CQ Target Read Address Register"]
+pub mod cqaddr;
+#[doc = "CQSTAT (rw) register accessor: an alias for `Reg<CQSTAT_SPEC>`"]
+pub type CQSTAT = crate::Reg<cqstat::CQSTAT_SPEC>;
+#[doc = "Command Queue Status Register"]
+pub mod cqstat;
+#[doc = "CQFLAGS (rw) register accessor: an alias for `Reg<CQFLAGS_SPEC>`"]
+pub type CQFLAGS = crate::Reg<cqflags::CQFLAGS_SPEC>;
+#[doc = "Command Queue Flag Register"]
+pub mod cqflags;
+#[doc = "CQSETCLEAR (rw) register accessor: an alias for `Reg<CQSETCLEAR_SPEC>`"]
+pub type CQSETCLEAR = crate::Reg<cqsetclear::CQSETCLEAR_SPEC>;
+#[doc = "Command Queue Flag Set/Clear Register"]
+pub mod cqsetclear;
+#[doc = "CQPAUSEEN (rw) register accessor: an alias for `Reg<CQPAUSEEN_SPEC>`"]
+pub type CQPAUSEEN = crate::Reg<cqpauseen::CQPAUSEEN_SPEC>;
+#[doc = "Command Queue Pause Enable Register"]
+pub mod cqpauseen;
+#[doc = "CQCURIDX (rw) register accessor: an alias for `Reg<CQCURIDX_SPEC>`"]
+pub type CQCURIDX = crate::Reg<cqcuridx::CQCURIDX_SPEC>;
+#[doc = "IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue"]
+pub mod cqcuridx;
+#[doc = "CQENDIDX (rw) register accessor: an alias for `Reg<CQENDIDX_SPEC>`"]
+pub type CQENDIDX = crate::Reg<cqendidx::CQENDIDX_SPEC>;
+#[doc = "IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue"]
+pub mod cqendidx;
+#[doc = "STATUS (rw) register accessor: an alias for `Reg<STATUS_SPEC>`"]
+pub type STATUS = crate::Reg<status::STATUS_SPEC>;
+#[doc = "IOM Module Status Register"]
+pub mod status;
+#[doc = "MSPICFG (rw) register accessor: an alias for `Reg<MSPICFG_SPEC>`"]
+pub type MSPICFG = crate::Reg<mspicfg::MSPICFG_SPEC>;
+#[doc = "SPI module master configuration"]
+pub mod mspicfg;
+#[doc = "BLECFG (rw) register accessor: an alias for `Reg<BLECFG_SPEC>`"]
+pub type BLECFG = crate::Reg<blecfg::BLECFG_SPEC>;
+#[doc = "BLE Core Control"]
+pub mod blecfg;
+#[doc = "PWRCMD (rw) register accessor: an alias for `Reg<PWRCMD_SPEC>`"]
+pub type PWRCMD = crate::Reg<pwrcmd::PWRCMD_SPEC>;
+#[doc = "BLE Power command interface"]
+pub mod pwrcmd;
+#[doc = "BSTATUS (rw) register accessor: an alias for `Reg<BSTATUS_SPEC>`"]
+pub type BSTATUS = crate::Reg<bstatus::BSTATUS_SPEC>;
+#[doc = "BLE Core status"]
+pub mod bstatus;
+#[doc = "BLEDBG (rw) register accessor: an alias for `Reg<BLEDBG_SPEC>`"]
+pub type BLEDBG = crate::Reg<bledbg::BLEDBG_SPEC>;
+#[doc = "BLEIF Master Debug Register"]
+pub mod bledbg;