initial commit

apollo3-pac/Cargo.toml

@@ -0,0 +1,22 @@
+[package]
+name = "ambiq-apollo3-pac2"
+version = "0.2.0"
+authors = ["Gaute Hope <eg@gaute.vetsj.com>"]
+description = "Peripheral access API for APOLLO3 microcontrollers"
+repository = "https://github.com/gauteh/ambiq-rs"
+license = "MIT/Apache-2.0"
+keywords = ["ambiq", "apollo3", "svd2rust", "embedded", "no_std"]
+categories = ["embedded", "no-std"]
+edition = "2021"
+
+[dependencies]
+bare-metal = "0.2.5"
+cortex-m = "0.7.6"
+vcell = "0.1.3"
+
+[dependencies.cortex-m-rt]
+optional = true
+version = "0.7.1"
+
+[features]
+rt = ["cortex-m-rt/device"]

apollo3-pac/LICENSE-APACHE

@@ -0,0 +1,201 @@
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apollo3-pac/LICENSE-MIT

@@ -0,0 +1,27 @@
+
+Copyright (c) by the authors listed in the associated
+COPYRIGHT file.
+
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
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+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

apollo3-pac/README.md

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+# ambiq-apollo3-pac
+Peripheral access API for APOLLO3 microcontrollers
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+## Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+dual licensed as above, without any additional terms or conditions.

apollo3-pac/build.rs

@@ -0,0 +1,16 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

apollo3-pac/device.x

@@ -0,0 +1,32 @@
+PROVIDE(BROWNOUT = DefaultHandler);
+PROVIDE(WDT = DefaultHandler);
+PROVIDE(RTC = DefaultHandler);
+PROVIDE(VCOMP = DefaultHandler);
+PROVIDE(IOSLAVE = DefaultHandler);
+PROVIDE(IOSLAVEACC = DefaultHandler);
+PROVIDE(IOMSTR0 = DefaultHandler);
+PROVIDE(IOMSTR1 = DefaultHandler);
+PROVIDE(IOMSTR2 = DefaultHandler);
+PROVIDE(IOMSTR3 = DefaultHandler);
+PROVIDE(IOMSTR4 = DefaultHandler);
+PROVIDE(IOMSTR5 = DefaultHandler);
+PROVIDE(BLE = DefaultHandler);
+PROVIDE(GPIO = DefaultHandler);
+PROVIDE(CTIMER = DefaultHandler);
+PROVIDE(UART0 = DefaultHandler);
+PROVIDE(UART1 = DefaultHandler);
+PROVIDE(SCARD = DefaultHandler);
+PROVIDE(ADC = DefaultHandler);
+PROVIDE(PDM = DefaultHandler);
+PROVIDE(MSPI = DefaultHandler);
+PROVIDE(STIMER = DefaultHandler);
+PROVIDE(STIMER_CMPR0 = DefaultHandler);
+PROVIDE(STIMER_CMPR1 = DefaultHandler);
+PROVIDE(STIMER_CMPR2 = DefaultHandler);
+PROVIDE(STIMER_CMPR3 = DefaultHandler);
+PROVIDE(STIMER_CMPR4 = DefaultHandler);
+PROVIDE(STIMER_CMPR5 = DefaultHandler);
+PROVIDE(STIMER_CMPR6 = DefaultHandler);
+PROVIDE(STIMER_CMPR7 = DefaultHandler);
+PROVIDE(CLKGEN = DefaultHandler);
+

apollo3-pac/src/adc.rs

@@ -0,0 +1,164 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Configuration Register"]
+    pub cfg: CFG,
+    #[doc = "0x04 - ADC Power Status"]
+    pub stat: STAT,
+    #[doc = "0x08 - Software trigger"]
+    pub swt: SWT,
+    #[doc = "0x0c - Slot 0 Configuration Register"]
+    pub sl0cfg: SL0CFG,
+    #[doc = "0x10 - Slot 1 Configuration Register"]
+    pub sl1cfg: SL1CFG,
+    #[doc = "0x14 - Slot 2 Configuration Register"]
+    pub sl2cfg: SL2CFG,
+    #[doc = "0x18 - Slot 3 Configuration Register"]
+    pub sl3cfg: SL3CFG,
+    #[doc = "0x1c - Slot 4 Configuration Register"]
+    pub sl4cfg: SL4CFG,
+    #[doc = "0x20 - Slot 5 Configuration Register"]
+    pub sl5cfg: SL5CFG,
+    #[doc = "0x24 - Slot 6 Configuration Register"]
+    pub sl6cfg: SL6CFG,
+    #[doc = "0x28 - Slot 7 Configuration Register"]
+    pub sl7cfg: SL7CFG,
+    #[doc = "0x2c - Window Comparator Upper Limits Register"]
+    pub wulim: WULIM,
+    #[doc = "0x30 - Window Comparator Lower Limits Register"]
+    pub wllim: WLLIM,
+    #[doc = "0x34 - Scale Window Comparator Limits"]
+    pub scwlim: SCWLIM,
+    #[doc = "0x38 - FIFO Data and Valid Count Register"]
+    pub fifo: FIFO,
+    #[doc = "0x3c - FIFO Data and Valid Count Register"]
+    pub fifopr: FIFOPR,
+    _reserved16: [u8; 0x01c0],
+    #[doc = "0x200 - ADC Interrupt registers: Enable"]
+    pub inten: INTEN,
+    #[doc = "0x204 - ADC Interrupt registers: Status"]
+    pub intstat: INTSTAT,
+    #[doc = "0x208 - ADC Interrupt registers: Clear"]
+    pub intclr: INTCLR,
+    #[doc = "0x20c - ADC Interrupt registers: Set"]
+    pub intset: INTSET,
+    _reserved20: [u8; 0x30],
+    #[doc = "0x240 - DMA Trigger Enable Register"]
+    pub dmatrigen: DMATRIGEN,
+    #[doc = "0x244 - DMA Trigger Status Register"]
+    pub dmatrigstat: DMATRIGSTAT,
+    _reserved22: [u8; 0x38],
+    #[doc = "0x280 - DMA Configuration Register"]
+    pub dmacfg: DMACFG,
+    _reserved23: [u8; 0x04],
+    #[doc = "0x288 - DMA Total Transfer Count"]
+    pub dmatotcount: DMATOTCOUNT,
+    #[doc = "0x28c - DMA Target Address Register"]
+    pub dmatargaddr: DMATARGADDR,
+    #[doc = "0x290 - DMA Status Register"]
+    pub dmastat: DMASTAT,
+}
+#[doc = "CFG (rw) register accessor: an alias for `Reg<CFG_SPEC>`"]
+pub type CFG = crate::Reg<cfg::CFG_SPEC>;
+#[doc = "Configuration Register"]
+pub mod cfg;
+#[doc = "STAT (rw) register accessor: an alias for `Reg<STAT_SPEC>`"]
+pub type STAT = crate::Reg<stat::STAT_SPEC>;
+#[doc = "ADC Power Status"]
+pub mod stat;
+#[doc = "SWT (rw) register accessor: an alias for `Reg<SWT_SPEC>`"]
+pub type SWT = crate::Reg<swt::SWT_SPEC>;
+#[doc = "Software trigger"]
+pub mod swt;
+#[doc = "SL0CFG (rw) register accessor: an alias for `Reg<SL0CFG_SPEC>`"]
+pub type SL0CFG = crate::Reg<sl0cfg::SL0CFG_SPEC>;
+#[doc = "Slot 0 Configuration Register"]
+pub mod sl0cfg;
+#[doc = "SL1CFG (rw) register accessor: an alias for `Reg<SL1CFG_SPEC>`"]
+pub type SL1CFG = crate::Reg<sl1cfg::SL1CFG_SPEC>;
+#[doc = "Slot 1 Configuration Register"]
+pub mod sl1cfg;
+#[doc = "SL2CFG (rw) register accessor: an alias for `Reg<SL2CFG_SPEC>`"]
+pub type SL2CFG = crate::Reg<sl2cfg::SL2CFG_SPEC>;
+#[doc = "Slot 2 Configuration Register"]
+pub mod sl2cfg;
+#[doc = "SL3CFG (rw) register accessor: an alias for `Reg<SL3CFG_SPEC>`"]
+pub type SL3CFG = crate::Reg<sl3cfg::SL3CFG_SPEC>;
+#[doc = "Slot 3 Configuration Register"]
+pub mod sl3cfg;
+#[doc = "SL4CFG (rw) register accessor: an alias for `Reg<SL4CFG_SPEC>`"]
+pub type SL4CFG = crate::Reg<sl4cfg::SL4CFG_SPEC>;
+#[doc = "Slot 4 Configuration Register"]
+pub mod sl4cfg;
+#[doc = "SL5CFG (rw) register accessor: an alias for `Reg<SL5CFG_SPEC>`"]
+pub type SL5CFG = crate::Reg<sl5cfg::SL5CFG_SPEC>;
+#[doc = "Slot 5 Configuration Register"]
+pub mod sl5cfg;
+#[doc = "SL6CFG (rw) register accessor: an alias for `Reg<SL6CFG_SPEC>`"]
+pub type SL6CFG = crate::Reg<sl6cfg::SL6CFG_SPEC>;
+#[doc = "Slot 6 Configuration Register"]
+pub mod sl6cfg;
+#[doc = "SL7CFG (rw) register accessor: an alias for `Reg<SL7CFG_SPEC>`"]
+pub type SL7CFG = crate::Reg<sl7cfg::SL7CFG_SPEC>;
+#[doc = "Slot 7 Configuration Register"]
+pub mod sl7cfg;
+#[doc = "WULIM (rw) register accessor: an alias for `Reg<WULIM_SPEC>`"]
+pub type WULIM = crate::Reg<wulim::WULIM_SPEC>;
+#[doc = "Window Comparator Upper Limits Register"]
+pub mod wulim;
+#[doc = "WLLIM (rw) register accessor: an alias for `Reg<WLLIM_SPEC>`"]
+pub type WLLIM = crate::Reg<wllim::WLLIM_SPEC>;
+#[doc = "Window Comparator Lower Limits Register"]
+pub mod wllim;
+#[doc = "SCWLIM (rw) register accessor: an alias for `Reg<SCWLIM_SPEC>`"]
+pub type SCWLIM = crate::Reg<scwlim::SCWLIM_SPEC>;
+#[doc = "Scale Window Comparator Limits"]
+pub mod scwlim;
+#[doc = "FIFO (rw) register accessor: an alias for `Reg<FIFO_SPEC>`"]
+pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
+#[doc = "FIFO Data and Valid Count Register"]
+pub mod fifo;
+#[doc = "FIFOPR (rw) register accessor: an alias for `Reg<FIFOPR_SPEC>`"]
+pub type FIFOPR = crate::Reg<fifopr::FIFOPR_SPEC>;
+#[doc = "FIFO Data and Valid Count Register"]
+pub mod fifopr;
+#[doc = "INTEN (rw) register accessor: an alias for `Reg<INTEN_SPEC>`"]
+pub type INTEN = crate::Reg<inten::INTEN_SPEC>;
+#[doc = "ADC Interrupt registers: Enable"]
+pub mod inten;
+#[doc = "INTSTAT (rw) register accessor: an alias for `Reg<INTSTAT_SPEC>`"]
+pub type INTSTAT = crate::Reg<intstat::INTSTAT_SPEC>;
+#[doc = "ADC Interrupt registers: Status"]
+pub mod intstat;
+#[doc = "INTCLR (rw) register accessor: an alias for `Reg<INTCLR_SPEC>`"]
+pub type INTCLR = crate::Reg<intclr::INTCLR_SPEC>;
+#[doc = "ADC Interrupt registers: Clear"]
+pub mod intclr;
+#[doc = "INTSET (rw) register accessor: an alias for `Reg<INTSET_SPEC>`"]
+pub type INTSET = crate::Reg<intset::INTSET_SPEC>;
+#[doc = "ADC Interrupt registers: Set"]
+pub mod intset;
+#[doc = "DMATRIGEN (rw) register accessor: an alias for `Reg<DMATRIGEN_SPEC>`"]
+pub type DMATRIGEN = crate::Reg<dmatrigen::DMATRIGEN_SPEC>;
+#[doc = "DMA Trigger Enable Register"]
+pub mod dmatrigen;
+#[doc = "DMATRIGSTAT (rw) register accessor: an alias for `Reg<DMATRIGSTAT_SPEC>`"]
+pub type DMATRIGSTAT = crate::Reg<dmatrigstat::DMATRIGSTAT_SPEC>;
+#[doc = "DMA Trigger Status Register"]
+pub mod dmatrigstat;
+#[doc = "DMACFG (rw) register accessor: an alias for `Reg<DMACFG_SPEC>`"]
+pub type DMACFG = crate::Reg<dmacfg::DMACFG_SPEC>;
+#[doc = "DMA Configuration Register"]
+pub mod dmacfg;
+#[doc = "DMATOTCOUNT (rw) register accessor: an alias for `Reg<DMATOTCOUNT_SPEC>`"]
+pub type DMATOTCOUNT = crate::Reg<dmatotcount::DMATOTCOUNT_SPEC>;
+#[doc = "DMA Total Transfer Count"]
+pub mod dmatotcount;
+#[doc = "DMATARGADDR (rw) register accessor: an alias for `Reg<DMATARGADDR_SPEC>`"]
+pub type DMATARGADDR = crate::Reg<dmatargaddr::DMATARGADDR_SPEC>;
+#[doc = "DMA Target Address Register"]
+pub mod dmatargaddr;
+#[doc = "DMASTAT (rw) register accessor: an alias for `Reg<DMASTAT_SPEC>`"]
+pub type DMASTAT = crate::Reg<dmastat::DMASTAT_SPEC>;
+#[doc = "DMA Status Register"]
+pub mod dmastat;

apollo3-pac/src/adc/cfg.rs

@@ -0,0 +1,703 @@
+#[doc = "Register `CFG` reader"]
+pub struct R(crate::R<CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CFG` writer"]
+pub struct W(crate::W<CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADCEN` reader - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'."]
+pub type ADCEN_R = crate::BitReader<ADCEN_A>;
+#[doc = "This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADCEN_A {
+    #[doc = "0: Disable the ADC module. value."]
+    DIS = 0,
+    #[doc = "1: Enable the ADC module. value."]
+    EN = 1,
+}
+impl From<ADCEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: ADCEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ADCEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADCEN_A {
+        match self.bits {
+            false => ADCEN_A::DIS,
+            true => ADCEN_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == ADCEN_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == ADCEN_A::EN
+    }
+}
+#[doc = "Field `ADCEN` writer - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'."]
+pub type ADCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, ADCEN_A, O>;
+impl<'a, const O: u8> ADCEN_W<'a, O> {
+    #[doc = "Disable the ADC module. value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(ADCEN_A::DIS)
+    }
+    #[doc = "Enable the ADC module. value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(ADCEN_A::EN)
+    }
+}
+#[doc = "Field `RPTEN` reader - This bit enables Repeating Scan Mode."]
+pub type RPTEN_R = crate::BitReader<RPTEN_A>;
+#[doc = "This bit enables Repeating Scan Mode.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RPTEN_A {
+    #[doc = "0: In Single Scan Mode, the ADC will complete a single scan upon each trigger event. value."]
+    SINGLE_SCAN = 0,
+    #[doc = "1: In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared. value."]
+    REPEATING_SCAN = 1,
+}
+impl From<RPTEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: RPTEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RPTEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RPTEN_A {
+        match self.bits {
+            false => RPTEN_A::SINGLE_SCAN,
+            true => RPTEN_A::REPEATING_SCAN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SINGLE_SCAN`"]
+    #[inline(always)]
+    pub fn is_single_scan(&self) -> bool {
+        *self == RPTEN_A::SINGLE_SCAN
+    }
+    #[doc = "Checks if the value of the field is `REPEATING_SCAN`"]
+    #[inline(always)]
+    pub fn is_repeating_scan(&self) -> bool {
+        *self == RPTEN_A::REPEATING_SCAN
+    }
+}
+#[doc = "Field `RPTEN` writer - This bit enables Repeating Scan Mode."]
+pub type RPTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, RPTEN_A, O>;
+impl<'a, const O: u8> RPTEN_W<'a, O> {
+    #[doc = "In Single Scan Mode, the ADC will complete a single scan upon each trigger event. value."]
+    #[inline(always)]
+    pub fn single_scan(self) -> &'a mut W {
+        self.variant(RPTEN_A::SINGLE_SCAN)
+    }
+    #[doc = "In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared. value."]
+    #[inline(always)]
+    pub fn repeating_scan(self) -> &'a mut W {
+        self.variant(RPTEN_A::REPEATING_SCAN)
+    }
+}
+#[doc = "Field `LPMODE` reader - Select power mode to enter between active scans."]
+pub type LPMODE_R = crate::BitReader<LPMODE_A>;
+#[doc = "Select power mode to enter between active scans.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPMODE_A {
+    #[doc = "0: Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection. value."]
+    MODE0 = 0,
+    #[doc = "1: Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode. value."]
+    MODE1 = 1,
+}
+impl From<LPMODE_A> for bool {
+    #[inline(always)]
+    fn from(variant: LPMODE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LPMODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LPMODE_A {
+        match self.bits {
+            false => LPMODE_A::MODE0,
+            true => LPMODE_A::MODE1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODE0`"]
+    #[inline(always)]
+    pub fn is_mode0(&self) -> bool {
+        *self == LPMODE_A::MODE0
+    }
+    #[doc = "Checks if the value of the field is `MODE1`"]
+    #[inline(always)]
+    pub fn is_mode1(&self) -> bool {
+        *self == LPMODE_A::MODE1
+    }
+}
+#[doc = "Field `LPMODE` writer - Select power mode to enter between active scans."]
+pub type LPMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, LPMODE_A, O>;
+impl<'a, const O: u8> LPMODE_W<'a, O> {
+    #[doc = "Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection. value."]
+    #[inline(always)]
+    pub fn mode0(self) -> &'a mut W {
+        self.variant(LPMODE_A::MODE0)
+    }
+    #[doc = "Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode. value."]
+    #[inline(always)]
+    pub fn mode1(self) -> &'a mut W {
+        self.variant(LPMODE_A::MODE1)
+    }
+}
+#[doc = "Field `CKMODE` reader - Clock mode register"]
+pub type CKMODE_R = crate::BitReader<CKMODE_A>;
+#[doc = "Clock mode register\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CKMODE_A {
+    #[doc = "0: Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC. value."]
+    LPCKMODE = 0,
+    #[doc = "1: Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0. value."]
+    LLCKMODE = 1,
+}
+impl From<CKMODE_A> for bool {
+    #[inline(always)]
+    fn from(variant: CKMODE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CKMODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CKMODE_A {
+        match self.bits {
+            false => CKMODE_A::LPCKMODE,
+            true => CKMODE_A::LLCKMODE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LPCKMODE`"]
+    #[inline(always)]
+    pub fn is_lpckmode(&self) -> bool {
+        *self == CKMODE_A::LPCKMODE
+    }
+    #[doc = "Checks if the value of the field is `LLCKMODE`"]
+    #[inline(always)]
+    pub fn is_llckmode(&self) -> bool {
+        *self == CKMODE_A::LLCKMODE
+    }
+}
+#[doc = "Field `CKMODE` writer - Clock mode register"]
+pub type CKMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, CKMODE_A, O>;
+impl<'a, const O: u8> CKMODE_W<'a, O> {
+    #[doc = "Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC. value."]
+    #[inline(always)]
+    pub fn lpckmode(self) -> &'a mut W {
+        self.variant(CKMODE_A::LPCKMODE)
+    }
+    #[doc = "Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0. value."]
+    #[inline(always)]
+    pub fn llckmode(self) -> &'a mut W {
+        self.variant(CKMODE_A::LLCKMODE)
+    }
+}
+#[doc = "Field `REFSEL` reader - Select the ADC reference voltage."]
+pub type REFSEL_R = crate::FieldReader<u8, REFSEL_A>;
+#[doc = "Select the ADC reference voltage.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum REFSEL_A {
+    #[doc = "0: Internal 2.0V Bandgap Reference Voltage value."]
+    INT2P0 = 0,
+    #[doc = "1: Internal 1.5V Bandgap Reference Voltage value."]
+    INT1P5 = 1,
+    #[doc = "2: Off Chip 2.0V Reference value."]
+    EXT2P0 = 2,
+    #[doc = "3: Off Chip 1.5V Reference value."]
+    EXT1P5 = 3,
+}
+impl From<REFSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: REFSEL_A) -> Self {
+        variant as _
+    }
+}
+impl REFSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> REFSEL_A {
+        match self.bits {
+            0 => REFSEL_A::INT2P0,
+            1 => REFSEL_A::INT1P5,
+            2 => REFSEL_A::EXT2P0,
+            3 => REFSEL_A::EXT1P5,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `INT2P0`"]
+    #[inline(always)]
+    pub fn is_int2p0(&self) -> bool {
+        *self == REFSEL_A::INT2P0
+    }
+    #[doc = "Checks if the value of the field is `INT1P5`"]
+    #[inline(always)]
+    pub fn is_int1p5(&self) -> bool {
+        *self == REFSEL_A::INT1P5
+    }
+    #[doc = "Checks if the value of the field is `EXT2P0`"]
+    #[inline(always)]
+    pub fn is_ext2p0(&self) -> bool {
+        *self == REFSEL_A::EXT2P0
+    }
+    #[doc = "Checks if the value of the field is `EXT1P5`"]
+    #[inline(always)]
+    pub fn is_ext1p5(&self) -> bool {
+        *self == REFSEL_A::EXT1P5
+    }
+}
+#[doc = "Field `REFSEL` writer - Select the ADC reference voltage."]
+pub type REFSEL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CFG_SPEC, u8, REFSEL_A, 2, O>;
+impl<'a, const O: u8> REFSEL_W<'a, O> {
+    #[doc = "Internal 2.0V Bandgap Reference Voltage value."]
+    #[inline(always)]
+    pub fn int2p0(self) -> &'a mut W {
+        self.variant(REFSEL_A::INT2P0)
+    }
+    #[doc = "Internal 1.5V Bandgap Reference Voltage value."]
+    #[inline(always)]
+    pub fn int1p5(self) -> &'a mut W {
+        self.variant(REFSEL_A::INT1P5)
+    }
+    #[doc = "Off Chip 2.0V Reference value."]
+    #[inline(always)]
+    pub fn ext2p0(self) -> &'a mut W {
+        self.variant(REFSEL_A::EXT2P0)
+    }
+    #[doc = "Off Chip 1.5V Reference value."]
+    #[inline(always)]
+    pub fn ext1p5(self) -> &'a mut W {
+        self.variant(REFSEL_A::EXT1P5)
+    }
+}
+#[doc = "Field `DFIFORDEN` reader - Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register."]
+pub type DFIFORDEN_R = crate::BitReader<DFIFORDEN_A>;
+#[doc = "Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DFIFORDEN_A {
+    #[doc = "0: Destructive Reads are prevented. Reads to the FIFOPR register will not POP an entry off the FIFO. value."]
+    DIS = 0,
+    #[doc = "1: Reads to the FIFOPR registger will automatically pop an entry off the FIFO. value."]
+    EN = 1,
+}
+impl From<DFIFORDEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: DFIFORDEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DFIFORDEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DFIFORDEN_A {
+        match self.bits {
+            false => DFIFORDEN_A::DIS,
+            true => DFIFORDEN_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == DFIFORDEN_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == DFIFORDEN_A::EN
+    }
+}
+#[doc = "Field `DFIFORDEN` writer - Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register."]
+pub type DFIFORDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, DFIFORDEN_A, O>;
+impl<'a, const O: u8> DFIFORDEN_W<'a, O> {
+    #[doc = "Destructive Reads are prevented. Reads to the FIFOPR register will not POP an entry off the FIFO. value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(DFIFORDEN_A::DIS)
+    }
+    #[doc = "Reads to the FIFOPR registger will automatically pop an entry off the FIFO. value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(DFIFORDEN_A::EN)
+    }
+}
+#[doc = "Field `TRIGSEL` reader - Select the ADC trigger source."]
+pub type TRIGSEL_R = crate::FieldReader<u8, TRIGSEL_A>;
+#[doc = "Select the ADC trigger source.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum TRIGSEL_A {
+    #[doc = "0: Off chip External Trigger0 (ADC_ET0) value."]
+    EXT0 = 0,
+    #[doc = "1: Off chip External Trigger1 (ADC_ET1) value."]
+    EXT1 = 1,
+    #[doc = "2: Off chip External Trigger2 (ADC_ET2) value."]
+    EXT2 = 2,
+    #[doc = "3: Off chip External Trigger3 (ADC_ET3) value."]
+    EXT3 = 3,
+    #[doc = "4: Voltage Comparator Output value."]
+    VCOMP = 4,
+    #[doc = "7: Software Trigger value."]
+    SWT = 7,
+}
+impl From<TRIGSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: TRIGSEL_A) -> Self {
+        variant as _
+    }
+}
+impl TRIGSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<TRIGSEL_A> {
+        match self.bits {
+            0 => Some(TRIGSEL_A::EXT0),
+            1 => Some(TRIGSEL_A::EXT1),
+            2 => Some(TRIGSEL_A::EXT2),
+            3 => Some(TRIGSEL_A::EXT3),
+            4 => Some(TRIGSEL_A::VCOMP),
+            7 => Some(TRIGSEL_A::SWT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `EXT0`"]
+    #[inline(always)]
+    pub fn is_ext0(&self) -> bool {
+        *self == TRIGSEL_A::EXT0
+    }
+    #[doc = "Checks if the value of the field is `EXT1`"]
+    #[inline(always)]
+    pub fn is_ext1(&self) -> bool {
+        *self == TRIGSEL_A::EXT1
+    }
+    #[doc = "Checks if the value of the field is `EXT2`"]
+    #[inline(always)]
+    pub fn is_ext2(&self) -> bool {
+        *self == TRIGSEL_A::EXT2
+    }
+    #[doc = "Checks if the value of the field is `EXT3`"]
+    #[inline(always)]
+    pub fn is_ext3(&self) -> bool {
+        *self == TRIGSEL_A::EXT3
+    }
+    #[doc = "Checks if the value of the field is `VCOMP`"]
+    #[inline(always)]
+    pub fn is_vcomp(&self) -> bool {
+        *self == TRIGSEL_A::VCOMP
+    }
+    #[doc = "Checks if the value of the field is `SWT`"]
+    #[inline(always)]
+    pub fn is_swt(&self) -> bool {
+        *self == TRIGSEL_A::SWT
+    }
+}
+#[doc = "Field `TRIGSEL` writer - Select the ADC trigger source."]
+pub type TRIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_SPEC, u8, TRIGSEL_A, 3, O>;
+impl<'a, const O: u8> TRIGSEL_W<'a, O> {
+    #[doc = "Off chip External Trigger0 (ADC_ET0) value."]
+    #[inline(always)]
+    pub fn ext0(self) -> &'a mut W {
+        self.variant(TRIGSEL_A::EXT0)
+    }
+    #[doc = "Off chip External Trigger1 (ADC_ET1) value."]
+    #[inline(always)]
+    pub fn ext1(self) -> &'a mut W {
+        self.variant(TRIGSEL_A::EXT1)
+    }
+    #[doc = "Off chip External Trigger2 (ADC_ET2) value."]
+    #[inline(always)]
+    pub fn ext2(self) -> &'a mut W {
+        self.variant(TRIGSEL_A::EXT2)
+    }
+    #[doc = "Off chip External Trigger3 (ADC_ET3) value."]
+    #[inline(always)]
+    pub fn ext3(self) -> &'a mut W {
+        self.variant(TRIGSEL_A::EXT3)
+    }
+    #[doc = "Voltage Comparator Output value."]
+    #[inline(always)]
+    pub fn vcomp(self) -> &'a mut W {
+        self.variant(TRIGSEL_A::VCOMP)
+    }
+    #[doc = "Software Trigger value."]
+    #[inline(always)]
+    pub fn swt(self) -> &'a mut W {
+        self.variant(TRIGSEL_A::SWT)
+    }
+}
+#[doc = "Field `TRIGPOL` reader - This bit selects the ADC trigger polarity for external off chip triggers."]
+pub type TRIGPOL_R = crate::BitReader<TRIGPOL_A>;
+#[doc = "This bit selects the ADC trigger polarity for external off chip triggers.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGPOL_A {
+    #[doc = "0: Trigger on rising edge. value."]
+    RISING_EDGE = 0,
+    #[doc = "1: Trigger on falling edge. value."]
+    FALLING_EDGE = 1,
+}
+impl From<TRIGPOL_A> for bool {
+    #[inline(always)]
+    fn from(variant: TRIGPOL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl TRIGPOL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TRIGPOL_A {
+        match self.bits {
+            false => TRIGPOL_A::RISING_EDGE,
+            true => TRIGPOL_A::FALLING_EDGE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RISING_EDGE`"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == TRIGPOL_A::RISING_EDGE
+    }
+    #[doc = "Checks if the value of the field is `FALLING_EDGE`"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == TRIGPOL_A::FALLING_EDGE
+    }
+}
+#[doc = "Field `TRIGPOL` writer - This bit selects the ADC trigger polarity for external off chip triggers."]
+pub type TRIGPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, TRIGPOL_A, O>;
+impl<'a, const O: u8> TRIGPOL_W<'a, O> {
+    #[doc = "Trigger on rising edge. value."]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut W {
+        self.variant(TRIGPOL_A::RISING_EDGE)
+    }
+    #[doc = "Trigger on falling edge. value."]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut W {
+        self.variant(TRIGPOL_A::FALLING_EDGE)
+    }
+}
+#[doc = "Field `CLKSEL` reader - Select the source and frequency for the ADC clock. All values not enumerated below are undefined."]
+pub type CLKSEL_R = crate::FieldReader<u8, CLKSEL_A>;
+#[doc = "Select the source and frequency for the ADC clock. All values not enumerated below are undefined.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CLKSEL_A {
+    #[doc = "0: Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing. value."]
+    OFF = 0,
+    #[doc = "1: HFRC Core Clock divided by (CORESEL+1) value."]
+    HFRC = 1,
+    #[doc = "2: HFRC Core Clock / 2 further divided by (CORESEL+1) value."]
+    HFRC_DIV2 = 2,
+}
+impl From<CLKSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CLKSEL_A) -> Self {
+        variant as _
+    }
+}
+impl CLKSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CLKSEL_A> {
+        match self.bits {
+            0 => Some(CLKSEL_A::OFF),
+            1 => Some(CLKSEL_A::HFRC),
+            2 => Some(CLKSEL_A::HFRC_DIV2),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == CLKSEL_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `HFRC`"]
+    #[inline(always)]
+    pub fn is_hfrc(&self) -> bool {
+        *self == CLKSEL_A::HFRC
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV2`"]
+    #[inline(always)]
+    pub fn is_hfrc_div2(&self) -> bool {
+        *self == CLKSEL_A::HFRC_DIV2
+    }
+}
+#[doc = "Field `CLKSEL` writer - Select the source and frequency for the ADC clock. All values not enumerated below are undefined."]
+pub type CLKSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_SPEC, u8, CLKSEL_A, 2, O>;
+impl<'a, const O: u8> CLKSEL_W<'a, O> {
+    #[doc = "Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing. value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(CLKSEL_A::OFF)
+    }
+    #[doc = "HFRC Core Clock divided by (CORESEL+1) value."]
+    #[inline(always)]
+    pub fn hfrc(self) -> &'a mut W {
+        self.variant(CLKSEL_A::HFRC)
+    }
+    #[doc = "HFRC Core Clock / 2 further divided by (CORESEL+1) value."]
+    #[inline(always)]
+    pub fn hfrc_div2(self) -> &'a mut W {
+        self.variant(CLKSEL_A::HFRC_DIV2)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'."]
+    #[inline(always)]
+    pub fn adcen(&self) -> ADCEN_R {
+        ADCEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 2 - This bit enables Repeating Scan Mode."]
+    #[inline(always)]
+    pub fn rpten(&self) -> RPTEN_R {
+        RPTEN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Select power mode to enter between active scans."]
+    #[inline(always)]
+    pub fn lpmode(&self) -> LPMODE_R {
+        LPMODE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Clock mode register"]
+    #[inline(always)]
+    pub fn ckmode(&self) -> CKMODE_R {
+        CKMODE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 8:9 - Select the ADC reference voltage."]
+    #[inline(always)]
+    pub fn refsel(&self) -> REFSEL_R {
+        REFSEL_R::new(((self.bits >> 8) & 3) as u8)
+    }
+    #[doc = "Bit 12 - Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register."]
+    #[inline(always)]
+    pub fn dfiforden(&self) -> DFIFORDEN_R {
+        DFIFORDEN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bits 16:18 - Select the ADC trigger source."]
+    #[inline(always)]
+    pub fn trigsel(&self) -> TRIGSEL_R {
+        TRIGSEL_R::new(((self.bits >> 16) & 7) as u8)
+    }
+    #[doc = "Bit 19 - This bit selects the ADC trigger polarity for external off chip triggers."]
+    #[inline(always)]
+    pub fn trigpol(&self) -> TRIGPOL_R {
+        TRIGPOL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bits 24:25 - Select the source and frequency for the ADC clock. All values not enumerated below are undefined."]
+    #[inline(always)]
+    pub fn clksel(&self) -> CLKSEL_R {
+        CLKSEL_R::new(((self.bits >> 24) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'."]
+    #[inline(always)]
+    pub fn adcen(&mut self) -> ADCEN_W<0> {
+        ADCEN_W::new(self)
+    }
+    #[doc = "Bit 2 - This bit enables Repeating Scan Mode."]
+    #[inline(always)]
+    pub fn rpten(&mut self) -> RPTEN_W<2> {
+        RPTEN_W::new(self)
+    }
+    #[doc = "Bit 3 - Select power mode to enter between active scans."]
+    #[inline(always)]
+    pub fn lpmode(&mut self) -> LPMODE_W<3> {
+        LPMODE_W::new(self)
+    }
+    #[doc = "Bit 4 - Clock mode register"]
+    #[inline(always)]
+    pub fn ckmode(&mut self) -> CKMODE_W<4> {
+        CKMODE_W::new(self)
+    }
+    #[doc = "Bits 8:9 - Select the ADC reference voltage."]
+    #[inline(always)]
+    pub fn refsel(&mut self) -> REFSEL_W<8> {
+        REFSEL_W::new(self)
+    }
+    #[doc = "Bit 12 - Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register."]
+    #[inline(always)]
+    pub fn dfiforden(&mut self) -> DFIFORDEN_W<12> {
+        DFIFORDEN_W::new(self)
+    }
+    #[doc = "Bits 16:18 - Select the ADC trigger source."]
+    #[inline(always)]
+    pub fn trigsel(&mut self) -> TRIGSEL_W<16> {
+        TRIGSEL_W::new(self)
+    }
+    #[doc = "Bit 19 - This bit selects the ADC trigger polarity for external off chip triggers."]
+    #[inline(always)]
+    pub fn trigpol(&mut self) -> TRIGPOL_W<19> {
+        TRIGPOL_W::new(self)
+    }
+    #[doc = "Bits 24:25 - Select the source and frequency for the ADC clock. All values not enumerated below are undefined."]
+    #[inline(always)]
+    pub fn clksel(&mut self) -> CLKSEL_W<24> {
+        CLKSEL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CFG_SPEC;
+impl crate::RegisterSpec for CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cfg::R](R) reader structure"]
+impl crate::Readable for CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"]
+impl crate::Writable for CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CFG to value 0"]
+impl crate::Resettable for CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/dmacfg.rs

@@ -0,0 +1,440 @@
+#[doc = "Register `DMACFG` reader"]
+pub struct R(crate::R<DMACFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMACFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMACFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMACFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMACFG` writer"]
+pub struct W(crate::W<DMACFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMACFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMACFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMACFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DMAEN` reader - DMA Enable"]
+pub type DMAEN_R = crate::BitReader<DMAEN_A>;
+#[doc = "DMA Enable\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAEN_A {
+    #[doc = "0: Disable DMA Function value."]
+    DIS = 0,
+    #[doc = "1: Enable DMA Function value."]
+    EN = 1,
+}
+impl From<DMAEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMAEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMAEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMAEN_A {
+        match self.bits {
+            false => DMAEN_A::DIS,
+            true => DMAEN_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == DMAEN_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == DMAEN_A::EN
+    }
+}
+#[doc = "Field `DMAEN` writer - DMA Enable"]
+pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMAEN_A, O>;
+impl<'a, const O: u8> DMAEN_W<'a, O> {
+    #[doc = "Disable DMA Function value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(DMAEN_A::DIS)
+    }
+    #[doc = "Enable DMA Function value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(DMAEN_A::EN)
+    }
+}
+#[doc = "Field `DMADIR` reader - Direction"]
+pub type DMADIR_R = crate::BitReader<DMADIR_A>;
+#[doc = "Direction\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMADIR_A {
+    #[doc = "0: Peripheral to Memory (SRAM) transaction value."]
+    P2M = 0,
+    #[doc = "1: Memory to Peripheral transaction value."]
+    M2P = 1,
+}
+impl From<DMADIR_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMADIR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMADIR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMADIR_A {
+        match self.bits {
+            false => DMADIR_A::P2M,
+            true => DMADIR_A::M2P,
+        }
+    }
+    #[doc = "Checks if the value of the field is `P2M`"]
+    #[inline(always)]
+    pub fn is_p2m(&self) -> bool {
+        *self == DMADIR_A::P2M
+    }
+    #[doc = "Checks if the value of the field is `M2P`"]
+    #[inline(always)]
+    pub fn is_m2p(&self) -> bool {
+        *self == DMADIR_A::M2P
+    }
+}
+#[doc = "Field `DMADIR` writer - Direction"]
+pub type DMADIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMADIR_A, O>;
+impl<'a, const O: u8> DMADIR_W<'a, O> {
+    #[doc = "Peripheral to Memory (SRAM) transaction value."]
+    #[inline(always)]
+    pub fn p2m(self) -> &'a mut W {
+        self.variant(DMADIR_A::P2M)
+    }
+    #[doc = "Memory to Peripheral transaction value."]
+    #[inline(always)]
+    pub fn m2p(self) -> &'a mut W {
+        self.variant(DMADIR_A::M2P)
+    }
+}
+#[doc = "Field `DMAPRI` reader - Sets the Priority of the DMA request"]
+pub type DMAPRI_R = crate::BitReader<DMAPRI_A>;
+#[doc = "Sets the Priority of the DMA request\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAPRI_A {
+    #[doc = "0: Low Priority (service as best effort) value."]
+    LOW = 0,
+    #[doc = "1: High Priority (service immediately) value."]
+    HIGH = 1,
+}
+impl From<DMAPRI_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMAPRI_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMAPRI_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMAPRI_A {
+        match self.bits {
+            false => DMAPRI_A::LOW,
+            true => DMAPRI_A::HIGH,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOW`"]
+    #[inline(always)]
+    pub fn is_low(&self) -> bool {
+        *self == DMAPRI_A::LOW
+    }
+    #[doc = "Checks if the value of the field is `HIGH`"]
+    #[inline(always)]
+    pub fn is_high(&self) -> bool {
+        *self == DMAPRI_A::HIGH
+    }
+}
+#[doc = "Field `DMAPRI` writer - Sets the Priority of the DMA request"]
+pub type DMAPRI_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMAPRI_A, O>;
+impl<'a, const O: u8> DMAPRI_W<'a, O> {
+    #[doc = "Low Priority (service as best effort) value."]
+    #[inline(always)]
+    pub fn low(self) -> &'a mut W {
+        self.variant(DMAPRI_A::LOW)
+    }
+    #[doc = "High Priority (service immediately) value."]
+    #[inline(always)]
+    pub fn high(self) -> &'a mut W {
+        self.variant(DMAPRI_A::HIGH)
+    }
+}
+#[doc = "Field `DMADYNPRI` reader - Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used."]
+pub type DMADYNPRI_R = crate::BitReader<DMADYNPRI_A>;
+#[doc = "Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMADYNPRI_A {
+    #[doc = "0: Disable dynamic priority (use DMAPRI setting only) value."]
+    DIS = 0,
+    #[doc = "1: Enable dynamic priority value."]
+    EN = 1,
+}
+impl From<DMADYNPRI_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMADYNPRI_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMADYNPRI_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMADYNPRI_A {
+        match self.bits {
+            false => DMADYNPRI_A::DIS,
+            true => DMADYNPRI_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == DMADYNPRI_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == DMADYNPRI_A::EN
+    }
+}
+#[doc = "Field `DMADYNPRI` writer - Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used."]
+pub type DMADYNPRI_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMADYNPRI_A, O>;
+impl<'a, const O: u8> DMADYNPRI_W<'a, O> {
+    #[doc = "Disable dynamic priority (use DMAPRI setting only) value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(DMADYNPRI_A::DIS)
+    }
+    #[doc = "Enable dynamic priority value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(DMADYNPRI_A::EN)
+    }
+}
+#[doc = "Field `DMAHONSTAT` reader - Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared."]
+pub type DMAHONSTAT_R = crate::BitReader<DMAHONSTAT_A>;
+#[doc = "Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAHONSTAT_A {
+    #[doc = "0: ADC conversions will continue regardless of DMA status register value."]
+    DIS = 0,
+    #[doc = "1: ADC conversions will not progress if DMAERR or DMACPL bits in DMA status register are set. value."]
+    EN = 1,
+}
+impl From<DMAHONSTAT_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMAHONSTAT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMAHONSTAT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMAHONSTAT_A {
+        match self.bits {
+            false => DMAHONSTAT_A::DIS,
+            true => DMAHONSTAT_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == DMAHONSTAT_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == DMAHONSTAT_A::EN
+    }
+}
+#[doc = "Field `DMAHONSTAT` writer - Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared."]
+pub type DMAHONSTAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMAHONSTAT_A, O>;
+impl<'a, const O: u8> DMAHONSTAT_W<'a, O> {
+    #[doc = "ADC conversions will continue regardless of DMA status register value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(DMAHONSTAT_A::DIS)
+    }
+    #[doc = "ADC conversions will not progress if DMAERR or DMACPL bits in DMA status register are set. value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(DMAHONSTAT_A::EN)
+    }
+}
+#[doc = "Field `DMAMSK` reader - Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory"]
+pub type DMAMSK_R = crate::BitReader<DMAMSK_A>;
+#[doc = "Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAMSK_A {
+    #[doc = "0: FIFO Contents are copied directly to memory without modification. value."]
+    DIS = 0,
+    #[doc = "1: Only the FIFODATA contents are copied to memory on DMA transfers. The SLOTNUM and FIFOCNT contents are cleared to zero. value."]
+    EN = 1,
+}
+impl From<DMAMSK_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMAMSK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMAMSK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMAMSK_A {
+        match self.bits {
+            false => DMAMSK_A::DIS,
+            true => DMAMSK_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == DMAMSK_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == DMAMSK_A::EN
+    }
+}
+#[doc = "Field `DMAMSK` writer - Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory"]
+pub type DMAMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMAMSK_A, O>;
+impl<'a, const O: u8> DMAMSK_W<'a, O> {
+    #[doc = "FIFO Contents are copied directly to memory without modification. value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(DMAMSK_A::DIS)
+    }
+    #[doc = "Only the FIFODATA contents are copied to memory on DMA transfers. The SLOTNUM and FIFOCNT contents are cleared to zero. value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(DMAMSK_A::EN)
+    }
+}
+#[doc = "Field `DPWROFF` reader - Power Off the ADC System upon DMACPL."]
+pub type DPWROFF_R = crate::BitReader<bool>;
+#[doc = "Field `DPWROFF` writer - Power Off the ADC System upon DMACPL."]
+pub type DPWROFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline(always)]
+    pub fn dmaen(&self) -> DMAEN_R {
+        DMAEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 2 - Direction"]
+    #[inline(always)]
+    pub fn dmadir(&self) -> DMADIR_R {
+        DMADIR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Sets the Priority of the DMA request"]
+    #[inline(always)]
+    pub fn dmapri(&self) -> DMAPRI_R {
+        DMAPRI_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used."]
+    #[inline(always)]
+    pub fn dmadynpri(&self) -> DMADYNPRI_R {
+        DMADYNPRI_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared."]
+    #[inline(always)]
+    pub fn dmahonstat(&self) -> DMAHONSTAT_R {
+        DMAHONSTAT_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory"]
+    #[inline(always)]
+    pub fn dmamsk(&self) -> DMAMSK_R {
+        DMAMSK_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Power Off the ADC System upon DMACPL."]
+    #[inline(always)]
+    pub fn dpwroff(&self) -> DPWROFF_R {
+        DPWROFF_R::new(((self.bits >> 18) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline(always)]
+    pub fn dmaen(&mut self) -> DMAEN_W<0> {
+        DMAEN_W::new(self)
+    }
+    #[doc = "Bit 2 - Direction"]
+    #[inline(always)]
+    pub fn dmadir(&mut self) -> DMADIR_W<2> {
+        DMADIR_W::new(self)
+    }
+    #[doc = "Bit 8 - Sets the Priority of the DMA request"]
+    #[inline(always)]
+    pub fn dmapri(&mut self) -> DMAPRI_W<8> {
+        DMAPRI_W::new(self)
+    }
+    #[doc = "Bit 9 - Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used."]
+    #[inline(always)]
+    pub fn dmadynpri(&mut self) -> DMADYNPRI_W<9> {
+        DMADYNPRI_W::new(self)
+    }
+    #[doc = "Bit 16 - Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared."]
+    #[inline(always)]
+    pub fn dmahonstat(&mut self) -> DMAHONSTAT_W<16> {
+        DMAHONSTAT_W::new(self)
+    }
+    #[doc = "Bit 17 - Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory"]
+    #[inline(always)]
+    pub fn dmamsk(&mut self) -> DMAMSK_W<17> {
+        DMAMSK_W::new(self)
+    }
+    #[doc = "Bit 18 - Power Off the ADC System upon DMACPL."]
+    #[inline(always)]
+    pub fn dpwroff(&mut self) -> DPWROFF_W<18> {
+        DPWROFF_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacfg](index.html) module"]
+pub struct DMACFG_SPEC;
+impl crate::RegisterSpec for DMACFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmacfg::R](R) reader structure"]
+impl crate::Readable for DMACFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmacfg::W](W) writer structure"]
+impl crate::Writable for DMACFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMACFG to value 0"]
+impl crate::Resettable for DMACFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/dmastat.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `DMASTAT` reader"]
+pub struct R(crate::R<DMASTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMASTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMASTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMASTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMASTAT` writer"]
+pub struct W(crate::W<DMASTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMASTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMASTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMASTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DMATIP` reader - DMA Transfer In Progress"]
+pub type DMATIP_R = crate::BitReader<bool>;
+#[doc = "Field `DMATIP` writer - DMA Transfer In Progress"]
+pub type DMATIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMASTAT_SPEC, bool, O>;
+#[doc = "Field `DMACPL` reader - DMA Transfer Complete"]
+pub type DMACPL_R = crate::BitReader<bool>;
+#[doc = "Field `DMACPL` writer - DMA Transfer Complete"]
+pub type DMACPL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMASTAT_SPEC, bool, O>;
+#[doc = "Field `DMAERR` reader - DMA Error"]
+pub type DMAERR_R = crate::BitReader<bool>;
+#[doc = "Field `DMAERR` writer - DMA Error"]
+pub type DMAERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMASTAT_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - DMA Transfer In Progress"]
+    #[inline(always)]
+    pub fn dmatip(&self) -> DMATIP_R {
+        DMATIP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dmacpl(&self) -> DMACPL_R {
+        DMACPL_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA Error"]
+    #[inline(always)]
+    pub fn dmaerr(&self) -> DMAERR_R {
+        DMAERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Transfer In Progress"]
+    #[inline(always)]
+    pub fn dmatip(&mut self) -> DMATIP_W<0> {
+        DMATIP_W::new(self)
+    }
+    #[doc = "Bit 1 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dmacpl(&mut self) -> DMACPL_W<1> {
+        DMACPL_W::new(self)
+    }
+    #[doc = "Bit 2 - DMA Error"]
+    #[inline(always)]
+    pub fn dmaerr(&mut self) -> DMAERR_W<2> {
+        DMAERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmastat](index.html) module"]
+pub struct DMASTAT_SPEC;
+impl crate::RegisterSpec for DMASTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmastat::R](R) reader structure"]
+impl crate::Readable for DMASTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmastat::W](W) writer structure"]
+impl crate::Writable for DMASTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMASTAT to value 0"]
+impl crate::Resettable for DMASTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/dmatargaddr.rs

@@ -0,0 +1,96 @@
+#[doc = "Register `DMATARGADDR` reader"]
+pub struct R(crate::R<DMATARGADDR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATARGADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATARGADDR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATARGADDR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATARGADDR` writer"]
+pub struct W(crate::W<DMATARGADDR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATARGADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATARGADDR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATARGADDR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LTARGADDR` reader - DMA Target Address"]
+pub type LTARGADDR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `LTARGADDR` writer - DMA Target Address"]
+pub type LTARGADDR_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DMATARGADDR_SPEC, u32, u32, 19, O>;
+#[doc = "Field `UTARGADDR` reader - SRAM Target"]
+pub type UTARGADDR_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `UTARGADDR` writer - SRAM Target"]
+pub type UTARGADDR_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DMATARGADDR_SPEC, u16, u16, 13, O>;
+impl R {
+    #[doc = "Bits 0:18 - DMA Target Address"]
+    #[inline(always)]
+    pub fn ltargaddr(&self) -> LTARGADDR_R {
+        LTARGADDR_R::new((self.bits & 0x0007_ffff) as u32)
+    }
+    #[doc = "Bits 19:31 - SRAM Target"]
+    #[inline(always)]
+    pub fn utargaddr(&self) -> UTARGADDR_R {
+        UTARGADDR_R::new(((self.bits >> 19) & 0x1fff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:18 - DMA Target Address"]
+    #[inline(always)]
+    pub fn ltargaddr(&mut self) -> LTARGADDR_W<0> {
+        LTARGADDR_W::new(self)
+    }
+    #[doc = "Bits 19:31 - SRAM Target"]
+    #[inline(always)]
+    pub fn utargaddr(&mut self) -> UTARGADDR_W<19> {
+        UTARGADDR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Target Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatargaddr](index.html) module"]
+pub struct DMATARGADDR_SPEC;
+impl crate::RegisterSpec for DMATARGADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatargaddr::R](R) reader structure"]
+impl crate::Readable for DMATARGADDR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatargaddr::W](W) writer structure"]
+impl crate::Writable for DMATARGADDR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATARGADDR to value 0x2000_0000"]
+impl crate::Resettable for DMATARGADDR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x2000_0000
+    }
+}

apollo3-pac/src/adc/dmatotcount.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `DMATOTCOUNT` reader"]
+pub struct R(crate::R<DMATOTCOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATOTCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATOTCOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATOTCOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATOTCOUNT` writer"]
+pub struct W(crate::W<DMATOTCOUNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATOTCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATOTCOUNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATOTCOUNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TOTCOUNT` reader - Total Transfer Count"]
+pub type TOTCOUNT_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `TOTCOUNT` writer - Total Transfer Count"]
+pub type TOTCOUNT_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DMATOTCOUNT_SPEC, u16, u16, 16, O>;
+impl R {
+    #[doc = "Bits 2:17 - Total Transfer Count"]
+    #[inline(always)]
+    pub fn totcount(&self) -> TOTCOUNT_R {
+        TOTCOUNT_R::new(((self.bits >> 2) & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 2:17 - Total Transfer Count"]
+    #[inline(always)]
+    pub fn totcount(&mut self) -> TOTCOUNT_W<2> {
+        TOTCOUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Total Transfer Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatotcount](index.html) module"]
+pub struct DMATOTCOUNT_SPEC;
+impl crate::RegisterSpec for DMATOTCOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatotcount::R](R) reader structure"]
+impl crate::Readable for DMATOTCOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatotcount::W](W) writer structure"]
+impl crate::Writable for DMATOTCOUNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATOTCOUNT to value 0"]
+impl crate::Resettable for DMATOTCOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/dmatrigen.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `DMATRIGEN` reader"]
+pub struct R(crate::R<DMATRIGEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATRIGEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATRIGEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATRIGEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATRIGEN` writer"]
+pub struct W(crate::W<DMATRIGEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATRIGEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATRIGEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATRIGEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DFIFO75` reader - Trigger DMA upon FIFO 75 percent Full"]
+pub type DFIFO75_R = crate::BitReader<bool>;
+#[doc = "Field `DFIFO75` writer - Trigger DMA upon FIFO 75 percent Full"]
+pub type DFIFO75_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGEN_SPEC, bool, O>;
+#[doc = "Field `DFIFOFULL` reader - Trigger DMA upon FIFO 100 percent Full"]
+pub type DFIFOFULL_R = crate::BitReader<bool>;
+#[doc = "Field `DFIFOFULL` writer - Trigger DMA upon FIFO 100 percent Full"]
+pub type DFIFOFULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGEN_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Trigger DMA upon FIFO 75 percent Full"]
+    #[inline(always)]
+    pub fn dfifo75(&self) -> DFIFO75_R {
+        DFIFO75_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Trigger DMA upon FIFO 100 percent Full"]
+    #[inline(always)]
+    pub fn dfifofull(&self) -> DFIFOFULL_R {
+        DFIFOFULL_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Trigger DMA upon FIFO 75 percent Full"]
+    #[inline(always)]
+    pub fn dfifo75(&mut self) -> DFIFO75_W<0> {
+        DFIFO75_W::new(self)
+    }
+    #[doc = "Bit 1 - Trigger DMA upon FIFO 100 percent Full"]
+    #[inline(always)]
+    pub fn dfifofull(&mut self) -> DFIFOFULL_W<1> {
+        DFIFOFULL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Trigger Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatrigen](index.html) module"]
+pub struct DMATRIGEN_SPEC;
+impl crate::RegisterSpec for DMATRIGEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatrigen::R](R) reader structure"]
+impl crate::Readable for DMATRIGEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatrigen::W](W) writer structure"]
+impl crate::Writable for DMATRIGEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATRIGEN to value 0"]
+impl crate::Resettable for DMATRIGEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/dmatrigstat.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `DMATRIGSTAT` reader"]
+pub struct R(crate::R<DMATRIGSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATRIGSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATRIGSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATRIGSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATRIGSTAT` writer"]
+pub struct W(crate::W<DMATRIGSTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATRIGSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATRIGSTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATRIGSTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `D75STAT` reader - Triggered DMA from FIFO 75 percent Full"]
+pub type D75STAT_R = crate::BitReader<bool>;
+#[doc = "Field `D75STAT` writer - Triggered DMA from FIFO 75 percent Full"]
+pub type D75STAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGSTAT_SPEC, bool, O>;
+#[doc = "Field `DFULLSTAT` reader - Triggered DMA from FIFO 100 percent Full"]
+pub type DFULLSTAT_R = crate::BitReader<bool>;
+#[doc = "Field `DFULLSTAT` writer - Triggered DMA from FIFO 100 percent Full"]
+pub type DFULLSTAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGSTAT_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Triggered DMA from FIFO 75 percent Full"]
+    #[inline(always)]
+    pub fn d75stat(&self) -> D75STAT_R {
+        D75STAT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Triggered DMA from FIFO 100 percent Full"]
+    #[inline(always)]
+    pub fn dfullstat(&self) -> DFULLSTAT_R {
+        DFULLSTAT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Triggered DMA from FIFO 75 percent Full"]
+    #[inline(always)]
+    pub fn d75stat(&mut self) -> D75STAT_W<0> {
+        D75STAT_W::new(self)
+    }
+    #[doc = "Bit 1 - Triggered DMA from FIFO 100 percent Full"]
+    #[inline(always)]
+    pub fn dfullstat(&mut self) -> DFULLSTAT_W<1> {
+        DFULLSTAT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Trigger Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatrigstat](index.html) module"]
+pub struct DMATRIGSTAT_SPEC;
+impl crate::RegisterSpec for DMATRIGSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatrigstat::R](R) reader structure"]
+impl crate::Readable for DMATRIGSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatrigstat::W](W) writer structure"]
+impl crate::Writable for DMATRIGSTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATRIGSTAT to value 0"]
+impl crate::Resettable for DMATRIGSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/fifo.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `FIFO` reader"]
+pub struct R(crate::R<FIFO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFO` writer"]
+pub struct W(crate::W<FIFO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DATA` reader - Oldest data in the FIFO."]
+pub type DATA_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DATA` writer - Oldest data in the FIFO."]
+pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 20, O>;
+#[doc = "Field `COUNT` reader - Number of valid entries in the ADC FIFO."]
+pub type COUNT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `COUNT` writer - Number of valid entries in the ADC FIFO."]
+pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 8, O>;
+#[doc = "Field `SLOTNUM` reader - Slot number associated with this FIFO data."]
+pub type SLOTNUM_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `SLOTNUM` writer - Slot number associated with this FIFO data."]
+pub type SLOTNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 3, O>;
+#[doc = "Field `RSVD` reader - RESERVED."]
+pub type RSVD_R = crate::BitReader<bool>;
+#[doc = "Field `RSVD` writer - RESERVED."]
+pub type RSVD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFO_SPEC, bool, O>;
+impl R {
+    #[doc = "Bits 0:19 - Oldest data in the FIFO."]
+    #[inline(always)]
+    pub fn data(&self) -> DATA_R {
+        DATA_R::new((self.bits & 0x000f_ffff) as u32)
+    }
+    #[doc = "Bits 20:27 - Number of valid entries in the ADC FIFO."]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new(((self.bits >> 20) & 0xff) as u8)
+    }
+    #[doc = "Bits 28:30 - Slot number associated with this FIFO data."]
+    #[inline(always)]
+    pub fn slotnum(&self) -> SLOTNUM_R {
+        SLOTNUM_R::new(((self.bits >> 28) & 7) as u8)
+    }
+    #[doc = "Bit 31 - RESERVED."]
+    #[inline(always)]
+    pub fn rsvd(&self) -> RSVD_R {
+        RSVD_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - Oldest data in the FIFO."]
+    #[inline(always)]
+    pub fn data(&mut self) -> DATA_W<0> {
+        DATA_W::new(self)
+    }
+    #[doc = "Bits 20:27 - Number of valid entries in the ADC FIFO."]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W<20> {
+        COUNT_W::new(self)
+    }
+    #[doc = "Bits 28:30 - Slot number associated with this FIFO data."]
+    #[inline(always)]
+    pub fn slotnum(&mut self) -> SLOTNUM_W<28> {
+        SLOTNUM_W::new(self)
+    }
+    #[doc = "Bit 31 - RESERVED."]
+    #[inline(always)]
+    pub fn rsvd(&mut self) -> RSVD_W<31> {
+        RSVD_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO Data and Valid Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"]
+pub struct FIFO_SPEC;
+impl crate::RegisterSpec for FIFO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifo::R](R) reader structure"]
+impl crate::Readable for FIFO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"]
+impl crate::Writable for FIFO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFO to value 0"]
+impl crate::Resettable for FIFO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/fifopr.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `FIFOPR` reader"]
+pub struct R(crate::R<FIFOPR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFOPR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFOPR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFOPR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFOPR` writer"]
+pub struct W(crate::W<FIFOPR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFOPR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFOPR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFOPR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DATA` reader - Oldest data in the FIFO."]
+pub type DATA_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DATA` writer - Oldest data in the FIFO."]
+pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPR_SPEC, u32, u32, 20, O>;
+#[doc = "Field `COUNT` reader - Number of valid entries in the ADC FIFO."]
+pub type COUNT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `COUNT` writer - Number of valid entries in the ADC FIFO."]
+pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `SLOTNUMPR` reader - Slot number associated with this FIFO data."]
+pub type SLOTNUMPR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `SLOTNUMPR` writer - Slot number associated with this FIFO data."]
+pub type SLOTNUMPR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPR_SPEC, u8, u8, 3, O>;
+#[doc = "Field `RSVDPR` reader - RESERVED."]
+pub type RSVDPR_R = crate::BitReader<bool>;
+#[doc = "Field `RSVDPR` writer - RESERVED."]
+pub type RSVDPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOPR_SPEC, bool, O>;
+impl R {
+    #[doc = "Bits 0:19 - Oldest data in the FIFO."]
+    #[inline(always)]
+    pub fn data(&self) -> DATA_R {
+        DATA_R::new((self.bits & 0x000f_ffff) as u32)
+    }
+    #[doc = "Bits 20:27 - Number of valid entries in the ADC FIFO."]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new(((self.bits >> 20) & 0xff) as u8)
+    }
+    #[doc = "Bits 28:30 - Slot number associated with this FIFO data."]
+    #[inline(always)]
+    pub fn slotnumpr(&self) -> SLOTNUMPR_R {
+        SLOTNUMPR_R::new(((self.bits >> 28) & 7) as u8)
+    }
+    #[doc = "Bit 31 - RESERVED."]
+    #[inline(always)]
+    pub fn rsvdpr(&self) -> RSVDPR_R {
+        RSVDPR_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - Oldest data in the FIFO."]
+    #[inline(always)]
+    pub fn data(&mut self) -> DATA_W<0> {
+        DATA_W::new(self)
+    }
+    #[doc = "Bits 20:27 - Number of valid entries in the ADC FIFO."]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W<20> {
+        COUNT_W::new(self)
+    }
+    #[doc = "Bits 28:30 - Slot number associated with this FIFO data."]
+    #[inline(always)]
+    pub fn slotnumpr(&mut self) -> SLOTNUMPR_W<28> {
+        SLOTNUMPR_W::new(self)
+    }
+    #[doc = "Bit 31 - RESERVED."]
+    #[inline(always)]
+    pub fn rsvdpr(&mut self) -> RSVDPR_W<31> {
+        RSVDPR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO Data and Valid Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifopr](index.html) module"]
+pub struct FIFOPR_SPEC;
+impl crate::RegisterSpec for FIFOPR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifopr::R](R) reader structure"]
+impl crate::Readable for FIFOPR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifopr::W](W) writer structure"]
+impl crate::Writable for FIFOPR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFOPR to value 0"]
+impl crate::Resettable for FIFOPR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/intclr.rs

@@ -0,0 +1,450 @@
+#[doc = "Register `INTCLR` reader"]
+pub struct R(crate::R<INTCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTCLR` writer"]
+pub struct W(crate::W<INTCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CNVCMP` reader - ADC conversion complete interrupt."]
+pub type CNVCMP_R = crate::BitReader<CNVCMP_A>;
+#[doc = "ADC conversion complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CNVCMP_A {
+    #[doc = "1: ADC conversion complete interrupt. value."]
+    CNVCMPINT = 1,
+}
+impl From<CNVCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: CNVCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CNVCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CNVCMP_A> {
+        match self.bits {
+            true => Some(CNVCMP_A::CNVCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CNVCMPINT`"]
+    #[inline(always)]
+    pub fn is_cnvcmpint(&self) -> bool {
+        *self == CNVCMP_A::CNVCMPINT
+    }
+}
+#[doc = "Field `CNVCMP` writer - ADC conversion complete interrupt."]
+pub type CNVCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, CNVCMP_A, O>;
+impl<'a, const O: u8> CNVCMP_W<'a, O> {
+    #[doc = "ADC conversion complete interrupt. value."]
+    #[inline(always)]
+    pub fn cnvcmpint(self) -> &'a mut W {
+        self.variant(CNVCMP_A::CNVCMPINT)
+    }
+}
+#[doc = "Field `SCNCMP` reader - ADC scan complete interrupt."]
+pub type SCNCMP_R = crate::BitReader<SCNCMP_A>;
+#[doc = "ADC scan complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCNCMP_A {
+    #[doc = "1: ADC scan complete interrupt. value."]
+    SCNCMPINT = 1,
+}
+impl From<SCNCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: SCNCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SCNCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SCNCMP_A> {
+        match self.bits {
+            true => Some(SCNCMP_A::SCNCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCNCMPINT`"]
+    #[inline(always)]
+    pub fn is_scncmpint(&self) -> bool {
+        *self == SCNCMP_A::SCNCMPINT
+    }
+}
+#[doc = "Field `SCNCMP` writer - ADC scan complete interrupt."]
+pub type SCNCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, SCNCMP_A, O>;
+impl<'a, const O: u8> SCNCMP_W<'a, O> {
+    #[doc = "ADC scan complete interrupt. value."]
+    #[inline(always)]
+    pub fn scncmpint(self) -> &'a mut W {
+        self.variant(SCNCMP_A::SCNCMPINT)
+    }
+}
+#[doc = "Field `FIFOOVR1` reader - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_R = crate::BitReader<FIFOOVR1_A>;
+#[doc = "FIFO 75 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR1_A {
+    #[doc = "1: FIFO 75 percent full interrupt. value."]
+    FIFO75INT = 1,
+}
+impl From<FIFOOVR1_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR1_A> {
+        match self.bits {
+            true => Some(FIFOOVR1_A::FIFO75INT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFO75INT`"]
+    #[inline(always)]
+    pub fn is_fifo75int(&self) -> bool {
+        *self == FIFOOVR1_A::FIFO75INT
+    }
+}
+#[doc = "Field `FIFOOVR1` writer - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, FIFOOVR1_A, O>;
+impl<'a, const O: u8> FIFOOVR1_W<'a, O> {
+    #[doc = "FIFO 75 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifo75int(self) -> &'a mut W {
+        self.variant(FIFOOVR1_A::FIFO75INT)
+    }
+}
+#[doc = "Field `FIFOOVR2` reader - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_R = crate::BitReader<FIFOOVR2_A>;
+#[doc = "FIFO 100 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR2_A {
+    #[doc = "1: FIFO 100 percent full interrupt. value."]
+    FIFOFULLINT = 1,
+}
+impl From<FIFOOVR2_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR2_A> {
+        match self.bits {
+            true => Some(FIFOOVR2_A::FIFOFULLINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFOFULLINT`"]
+    #[inline(always)]
+    pub fn is_fifofullint(&self) -> bool {
+        *self == FIFOOVR2_A::FIFOFULLINT
+    }
+}
+#[doc = "Field `FIFOOVR2` writer - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, FIFOOVR2_A, O>;
+impl<'a, const O: u8> FIFOOVR2_W<'a, O> {
+    #[doc = "FIFO 100 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifofullint(self) -> &'a mut W {
+        self.variant(FIFOOVR2_A::FIFOFULLINT)
+    }
+}
+#[doc = "Field `WCEXC` reader - Window comparator voltage excursion interrupt."]
+pub type WCEXC_R = crate::BitReader<WCEXC_A>;
+#[doc = "Window comparator voltage excursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEXC_A {
+    #[doc = "1: Window comparitor voltage excursion interrupt. value."]
+    WCEXCINT = 1,
+}
+impl From<WCEXC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEXC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEXC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEXC_A> {
+        match self.bits {
+            true => Some(WCEXC_A::WCEXCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEXCINT`"]
+    #[inline(always)]
+    pub fn is_wcexcint(&self) -> bool {
+        *self == WCEXC_A::WCEXCINT
+    }
+}
+#[doc = "Field `WCEXC` writer - Window comparator voltage excursion interrupt."]
+pub type WCEXC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, WCEXC_A, O>;
+impl<'a, const O: u8> WCEXC_W<'a, O> {
+    #[doc = "Window comparitor voltage excursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcexcint(self) -> &'a mut W {
+        self.variant(WCEXC_A::WCEXCINT)
+    }
+}
+#[doc = "Field `WCINC` reader - Window comparator voltage incursion interrupt."]
+pub type WCINC_R = crate::BitReader<WCINC_A>;
+#[doc = "Window comparator voltage incursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCINC_A {
+    #[doc = "1: Window comparitor voltage incursion interrupt. value."]
+    WCINCINT = 1,
+}
+impl From<WCINC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCINC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCINC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCINC_A> {
+        match self.bits {
+            true => Some(WCINC_A::WCINCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCINCINT`"]
+    #[inline(always)]
+    pub fn is_wcincint(&self) -> bool {
+        *self == WCINC_A::WCINCINT
+    }
+}
+#[doc = "Field `WCINC` writer - Window comparator voltage incursion interrupt."]
+pub type WCINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, WCINC_A, O>;
+impl<'a, const O: u8> WCINC_W<'a, O> {
+    #[doc = "Window comparitor voltage incursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcincint(self) -> &'a mut W {
+        self.variant(WCINC_A::WCINCINT)
+    }
+}
+#[doc = "Field `DCMP` reader - DMA Transfer Complete"]
+pub type DCMP_R = crate::BitReader<DCMP_A>;
+#[doc = "DMA Transfer Complete\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCMP_A {
+    #[doc = "1: DMA Completed a transfer value."]
+    DMACOMPLETE = 1,
+}
+impl From<DCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: DCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DCMP_A> {
+        match self.bits {
+            true => Some(DCMP_A::DMACOMPLETE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMACOMPLETE`"]
+    #[inline(always)]
+    pub fn is_dmacomplete(&self) -> bool {
+        *self == DCMP_A::DMACOMPLETE
+    }
+}
+#[doc = "Field `DCMP` writer - DMA Transfer Complete"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, DCMP_A, O>;
+impl<'a, const O: u8> DCMP_W<'a, O> {
+    #[doc = "DMA Completed a transfer value."]
+    #[inline(always)]
+    pub fn dmacomplete(self) -> &'a mut W {
+        self.variant(DCMP_A::DMACOMPLETE)
+    }
+}
+#[doc = "Field `DERR` reader - DMA Error Condition"]
+pub type DERR_R = crate::BitReader<DERR_A>;
+#[doc = "DMA Error Condition\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DERR_A {
+    #[doc = "1: DMA Error Condition Occurred value."]
+    DMAERROR = 1,
+}
+impl From<DERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: DERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DERR_A> {
+        match self.bits {
+            true => Some(DERR_A::DMAERROR),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMAERROR`"]
+    #[inline(always)]
+    pub fn is_dmaerror(&self) -> bool {
+        *self == DERR_A::DMAERROR
+    }
+}
+#[doc = "Field `DERR` writer - DMA Error Condition"]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, DERR_A, O>;
+impl<'a, const O: u8> DERR_W<'a, O> {
+    #[doc = "DMA Error Condition Occurred value."]
+    #[inline(always)]
+    pub fn dmaerror(self) -> &'a mut W {
+        self.variant(DERR_A::DMAERROR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&self) -> CNVCMP_R {
+        CNVCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&self) -> SCNCMP_R {
+        SCNCMP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&self) -> FIFOOVR1_R {
+        FIFOOVR1_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&self) -> FIFOOVR2_R {
+        FIFOOVR2_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&self) -> WCEXC_R {
+        WCEXC_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&self) -> WCINC_R {
+        WCINC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&mut self) -> CNVCMP_W<0> {
+        CNVCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&mut self) -> SCNCMP_W<1> {
+        SCNCMP_W::new(self)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&mut self) -> FIFOOVR1_W<2> {
+        FIFOOVR1_W::new(self)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&mut self) -> FIFOOVR2_W<3> {
+        FIFOOVR2_W::new(self)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&mut self) -> WCEXC_W<4> {
+        WCEXC_W::new(self)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&mut self) -> WCINC_W<5> {
+        WCINC_W::new(self)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<6> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<7> {
+        DERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC Interrupt registers: Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intclr](index.html) module"]
+pub struct INTCLR_SPEC;
+impl crate::RegisterSpec for INTCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intclr::R](R) reader structure"]
+impl crate::Readable for INTCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intclr::W](W) writer structure"]
+impl crate::Writable for INTCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTCLR to value 0"]
+impl crate::Resettable for INTCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/inten.rs

@@ -0,0 +1,450 @@
+#[doc = "Register `INTEN` reader"]
+pub struct R(crate::R<INTEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTEN` writer"]
+pub struct W(crate::W<INTEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CNVCMP` reader - ADC conversion complete interrupt."]
+pub type CNVCMP_R = crate::BitReader<CNVCMP_A>;
+#[doc = "ADC conversion complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CNVCMP_A {
+    #[doc = "1: ADC conversion complete interrupt. value."]
+    CNVCMPINT = 1,
+}
+impl From<CNVCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: CNVCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CNVCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CNVCMP_A> {
+        match self.bits {
+            true => Some(CNVCMP_A::CNVCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CNVCMPINT`"]
+    #[inline(always)]
+    pub fn is_cnvcmpint(&self) -> bool {
+        *self == CNVCMP_A::CNVCMPINT
+    }
+}
+#[doc = "Field `CNVCMP` writer - ADC conversion complete interrupt."]
+pub type CNVCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CNVCMP_A, O>;
+impl<'a, const O: u8> CNVCMP_W<'a, O> {
+    #[doc = "ADC conversion complete interrupt. value."]
+    #[inline(always)]
+    pub fn cnvcmpint(self) -> &'a mut W {
+        self.variant(CNVCMP_A::CNVCMPINT)
+    }
+}
+#[doc = "Field `SCNCMP` reader - ADC scan complete interrupt."]
+pub type SCNCMP_R = crate::BitReader<SCNCMP_A>;
+#[doc = "ADC scan complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCNCMP_A {
+    #[doc = "1: ADC scan complete interrupt. value."]
+    SCNCMPINT = 1,
+}
+impl From<SCNCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: SCNCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SCNCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SCNCMP_A> {
+        match self.bits {
+            true => Some(SCNCMP_A::SCNCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCNCMPINT`"]
+    #[inline(always)]
+    pub fn is_scncmpint(&self) -> bool {
+        *self == SCNCMP_A::SCNCMPINT
+    }
+}
+#[doc = "Field `SCNCMP` writer - ADC scan complete interrupt."]
+pub type SCNCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SCNCMP_A, O>;
+impl<'a, const O: u8> SCNCMP_W<'a, O> {
+    #[doc = "ADC scan complete interrupt. value."]
+    #[inline(always)]
+    pub fn scncmpint(self) -> &'a mut W {
+        self.variant(SCNCMP_A::SCNCMPINT)
+    }
+}
+#[doc = "Field `FIFOOVR1` reader - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_R = crate::BitReader<FIFOOVR1_A>;
+#[doc = "FIFO 75 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR1_A {
+    #[doc = "1: FIFO 75 percent full interrupt. value."]
+    FIFO75INT = 1,
+}
+impl From<FIFOOVR1_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR1_A> {
+        match self.bits {
+            true => Some(FIFOOVR1_A::FIFO75INT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFO75INT`"]
+    #[inline(always)]
+    pub fn is_fifo75int(&self) -> bool {
+        *self == FIFOOVR1_A::FIFO75INT
+    }
+}
+#[doc = "Field `FIFOOVR1` writer - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, FIFOOVR1_A, O>;
+impl<'a, const O: u8> FIFOOVR1_W<'a, O> {
+    #[doc = "FIFO 75 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifo75int(self) -> &'a mut W {
+        self.variant(FIFOOVR1_A::FIFO75INT)
+    }
+}
+#[doc = "Field `FIFOOVR2` reader - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_R = crate::BitReader<FIFOOVR2_A>;
+#[doc = "FIFO 100 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR2_A {
+    #[doc = "1: FIFO 100 percent full interrupt. value."]
+    FIFOFULLINT = 1,
+}
+impl From<FIFOOVR2_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR2_A> {
+        match self.bits {
+            true => Some(FIFOOVR2_A::FIFOFULLINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFOFULLINT`"]
+    #[inline(always)]
+    pub fn is_fifofullint(&self) -> bool {
+        *self == FIFOOVR2_A::FIFOFULLINT
+    }
+}
+#[doc = "Field `FIFOOVR2` writer - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, FIFOOVR2_A, O>;
+impl<'a, const O: u8> FIFOOVR2_W<'a, O> {
+    #[doc = "FIFO 100 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifofullint(self) -> &'a mut W {
+        self.variant(FIFOOVR2_A::FIFOFULLINT)
+    }
+}
+#[doc = "Field `WCEXC` reader - Window comparator voltage excursion interrupt."]
+pub type WCEXC_R = crate::BitReader<WCEXC_A>;
+#[doc = "Window comparator voltage excursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEXC_A {
+    #[doc = "1: Window comparitor voltage excursion interrupt. value."]
+    WCEXCINT = 1,
+}
+impl From<WCEXC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEXC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEXC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEXC_A> {
+        match self.bits {
+            true => Some(WCEXC_A::WCEXCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEXCINT`"]
+    #[inline(always)]
+    pub fn is_wcexcint(&self) -> bool {
+        *self == WCEXC_A::WCEXCINT
+    }
+}
+#[doc = "Field `WCEXC` writer - Window comparator voltage excursion interrupt."]
+pub type WCEXC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, WCEXC_A, O>;
+impl<'a, const O: u8> WCEXC_W<'a, O> {
+    #[doc = "Window comparitor voltage excursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcexcint(self) -> &'a mut W {
+        self.variant(WCEXC_A::WCEXCINT)
+    }
+}
+#[doc = "Field `WCINC` reader - Window comparator voltage incursion interrupt."]
+pub type WCINC_R = crate::BitReader<WCINC_A>;
+#[doc = "Window comparator voltage incursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCINC_A {
+    #[doc = "1: Window comparitor voltage incursion interrupt. value."]
+    WCINCINT = 1,
+}
+impl From<WCINC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCINC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCINC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCINC_A> {
+        match self.bits {
+            true => Some(WCINC_A::WCINCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCINCINT`"]
+    #[inline(always)]
+    pub fn is_wcincint(&self) -> bool {
+        *self == WCINC_A::WCINCINT
+    }
+}
+#[doc = "Field `WCINC` writer - Window comparator voltage incursion interrupt."]
+pub type WCINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, WCINC_A, O>;
+impl<'a, const O: u8> WCINC_W<'a, O> {
+    #[doc = "Window comparitor voltage incursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcincint(self) -> &'a mut W {
+        self.variant(WCINC_A::WCINCINT)
+    }
+}
+#[doc = "Field `DCMP` reader - DMA Transfer Complete"]
+pub type DCMP_R = crate::BitReader<DCMP_A>;
+#[doc = "DMA Transfer Complete\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCMP_A {
+    #[doc = "1: DMA Completed a transfer value."]
+    DMACOMPLETE = 1,
+}
+impl From<DCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: DCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DCMP_A> {
+        match self.bits {
+            true => Some(DCMP_A::DMACOMPLETE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMACOMPLETE`"]
+    #[inline(always)]
+    pub fn is_dmacomplete(&self) -> bool {
+        *self == DCMP_A::DMACOMPLETE
+    }
+}
+#[doc = "Field `DCMP` writer - DMA Transfer Complete"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, DCMP_A, O>;
+impl<'a, const O: u8> DCMP_W<'a, O> {
+    #[doc = "DMA Completed a transfer value."]
+    #[inline(always)]
+    pub fn dmacomplete(self) -> &'a mut W {
+        self.variant(DCMP_A::DMACOMPLETE)
+    }
+}
+#[doc = "Field `DERR` reader - DMA Error Condition"]
+pub type DERR_R = crate::BitReader<DERR_A>;
+#[doc = "DMA Error Condition\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DERR_A {
+    #[doc = "1: DMA Error Condition Occurred value."]
+    DMAERROR = 1,
+}
+impl From<DERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: DERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DERR_A> {
+        match self.bits {
+            true => Some(DERR_A::DMAERROR),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMAERROR`"]
+    #[inline(always)]
+    pub fn is_dmaerror(&self) -> bool {
+        *self == DERR_A::DMAERROR
+    }
+}
+#[doc = "Field `DERR` writer - DMA Error Condition"]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, DERR_A, O>;
+impl<'a, const O: u8> DERR_W<'a, O> {
+    #[doc = "DMA Error Condition Occurred value."]
+    #[inline(always)]
+    pub fn dmaerror(self) -> &'a mut W {
+        self.variant(DERR_A::DMAERROR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&self) -> CNVCMP_R {
+        CNVCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&self) -> SCNCMP_R {
+        SCNCMP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&self) -> FIFOOVR1_R {
+        FIFOOVR1_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&self) -> FIFOOVR2_R {
+        FIFOOVR2_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&self) -> WCEXC_R {
+        WCEXC_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&self) -> WCINC_R {
+        WCINC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&mut self) -> CNVCMP_W<0> {
+        CNVCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&mut self) -> SCNCMP_W<1> {
+        SCNCMP_W::new(self)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&mut self) -> FIFOOVR1_W<2> {
+        FIFOOVR1_W::new(self)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&mut self) -> FIFOOVR2_W<3> {
+        FIFOOVR2_W::new(self)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&mut self) -> WCEXC_W<4> {
+        WCEXC_W::new(self)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&mut self) -> WCINC_W<5> {
+        WCINC_W::new(self)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<6> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<7> {
+        DERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC Interrupt registers: Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
+pub struct INTEN_SPEC;
+impl crate::RegisterSpec for INTEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [inten::R](R) reader structure"]
+impl crate::Readable for INTEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
+impl crate::Writable for INTEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTEN to value 0"]
+impl crate::Resettable for INTEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/intset.rs

@@ -0,0 +1,450 @@
+#[doc = "Register `INTSET` reader"]
+pub struct R(crate::R<INTSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTSET` writer"]
+pub struct W(crate::W<INTSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CNVCMP` reader - ADC conversion complete interrupt."]
+pub type CNVCMP_R = crate::BitReader<CNVCMP_A>;
+#[doc = "ADC conversion complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CNVCMP_A {
+    #[doc = "1: ADC conversion complete interrupt. value."]
+    CNVCMPINT = 1,
+}
+impl From<CNVCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: CNVCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CNVCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CNVCMP_A> {
+        match self.bits {
+            true => Some(CNVCMP_A::CNVCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CNVCMPINT`"]
+    #[inline(always)]
+    pub fn is_cnvcmpint(&self) -> bool {
+        *self == CNVCMP_A::CNVCMPINT
+    }
+}
+#[doc = "Field `CNVCMP` writer - ADC conversion complete interrupt."]
+pub type CNVCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, CNVCMP_A, O>;
+impl<'a, const O: u8> CNVCMP_W<'a, O> {
+    #[doc = "ADC conversion complete interrupt. value."]
+    #[inline(always)]
+    pub fn cnvcmpint(self) -> &'a mut W {
+        self.variant(CNVCMP_A::CNVCMPINT)
+    }
+}
+#[doc = "Field `SCNCMP` reader - ADC scan complete interrupt."]
+pub type SCNCMP_R = crate::BitReader<SCNCMP_A>;
+#[doc = "ADC scan complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCNCMP_A {
+    #[doc = "1: ADC scan complete interrupt. value."]
+    SCNCMPINT = 1,
+}
+impl From<SCNCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: SCNCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SCNCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SCNCMP_A> {
+        match self.bits {
+            true => Some(SCNCMP_A::SCNCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCNCMPINT`"]
+    #[inline(always)]
+    pub fn is_scncmpint(&self) -> bool {
+        *self == SCNCMP_A::SCNCMPINT
+    }
+}
+#[doc = "Field `SCNCMP` writer - ADC scan complete interrupt."]
+pub type SCNCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, SCNCMP_A, O>;
+impl<'a, const O: u8> SCNCMP_W<'a, O> {
+    #[doc = "ADC scan complete interrupt. value."]
+    #[inline(always)]
+    pub fn scncmpint(self) -> &'a mut W {
+        self.variant(SCNCMP_A::SCNCMPINT)
+    }
+}
+#[doc = "Field `FIFOOVR1` reader - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_R = crate::BitReader<FIFOOVR1_A>;
+#[doc = "FIFO 75 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR1_A {
+    #[doc = "1: FIFO 75 percent full interrupt. value."]
+    FIFO75INT = 1,
+}
+impl From<FIFOOVR1_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR1_A> {
+        match self.bits {
+            true => Some(FIFOOVR1_A::FIFO75INT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFO75INT`"]
+    #[inline(always)]
+    pub fn is_fifo75int(&self) -> bool {
+        *self == FIFOOVR1_A::FIFO75INT
+    }
+}
+#[doc = "Field `FIFOOVR1` writer - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, FIFOOVR1_A, O>;
+impl<'a, const O: u8> FIFOOVR1_W<'a, O> {
+    #[doc = "FIFO 75 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifo75int(self) -> &'a mut W {
+        self.variant(FIFOOVR1_A::FIFO75INT)
+    }
+}
+#[doc = "Field `FIFOOVR2` reader - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_R = crate::BitReader<FIFOOVR2_A>;
+#[doc = "FIFO 100 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR2_A {
+    #[doc = "1: FIFO 100 percent full interrupt. value."]
+    FIFOFULLINT = 1,
+}
+impl From<FIFOOVR2_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR2_A> {
+        match self.bits {
+            true => Some(FIFOOVR2_A::FIFOFULLINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFOFULLINT`"]
+    #[inline(always)]
+    pub fn is_fifofullint(&self) -> bool {
+        *self == FIFOOVR2_A::FIFOFULLINT
+    }
+}
+#[doc = "Field `FIFOOVR2` writer - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, FIFOOVR2_A, O>;
+impl<'a, const O: u8> FIFOOVR2_W<'a, O> {
+    #[doc = "FIFO 100 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifofullint(self) -> &'a mut W {
+        self.variant(FIFOOVR2_A::FIFOFULLINT)
+    }
+}
+#[doc = "Field `WCEXC` reader - Window comparator voltage excursion interrupt."]
+pub type WCEXC_R = crate::BitReader<WCEXC_A>;
+#[doc = "Window comparator voltage excursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEXC_A {
+    #[doc = "1: Window comparitor voltage excursion interrupt. value."]
+    WCEXCINT = 1,
+}
+impl From<WCEXC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEXC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEXC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEXC_A> {
+        match self.bits {
+            true => Some(WCEXC_A::WCEXCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEXCINT`"]
+    #[inline(always)]
+    pub fn is_wcexcint(&self) -> bool {
+        *self == WCEXC_A::WCEXCINT
+    }
+}
+#[doc = "Field `WCEXC` writer - Window comparator voltage excursion interrupt."]
+pub type WCEXC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, WCEXC_A, O>;
+impl<'a, const O: u8> WCEXC_W<'a, O> {
+    #[doc = "Window comparitor voltage excursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcexcint(self) -> &'a mut W {
+        self.variant(WCEXC_A::WCEXCINT)
+    }
+}
+#[doc = "Field `WCINC` reader - Window comparator voltage incursion interrupt."]
+pub type WCINC_R = crate::BitReader<WCINC_A>;
+#[doc = "Window comparator voltage incursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCINC_A {
+    #[doc = "1: Window comparitor voltage incursion interrupt. value."]
+    WCINCINT = 1,
+}
+impl From<WCINC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCINC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCINC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCINC_A> {
+        match self.bits {
+            true => Some(WCINC_A::WCINCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCINCINT`"]
+    #[inline(always)]
+    pub fn is_wcincint(&self) -> bool {
+        *self == WCINC_A::WCINCINT
+    }
+}
+#[doc = "Field `WCINC` writer - Window comparator voltage incursion interrupt."]
+pub type WCINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, WCINC_A, O>;
+impl<'a, const O: u8> WCINC_W<'a, O> {
+    #[doc = "Window comparitor voltage incursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcincint(self) -> &'a mut W {
+        self.variant(WCINC_A::WCINCINT)
+    }
+}
+#[doc = "Field `DCMP` reader - DMA Transfer Complete"]
+pub type DCMP_R = crate::BitReader<DCMP_A>;
+#[doc = "DMA Transfer Complete\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCMP_A {
+    #[doc = "1: DMA Completed a transfer value."]
+    DMACOMPLETE = 1,
+}
+impl From<DCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: DCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DCMP_A> {
+        match self.bits {
+            true => Some(DCMP_A::DMACOMPLETE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMACOMPLETE`"]
+    #[inline(always)]
+    pub fn is_dmacomplete(&self) -> bool {
+        *self == DCMP_A::DMACOMPLETE
+    }
+}
+#[doc = "Field `DCMP` writer - DMA Transfer Complete"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, DCMP_A, O>;
+impl<'a, const O: u8> DCMP_W<'a, O> {
+    #[doc = "DMA Completed a transfer value."]
+    #[inline(always)]
+    pub fn dmacomplete(self) -> &'a mut W {
+        self.variant(DCMP_A::DMACOMPLETE)
+    }
+}
+#[doc = "Field `DERR` reader - DMA Error Condition"]
+pub type DERR_R = crate::BitReader<DERR_A>;
+#[doc = "DMA Error Condition\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DERR_A {
+    #[doc = "1: DMA Error Condition Occurred value."]
+    DMAERROR = 1,
+}
+impl From<DERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: DERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DERR_A> {
+        match self.bits {
+            true => Some(DERR_A::DMAERROR),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMAERROR`"]
+    #[inline(always)]
+    pub fn is_dmaerror(&self) -> bool {
+        *self == DERR_A::DMAERROR
+    }
+}
+#[doc = "Field `DERR` writer - DMA Error Condition"]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, DERR_A, O>;
+impl<'a, const O: u8> DERR_W<'a, O> {
+    #[doc = "DMA Error Condition Occurred value."]
+    #[inline(always)]
+    pub fn dmaerror(self) -> &'a mut W {
+        self.variant(DERR_A::DMAERROR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&self) -> CNVCMP_R {
+        CNVCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&self) -> SCNCMP_R {
+        SCNCMP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&self) -> FIFOOVR1_R {
+        FIFOOVR1_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&self) -> FIFOOVR2_R {
+        FIFOOVR2_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&self) -> WCEXC_R {
+        WCEXC_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&self) -> WCINC_R {
+        WCINC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&mut self) -> CNVCMP_W<0> {
+        CNVCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&mut self) -> SCNCMP_W<1> {
+        SCNCMP_W::new(self)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&mut self) -> FIFOOVR1_W<2> {
+        FIFOOVR1_W::new(self)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&mut self) -> FIFOOVR2_W<3> {
+        FIFOOVR2_W::new(self)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&mut self) -> WCEXC_W<4> {
+        WCEXC_W::new(self)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&mut self) -> WCINC_W<5> {
+        WCINC_W::new(self)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<6> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<7> {
+        DERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC Interrupt registers: Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intset](index.html) module"]
+pub struct INTSET_SPEC;
+impl crate::RegisterSpec for INTSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intset::R](R) reader structure"]
+impl crate::Readable for INTSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intset::W](W) writer structure"]
+impl crate::Writable for INTSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTSET to value 0"]
+impl crate::Resettable for INTSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/intstat.rs

@@ -0,0 +1,450 @@
+#[doc = "Register `INTSTAT` reader"]
+pub struct R(crate::R<INTSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTSTAT` writer"]
+pub struct W(crate::W<INTSTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTSTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTSTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CNVCMP` reader - ADC conversion complete interrupt."]
+pub type CNVCMP_R = crate::BitReader<CNVCMP_A>;
+#[doc = "ADC conversion complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CNVCMP_A {
+    #[doc = "1: ADC conversion complete interrupt. value."]
+    CNVCMPINT = 1,
+}
+impl From<CNVCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: CNVCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CNVCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CNVCMP_A> {
+        match self.bits {
+            true => Some(CNVCMP_A::CNVCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CNVCMPINT`"]
+    #[inline(always)]
+    pub fn is_cnvcmpint(&self) -> bool {
+        *self == CNVCMP_A::CNVCMPINT
+    }
+}
+#[doc = "Field `CNVCMP` writer - ADC conversion complete interrupt."]
+pub type CNVCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, CNVCMP_A, O>;
+impl<'a, const O: u8> CNVCMP_W<'a, O> {
+    #[doc = "ADC conversion complete interrupt. value."]
+    #[inline(always)]
+    pub fn cnvcmpint(self) -> &'a mut W {
+        self.variant(CNVCMP_A::CNVCMPINT)
+    }
+}
+#[doc = "Field `SCNCMP` reader - ADC scan complete interrupt."]
+pub type SCNCMP_R = crate::BitReader<SCNCMP_A>;
+#[doc = "ADC scan complete interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SCNCMP_A {
+    #[doc = "1: ADC scan complete interrupt. value."]
+    SCNCMPINT = 1,
+}
+impl From<SCNCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: SCNCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SCNCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SCNCMP_A> {
+        match self.bits {
+            true => Some(SCNCMP_A::SCNCMPINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SCNCMPINT`"]
+    #[inline(always)]
+    pub fn is_scncmpint(&self) -> bool {
+        *self == SCNCMP_A::SCNCMPINT
+    }
+}
+#[doc = "Field `SCNCMP` writer - ADC scan complete interrupt."]
+pub type SCNCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, SCNCMP_A, O>;
+impl<'a, const O: u8> SCNCMP_W<'a, O> {
+    #[doc = "ADC scan complete interrupt. value."]
+    #[inline(always)]
+    pub fn scncmpint(self) -> &'a mut W {
+        self.variant(SCNCMP_A::SCNCMPINT)
+    }
+}
+#[doc = "Field `FIFOOVR1` reader - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_R = crate::BitReader<FIFOOVR1_A>;
+#[doc = "FIFO 75 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR1_A {
+    #[doc = "1: FIFO 75 percent full interrupt. value."]
+    FIFO75INT = 1,
+}
+impl From<FIFOOVR1_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR1_A> {
+        match self.bits {
+            true => Some(FIFOOVR1_A::FIFO75INT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFO75INT`"]
+    #[inline(always)]
+    pub fn is_fifo75int(&self) -> bool {
+        *self == FIFOOVR1_A::FIFO75INT
+    }
+}
+#[doc = "Field `FIFOOVR1` writer - FIFO 75 percent full interrupt."]
+pub type FIFOOVR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, FIFOOVR1_A, O>;
+impl<'a, const O: u8> FIFOOVR1_W<'a, O> {
+    #[doc = "FIFO 75 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifo75int(self) -> &'a mut W {
+        self.variant(FIFOOVR1_A::FIFO75INT)
+    }
+}
+#[doc = "Field `FIFOOVR2` reader - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_R = crate::BitReader<FIFOOVR2_A>;
+#[doc = "FIFO 100 percent full interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FIFOOVR2_A {
+    #[doc = "1: FIFO 100 percent full interrupt. value."]
+    FIFOFULLINT = 1,
+}
+impl From<FIFOOVR2_A> for bool {
+    #[inline(always)]
+    fn from(variant: FIFOOVR2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FIFOOVR2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FIFOOVR2_A> {
+        match self.bits {
+            true => Some(FIFOOVR2_A::FIFOFULLINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FIFOFULLINT`"]
+    #[inline(always)]
+    pub fn is_fifofullint(&self) -> bool {
+        *self == FIFOOVR2_A::FIFOFULLINT
+    }
+}
+#[doc = "Field `FIFOOVR2` writer - FIFO 100 percent full interrupt."]
+pub type FIFOOVR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, FIFOOVR2_A, O>;
+impl<'a, const O: u8> FIFOOVR2_W<'a, O> {
+    #[doc = "FIFO 100 percent full interrupt. value."]
+    #[inline(always)]
+    pub fn fifofullint(self) -> &'a mut W {
+        self.variant(FIFOOVR2_A::FIFOFULLINT)
+    }
+}
+#[doc = "Field `WCEXC` reader - Window comparator voltage excursion interrupt."]
+pub type WCEXC_R = crate::BitReader<WCEXC_A>;
+#[doc = "Window comparator voltage excursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEXC_A {
+    #[doc = "1: Window comparitor voltage excursion interrupt. value."]
+    WCEXCINT = 1,
+}
+impl From<WCEXC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEXC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEXC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEXC_A> {
+        match self.bits {
+            true => Some(WCEXC_A::WCEXCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEXCINT`"]
+    #[inline(always)]
+    pub fn is_wcexcint(&self) -> bool {
+        *self == WCEXC_A::WCEXCINT
+    }
+}
+#[doc = "Field `WCEXC` writer - Window comparator voltage excursion interrupt."]
+pub type WCEXC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, WCEXC_A, O>;
+impl<'a, const O: u8> WCEXC_W<'a, O> {
+    #[doc = "Window comparitor voltage excursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcexcint(self) -> &'a mut W {
+        self.variant(WCEXC_A::WCEXCINT)
+    }
+}
+#[doc = "Field `WCINC` reader - Window comparator voltage incursion interrupt."]
+pub type WCINC_R = crate::BitReader<WCINC_A>;
+#[doc = "Window comparator voltage incursion interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCINC_A {
+    #[doc = "1: Window comparitor voltage incursion interrupt. value."]
+    WCINCINT = 1,
+}
+impl From<WCINC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCINC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCINC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCINC_A> {
+        match self.bits {
+            true => Some(WCINC_A::WCINCINT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCINCINT`"]
+    #[inline(always)]
+    pub fn is_wcincint(&self) -> bool {
+        *self == WCINC_A::WCINCINT
+    }
+}
+#[doc = "Field `WCINC` writer - Window comparator voltage incursion interrupt."]
+pub type WCINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, WCINC_A, O>;
+impl<'a, const O: u8> WCINC_W<'a, O> {
+    #[doc = "Window comparitor voltage incursion interrupt. value."]
+    #[inline(always)]
+    pub fn wcincint(self) -> &'a mut W {
+        self.variant(WCINC_A::WCINCINT)
+    }
+}
+#[doc = "Field `DCMP` reader - DMA Transfer Complete"]
+pub type DCMP_R = crate::BitReader<DCMP_A>;
+#[doc = "DMA Transfer Complete\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DCMP_A {
+    #[doc = "1: DMA Completed a transfer value."]
+    DMACOMPLETE = 1,
+}
+impl From<DCMP_A> for bool {
+    #[inline(always)]
+    fn from(variant: DCMP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DCMP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DCMP_A> {
+        match self.bits {
+            true => Some(DCMP_A::DMACOMPLETE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMACOMPLETE`"]
+    #[inline(always)]
+    pub fn is_dmacomplete(&self) -> bool {
+        *self == DCMP_A::DMACOMPLETE
+    }
+}
+#[doc = "Field `DCMP` writer - DMA Transfer Complete"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, DCMP_A, O>;
+impl<'a, const O: u8> DCMP_W<'a, O> {
+    #[doc = "DMA Completed a transfer value."]
+    #[inline(always)]
+    pub fn dmacomplete(self) -> &'a mut W {
+        self.variant(DCMP_A::DMACOMPLETE)
+    }
+}
+#[doc = "Field `DERR` reader - DMA Error Condition"]
+pub type DERR_R = crate::BitReader<DERR_A>;
+#[doc = "DMA Error Condition\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DERR_A {
+    #[doc = "1: DMA Error Condition Occurred value."]
+    DMAERROR = 1,
+}
+impl From<DERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: DERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DERR_A> {
+        match self.bits {
+            true => Some(DERR_A::DMAERROR),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DMAERROR`"]
+    #[inline(always)]
+    pub fn is_dmaerror(&self) -> bool {
+        *self == DERR_A::DMAERROR
+    }
+}
+#[doc = "Field `DERR` writer - DMA Error Condition"]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, DERR_A, O>;
+impl<'a, const O: u8> DERR_W<'a, O> {
+    #[doc = "DMA Error Condition Occurred value."]
+    #[inline(always)]
+    pub fn dmaerror(self) -> &'a mut W {
+        self.variant(DERR_A::DMAERROR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&self) -> CNVCMP_R {
+        CNVCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&self) -> SCNCMP_R {
+        SCNCMP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&self) -> FIFOOVR1_R {
+        FIFOOVR1_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&self) -> FIFOOVR2_R {
+        FIFOOVR2_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&self) -> WCEXC_R {
+        WCEXC_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&self) -> WCINC_R {
+        WCINC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ADC conversion complete interrupt."]
+    #[inline(always)]
+    pub fn cnvcmp(&mut self) -> CNVCMP_W<0> {
+        CNVCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - ADC scan complete interrupt."]
+    #[inline(always)]
+    pub fn scncmp(&mut self) -> SCNCMP_W<1> {
+        SCNCMP_W::new(self)
+    }
+    #[doc = "Bit 2 - FIFO 75 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr1(&mut self) -> FIFOOVR1_W<2> {
+        FIFOOVR1_W::new(self)
+    }
+    #[doc = "Bit 3 - FIFO 100 percent full interrupt."]
+    #[inline(always)]
+    pub fn fifoovr2(&mut self) -> FIFOOVR2_W<3> {
+        FIFOOVR2_W::new(self)
+    }
+    #[doc = "Bit 4 - Window comparator voltage excursion interrupt."]
+    #[inline(always)]
+    pub fn wcexc(&mut self) -> WCEXC_W<4> {
+        WCEXC_W::new(self)
+    }
+    #[doc = "Bit 5 - Window comparator voltage incursion interrupt."]
+    #[inline(always)]
+    pub fn wcinc(&mut self) -> WCINC_W<5> {
+        WCINC_W::new(self)
+    }
+    #[doc = "Bit 6 - DMA Transfer Complete"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<6> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 7 - DMA Error Condition"]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<7> {
+        DERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC Interrupt registers: Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstat](index.html) module"]
+pub struct INTSTAT_SPEC;
+impl crate::RegisterSpec for INTSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intstat::R](R) reader structure"]
+impl crate::Readable for INTSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intstat::W](W) writer structure"]
+impl crate::Writable for INTSTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTSTAT to value 0"]
+impl crate::Resettable for INTSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/scwlim.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `SCWLIM` reader"]
+pub struct R(crate::R<SCWLIM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SCWLIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SCWLIM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SCWLIM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SCWLIM` writer"]
+pub struct W(crate::W<SCWLIM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SCWLIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SCWLIM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SCWLIM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SCWLIMEN` reader - Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons."]
+pub type SCWLIMEN_R = crate::BitReader<bool>;
+#[doc = "Field `SCWLIMEN` writer - Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons."]
+pub type SCWLIMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCWLIM_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons."]
+    #[inline(always)]
+    pub fn scwlimen(&self) -> SCWLIMEN_R {
+        SCWLIMEN_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons."]
+    #[inline(always)]
+    pub fn scwlimen(&mut self) -> SCWLIMEN_W<0> {
+        SCWLIMEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Scale Window Comparator Limits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scwlim](index.html) module"]
+pub struct SCWLIM_SPEC;
+impl crate::RegisterSpec for SCWLIM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [scwlim::R](R) reader structure"]
+impl crate::Readable for SCWLIM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [scwlim::W](W) writer structure"]
+impl crate::Writable for SCWLIM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SCWLIM to value 0"]
+impl crate::Resettable for SCWLIM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl0cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL0CFG` reader"]
+pub struct R(crate::R<SL0CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL0CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL0CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL0CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL0CFG` writer"]
+pub struct W(crate::W<SL0CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL0CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL0CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL0CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN0` reader - This bit enables slot 0 for ADC conversions."]
+pub type SLEN0_R = crate::BitReader<SLEN0_A>;
+#[doc = "This bit enables slot 0 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN0_A {
+    #[doc = "1: Enable slot 0 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN0_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN0_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN0_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN0_A> {
+        match self.bits {
+            true => Some(SLEN0_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN0_A::SLEN
+    }
+}
+#[doc = "Field `SLEN0` writer - This bit enables slot 0 for ADC conversions."]
+pub type SLEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL0CFG_SPEC, SLEN0_A, O>;
+impl<'a, const O: u8> SLEN0_W<'a, O> {
+    #[doc = "Enable slot 0 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN0_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN0` reader - This bit enables the window compare function for slot 0."]
+pub type WCEN0_R = crate::BitReader<WCEN0_A>;
+#[doc = "This bit enables the window compare function for slot 0.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN0_A {
+    #[doc = "1: Enable the window compare for slot 0. value."]
+    WCEN = 1,
+}
+impl From<WCEN0_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN0_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN0_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN0_A> {
+        match self.bits {
+            true => Some(WCEN0_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN0_A::WCEN
+    }
+}
+#[doc = "Field `WCEN0` writer - This bit enables the window compare function for slot 0."]
+pub type WCEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL0CFG_SPEC, WCEN0_A, O>;
+impl<'a, const O: u8> WCEN0_W<'a, O> {
+    #[doc = "Enable the window compare for slot 0. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN0_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL0` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL0_R = crate::FieldReader<u8, CHSEL0_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL0_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL0_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL0_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL0_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL0_A> {
+        match self.bits {
+            0 => Some(CHSEL0_A::SE0),
+            1 => Some(CHSEL0_A::SE1),
+            2 => Some(CHSEL0_A::SE2),
+            3 => Some(CHSEL0_A::SE3),
+            4 => Some(CHSEL0_A::SE4),
+            5 => Some(CHSEL0_A::SE5),
+            6 => Some(CHSEL0_A::SE6),
+            7 => Some(CHSEL0_A::SE7),
+            8 => Some(CHSEL0_A::SE8),
+            9 => Some(CHSEL0_A::SE9),
+            10 => Some(CHSEL0_A::DF0),
+            11 => Some(CHSEL0_A::DF1),
+            12 => Some(CHSEL0_A::TEMP),
+            13 => Some(CHSEL0_A::BATT),
+            14 => Some(CHSEL0_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL0_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL0_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL0_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL0_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL0_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL0_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL0_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL0_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL0_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL0_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL0_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL0_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL0_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL0_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL0_A::VSS
+    }
+}
+#[doc = "Field `CHSEL0` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL0CFG_SPEC, u8, CHSEL0_A, 4, O>;
+impl<'a, const O: u8> CHSEL0_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL0_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL0_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL0_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL0_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL0_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL0_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE0` reader - Set the Precision Mode For Slot."]
+pub type PRMODE0_R = crate::FieldReader<u8, PRMODE0_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE0_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE0_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE0_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE0_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE0_A {
+        match self.bits {
+            0 => PRMODE0_A::P14B,
+            1 => PRMODE0_A::P12B,
+            2 => PRMODE0_A::P10B,
+            3 => PRMODE0_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE0_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE0_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE0_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE0_A::P8B
+    }
+}
+#[doc = "Field `PRMODE0` writer - Set the Precision Mode For Slot."]
+pub type PRMODE0_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL0CFG_SPEC, u8, PRMODE0_A, 2, O>;
+impl<'a, const O: u8> PRMODE0_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE0_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE0_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE0_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE0_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL0` reader - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL0_R = crate::FieldReader<u8, ADSEL0_A>;
+#[doc = "Select the number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL0_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL0_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL0_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL0_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL0_A {
+        match self.bits {
+            0 => ADSEL0_A::AVG_1_MSRMT,
+            1 => ADSEL0_A::AVG_2_MSRMTS,
+            2 => ADSEL0_A::AVG_4_MSRMTS,
+            3 => ADSEL0_A::AVG_8_MSRMT,
+            4 => ADSEL0_A::AVG_16_MSRMTS,
+            5 => ADSEL0_A::AVG_32_MSRMTS,
+            6 => ADSEL0_A::AVG_64_MSRMTS,
+            7 => ADSEL0_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL0_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL0_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL0_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL0_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL0_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL0_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL0_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL0_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL0` writer - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL0_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL0CFG_SPEC, u8, ADSEL0_A, 3, O>;
+impl<'a, const O: u8> ADSEL0_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL0_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 0 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen0(&self) -> SLEN0_R {
+        SLEN0_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 0."]
+    #[inline(always)]
+    pub fn wcen0(&self) -> WCEN0_R {
+        WCEN0_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel0(&self) -> CHSEL0_R {
+        CHSEL0_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode0(&self) -> PRMODE0_R {
+        PRMODE0_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel0(&self) -> ADSEL0_R {
+        ADSEL0_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 0 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen0(&mut self) -> SLEN0_W<0> {
+        SLEN0_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 0."]
+    #[inline(always)]
+    pub fn wcen0(&mut self) -> WCEN0_W<1> {
+        WCEN0_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel0(&mut self) -> CHSEL0_W<8> {
+        CHSEL0_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode0(&mut self) -> PRMODE0_W<16> {
+        PRMODE0_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel0(&mut self) -> ADSEL0_W<24> {
+        ADSEL0_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 0 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl0cfg](index.html) module"]
+pub struct SL0CFG_SPEC;
+impl crate::RegisterSpec for SL0CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl0cfg::R](R) reader structure"]
+impl crate::Readable for SL0CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl0cfg::W](W) writer structure"]
+impl crate::Writable for SL0CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL0CFG to value 0"]
+impl crate::Resettable for SL0CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl1cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL1CFG` reader"]
+pub struct R(crate::R<SL1CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL1CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL1CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL1CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL1CFG` writer"]
+pub struct W(crate::W<SL1CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL1CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL1CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL1CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN1` reader - This bit enables slot 1 for ADC conversions."]
+pub type SLEN1_R = crate::BitReader<SLEN1_A>;
+#[doc = "This bit enables slot 1 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN1_A {
+    #[doc = "1: Enable slot 1 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN1_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN1_A> {
+        match self.bits {
+            true => Some(SLEN1_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN1_A::SLEN
+    }
+}
+#[doc = "Field `SLEN1` writer - This bit enables slot 1 for ADC conversions."]
+pub type SLEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL1CFG_SPEC, SLEN1_A, O>;
+impl<'a, const O: u8> SLEN1_W<'a, O> {
+    #[doc = "Enable slot 1 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN1_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN1` reader - This bit enables the window compare function for slot 1."]
+pub type WCEN1_R = crate::BitReader<WCEN1_A>;
+#[doc = "This bit enables the window compare function for slot 1.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN1_A {
+    #[doc = "1: Enable the window compare for slot 1. value."]
+    WCEN = 1,
+}
+impl From<WCEN1_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN1_A> {
+        match self.bits {
+            true => Some(WCEN1_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN1_A::WCEN
+    }
+}
+#[doc = "Field `WCEN1` writer - This bit enables the window compare function for slot 1."]
+pub type WCEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL1CFG_SPEC, WCEN1_A, O>;
+impl<'a, const O: u8> WCEN1_W<'a, O> {
+    #[doc = "Enable the window compare for slot 1. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN1_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL1` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL1_R = crate::FieldReader<u8, CHSEL1_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL1_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL1_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL1_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL1_A> {
+        match self.bits {
+            0 => Some(CHSEL1_A::SE0),
+            1 => Some(CHSEL1_A::SE1),
+            2 => Some(CHSEL1_A::SE2),
+            3 => Some(CHSEL1_A::SE3),
+            4 => Some(CHSEL1_A::SE4),
+            5 => Some(CHSEL1_A::SE5),
+            6 => Some(CHSEL1_A::SE6),
+            7 => Some(CHSEL1_A::SE7),
+            8 => Some(CHSEL1_A::SE8),
+            9 => Some(CHSEL1_A::SE9),
+            10 => Some(CHSEL1_A::DF0),
+            11 => Some(CHSEL1_A::DF1),
+            12 => Some(CHSEL1_A::TEMP),
+            13 => Some(CHSEL1_A::BATT),
+            14 => Some(CHSEL1_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL1_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL1_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL1_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL1_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL1_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL1_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL1_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL1_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL1_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL1_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL1_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL1_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL1_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL1_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL1_A::VSS
+    }
+}
+#[doc = "Field `CHSEL1` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL1CFG_SPEC, u8, CHSEL1_A, 4, O>;
+impl<'a, const O: u8> CHSEL1_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL1_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL1_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL1_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL1_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL1_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL1_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE1` reader - Set the Precision Mode For Slot."]
+pub type PRMODE1_R = crate::FieldReader<u8, PRMODE1_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE1_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE1_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE1_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE1_A {
+        match self.bits {
+            0 => PRMODE1_A::P14B,
+            1 => PRMODE1_A::P12B,
+            2 => PRMODE1_A::P10B,
+            3 => PRMODE1_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE1_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE1_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE1_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE1_A::P8B
+    }
+}
+#[doc = "Field `PRMODE1` writer - Set the Precision Mode For Slot."]
+pub type PRMODE1_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL1CFG_SPEC, u8, PRMODE1_A, 2, O>;
+impl<'a, const O: u8> PRMODE1_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE1_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE1_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE1_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE1_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL1` reader - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL1_R = crate::FieldReader<u8, ADSEL1_A>;
+#[doc = "Select the number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL1_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL1_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL1_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL1_A {
+        match self.bits {
+            0 => ADSEL1_A::AVG_1_MSRMT,
+            1 => ADSEL1_A::AVG_2_MSRMTS,
+            2 => ADSEL1_A::AVG_4_MSRMTS,
+            3 => ADSEL1_A::AVG_8_MSRMT,
+            4 => ADSEL1_A::AVG_16_MSRMTS,
+            5 => ADSEL1_A::AVG_32_MSRMTS,
+            6 => ADSEL1_A::AVG_64_MSRMTS,
+            7 => ADSEL1_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL1_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL1_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL1_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL1_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL1_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL1_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL1_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL1_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL1` writer - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL1_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL1CFG_SPEC, u8, ADSEL1_A, 3, O>;
+impl<'a, const O: u8> ADSEL1_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL1_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 1 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen1(&self) -> SLEN1_R {
+        SLEN1_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 1."]
+    #[inline(always)]
+    pub fn wcen1(&self) -> WCEN1_R {
+        WCEN1_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel1(&self) -> CHSEL1_R {
+        CHSEL1_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode1(&self) -> PRMODE1_R {
+        PRMODE1_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel1(&self) -> ADSEL1_R {
+        ADSEL1_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 1 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen1(&mut self) -> SLEN1_W<0> {
+        SLEN1_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 1."]
+    #[inline(always)]
+    pub fn wcen1(&mut self) -> WCEN1_W<1> {
+        WCEN1_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel1(&mut self) -> CHSEL1_W<8> {
+        CHSEL1_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode1(&mut self) -> PRMODE1_W<16> {
+        PRMODE1_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel1(&mut self) -> ADSEL1_W<24> {
+        ADSEL1_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 1 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl1cfg](index.html) module"]
+pub struct SL1CFG_SPEC;
+impl crate::RegisterSpec for SL1CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl1cfg::R](R) reader structure"]
+impl crate::Readable for SL1CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl1cfg::W](W) writer structure"]
+impl crate::Writable for SL1CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL1CFG to value 0"]
+impl crate::Resettable for SL1CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl2cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL2CFG` reader"]
+pub struct R(crate::R<SL2CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL2CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL2CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL2CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL2CFG` writer"]
+pub struct W(crate::W<SL2CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL2CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL2CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL2CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN2` reader - This bit enables slot 2 for ADC conversions."]
+pub type SLEN2_R = crate::BitReader<SLEN2_A>;
+#[doc = "This bit enables slot 2 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN2_A {
+    #[doc = "1: Enable slot 2 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN2_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN2_A> {
+        match self.bits {
+            true => Some(SLEN2_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN2_A::SLEN
+    }
+}
+#[doc = "Field `SLEN2` writer - This bit enables slot 2 for ADC conversions."]
+pub type SLEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL2CFG_SPEC, SLEN2_A, O>;
+impl<'a, const O: u8> SLEN2_W<'a, O> {
+    #[doc = "Enable slot 2 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN2_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN2` reader - This bit enables the window compare function for slot 2."]
+pub type WCEN2_R = crate::BitReader<WCEN2_A>;
+#[doc = "This bit enables the window compare function for slot 2.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN2_A {
+    #[doc = "1: Enable the window compare for slot 2. value."]
+    WCEN = 1,
+}
+impl From<WCEN2_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN2_A> {
+        match self.bits {
+            true => Some(WCEN2_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN2_A::WCEN
+    }
+}
+#[doc = "Field `WCEN2` writer - This bit enables the window compare function for slot 2."]
+pub type WCEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL2CFG_SPEC, WCEN2_A, O>;
+impl<'a, const O: u8> WCEN2_W<'a, O> {
+    #[doc = "Enable the window compare for slot 2. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN2_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL2` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL2_R = crate::FieldReader<u8, CHSEL2_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL2_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL2_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL2_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL2_A> {
+        match self.bits {
+            0 => Some(CHSEL2_A::SE0),
+            1 => Some(CHSEL2_A::SE1),
+            2 => Some(CHSEL2_A::SE2),
+            3 => Some(CHSEL2_A::SE3),
+            4 => Some(CHSEL2_A::SE4),
+            5 => Some(CHSEL2_A::SE5),
+            6 => Some(CHSEL2_A::SE6),
+            7 => Some(CHSEL2_A::SE7),
+            8 => Some(CHSEL2_A::SE8),
+            9 => Some(CHSEL2_A::SE9),
+            10 => Some(CHSEL2_A::DF0),
+            11 => Some(CHSEL2_A::DF1),
+            12 => Some(CHSEL2_A::TEMP),
+            13 => Some(CHSEL2_A::BATT),
+            14 => Some(CHSEL2_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL2_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL2_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL2_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL2_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL2_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL2_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL2_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL2_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL2_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL2_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL2_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL2_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL2_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL2_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL2_A::VSS
+    }
+}
+#[doc = "Field `CHSEL2` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL2CFG_SPEC, u8, CHSEL2_A, 4, O>;
+impl<'a, const O: u8> CHSEL2_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL2_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL2_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL2_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL2_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL2_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL2_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE2` reader - Set the Precision Mode For Slot."]
+pub type PRMODE2_R = crate::FieldReader<u8, PRMODE2_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE2_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE2_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE2_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE2_A {
+        match self.bits {
+            0 => PRMODE2_A::P14B,
+            1 => PRMODE2_A::P12B,
+            2 => PRMODE2_A::P10B,
+            3 => PRMODE2_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE2_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE2_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE2_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE2_A::P8B
+    }
+}
+#[doc = "Field `PRMODE2` writer - Set the Precision Mode For Slot."]
+pub type PRMODE2_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL2CFG_SPEC, u8, PRMODE2_A, 2, O>;
+impl<'a, const O: u8> PRMODE2_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE2_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE2_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE2_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE2_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL2` reader - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL2_R = crate::FieldReader<u8, ADSEL2_A>;
+#[doc = "Select the number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL2_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL2_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL2_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL2_A {
+        match self.bits {
+            0 => ADSEL2_A::AVG_1_MSRMT,
+            1 => ADSEL2_A::AVG_2_MSRMTS,
+            2 => ADSEL2_A::AVG_4_MSRMTS,
+            3 => ADSEL2_A::AVG_8_MSRMT,
+            4 => ADSEL2_A::AVG_16_MSRMTS,
+            5 => ADSEL2_A::AVG_32_MSRMTS,
+            6 => ADSEL2_A::AVG_64_MSRMTS,
+            7 => ADSEL2_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL2_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL2_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL2_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL2_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL2_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL2_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL2_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL2_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL2` writer - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL2_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL2CFG_SPEC, u8, ADSEL2_A, 3, O>;
+impl<'a, const O: u8> ADSEL2_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL2_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 2 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen2(&self) -> SLEN2_R {
+        SLEN2_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 2."]
+    #[inline(always)]
+    pub fn wcen2(&self) -> WCEN2_R {
+        WCEN2_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel2(&self) -> CHSEL2_R {
+        CHSEL2_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode2(&self) -> PRMODE2_R {
+        PRMODE2_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel2(&self) -> ADSEL2_R {
+        ADSEL2_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 2 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen2(&mut self) -> SLEN2_W<0> {
+        SLEN2_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 2."]
+    #[inline(always)]
+    pub fn wcen2(&mut self) -> WCEN2_W<1> {
+        WCEN2_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel2(&mut self) -> CHSEL2_W<8> {
+        CHSEL2_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode2(&mut self) -> PRMODE2_W<16> {
+        PRMODE2_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel2(&mut self) -> ADSEL2_W<24> {
+        ADSEL2_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 2 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl2cfg](index.html) module"]
+pub struct SL2CFG_SPEC;
+impl crate::RegisterSpec for SL2CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl2cfg::R](R) reader structure"]
+impl crate::Readable for SL2CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl2cfg::W](W) writer structure"]
+impl crate::Writable for SL2CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL2CFG to value 0"]
+impl crate::Resettable for SL2CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl3cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL3CFG` reader"]
+pub struct R(crate::R<SL3CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL3CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL3CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL3CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL3CFG` writer"]
+pub struct W(crate::W<SL3CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL3CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL3CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL3CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN3` reader - This bit enables slot 3 for ADC conversions."]
+pub type SLEN3_R = crate::BitReader<SLEN3_A>;
+#[doc = "This bit enables slot 3 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN3_A {
+    #[doc = "1: Enable slot 3 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN3_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN3_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN3_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN3_A> {
+        match self.bits {
+            true => Some(SLEN3_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN3_A::SLEN
+    }
+}
+#[doc = "Field `SLEN3` writer - This bit enables slot 3 for ADC conversions."]
+pub type SLEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL3CFG_SPEC, SLEN3_A, O>;
+impl<'a, const O: u8> SLEN3_W<'a, O> {
+    #[doc = "Enable slot 3 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN3_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN3` reader - This bit enables the window compare function for slot 3."]
+pub type WCEN3_R = crate::BitReader<WCEN3_A>;
+#[doc = "This bit enables the window compare function for slot 3.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN3_A {
+    #[doc = "1: Enable the window compare for slot 3. value."]
+    WCEN = 1,
+}
+impl From<WCEN3_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN3_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN3_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN3_A> {
+        match self.bits {
+            true => Some(WCEN3_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN3_A::WCEN
+    }
+}
+#[doc = "Field `WCEN3` writer - This bit enables the window compare function for slot 3."]
+pub type WCEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL3CFG_SPEC, WCEN3_A, O>;
+impl<'a, const O: u8> WCEN3_W<'a, O> {
+    #[doc = "Enable the window compare for slot 3. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN3_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL3` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL3_R = crate::FieldReader<u8, CHSEL3_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL3_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL3_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL3_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL3_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL3_A> {
+        match self.bits {
+            0 => Some(CHSEL3_A::SE0),
+            1 => Some(CHSEL3_A::SE1),
+            2 => Some(CHSEL3_A::SE2),
+            3 => Some(CHSEL3_A::SE3),
+            4 => Some(CHSEL3_A::SE4),
+            5 => Some(CHSEL3_A::SE5),
+            6 => Some(CHSEL3_A::SE6),
+            7 => Some(CHSEL3_A::SE7),
+            8 => Some(CHSEL3_A::SE8),
+            9 => Some(CHSEL3_A::SE9),
+            10 => Some(CHSEL3_A::DF0),
+            11 => Some(CHSEL3_A::DF1),
+            12 => Some(CHSEL3_A::TEMP),
+            13 => Some(CHSEL3_A::BATT),
+            14 => Some(CHSEL3_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL3_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL3_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL3_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL3_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL3_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL3_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL3_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL3_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL3_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL3_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL3_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL3_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL3_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL3_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL3_A::VSS
+    }
+}
+#[doc = "Field `CHSEL3` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL3CFG_SPEC, u8, CHSEL3_A, 4, O>;
+impl<'a, const O: u8> CHSEL3_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL3_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL3_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL3_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL3_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL3_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL3_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE3` reader - Set the Precision Mode For Slot."]
+pub type PRMODE3_R = crate::FieldReader<u8, PRMODE3_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE3_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE3_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE3_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE3_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE3_A {
+        match self.bits {
+            0 => PRMODE3_A::P14B,
+            1 => PRMODE3_A::P12B,
+            2 => PRMODE3_A::P10B,
+            3 => PRMODE3_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE3_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE3_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE3_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE3_A::P8B
+    }
+}
+#[doc = "Field `PRMODE3` writer - Set the Precision Mode For Slot."]
+pub type PRMODE3_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL3CFG_SPEC, u8, PRMODE3_A, 2, O>;
+impl<'a, const O: u8> PRMODE3_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE3_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE3_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE3_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE3_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL3` reader - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL3_R = crate::FieldReader<u8, ADSEL3_A>;
+#[doc = "Select the number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL3_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL3_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL3_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL3_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL3_A {
+        match self.bits {
+            0 => ADSEL3_A::AVG_1_MSRMT,
+            1 => ADSEL3_A::AVG_2_MSRMTS,
+            2 => ADSEL3_A::AVG_4_MSRMTS,
+            3 => ADSEL3_A::AVG_8_MSRMT,
+            4 => ADSEL3_A::AVG_16_MSRMTS,
+            5 => ADSEL3_A::AVG_32_MSRMTS,
+            6 => ADSEL3_A::AVG_64_MSRMTS,
+            7 => ADSEL3_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL3_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL3_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL3_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL3_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL3_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL3_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL3_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL3_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL3` writer - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL3_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL3CFG_SPEC, u8, ADSEL3_A, 3, O>;
+impl<'a, const O: u8> ADSEL3_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL3_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 3 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen3(&self) -> SLEN3_R {
+        SLEN3_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 3."]
+    #[inline(always)]
+    pub fn wcen3(&self) -> WCEN3_R {
+        WCEN3_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel3(&self) -> CHSEL3_R {
+        CHSEL3_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode3(&self) -> PRMODE3_R {
+        PRMODE3_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel3(&self) -> ADSEL3_R {
+        ADSEL3_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 3 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen3(&mut self) -> SLEN3_W<0> {
+        SLEN3_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 3."]
+    #[inline(always)]
+    pub fn wcen3(&mut self) -> WCEN3_W<1> {
+        WCEN3_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel3(&mut self) -> CHSEL3_W<8> {
+        CHSEL3_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode3(&mut self) -> PRMODE3_W<16> {
+        PRMODE3_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel3(&mut self) -> ADSEL3_W<24> {
+        ADSEL3_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 3 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl3cfg](index.html) module"]
+pub struct SL3CFG_SPEC;
+impl crate::RegisterSpec for SL3CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl3cfg::R](R) reader structure"]
+impl crate::Readable for SL3CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl3cfg::W](W) writer structure"]
+impl crate::Writable for SL3CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL3CFG to value 0"]
+impl crate::Resettable for SL3CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl4cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL4CFG` reader"]
+pub struct R(crate::R<SL4CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL4CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL4CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL4CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL4CFG` writer"]
+pub struct W(crate::W<SL4CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL4CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL4CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL4CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN4` reader - This bit enables slot 4 for ADC conversions."]
+pub type SLEN4_R = crate::BitReader<SLEN4_A>;
+#[doc = "This bit enables slot 4 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN4_A {
+    #[doc = "1: Enable slot 4 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN4_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN4_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN4_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN4_A> {
+        match self.bits {
+            true => Some(SLEN4_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN4_A::SLEN
+    }
+}
+#[doc = "Field `SLEN4` writer - This bit enables slot 4 for ADC conversions."]
+pub type SLEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL4CFG_SPEC, SLEN4_A, O>;
+impl<'a, const O: u8> SLEN4_W<'a, O> {
+    #[doc = "Enable slot 4 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN4_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN4` reader - This bit enables the window compare function for slot 4."]
+pub type WCEN4_R = crate::BitReader<WCEN4_A>;
+#[doc = "This bit enables the window compare function for slot 4.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN4_A {
+    #[doc = "1: Enable the window compare for slot 4. value."]
+    WCEN = 1,
+}
+impl From<WCEN4_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN4_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN4_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN4_A> {
+        match self.bits {
+            true => Some(WCEN4_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN4_A::WCEN
+    }
+}
+#[doc = "Field `WCEN4` writer - This bit enables the window compare function for slot 4."]
+pub type WCEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL4CFG_SPEC, WCEN4_A, O>;
+impl<'a, const O: u8> WCEN4_W<'a, O> {
+    #[doc = "Enable the window compare for slot 4. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN4_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL4` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL4_R = crate::FieldReader<u8, CHSEL4_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL4_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL4_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL4_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL4_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL4_A> {
+        match self.bits {
+            0 => Some(CHSEL4_A::SE0),
+            1 => Some(CHSEL4_A::SE1),
+            2 => Some(CHSEL4_A::SE2),
+            3 => Some(CHSEL4_A::SE3),
+            4 => Some(CHSEL4_A::SE4),
+            5 => Some(CHSEL4_A::SE5),
+            6 => Some(CHSEL4_A::SE6),
+            7 => Some(CHSEL4_A::SE7),
+            8 => Some(CHSEL4_A::SE8),
+            9 => Some(CHSEL4_A::SE9),
+            10 => Some(CHSEL4_A::DF0),
+            11 => Some(CHSEL4_A::DF1),
+            12 => Some(CHSEL4_A::TEMP),
+            13 => Some(CHSEL4_A::BATT),
+            14 => Some(CHSEL4_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL4_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL4_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL4_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL4_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL4_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL4_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL4_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL4_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL4_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL4_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL4_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL4_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL4_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL4_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL4_A::VSS
+    }
+}
+#[doc = "Field `CHSEL4` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL4CFG_SPEC, u8, CHSEL4_A, 4, O>;
+impl<'a, const O: u8> CHSEL4_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL4_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL4_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL4_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL4_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL4_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL4_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE4` reader - Set the Precision Mode For Slot."]
+pub type PRMODE4_R = crate::FieldReader<u8, PRMODE4_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE4_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE4_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE4_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE4_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE4_A {
+        match self.bits {
+            0 => PRMODE4_A::P14B,
+            1 => PRMODE4_A::P12B,
+            2 => PRMODE4_A::P10B,
+            3 => PRMODE4_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE4_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE4_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE4_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE4_A::P8B
+    }
+}
+#[doc = "Field `PRMODE4` writer - Set the Precision Mode For Slot."]
+pub type PRMODE4_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL4CFG_SPEC, u8, PRMODE4_A, 2, O>;
+impl<'a, const O: u8> PRMODE4_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE4_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE4_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE4_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE4_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL4` reader - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL4_R = crate::FieldReader<u8, ADSEL4_A>;
+#[doc = "Select the number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL4_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL4_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL4_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL4_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL4_A {
+        match self.bits {
+            0 => ADSEL4_A::AVG_1_MSRMT,
+            1 => ADSEL4_A::AVG_2_MSRMTS,
+            2 => ADSEL4_A::AVG_4_MSRMTS,
+            3 => ADSEL4_A::AVG_8_MSRMT,
+            4 => ADSEL4_A::AVG_16_MSRMTS,
+            5 => ADSEL4_A::AVG_32_MSRMTS,
+            6 => ADSEL4_A::AVG_64_MSRMTS,
+            7 => ADSEL4_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL4_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL4_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL4_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL4_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL4_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL4_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL4_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL4_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL4` writer - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL4_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL4CFG_SPEC, u8, ADSEL4_A, 3, O>;
+impl<'a, const O: u8> ADSEL4_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL4_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 4 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen4(&self) -> SLEN4_R {
+        SLEN4_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 4."]
+    #[inline(always)]
+    pub fn wcen4(&self) -> WCEN4_R {
+        WCEN4_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel4(&self) -> CHSEL4_R {
+        CHSEL4_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode4(&self) -> PRMODE4_R {
+        PRMODE4_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel4(&self) -> ADSEL4_R {
+        ADSEL4_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 4 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen4(&mut self) -> SLEN4_W<0> {
+        SLEN4_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 4."]
+    #[inline(always)]
+    pub fn wcen4(&mut self) -> WCEN4_W<1> {
+        WCEN4_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel4(&mut self) -> CHSEL4_W<8> {
+        CHSEL4_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode4(&mut self) -> PRMODE4_W<16> {
+        PRMODE4_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel4(&mut self) -> ADSEL4_W<24> {
+        ADSEL4_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 4 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl4cfg](index.html) module"]
+pub struct SL4CFG_SPEC;
+impl crate::RegisterSpec for SL4CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl4cfg::R](R) reader structure"]
+impl crate::Readable for SL4CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl4cfg::W](W) writer structure"]
+impl crate::Writable for SL4CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL4CFG to value 0"]
+impl crate::Resettable for SL4CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl5cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL5CFG` reader"]
+pub struct R(crate::R<SL5CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL5CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL5CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL5CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL5CFG` writer"]
+pub struct W(crate::W<SL5CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL5CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL5CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL5CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN5` reader - This bit enables slot 5 for ADC conversions."]
+pub type SLEN5_R = crate::BitReader<SLEN5_A>;
+#[doc = "This bit enables slot 5 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN5_A {
+    #[doc = "1: Enable slot 5 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN5_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN5_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN5_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN5_A> {
+        match self.bits {
+            true => Some(SLEN5_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN5_A::SLEN
+    }
+}
+#[doc = "Field `SLEN5` writer - This bit enables slot 5 for ADC conversions."]
+pub type SLEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL5CFG_SPEC, SLEN5_A, O>;
+impl<'a, const O: u8> SLEN5_W<'a, O> {
+    #[doc = "Enable slot 5 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN5_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN5` reader - This bit enables the window compare function for slot 5."]
+pub type WCEN5_R = crate::BitReader<WCEN5_A>;
+#[doc = "This bit enables the window compare function for slot 5.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN5_A {
+    #[doc = "1: Enable the window compare for slot 5. value."]
+    WCEN = 1,
+}
+impl From<WCEN5_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN5_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN5_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN5_A> {
+        match self.bits {
+            true => Some(WCEN5_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN5_A::WCEN
+    }
+}
+#[doc = "Field `WCEN5` writer - This bit enables the window compare function for slot 5."]
+pub type WCEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL5CFG_SPEC, WCEN5_A, O>;
+impl<'a, const O: u8> WCEN5_W<'a, O> {
+    #[doc = "Enable the window compare for slot 5. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN5_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL5` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL5_R = crate::FieldReader<u8, CHSEL5_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL5_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL5_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL5_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL5_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL5_A> {
+        match self.bits {
+            0 => Some(CHSEL5_A::SE0),
+            1 => Some(CHSEL5_A::SE1),
+            2 => Some(CHSEL5_A::SE2),
+            3 => Some(CHSEL5_A::SE3),
+            4 => Some(CHSEL5_A::SE4),
+            5 => Some(CHSEL5_A::SE5),
+            6 => Some(CHSEL5_A::SE6),
+            7 => Some(CHSEL5_A::SE7),
+            8 => Some(CHSEL5_A::SE8),
+            9 => Some(CHSEL5_A::SE9),
+            10 => Some(CHSEL5_A::DF0),
+            11 => Some(CHSEL5_A::DF1),
+            12 => Some(CHSEL5_A::TEMP),
+            13 => Some(CHSEL5_A::BATT),
+            14 => Some(CHSEL5_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL5_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL5_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL5_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL5_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL5_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL5_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL5_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL5_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL5_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL5_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL5_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL5_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL5_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL5_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL5_A::VSS
+    }
+}
+#[doc = "Field `CHSEL5` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL5CFG_SPEC, u8, CHSEL5_A, 4, O>;
+impl<'a, const O: u8> CHSEL5_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL5_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL5_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL5_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL5_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL5_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL5_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE5` reader - Set the Precision Mode For Slot."]
+pub type PRMODE5_R = crate::FieldReader<u8, PRMODE5_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE5_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE5_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE5_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE5_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE5_A {
+        match self.bits {
+            0 => PRMODE5_A::P14B,
+            1 => PRMODE5_A::P12B,
+            2 => PRMODE5_A::P10B,
+            3 => PRMODE5_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE5_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE5_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE5_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE5_A::P8B
+    }
+}
+#[doc = "Field `PRMODE5` writer - Set the Precision Mode For Slot."]
+pub type PRMODE5_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL5CFG_SPEC, u8, PRMODE5_A, 2, O>;
+impl<'a, const O: u8> PRMODE5_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE5_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE5_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE5_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE5_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL5` reader - Select number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL5_R = crate::FieldReader<u8, ADSEL5_A>;
+#[doc = "Select number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL5_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL5_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL5_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL5_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL5_A {
+        match self.bits {
+            0 => ADSEL5_A::AVG_1_MSRMT,
+            1 => ADSEL5_A::AVG_2_MSRMTS,
+            2 => ADSEL5_A::AVG_4_MSRMTS,
+            3 => ADSEL5_A::AVG_8_MSRMT,
+            4 => ADSEL5_A::AVG_16_MSRMTS,
+            5 => ADSEL5_A::AVG_32_MSRMTS,
+            6 => ADSEL5_A::AVG_64_MSRMTS,
+            7 => ADSEL5_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL5_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL5_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL5_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL5_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL5_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL5_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL5_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL5_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL5` writer - Select number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL5_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL5CFG_SPEC, u8, ADSEL5_A, 3, O>;
+impl<'a, const O: u8> ADSEL5_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL5_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 5 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen5(&self) -> SLEN5_R {
+        SLEN5_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 5."]
+    #[inline(always)]
+    pub fn wcen5(&self) -> WCEN5_R {
+        WCEN5_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel5(&self) -> CHSEL5_R {
+        CHSEL5_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode5(&self) -> PRMODE5_R {
+        PRMODE5_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel5(&self) -> ADSEL5_R {
+        ADSEL5_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 5 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen5(&mut self) -> SLEN5_W<0> {
+        SLEN5_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 5."]
+    #[inline(always)]
+    pub fn wcen5(&mut self) -> WCEN5_W<1> {
+        WCEN5_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel5(&mut self) -> CHSEL5_W<8> {
+        CHSEL5_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode5(&mut self) -> PRMODE5_W<16> {
+        PRMODE5_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel5(&mut self) -> ADSEL5_W<24> {
+        ADSEL5_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 5 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl5cfg](index.html) module"]
+pub struct SL5CFG_SPEC;
+impl crate::RegisterSpec for SL5CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl5cfg::R](R) reader structure"]
+impl crate::Readable for SL5CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl5cfg::W](W) writer structure"]
+impl crate::Writable for SL5CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL5CFG to value 0"]
+impl crate::Resettable for SL5CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl6cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL6CFG` reader"]
+pub struct R(crate::R<SL6CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL6CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL6CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL6CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL6CFG` writer"]
+pub struct W(crate::W<SL6CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL6CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL6CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL6CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN6` reader - This bit enables slot 6 for ADC conversions."]
+pub type SLEN6_R = crate::BitReader<SLEN6_A>;
+#[doc = "This bit enables slot 6 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN6_A {
+    #[doc = "1: Enable slot 6 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN6_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN6_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN6_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN6_A> {
+        match self.bits {
+            true => Some(SLEN6_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN6_A::SLEN
+    }
+}
+#[doc = "Field `SLEN6` writer - This bit enables slot 6 for ADC conversions."]
+pub type SLEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL6CFG_SPEC, SLEN6_A, O>;
+impl<'a, const O: u8> SLEN6_W<'a, O> {
+    #[doc = "Enable slot 6 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN6_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN6` reader - This bit enables the window compare function for slot 6."]
+pub type WCEN6_R = crate::BitReader<WCEN6_A>;
+#[doc = "This bit enables the window compare function for slot 6.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN6_A {
+    #[doc = "1: Enable the window compare for slot 6. value."]
+    WCEN = 1,
+}
+impl From<WCEN6_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN6_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN6_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN6_A> {
+        match self.bits {
+            true => Some(WCEN6_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN6_A::WCEN
+    }
+}
+#[doc = "Field `WCEN6` writer - This bit enables the window compare function for slot 6."]
+pub type WCEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL6CFG_SPEC, WCEN6_A, O>;
+impl<'a, const O: u8> WCEN6_W<'a, O> {
+    #[doc = "Enable the window compare for slot 6. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN6_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL6` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL6_R = crate::FieldReader<u8, CHSEL6_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL6_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL6_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL6_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL6_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL6_A> {
+        match self.bits {
+            0 => Some(CHSEL6_A::SE0),
+            1 => Some(CHSEL6_A::SE1),
+            2 => Some(CHSEL6_A::SE2),
+            3 => Some(CHSEL6_A::SE3),
+            4 => Some(CHSEL6_A::SE4),
+            5 => Some(CHSEL6_A::SE5),
+            6 => Some(CHSEL6_A::SE6),
+            7 => Some(CHSEL6_A::SE7),
+            8 => Some(CHSEL6_A::SE8),
+            9 => Some(CHSEL6_A::SE9),
+            10 => Some(CHSEL6_A::DF0),
+            11 => Some(CHSEL6_A::DF1),
+            12 => Some(CHSEL6_A::TEMP),
+            13 => Some(CHSEL6_A::BATT),
+            14 => Some(CHSEL6_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL6_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL6_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL6_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL6_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL6_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL6_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL6_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL6_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL6_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL6_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL6_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL6_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL6_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL6_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL6_A::VSS
+    }
+}
+#[doc = "Field `CHSEL6` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL6CFG_SPEC, u8, CHSEL6_A, 4, O>;
+impl<'a, const O: u8> CHSEL6_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL6_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL6_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL6_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL6_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL6_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL6_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE6` reader - Set the Precision Mode For Slot."]
+pub type PRMODE6_R = crate::FieldReader<u8, PRMODE6_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE6_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE6_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE6_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE6_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE6_A {
+        match self.bits {
+            0 => PRMODE6_A::P14B,
+            1 => PRMODE6_A::P12B,
+            2 => PRMODE6_A::P10B,
+            3 => PRMODE6_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE6_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE6_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE6_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE6_A::P8B
+    }
+}
+#[doc = "Field `PRMODE6` writer - Set the Precision Mode For Slot."]
+pub type PRMODE6_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL6CFG_SPEC, u8, PRMODE6_A, 2, O>;
+impl<'a, const O: u8> PRMODE6_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE6_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE6_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE6_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE6_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL6` reader - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL6_R = crate::FieldReader<u8, ADSEL6_A>;
+#[doc = "Select the number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL6_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL6_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL6_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL6_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL6_A {
+        match self.bits {
+            0 => ADSEL6_A::AVG_1_MSRMT,
+            1 => ADSEL6_A::AVG_2_MSRMTS,
+            2 => ADSEL6_A::AVG_4_MSRMTS,
+            3 => ADSEL6_A::AVG_8_MSRMT,
+            4 => ADSEL6_A::AVG_16_MSRMTS,
+            5 => ADSEL6_A::AVG_32_MSRMTS,
+            6 => ADSEL6_A::AVG_64_MSRMTS,
+            7 => ADSEL6_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL6_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL6_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL6_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL6_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL6_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL6_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL6_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL6_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL6` writer - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL6_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL6CFG_SPEC, u8, ADSEL6_A, 3, O>;
+impl<'a, const O: u8> ADSEL6_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL6_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 6 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen6(&self) -> SLEN6_R {
+        SLEN6_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 6."]
+    #[inline(always)]
+    pub fn wcen6(&self) -> WCEN6_R {
+        WCEN6_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel6(&self) -> CHSEL6_R {
+        CHSEL6_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode6(&self) -> PRMODE6_R {
+        PRMODE6_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel6(&self) -> ADSEL6_R {
+        ADSEL6_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 6 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen6(&mut self) -> SLEN6_W<0> {
+        SLEN6_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 6."]
+    #[inline(always)]
+    pub fn wcen6(&mut self) -> WCEN6_W<1> {
+        WCEN6_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel6(&mut self) -> CHSEL6_W<8> {
+        CHSEL6_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode6(&mut self) -> PRMODE6_W<16> {
+        PRMODE6_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel6(&mut self) -> ADSEL6_W<24> {
+        ADSEL6_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 6 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl6cfg](index.html) module"]
+pub struct SL6CFG_SPEC;
+impl crate::RegisterSpec for SL6CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl6cfg::R](R) reader structure"]
+impl crate::Readable for SL6CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl6cfg::W](W) writer structure"]
+impl crate::Writable for SL6CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL6CFG to value 0"]
+impl crate::Resettable for SL6CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/sl7cfg.rs

@@ -0,0 +1,623 @@
+#[doc = "Register `SL7CFG` reader"]
+pub struct R(crate::R<SL7CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SL7CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SL7CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SL7CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SL7CFG` writer"]
+pub struct W(crate::W<SL7CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SL7CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SL7CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SL7CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SLEN7` reader - This bit enables slot 7 for ADC conversions."]
+pub type SLEN7_R = crate::BitReader<SLEN7_A>;
+#[doc = "This bit enables slot 7 for ADC conversions.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLEN7_A {
+    #[doc = "1: Enable slot 7 for ADC conversions. value."]
+    SLEN = 1,
+}
+impl From<SLEN7_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLEN7_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SLEN7_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SLEN7_A> {
+        match self.bits {
+            true => Some(SLEN7_A::SLEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SLEN`"]
+    #[inline(always)]
+    pub fn is_slen(&self) -> bool {
+        *self == SLEN7_A::SLEN
+    }
+}
+#[doc = "Field `SLEN7` writer - This bit enables slot 7 for ADC conversions."]
+pub type SLEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL7CFG_SPEC, SLEN7_A, O>;
+impl<'a, const O: u8> SLEN7_W<'a, O> {
+    #[doc = "Enable slot 7 for ADC conversions. value."]
+    #[inline(always)]
+    pub fn slen(self) -> &'a mut W {
+        self.variant(SLEN7_A::SLEN)
+    }
+}
+#[doc = "Field `WCEN7` reader - This bit enables the window compare function for slot 7."]
+pub type WCEN7_R = crate::BitReader<WCEN7_A>;
+#[doc = "This bit enables the window compare function for slot 7.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WCEN7_A {
+    #[doc = "1: Enable the window compare for slot 7. value."]
+    WCEN = 1,
+}
+impl From<WCEN7_A> for bool {
+    #[inline(always)]
+    fn from(variant: WCEN7_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WCEN7_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WCEN7_A> {
+        match self.bits {
+            true => Some(WCEN7_A::WCEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WCEN`"]
+    #[inline(always)]
+    pub fn is_wcen(&self) -> bool {
+        *self == WCEN7_A::WCEN
+    }
+}
+#[doc = "Field `WCEN7` writer - This bit enables the window compare function for slot 7."]
+pub type WCEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, SL7CFG_SPEC, WCEN7_A, O>;
+impl<'a, const O: u8> WCEN7_W<'a, O> {
+    #[doc = "Enable the window compare for slot 7. value."]
+    #[inline(always)]
+    pub fn wcen(self) -> &'a mut W {
+        self.variant(WCEN7_A::WCEN)
+    }
+}
+#[doc = "Field `CHSEL7` reader - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL7_R = crate::FieldReader<u8, CHSEL7_A>;
+#[doc = "Select one of the 14 channel inputs for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHSEL7_A {
+    #[doc = "0: single ended external GPIO connection to pad16. value."]
+    SE0 = 0,
+    #[doc = "1: single ended external GPIO connection to pad29. value."]
+    SE1 = 1,
+    #[doc = "2: single ended external GPIO connection to pad11. value."]
+    SE2 = 2,
+    #[doc = "3: single ended external GPIO connection to pad31. value."]
+    SE3 = 3,
+    #[doc = "4: single ended external GPIO connection to pad32. value."]
+    SE4 = 4,
+    #[doc = "5: single ended external GPIO connection to pad33. value."]
+    SE5 = 5,
+    #[doc = "6: single ended external GPIO connection to pad34. value."]
+    SE6 = 6,
+    #[doc = "7: single ended external GPIO connection to pad35. value."]
+    SE7 = 7,
+    #[doc = "8: single ended external GPIO connection to pad13. value."]
+    SE8 = 8,
+    #[doc = "9: single ended external GPIO connection to pad12. value."]
+    SE9 = 9,
+    #[doc = "10: differential external GPIO connections to pad12(N) and pad13(P). value."]
+    DF0 = 10,
+    #[doc = "11: differential external GPIO connections to pad15(N) and pad14(P). value."]
+    DF1 = 11,
+    #[doc = "12: internal temperature sensor. value."]
+    TEMP = 12,
+    #[doc = "13: internal voltage divide-by-3 connection. value."]
+    BATT = 13,
+    #[doc = "14: Input VSS value."]
+    VSS = 14,
+}
+impl From<CHSEL7_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHSEL7_A) -> Self {
+        variant as _
+    }
+}
+impl CHSEL7_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHSEL7_A> {
+        match self.bits {
+            0 => Some(CHSEL7_A::SE0),
+            1 => Some(CHSEL7_A::SE1),
+            2 => Some(CHSEL7_A::SE2),
+            3 => Some(CHSEL7_A::SE3),
+            4 => Some(CHSEL7_A::SE4),
+            5 => Some(CHSEL7_A::SE5),
+            6 => Some(CHSEL7_A::SE6),
+            7 => Some(CHSEL7_A::SE7),
+            8 => Some(CHSEL7_A::SE8),
+            9 => Some(CHSEL7_A::SE9),
+            10 => Some(CHSEL7_A::DF0),
+            11 => Some(CHSEL7_A::DF1),
+            12 => Some(CHSEL7_A::TEMP),
+            13 => Some(CHSEL7_A::BATT),
+            14 => Some(CHSEL7_A::VSS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SE0`"]
+    #[inline(always)]
+    pub fn is_se0(&self) -> bool {
+        *self == CHSEL7_A::SE0
+    }
+    #[doc = "Checks if the value of the field is `SE1`"]
+    #[inline(always)]
+    pub fn is_se1(&self) -> bool {
+        *self == CHSEL7_A::SE1
+    }
+    #[doc = "Checks if the value of the field is `SE2`"]
+    #[inline(always)]
+    pub fn is_se2(&self) -> bool {
+        *self == CHSEL7_A::SE2
+    }
+    #[doc = "Checks if the value of the field is `SE3`"]
+    #[inline(always)]
+    pub fn is_se3(&self) -> bool {
+        *self == CHSEL7_A::SE3
+    }
+    #[doc = "Checks if the value of the field is `SE4`"]
+    #[inline(always)]
+    pub fn is_se4(&self) -> bool {
+        *self == CHSEL7_A::SE4
+    }
+    #[doc = "Checks if the value of the field is `SE5`"]
+    #[inline(always)]
+    pub fn is_se5(&self) -> bool {
+        *self == CHSEL7_A::SE5
+    }
+    #[doc = "Checks if the value of the field is `SE6`"]
+    #[inline(always)]
+    pub fn is_se6(&self) -> bool {
+        *self == CHSEL7_A::SE6
+    }
+    #[doc = "Checks if the value of the field is `SE7`"]
+    #[inline(always)]
+    pub fn is_se7(&self) -> bool {
+        *self == CHSEL7_A::SE7
+    }
+    #[doc = "Checks if the value of the field is `SE8`"]
+    #[inline(always)]
+    pub fn is_se8(&self) -> bool {
+        *self == CHSEL7_A::SE8
+    }
+    #[doc = "Checks if the value of the field is `SE9`"]
+    #[inline(always)]
+    pub fn is_se9(&self) -> bool {
+        *self == CHSEL7_A::SE9
+    }
+    #[doc = "Checks if the value of the field is `DF0`"]
+    #[inline(always)]
+    pub fn is_df0(&self) -> bool {
+        *self == CHSEL7_A::DF0
+    }
+    #[doc = "Checks if the value of the field is `DF1`"]
+    #[inline(always)]
+    pub fn is_df1(&self) -> bool {
+        *self == CHSEL7_A::DF1
+    }
+    #[doc = "Checks if the value of the field is `TEMP`"]
+    #[inline(always)]
+    pub fn is_temp(&self) -> bool {
+        *self == CHSEL7_A::TEMP
+    }
+    #[doc = "Checks if the value of the field is `BATT`"]
+    #[inline(always)]
+    pub fn is_batt(&self) -> bool {
+        *self == CHSEL7_A::BATT
+    }
+    #[doc = "Checks if the value of the field is `VSS`"]
+    #[inline(always)]
+    pub fn is_vss(&self) -> bool {
+        *self == CHSEL7_A::VSS
+    }
+}
+#[doc = "Field `CHSEL7` writer - Select one of the 14 channel inputs for this slot."]
+pub type CHSEL7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SL7CFG_SPEC, u8, CHSEL7_A, 4, O>;
+impl<'a, const O: u8> CHSEL7_W<'a, O> {
+    #[doc = "single ended external GPIO connection to pad16. value."]
+    #[inline(always)]
+    pub fn se0(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE0)
+    }
+    #[doc = "single ended external GPIO connection to pad29. value."]
+    #[inline(always)]
+    pub fn se1(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE1)
+    }
+    #[doc = "single ended external GPIO connection to pad11. value."]
+    #[inline(always)]
+    pub fn se2(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE2)
+    }
+    #[doc = "single ended external GPIO connection to pad31. value."]
+    #[inline(always)]
+    pub fn se3(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE3)
+    }
+    #[doc = "single ended external GPIO connection to pad32. value."]
+    #[inline(always)]
+    pub fn se4(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE4)
+    }
+    #[doc = "single ended external GPIO connection to pad33. value."]
+    #[inline(always)]
+    pub fn se5(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE5)
+    }
+    #[doc = "single ended external GPIO connection to pad34. value."]
+    #[inline(always)]
+    pub fn se6(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE6)
+    }
+    #[doc = "single ended external GPIO connection to pad35. value."]
+    #[inline(always)]
+    pub fn se7(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE7)
+    }
+    #[doc = "single ended external GPIO connection to pad13. value."]
+    #[inline(always)]
+    pub fn se8(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE8)
+    }
+    #[doc = "single ended external GPIO connection to pad12. value."]
+    #[inline(always)]
+    pub fn se9(self) -> &'a mut W {
+        self.variant(CHSEL7_A::SE9)
+    }
+    #[doc = "differential external GPIO connections to pad12(N) and pad13(P). value."]
+    #[inline(always)]
+    pub fn df0(self) -> &'a mut W {
+        self.variant(CHSEL7_A::DF0)
+    }
+    #[doc = "differential external GPIO connections to pad15(N) and pad14(P). value."]
+    #[inline(always)]
+    pub fn df1(self) -> &'a mut W {
+        self.variant(CHSEL7_A::DF1)
+    }
+    #[doc = "internal temperature sensor. value."]
+    #[inline(always)]
+    pub fn temp(self) -> &'a mut W {
+        self.variant(CHSEL7_A::TEMP)
+    }
+    #[doc = "internal voltage divide-by-3 connection. value."]
+    #[inline(always)]
+    pub fn batt(self) -> &'a mut W {
+        self.variant(CHSEL7_A::BATT)
+    }
+    #[doc = "Input VSS value."]
+    #[inline(always)]
+    pub fn vss(self) -> &'a mut W {
+        self.variant(CHSEL7_A::VSS)
+    }
+}
+#[doc = "Field `PRMODE7` reader - Set the Precision Mode For Slot."]
+pub type PRMODE7_R = crate::FieldReader<u8, PRMODE7_A>;
+#[doc = "Set the Precision Mode For Slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRMODE7_A {
+    #[doc = "0: 14-bit precision mode value."]
+    P14B = 0,
+    #[doc = "1: 12-bit precision mode value."]
+    P12B = 1,
+    #[doc = "2: 10-bit precision mode value."]
+    P10B = 2,
+    #[doc = "3: 8-bit precision mode value."]
+    P8B = 3,
+}
+impl From<PRMODE7_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRMODE7_A) -> Self {
+        variant as _
+    }
+}
+impl PRMODE7_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRMODE7_A {
+        match self.bits {
+            0 => PRMODE7_A::P14B,
+            1 => PRMODE7_A::P12B,
+            2 => PRMODE7_A::P10B,
+            3 => PRMODE7_A::P8B,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `P14B`"]
+    #[inline(always)]
+    pub fn is_p14b(&self) -> bool {
+        *self == PRMODE7_A::P14B
+    }
+    #[doc = "Checks if the value of the field is `P12B`"]
+    #[inline(always)]
+    pub fn is_p12b(&self) -> bool {
+        *self == PRMODE7_A::P12B
+    }
+    #[doc = "Checks if the value of the field is `P10B`"]
+    #[inline(always)]
+    pub fn is_p10b(&self) -> bool {
+        *self == PRMODE7_A::P10B
+    }
+    #[doc = "Checks if the value of the field is `P8B`"]
+    #[inline(always)]
+    pub fn is_p8b(&self) -> bool {
+        *self == PRMODE7_A::P8B
+    }
+}
+#[doc = "Field `PRMODE7` writer - Set the Precision Mode For Slot."]
+pub type PRMODE7_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL7CFG_SPEC, u8, PRMODE7_A, 2, O>;
+impl<'a, const O: u8> PRMODE7_W<'a, O> {
+    #[doc = "14-bit precision mode value."]
+    #[inline(always)]
+    pub fn p14b(self) -> &'a mut W {
+        self.variant(PRMODE7_A::P14B)
+    }
+    #[doc = "12-bit precision mode value."]
+    #[inline(always)]
+    pub fn p12b(self) -> &'a mut W {
+        self.variant(PRMODE7_A::P12B)
+    }
+    #[doc = "10-bit precision mode value."]
+    #[inline(always)]
+    pub fn p10b(self) -> &'a mut W {
+        self.variant(PRMODE7_A::P10B)
+    }
+    #[doc = "8-bit precision mode value."]
+    #[inline(always)]
+    pub fn p8b(self) -> &'a mut W {
+        self.variant(PRMODE7_A::P8B)
+    }
+}
+#[doc = "Field `ADSEL7` reader - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL7_R = crate::FieldReader<u8, ADSEL7_A>;
+#[doc = "Select the number of measurements to average in the accumulate divide module for this slot.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ADSEL7_A {
+    #[doc = "0: Average in 1 measurement in the accumulate divide module for this slot. value."]
+    AVG_1_MSRMT = 0,
+    #[doc = "1: Average in 2 measurements in the accumulate divide module for this slot. value."]
+    AVG_2_MSRMTS = 1,
+    #[doc = "2: Average in 4 measurements in the accumulate divide module for this slot. value."]
+    AVG_4_MSRMTS = 2,
+    #[doc = "3: Average in 8 measurements in the accumulate divide module for this slot. value."]
+    AVG_8_MSRMT = 3,
+    #[doc = "4: Average in 16 measurements in the accumulate divide module for this slot. value."]
+    AVG_16_MSRMTS = 4,
+    #[doc = "5: Average in 32 measurements in the accumulate divide module for this slot. value."]
+    AVG_32_MSRMTS = 5,
+    #[doc = "6: Average in 64 measurements in the accumulate divide module for this slot. value."]
+    AVG_64_MSRMTS = 6,
+    #[doc = "7: Average in 128 measurements in the accumulate divide module for this slot. value."]
+    AVG_128_MSRMTS = 7,
+}
+impl From<ADSEL7_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ADSEL7_A) -> Self {
+        variant as _
+    }
+}
+impl ADSEL7_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADSEL7_A {
+        match self.bits {
+            0 => ADSEL7_A::AVG_1_MSRMT,
+            1 => ADSEL7_A::AVG_2_MSRMTS,
+            2 => ADSEL7_A::AVG_4_MSRMTS,
+            3 => ADSEL7_A::AVG_8_MSRMT,
+            4 => ADSEL7_A::AVG_16_MSRMTS,
+            5 => ADSEL7_A::AVG_32_MSRMTS,
+            6 => ADSEL7_A::AVG_64_MSRMTS,
+            7 => ADSEL7_A::AVG_128_MSRMTS,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `AVG_1_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_1_msrmt(&self) -> bool {
+        *self == ADSEL7_A::AVG_1_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_2_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_2_msrmts(&self) -> bool {
+        *self == ADSEL7_A::AVG_2_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_4_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_4_msrmts(&self) -> bool {
+        *self == ADSEL7_A::AVG_4_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_8_MSRMT`"]
+    #[inline(always)]
+    pub fn is_avg_8_msrmt(&self) -> bool {
+        *self == ADSEL7_A::AVG_8_MSRMT
+    }
+    #[doc = "Checks if the value of the field is `AVG_16_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_16_msrmts(&self) -> bool {
+        *self == ADSEL7_A::AVG_16_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_32_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_32_msrmts(&self) -> bool {
+        *self == ADSEL7_A::AVG_32_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_64_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_64_msrmts(&self) -> bool {
+        *self == ADSEL7_A::AVG_64_MSRMTS
+    }
+    #[doc = "Checks if the value of the field is `AVG_128_MSRMTS`"]
+    #[inline(always)]
+    pub fn is_avg_128_msrmts(&self) -> bool {
+        *self == ADSEL7_A::AVG_128_MSRMTS
+    }
+}
+#[doc = "Field `ADSEL7` writer - Select the number of measurements to average in the accumulate divide module for this slot."]
+pub type ADSEL7_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, SL7CFG_SPEC, u8, ADSEL7_A, 3, O>;
+impl<'a, const O: u8> ADSEL7_W<'a, O> {
+    #[doc = "Average in 1 measurement in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_1_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_1_MSRMT)
+    }
+    #[doc = "Average in 2 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_2_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_2_MSRMTS)
+    }
+    #[doc = "Average in 4 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_4_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_4_MSRMTS)
+    }
+    #[doc = "Average in 8 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_8_msrmt(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_8_MSRMT)
+    }
+    #[doc = "Average in 16 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_16_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_16_MSRMTS)
+    }
+    #[doc = "Average in 32 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_32_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_32_MSRMTS)
+    }
+    #[doc = "Average in 64 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_64_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_64_MSRMTS)
+    }
+    #[doc = "Average in 128 measurements in the accumulate divide module for this slot. value."]
+    #[inline(always)]
+    pub fn avg_128_msrmts(self) -> &'a mut W {
+        self.variant(ADSEL7_A::AVG_128_MSRMTS)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This bit enables slot 7 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen7(&self) -> SLEN7_R {
+        SLEN7_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 7."]
+    #[inline(always)]
+    pub fn wcen7(&self) -> WCEN7_R {
+        WCEN7_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel7(&self) -> CHSEL7_R {
+        CHSEL7_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode7(&self) -> PRMODE7_R {
+        PRMODE7_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel7(&self) -> ADSEL7_R {
+        ADSEL7_R::new(((self.bits >> 24) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit enables slot 7 for ADC conversions."]
+    #[inline(always)]
+    pub fn slen7(&mut self) -> SLEN7_W<0> {
+        SLEN7_W::new(self)
+    }
+    #[doc = "Bit 1 - This bit enables the window compare function for slot 7."]
+    #[inline(always)]
+    pub fn wcen7(&mut self) -> WCEN7_W<1> {
+        WCEN7_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Select one of the 14 channel inputs for this slot."]
+    #[inline(always)]
+    pub fn chsel7(&mut self) -> CHSEL7_W<8> {
+        CHSEL7_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Set the Precision Mode For Slot."]
+    #[inline(always)]
+    pub fn prmode7(&mut self) -> PRMODE7_W<16> {
+        PRMODE7_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot."]
+    #[inline(always)]
+    pub fn adsel7(&mut self) -> ADSEL7_W<24> {
+        ADSEL7_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slot 7 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sl7cfg](index.html) module"]
+pub struct SL7CFG_SPEC;
+impl crate::RegisterSpec for SL7CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sl7cfg::R](R) reader structure"]
+impl crate::Readable for SL7CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sl7cfg::W](W) writer structure"]
+impl crate::Writable for SL7CFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SL7CFG to value 0"]
+impl crate::Resettable for SL7CFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/stat.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `STAT` reader"]
+pub struct R(crate::R<STAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `STAT` writer"]
+pub struct W(crate::W<STAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<STAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<STAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<STAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PWDSTAT` reader - Indicates the power-status of the ADC."]
+pub type PWDSTAT_R = crate::BitReader<PWDSTAT_A>;
+#[doc = "Indicates the power-status of the ADC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PWDSTAT_A {
+    #[doc = "0: Powered on. value."]
+    ON = 0,
+    #[doc = "1: ADC Low Power Mode 1. value."]
+    POWERED_DOWN = 1,
+}
+impl From<PWDSTAT_A> for bool {
+    #[inline(always)]
+    fn from(variant: PWDSTAT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PWDSTAT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PWDSTAT_A {
+        match self.bits {
+            false => PWDSTAT_A::ON,
+            true => PWDSTAT_A::POWERED_DOWN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ON`"]
+    #[inline(always)]
+    pub fn is_on(&self) -> bool {
+        *self == PWDSTAT_A::ON
+    }
+    #[doc = "Checks if the value of the field is `POWERED_DOWN`"]
+    #[inline(always)]
+    pub fn is_powered_down(&self) -> bool {
+        *self == PWDSTAT_A::POWERED_DOWN
+    }
+}
+#[doc = "Field `PWDSTAT` writer - Indicates the power-status of the ADC."]
+pub type PWDSTAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, PWDSTAT_A, O>;
+impl<'a, const O: u8> PWDSTAT_W<'a, O> {
+    #[doc = "Powered on. value."]
+    #[inline(always)]
+    pub fn on(self) -> &'a mut W {
+        self.variant(PWDSTAT_A::ON)
+    }
+    #[doc = "ADC Low Power Mode 1. value."]
+    #[inline(always)]
+    pub fn powered_down(self) -> &'a mut W {
+        self.variant(PWDSTAT_A::POWERED_DOWN)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Indicates the power-status of the ADC."]
+    #[inline(always)]
+    pub fn pwdstat(&self) -> PWDSTAT_R {
+        PWDSTAT_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Indicates the power-status of the ADC."]
+    #[inline(always)]
+    pub fn pwdstat(&mut self) -> PWDSTAT_W<0> {
+        PWDSTAT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC Power Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"]
+pub struct STAT_SPEC;
+impl crate::RegisterSpec for STAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [stat::R](R) reader structure"]
+impl crate::Readable for STAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"]
+impl crate::Writable for STAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets STAT to value 0"]
+impl crate::Resettable for STAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/swt.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `SWT` reader"]
+pub struct R(crate::R<SWT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SWT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SWT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SWT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SWT` writer"]
+pub struct W(crate::W<SWT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SWT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SWT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SWT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SWT` reader - Writing 0x37 to this register generates a software trigger."]
+pub type SWT_R = crate::FieldReader<u8, SWT_A>;
+#[doc = "Writing 0x37 to this register generates a software trigger.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SWT_A {
+    #[doc = "55: Writing this value generates a software trigger. value."]
+    GEN_SW_TRIGGER = 55,
+}
+impl From<SWT_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SWT_A) -> Self {
+        variant as _
+    }
+}
+impl SWT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SWT_A> {
+        match self.bits {
+            55 => Some(SWT_A::GEN_SW_TRIGGER),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `GEN_SW_TRIGGER`"]
+    #[inline(always)]
+    pub fn is_gen_sw_trigger(&self) -> bool {
+        *self == SWT_A::GEN_SW_TRIGGER
+    }
+}
+#[doc = "Field `SWT` writer - Writing 0x37 to this register generates a software trigger."]
+pub type SWT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SWT_SPEC, u8, SWT_A, 8, O>;
+impl<'a, const O: u8> SWT_W<'a, O> {
+    #[doc = "Writing this value generates a software trigger. value."]
+    #[inline(always)]
+    pub fn gen_sw_trigger(self) -> &'a mut W {
+        self.variant(SWT_A::GEN_SW_TRIGGER)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Writing 0x37 to this register generates a software trigger."]
+    #[inline(always)]
+    pub fn swt(&self) -> SWT_R {
+        SWT_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Writing 0x37 to this register generates a software trigger."]
+    #[inline(always)]
+    pub fn swt(&mut self) -> SWT_W<0> {
+        SWT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Software trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swt](index.html) module"]
+pub struct SWT_SPEC;
+impl crate::RegisterSpec for SWT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [swt::R](R) reader structure"]
+impl crate::Readable for SWT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [swt::W](W) writer structure"]
+impl crate::Writable for SWT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SWT to value 0"]
+impl crate::Resettable for SWT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/wllim.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `WLLIM` reader"]
+pub struct R(crate::R<WLLIM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<WLLIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<WLLIM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<WLLIM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `WLLIM` writer"]
+pub struct W(crate::W<WLLIM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<WLLIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<WLLIM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<WLLIM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LLIM` reader - Sets the lower limit for the window comparator."]
+pub type LLIM_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `LLIM` writer - Sets the lower limit for the window comparator."]
+pub type LLIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WLLIM_SPEC, u32, u32, 20, O>;
+impl R {
+    #[doc = "Bits 0:19 - Sets the lower limit for the window comparator."]
+    #[inline(always)]
+    pub fn llim(&self) -> LLIM_R {
+        LLIM_R::new((self.bits & 0x000f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - Sets the lower limit for the window comparator."]
+    #[inline(always)]
+    pub fn llim(&mut self) -> LLIM_W<0> {
+        LLIM_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Window Comparator Lower Limits Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wllim](index.html) module"]
+pub struct WLLIM_SPEC;
+impl crate::RegisterSpec for WLLIM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [wllim::R](R) reader structure"]
+impl crate::Readable for WLLIM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [wllim::W](W) writer structure"]
+impl crate::Writable for WLLIM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets WLLIM to value 0"]
+impl crate::Resettable for WLLIM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/adc/wulim.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `WULIM` reader"]
+pub struct R(crate::R<WULIM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<WULIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<WULIM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<WULIM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `WULIM` writer"]
+pub struct W(crate::W<WULIM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<WULIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<WULIM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<WULIM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ULIM` reader - Sets the upper limit for the window comparator."]
+pub type ULIM_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ULIM` writer - Sets the upper limit for the window comparator."]
+pub type ULIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WULIM_SPEC, u32, u32, 20, O>;
+impl R {
+    #[doc = "Bits 0:19 - Sets the upper limit for the window comparator."]
+    #[inline(always)]
+    pub fn ulim(&self) -> ULIM_R {
+        ULIM_R::new((self.bits & 0x000f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - Sets the upper limit for the window comparator."]
+    #[inline(always)]
+    pub fn ulim(&mut self) -> ULIM_W<0> {
+        ULIM_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Window Comparator Upper Limits Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wulim](index.html) module"]
+pub struct WULIM_SPEC;
+impl crate::RegisterSpec for WULIM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [wulim::R](R) reader structure"]
+impl crate::Readable for WULIM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [wulim::W](W) writer structure"]
+impl crate::Writable for WULIM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets WULIM to value 0"]
+impl crate::Resettable for WULIM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/apbdma.rs

@@ -0,0 +1,36 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Control Register"]
+    pub bbvalue: BBVALUE,
+    #[doc = "0x04 - Set/Clear Register"]
+    pub bbsetclear: BBSETCLEAR,
+    #[doc = "0x08 - PIO Input Values"]
+    pub bbinput: BBINPUT,
+    _reserved3: [u8; 0x14],
+    #[doc = "0x20 - PIO Input Values"]
+    pub debugdata: DEBUGDATA,
+    _reserved4: [u8; 0x1c],
+    #[doc = "0x40 - PIO Input Values"]
+    pub debug: DEBUG,
+}
+#[doc = "BBVALUE (rw) register accessor: an alias for `Reg<BBVALUE_SPEC>`"]
+pub type BBVALUE = crate::Reg<bbvalue::BBVALUE_SPEC>;
+#[doc = "Control Register"]
+pub mod bbvalue;
+#[doc = "BBSETCLEAR (rw) register accessor: an alias for `Reg<BBSETCLEAR_SPEC>`"]
+pub type BBSETCLEAR = crate::Reg<bbsetclear::BBSETCLEAR_SPEC>;
+#[doc = "Set/Clear Register"]
+pub mod bbsetclear;
+#[doc = "BBINPUT (rw) register accessor: an alias for `Reg<BBINPUT_SPEC>`"]
+pub type BBINPUT = crate::Reg<bbinput::BBINPUT_SPEC>;
+#[doc = "PIO Input Values"]
+pub mod bbinput;
+#[doc = "DEBUGDATA (rw) register accessor: an alias for `Reg<DEBUGDATA_SPEC>`"]
+pub type DEBUGDATA = crate::Reg<debugdata::DEBUGDATA_SPEC>;
+#[doc = "PIO Input Values"]
+pub mod debugdata;
+#[doc = "DEBUG (rw) register accessor: an alias for `Reg<DEBUG_SPEC>`"]
+pub type DEBUG = crate::Reg<debug::DEBUG_SPEC>;
+#[doc = "PIO Input Values"]
+pub mod debug;

apollo3-pac/src/apbdma/bbinput.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `BBINPUT` reader"]
+pub struct R(crate::R<BBINPUT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BBINPUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BBINPUT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BBINPUT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `BBINPUT` writer"]
+pub struct W(crate::W<BBINPUT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<BBINPUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<BBINPUT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<BBINPUT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DATAIN` reader - PIO values"]
+pub type DATAIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `DATAIN` writer - PIO values"]
+pub type DATAIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BBINPUT_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - PIO values"]
+    #[inline(always)]
+    pub fn datain(&self) -> DATAIN_R {
+        DATAIN_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - PIO values"]
+    #[inline(always)]
+    pub fn datain(&mut self) -> DATAIN_W<0> {
+        DATAIN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PIO Input Values\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bbinput](index.html) module"]
+pub struct BBINPUT_SPEC;
+impl crate::RegisterSpec for BBINPUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [bbinput::R](R) reader structure"]
+impl crate::Readable for BBINPUT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [bbinput::W](W) writer structure"]
+impl crate::Writable for BBINPUT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets BBINPUT to value 0"]
+impl crate::Resettable for BBINPUT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/apbdma/bbsetclear.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `BBSETCLEAR` reader"]
+pub struct R(crate::R<BBSETCLEAR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BBSETCLEAR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BBSETCLEAR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BBSETCLEAR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `BBSETCLEAR` writer"]
+pub struct W(crate::W<BBSETCLEAR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<BBSETCLEAR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<BBSETCLEAR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<BBSETCLEAR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SET` reader - Write 1 to Set PIO value (set hier priority than clear if both bit set)"]
+pub type SET_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `SET` writer - Write 1 to Set PIO value (set hier priority than clear if both bit set)"]
+pub type SET_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BBSETCLEAR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `CLEAR` reader - Write 1 to Clear PIO value"]
+pub type CLEAR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CLEAR` writer - Write 1 to Clear PIO value"]
+pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BBSETCLEAR_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Write 1 to Set PIO value (set hier priority than clear if both bit set)"]
+    #[inline(always)]
+    pub fn set(&self) -> SET_R {
+        SET_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - Write 1 to Clear PIO value"]
+    #[inline(always)]
+    pub fn clear(&self) -> CLEAR_R {
+        CLEAR_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Write 1 to Set PIO value (set hier priority than clear if both bit set)"]
+    #[inline(always)]
+    pub fn set(&mut self) -> SET_W<0> {
+        SET_W::new(self)
+    }
+    #[doc = "Bits 16:23 - Write 1 to Clear PIO value"]
+    #[inline(always)]
+    pub fn clear(&mut self) -> CLEAR_W<16> {
+        CLEAR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Set/Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bbsetclear](index.html) module"]
+pub struct BBSETCLEAR_SPEC;
+impl crate::RegisterSpec for BBSETCLEAR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [bbsetclear::R](R) reader structure"]
+impl crate::Readable for BBSETCLEAR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [bbsetclear::W](W) writer structure"]
+impl crate::Writable for BBSETCLEAR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets BBSETCLEAR to value 0"]
+impl crate::Resettable for BBSETCLEAR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/apbdma/bbvalue.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `BBVALUE` reader"]
+pub struct R(crate::R<BBVALUE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BBVALUE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BBVALUE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BBVALUE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `BBVALUE` writer"]
+pub struct W(crate::W<BBVALUE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<BBVALUE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<BBVALUE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<BBVALUE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DATAOUT` reader - Data Output Values"]
+pub type DATAOUT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `DATAOUT` writer - Data Output Values"]
+pub type DATAOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BBVALUE_SPEC, u8, u8, 8, O>;
+#[doc = "Field `PIN` reader - PIO values"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - PIO values"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BBVALUE_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Data Output Values"]
+    #[inline(always)]
+    pub fn dataout(&self) -> DATAOUT_R {
+        DATAOUT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - PIO values"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Output Values"]
+    #[inline(always)]
+    pub fn dataout(&mut self) -> DATAOUT_W<0> {
+        DATAOUT_W::new(self)
+    }
+    #[doc = "Bits 16:23 - PIO values"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<16> {
+        PIN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bbvalue](index.html) module"]
+pub struct BBVALUE_SPEC;
+impl crate::RegisterSpec for BBVALUE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [bbvalue::R](R) reader structure"]
+impl crate::Readable for BBVALUE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [bbvalue::W](W) writer structure"]
+impl crate::Writable for BBVALUE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets BBVALUE to value 0"]
+impl crate::Resettable for BBVALUE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/apbdma/debug.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `DEBUG` reader"]
+pub struct R(crate::R<DEBUG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DEBUG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DEBUG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DEBUG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DEBUG` writer"]
+pub struct W(crate::W<DEBUG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DEBUG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DEBUG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DEBUG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DEBUGEN` reader - Debug Enable"]
+pub type DEBUGEN_R = crate::FieldReader<u8, DEBUGEN_A>;
+#[doc = "Debug Enable\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum DEBUGEN_A {
+    #[doc = "0: Debug Disabled value."]
+    OFF = 0,
+    #[doc = "1: Debug Arb values value."]
+    ARB = 1,
+}
+impl From<DEBUGEN_A> for u8 {
+    #[inline(always)]
+    fn from(variant: DEBUGEN_A) -> Self {
+        variant as _
+    }
+}
+impl DEBUGEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DEBUGEN_A> {
+        match self.bits {
+            0 => Some(DEBUGEN_A::OFF),
+            1 => Some(DEBUGEN_A::ARB),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == DEBUGEN_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `ARB`"]
+    #[inline(always)]
+    pub fn is_arb(&self) -> bool {
+        *self == DEBUGEN_A::ARB
+    }
+}
+#[doc = "Field `DEBUGEN` writer - Debug Enable"]
+pub type DEBUGEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEBUG_SPEC, u8, DEBUGEN_A, 4, O>;
+impl<'a, const O: u8> DEBUGEN_W<'a, O> {
+    #[doc = "Debug Disabled value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(DEBUGEN_A::OFF)
+    }
+    #[doc = "Debug Arb values value."]
+    #[inline(always)]
+    pub fn arb(self) -> &'a mut W {
+        self.variant(DEBUGEN_A::ARB)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Debug Enable"]
+    #[inline(always)]
+    pub fn debugen(&self) -> DEBUGEN_R {
+        DEBUGEN_R::new((self.bits & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Debug Enable"]
+    #[inline(always)]
+    pub fn debugen(&mut self) -> DEBUGEN_W<0> {
+        DEBUGEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PIO Input Values\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debug](index.html) module"]
+pub struct DEBUG_SPEC;
+impl crate::RegisterSpec for DEBUG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [debug::R](R) reader structure"]
+impl crate::Readable for DEBUG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [debug::W](W) writer structure"]
+impl crate::Writable for DEBUG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DEBUG to value 0"]
+impl crate::Resettable for DEBUG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/apbdma/debugdata.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `DEBUGDATA` reader"]
+pub struct R(crate::R<DEBUGDATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DEBUGDATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DEBUGDATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DEBUGDATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DEBUGDATA` writer"]
+pub struct W(crate::W<DEBUGDATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DEBUGDATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DEBUGDATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DEBUGDATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DEBUGDATA` reader - Debug Data"]
+pub type DEBUGDATA_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DEBUGDATA` writer - Debug Data"]
+pub type DEBUGDATA_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DEBUGDATA_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Debug Data"]
+    #[inline(always)]
+    pub fn debugdata(&self) -> DEBUGDATA_R {
+        DEBUGDATA_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Debug Data"]
+    #[inline(always)]
+    pub fn debugdata(&mut self) -> DEBUGDATA_W<0> {
+        DEBUGDATA_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PIO Input Values\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debugdata](index.html) module"]
+pub struct DEBUGDATA_SPEC;
+impl crate::RegisterSpec for DEBUGDATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [debugdata::R](R) reader structure"]
+impl crate::Readable for DEBUGDATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [debugdata::W](W) writer structure"]
+impl crate::Writable for DEBUGDATA_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DEBUGDATA to value 0"]
+impl crate::Resettable for DEBUGDATA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif.rs

@@ -0,0 +1,226 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - FIFO Access Port"]
+    pub fifo: FIFO,
+    _reserved1: [u8; 0xfc],
+    #[doc = "0x100 - FIFO size and remaining slots open values"]
+    pub fifoptr: FIFOPTR,
+    #[doc = "0x104 - FIFO Threshold Configuration"]
+    pub fifothr: FIFOTHR,
+    #[doc = "0x108 - FIFO POP register"]
+    pub fifopop: FIFOPOP,
+    #[doc = "0x10c - FIFO PUSH register"]
+    pub fifopush: FIFOPUSH,
+    #[doc = "0x110 - FIFO Control Register"]
+    pub fifoctrl: FIFOCTRL,
+    #[doc = "0x114 - FIFO Pointers"]
+    pub fifoloc: FIFOLOC,
+    _reserved7: [u8; 0xe8],
+    #[doc = "0x200 - I/O Clock Configuration"]
+    pub clkcfg: CLKCFG,
+    _reserved8: [u8; 0x08],
+    #[doc = "0x20c - Command and offset Register"]
+    pub cmd: CMD,
+    #[doc = "0x210 - Command Repeat Register"]
+    pub cmdrpt: CMDRPT,
+    #[doc = "0x214 - High order offset bytes"]
+    pub offsethi: OFFSETHI,
+    #[doc = "0x218 - Command status"]
+    pub cmdstat: CMDSTAT,
+    _reserved12: [u8; 0x04],
+    #[doc = "0x220 - IO Master Interrupts: Enable"]
+    pub inten: INTEN,
+    #[doc = "0x224 - IO Master Interrupts: Status"]
+    pub intstat: INTSTAT,
+    #[doc = "0x228 - IO Master Interrupts: Clear"]
+    pub intclr: INTCLR,
+    #[doc = "0x22c - IO Master Interrupts: Set"]
+    pub intset: INTSET,
+    #[doc = "0x230 - DMA Trigger Enable Register"]
+    pub dmatrigen: DMATRIGEN,
+    #[doc = "0x234 - DMA Trigger Status Register"]
+    pub dmatrigstat: DMATRIGSTAT,
+    #[doc = "0x238 - DMA Configuration Register"]
+    pub dmacfg: DMACFG,
+    #[doc = "0x23c - DMA Total Transfer Count"]
+    pub dmatotcount: DMATOTCOUNT,
+    #[doc = "0x240 - DMA Target Address Register"]
+    pub dmatargaddr: DMATARGADDR,
+    #[doc = "0x244 - DMA Status Register"]
+    pub dmastat: DMASTAT,
+    #[doc = "0x248 - Command Queue Configuration Register"]
+    pub cqcfg: CQCFG,
+    #[doc = "0x24c - CQ Target Read Address Register"]
+    pub cqaddr: CQADDR,
+    #[doc = "0x250 - Command Queue Status Register"]
+    pub cqstat: CQSTAT,
+    #[doc = "0x254 - Command Queue Flag Register"]
+    pub cqflags: CQFLAGS,
+    #[doc = "0x258 - Command Queue Flag Set/Clear Register"]
+    pub cqsetclear: CQSETCLEAR,
+    #[doc = "0x25c - Command Queue Pause Enable Register"]
+    pub cqpauseen: CQPAUSEEN,
+    #[doc = "0x260 - IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue"]
+    pub cqcuridx: CQCURIDX,
+    #[doc = "0x264 - IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue"]
+    pub cqendidx: CQENDIDX,
+    #[doc = "0x268 - IOM Module Status Register"]
+    pub status: STATUS,
+    _reserved31: [u8; 0x94],
+    #[doc = "0x300 - SPI module master configuration"]
+    pub mspicfg: MSPICFG,
+    #[doc = "0x304 - BLE Core Control"]
+    pub blecfg: BLECFG,
+    #[doc = "0x308 - BLE Power command interface"]
+    pub pwrcmd: PWRCMD,
+    #[doc = "0x30c - BLE Core status"]
+    pub bstatus: BSTATUS,
+    _reserved35: [u8; 0x0100],
+    #[doc = "0x410 - BLEIF Master Debug Register"]
+    pub bledbg: BLEDBG,
+}
+#[doc = "FIFO (rw) register accessor: an alias for `Reg<FIFO_SPEC>`"]
+pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
+#[doc = "FIFO Access Port"]
+pub mod fifo;
+#[doc = "FIFOPTR (rw) register accessor: an alias for `Reg<FIFOPTR_SPEC>`"]
+pub type FIFOPTR = crate::Reg<fifoptr::FIFOPTR_SPEC>;
+#[doc = "FIFO size and remaining slots open values"]
+pub mod fifoptr;
+#[doc = "FIFOTHR (rw) register accessor: an alias for `Reg<FIFOTHR_SPEC>`"]
+pub type FIFOTHR = crate::Reg<fifothr::FIFOTHR_SPEC>;
+#[doc = "FIFO Threshold Configuration"]
+pub mod fifothr;
+#[doc = "FIFOPOP (rw) register accessor: an alias for `Reg<FIFOPOP_SPEC>`"]
+pub type FIFOPOP = crate::Reg<fifopop::FIFOPOP_SPEC>;
+#[doc = "FIFO POP register"]
+pub mod fifopop;
+#[doc = "FIFOPUSH (rw) register accessor: an alias for `Reg<FIFOPUSH_SPEC>`"]
+pub type FIFOPUSH = crate::Reg<fifopush::FIFOPUSH_SPEC>;
+#[doc = "FIFO PUSH register"]
+pub mod fifopush;
+#[doc = "FIFOCTRL (rw) register accessor: an alias for `Reg<FIFOCTRL_SPEC>`"]
+pub type FIFOCTRL = crate::Reg<fifoctrl::FIFOCTRL_SPEC>;
+#[doc = "FIFO Control Register"]
+pub mod fifoctrl;
+#[doc = "FIFOLOC (rw) register accessor: an alias for `Reg<FIFOLOC_SPEC>`"]
+pub type FIFOLOC = crate::Reg<fifoloc::FIFOLOC_SPEC>;
+#[doc = "FIFO Pointers"]
+pub mod fifoloc;
+#[doc = "CLKCFG (rw) register accessor: an alias for `Reg<CLKCFG_SPEC>`"]
+pub type CLKCFG = crate::Reg<clkcfg::CLKCFG_SPEC>;
+#[doc = "I/O Clock Configuration"]
+pub mod clkcfg;
+#[doc = "CMD (rw) register accessor: an alias for `Reg<CMD_SPEC>`"]
+pub type CMD = crate::Reg<cmd::CMD_SPEC>;
+#[doc = "Command and offset Register"]
+pub mod cmd;
+#[doc = "CMDRPT (rw) register accessor: an alias for `Reg<CMDRPT_SPEC>`"]
+pub type CMDRPT = crate::Reg<cmdrpt::CMDRPT_SPEC>;
+#[doc = "Command Repeat Register"]
+pub mod cmdrpt;
+#[doc = "OFFSETHI (rw) register accessor: an alias for `Reg<OFFSETHI_SPEC>`"]
+pub type OFFSETHI = crate::Reg<offsethi::OFFSETHI_SPEC>;
+#[doc = "High order offset bytes"]
+pub mod offsethi;
+#[doc = "CMDSTAT (rw) register accessor: an alias for `Reg<CMDSTAT_SPEC>`"]
+pub type CMDSTAT = crate::Reg<cmdstat::CMDSTAT_SPEC>;
+#[doc = "Command status"]
+pub mod cmdstat;
+#[doc = "INTEN (rw) register accessor: an alias for `Reg<INTEN_SPEC>`"]
+pub type INTEN = crate::Reg<inten::INTEN_SPEC>;
+#[doc = "IO Master Interrupts: Enable"]
+pub mod inten;
+#[doc = "INTSTAT (rw) register accessor: an alias for `Reg<INTSTAT_SPEC>`"]
+pub type INTSTAT = crate::Reg<intstat::INTSTAT_SPEC>;
+#[doc = "IO Master Interrupts: Status"]
+pub mod intstat;
+#[doc = "INTCLR (rw) register accessor: an alias for `Reg<INTCLR_SPEC>`"]
+pub type INTCLR = crate::Reg<intclr::INTCLR_SPEC>;
+#[doc = "IO Master Interrupts: Clear"]
+pub mod intclr;
+#[doc = "INTSET (rw) register accessor: an alias for `Reg<INTSET_SPEC>`"]
+pub type INTSET = crate::Reg<intset::INTSET_SPEC>;
+#[doc = "IO Master Interrupts: Set"]
+pub mod intset;
+#[doc = "DMATRIGEN (rw) register accessor: an alias for `Reg<DMATRIGEN_SPEC>`"]
+pub type DMATRIGEN = crate::Reg<dmatrigen::DMATRIGEN_SPEC>;
+#[doc = "DMA Trigger Enable Register"]
+pub mod dmatrigen;
+#[doc = "DMATRIGSTAT (rw) register accessor: an alias for `Reg<DMATRIGSTAT_SPEC>`"]
+pub type DMATRIGSTAT = crate::Reg<dmatrigstat::DMATRIGSTAT_SPEC>;
+#[doc = "DMA Trigger Status Register"]
+pub mod dmatrigstat;
+#[doc = "DMACFG (rw) register accessor: an alias for `Reg<DMACFG_SPEC>`"]
+pub type DMACFG = crate::Reg<dmacfg::DMACFG_SPEC>;
+#[doc = "DMA Configuration Register"]
+pub mod dmacfg;
+#[doc = "DMATOTCOUNT (rw) register accessor: an alias for `Reg<DMATOTCOUNT_SPEC>`"]
+pub type DMATOTCOUNT = crate::Reg<dmatotcount::DMATOTCOUNT_SPEC>;
+#[doc = "DMA Total Transfer Count"]
+pub mod dmatotcount;
+#[doc = "DMATARGADDR (rw) register accessor: an alias for `Reg<DMATARGADDR_SPEC>`"]
+pub type DMATARGADDR = crate::Reg<dmatargaddr::DMATARGADDR_SPEC>;
+#[doc = "DMA Target Address Register"]
+pub mod dmatargaddr;
+#[doc = "DMASTAT (rw) register accessor: an alias for `Reg<DMASTAT_SPEC>`"]
+pub type DMASTAT = crate::Reg<dmastat::DMASTAT_SPEC>;
+#[doc = "DMA Status Register"]
+pub mod dmastat;
+#[doc = "CQCFG (rw) register accessor: an alias for `Reg<CQCFG_SPEC>`"]
+pub type CQCFG = crate::Reg<cqcfg::CQCFG_SPEC>;
+#[doc = "Command Queue Configuration Register"]
+pub mod cqcfg;
+#[doc = "CQADDR (rw) register accessor: an alias for `Reg<CQADDR_SPEC>`"]
+pub type CQADDR = crate::Reg<cqaddr::CQADDR_SPEC>;
+#[doc = "CQ Target Read Address Register"]
+pub mod cqaddr;
+#[doc = "CQSTAT (rw) register accessor: an alias for `Reg<CQSTAT_SPEC>`"]
+pub type CQSTAT = crate::Reg<cqstat::CQSTAT_SPEC>;
+#[doc = "Command Queue Status Register"]
+pub mod cqstat;
+#[doc = "CQFLAGS (rw) register accessor: an alias for `Reg<CQFLAGS_SPEC>`"]
+pub type CQFLAGS = crate::Reg<cqflags::CQFLAGS_SPEC>;
+#[doc = "Command Queue Flag Register"]
+pub mod cqflags;
+#[doc = "CQSETCLEAR (rw) register accessor: an alias for `Reg<CQSETCLEAR_SPEC>`"]
+pub type CQSETCLEAR = crate::Reg<cqsetclear::CQSETCLEAR_SPEC>;
+#[doc = "Command Queue Flag Set/Clear Register"]
+pub mod cqsetclear;
+#[doc = "CQPAUSEEN (rw) register accessor: an alias for `Reg<CQPAUSEEN_SPEC>`"]
+pub type CQPAUSEEN = crate::Reg<cqpauseen::CQPAUSEEN_SPEC>;
+#[doc = "Command Queue Pause Enable Register"]
+pub mod cqpauseen;
+#[doc = "CQCURIDX (rw) register accessor: an alias for `Reg<CQCURIDX_SPEC>`"]
+pub type CQCURIDX = crate::Reg<cqcuridx::CQCURIDX_SPEC>;
+#[doc = "IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue"]
+pub mod cqcuridx;
+#[doc = "CQENDIDX (rw) register accessor: an alias for `Reg<CQENDIDX_SPEC>`"]
+pub type CQENDIDX = crate::Reg<cqendidx::CQENDIDX_SPEC>;
+#[doc = "IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue"]
+pub mod cqendidx;
+#[doc = "STATUS (rw) register accessor: an alias for `Reg<STATUS_SPEC>`"]
+pub type STATUS = crate::Reg<status::STATUS_SPEC>;
+#[doc = "IOM Module Status Register"]
+pub mod status;
+#[doc = "MSPICFG (rw) register accessor: an alias for `Reg<MSPICFG_SPEC>`"]
+pub type MSPICFG = crate::Reg<mspicfg::MSPICFG_SPEC>;
+#[doc = "SPI module master configuration"]
+pub mod mspicfg;
+#[doc = "BLECFG (rw) register accessor: an alias for `Reg<BLECFG_SPEC>`"]
+pub type BLECFG = crate::Reg<blecfg::BLECFG_SPEC>;
+#[doc = "BLE Core Control"]
+pub mod blecfg;
+#[doc = "PWRCMD (rw) register accessor: an alias for `Reg<PWRCMD_SPEC>`"]
+pub type PWRCMD = crate::Reg<pwrcmd::PWRCMD_SPEC>;
+#[doc = "BLE Power command interface"]
+pub mod pwrcmd;
+#[doc = "BSTATUS (rw) register accessor: an alias for `Reg<BSTATUS_SPEC>`"]
+pub type BSTATUS = crate::Reg<bstatus::BSTATUS_SPEC>;
+#[doc = "BLE Core status"]
+pub mod bstatus;
+#[doc = "BLEDBG (rw) register accessor: an alias for `Reg<BLEDBG_SPEC>`"]
+pub type BLEDBG = crate::Reg<bledbg::BLEDBG_SPEC>;
+#[doc = "BLEIF Master Debug Register"]
+pub mod bledbg;

apollo3-pac/src/bleif/blecfg.rs

@@ -0,0 +1,622 @@
+#[doc = "Register `BLECFG` reader"]
+pub struct R(crate::R<BLECFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BLECFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BLECFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BLECFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `BLECFG` writer"]
+pub struct W(crate::W<BLECFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<BLECFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<BLECFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<BLECFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PWRSMEN` reader - Enable the power state machine for automatic sequencing and control of power states of the BLE Core module."]
+pub type PWRSMEN_R = crate::BitReader<PWRSMEN_A>;
+#[doc = "Enable the power state machine for automatic sequencing and control of power states of the BLE Core module.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PWRSMEN_A {
+    #[doc = "1: Internal power state machine is enabled and will sequence the BLEH power domain as indicated in the design document. Overrides for the power signals are not enabled. value."]
+    ON = 1,
+    #[doc = "0: Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals value."]
+    OFF = 0,
+}
+impl From<PWRSMEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: PWRSMEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PWRSMEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PWRSMEN_A {
+        match self.bits {
+            true => PWRSMEN_A::ON,
+            false => PWRSMEN_A::OFF,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ON`"]
+    #[inline(always)]
+    pub fn is_on(&self) -> bool {
+        *self == PWRSMEN_A::ON
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == PWRSMEN_A::OFF
+    }
+}
+#[doc = "Field `PWRSMEN` writer - Enable the power state machine for automatic sequencing and control of power states of the BLE Core module."]
+pub type PWRSMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLECFG_SPEC, PWRSMEN_A, O>;
+impl<'a, const O: u8> PWRSMEN_W<'a, O> {
+    #[doc = "Internal power state machine is enabled and will sequence the BLEH power domain as indicated in the design document. Overrides for the power signals are not enabled. value."]
+    #[inline(always)]
+    pub fn on(self) -> &'a mut W {
+        self.variant(PWRSMEN_A::ON)
+    }
+    #[doc = "Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(PWRSMEN_A::OFF)
+    }
+}
+#[doc = "Field `BLERSTN` reader - Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core."]
+pub type BLERSTN_R = crate::BitReader<BLERSTN_A>;
+#[doc = "Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BLERSTN_A {
+    #[doc = "1: The reset signal is active (0) value."]
+    ACTIVE = 1,
+    #[doc = "0: The reset signal is inactive (1) value."]
+    INACTIVE = 0,
+}
+impl From<BLERSTN_A> for bool {
+    #[inline(always)]
+    fn from(variant: BLERSTN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl BLERSTN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> BLERSTN_A {
+        match self.bits {
+            true => BLERSTN_A::ACTIVE,
+            false => BLERSTN_A::INACTIVE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE`"]
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == BLERSTN_A::ACTIVE
+    }
+    #[doc = "Checks if the value of the field is `INACTIVE`"]
+    #[inline(always)]
+    pub fn is_inactive(&self) -> bool {
+        *self == BLERSTN_A::INACTIVE
+    }
+}
+#[doc = "Field `BLERSTN` writer - Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core."]
+pub type BLERSTN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLECFG_SPEC, BLERSTN_A, O>;
+impl<'a, const O: u8> BLERSTN_W<'a, O> {
+    #[doc = "The reset signal is active (0) value."]
+    #[inline(always)]
+    pub fn active(self) -> &'a mut W {
+        self.variant(BLERSTN_A::ACTIVE)
+    }
+    #[doc = "The reset signal is inactive (1) value."]
+    #[inline(always)]
+    pub fn inactive(self) -> &'a mut W {
+        self.variant(BLERSTN_A::INACTIVE)
+    }
+}
+#[doc = "Field `WAKEUPCTL` reader - WAKE signal override. Controls the source of the WAKE signal to the BLE Core."]
+pub type WAKEUPCTL_R = crate::FieldReader<u8, WAKEUPCTL_A>;
+#[doc = "WAKE signal override. Controls the source of the WAKE signal to the BLE Core.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum WAKEUPCTL_A {
+    #[doc = "3: Wake signal is set to on (1). value."]
+    ON = 3,
+    #[doc = "2: Wake signal is set to off (0). value."]
+    OFF = 2,
+    #[doc = "0: Wake signal is controlled by the PWRSM logic and automatically controlled value."]
+    AUTO = 0,
+}
+impl From<WAKEUPCTL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: WAKEUPCTL_A) -> Self {
+        variant as _
+    }
+}
+impl WAKEUPCTL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WAKEUPCTL_A> {
+        match self.bits {
+            3 => Some(WAKEUPCTL_A::ON),
+            2 => Some(WAKEUPCTL_A::OFF),
+            0 => Some(WAKEUPCTL_A::AUTO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ON`"]
+    #[inline(always)]
+    pub fn is_on(&self) -> bool {
+        *self == WAKEUPCTL_A::ON
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == WAKEUPCTL_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `AUTO`"]
+    #[inline(always)]
+    pub fn is_auto(&self) -> bool {
+        *self == WAKEUPCTL_A::AUTO
+    }
+}
+#[doc = "Field `WAKEUPCTL` writer - WAKE signal override. Controls the source of the WAKE signal to the BLE Core."]
+pub type WAKEUPCTL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BLECFG_SPEC, u8, WAKEUPCTL_A, 2, O>;
+impl<'a, const O: u8> WAKEUPCTL_W<'a, O> {
+    #[doc = "Wake signal is set to on (1). value."]
+    #[inline(always)]
+    pub fn on(self) -> &'a mut W {
+        self.variant(WAKEUPCTL_A::ON)
+    }
+    #[doc = "Wake signal is set to off (0). value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(WAKEUPCTL_A::OFF)
+    }
+    #[doc = "Wake signal is controlled by the PWRSM logic and automatically controlled value."]
+    #[inline(always)]
+    pub fn auto(self) -> &'a mut W {
+        self.variant(WAKEUPCTL_A::AUTO)
+    }
+}
+#[doc = "Field `DCDCFLGCTL` reader - DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+pub type DCDCFLGCTL_R = crate::FieldReader<u8, DCDCFLGCTL_A>;
+#[doc = "DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum DCDCFLGCTL_A {
+    #[doc = "3: DCDC Flag signal is set to on (1). value."]
+    ON = 3,
+    #[doc = "2: DCDC Flag signal is set to off (0). value."]
+    OFF = 2,
+    #[doc = "0: DCDC Flag signal is controlled by the PWRSM logic and automatically controlled value."]
+    AUTO = 0,
+}
+impl From<DCDCFLGCTL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: DCDCFLGCTL_A) -> Self {
+        variant as _
+    }
+}
+impl DCDCFLGCTL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DCDCFLGCTL_A> {
+        match self.bits {
+            3 => Some(DCDCFLGCTL_A::ON),
+            2 => Some(DCDCFLGCTL_A::OFF),
+            0 => Some(DCDCFLGCTL_A::AUTO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ON`"]
+    #[inline(always)]
+    pub fn is_on(&self) -> bool {
+        *self == DCDCFLGCTL_A::ON
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == DCDCFLGCTL_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `AUTO`"]
+    #[inline(always)]
+    pub fn is_auto(&self) -> bool {
+        *self == DCDCFLGCTL_A::AUTO
+    }
+}
+#[doc = "Field `DCDCFLGCTL` writer - DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+pub type DCDCFLGCTL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BLECFG_SPEC, u8, DCDCFLGCTL_A, 2, O>;
+impl<'a, const O: u8> DCDCFLGCTL_W<'a, O> {
+    #[doc = "DCDC Flag signal is set to on (1). value."]
+    #[inline(always)]
+    pub fn on(self) -> &'a mut W {
+        self.variant(DCDCFLGCTL_A::ON)
+    }
+    #[doc = "DCDC Flag signal is set to off (0). value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(DCDCFLGCTL_A::OFF)
+    }
+    #[doc = "DCDC Flag signal is controlled by the PWRSM logic and automatically controlled value."]
+    #[inline(always)]
+    pub fn auto(self) -> &'a mut W {
+        self.variant(DCDCFLGCTL_A::AUTO)
+    }
+}
+#[doc = "Field `BLEHREQCTL` reader - BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+pub type BLEHREQCTL_R = crate::FieldReader<u8, BLEHREQCTL_A>;
+#[doc = "BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum BLEHREQCTL_A {
+    #[doc = "3: BLEH Power-on reg signal is set to on (1). value."]
+    ON = 3,
+    #[doc = "2: BLEH Power-on signal is set to off (0). value."]
+    OFF = 2,
+    #[doc = "0: BLEH Power-on signal is controlled by the PWRSM logic and automatically controlled value."]
+    AUTO = 0,
+}
+impl From<BLEHREQCTL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: BLEHREQCTL_A) -> Self {
+        variant as _
+    }
+}
+impl BLEHREQCTL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<BLEHREQCTL_A> {
+        match self.bits {
+            3 => Some(BLEHREQCTL_A::ON),
+            2 => Some(BLEHREQCTL_A::OFF),
+            0 => Some(BLEHREQCTL_A::AUTO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ON`"]
+    #[inline(always)]
+    pub fn is_on(&self) -> bool {
+        *self == BLEHREQCTL_A::ON
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == BLEHREQCTL_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `AUTO`"]
+    #[inline(always)]
+    pub fn is_auto(&self) -> bool {
+        *self == BLEHREQCTL_A::AUTO
+    }
+}
+#[doc = "Field `BLEHREQCTL` writer - BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+pub type BLEHREQCTL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BLECFG_SPEC, u8, BLEHREQCTL_A, 2, O>;
+impl<'a, const O: u8> BLEHREQCTL_W<'a, O> {
+    #[doc = "BLEH Power-on reg signal is set to on (1). value."]
+    #[inline(always)]
+    pub fn on(self) -> &'a mut W {
+        self.variant(BLEHREQCTL_A::ON)
+    }
+    #[doc = "BLEH Power-on signal is set to off (0). value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(BLEHREQCTL_A::OFF)
+    }
+    #[doc = "BLEH Power-on signal is controlled by the PWRSM logic and automatically controlled value."]
+    #[inline(always)]
+    pub fn auto(self) -> &'a mut W {
+        self.variant(BLEHREQCTL_A::AUTO)
+    }
+}
+#[doc = "Field `WT4ACTOFF` reader - Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for dcdc req from BLE Core."]
+pub type WT4ACTOFF_R = crate::BitReader<bool>;
+#[doc = "Field `WT4ACTOFF` writer - Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for dcdc req from BLE Core."]
+pub type WT4ACTOFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLECFG_SPEC, bool, O>;
+#[doc = "Field `MCUFRCSLP` reader - Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine."]
+pub type MCUFRCSLP_R = crate::BitReader<bool>;
+#[doc = "Field `MCUFRCSLP` writer - Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine."]
+pub type MCUFRCSLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLECFG_SPEC, bool, O>;
+#[doc = "Field `FRCCLK` reader - Force the clock in the BLEIF to be always running"]
+pub type FRCCLK_R = crate::BitReader<bool>;
+#[doc = "Field `FRCCLK` writer - Force the clock in the BLEIF to be always running"]
+pub type FRCCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLECFG_SPEC, bool, O>;
+#[doc = "Field `STAYASLEEP` reader - Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state."]
+pub type STAYASLEEP_R = crate::BitReader<bool>;
+#[doc = "Field `STAYASLEEP` writer - Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state."]
+pub type STAYASLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLECFG_SPEC, bool, O>;
+#[doc = "Field `PWRISOCTL` reader - Configuration of BLEH isolation control for power related signals."]
+pub type PWRISOCTL_R = crate::FieldReader<u8, PWRISOCTL_A>;
+#[doc = "Configuration of BLEH isolation control for power related signals.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PWRISOCTL_A {
+    #[doc = "3: BLEH power signal isolation to on (isolated). value."]
+    ON = 3,
+    #[doc = "2: BLEH power signal isolation to off (not isolated). value."]
+    OFF = 2,
+    #[doc = "0: BLEH Power signal isolation is controlled automatically through the interface logic value."]
+    AUTO = 0,
+}
+impl From<PWRISOCTL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PWRISOCTL_A) -> Self {
+        variant as _
+    }
+}
+impl PWRISOCTL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<PWRISOCTL_A> {
+        match self.bits {
+            3 => Some(PWRISOCTL_A::ON),
+            2 => Some(PWRISOCTL_A::OFF),
+            0 => Some(PWRISOCTL_A::AUTO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ON`"]
+    #[inline(always)]
+    pub fn is_on(&self) -> bool {
+        *self == PWRISOCTL_A::ON
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == PWRISOCTL_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `AUTO`"]
+    #[inline(always)]
+    pub fn is_auto(&self) -> bool {
+        *self == PWRISOCTL_A::AUTO
+    }
+}
+#[doc = "Field `PWRISOCTL` writer - Configuration of BLEH isolation control for power related signals."]
+pub type PWRISOCTL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BLECFG_SPEC, u8, PWRISOCTL_A, 2, O>;
+impl<'a, const O: u8> PWRISOCTL_W<'a, O> {
+    #[doc = "BLEH power signal isolation to on (isolated). value."]
+    #[inline(always)]
+    pub fn on(self) -> &'a mut W {
+        self.variant(PWRISOCTL_A::ON)
+    }
+    #[doc = "BLEH power signal isolation to off (not isolated). value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(PWRISOCTL_A::OFF)
+    }
+    #[doc = "BLEH Power signal isolation is controlled automatically through the interface logic value."]
+    #[inline(always)]
+    pub fn auto(self) -> &'a mut W {
+        self.variant(PWRISOCTL_A::AUTO)
+    }
+}
+#[doc = "Field `SPIISOCTL` reader - Configuration of BLEH isolation controls for SPI related signals."]
+pub type SPIISOCTL_R = crate::FieldReader<u8, SPIISOCTL_A>;
+#[doc = "Configuration of BLEH isolation controls for SPI related signals.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SPIISOCTL_A {
+    #[doc = "3: SPI signals from BLE Core to/from MCU Core are isolated. value."]
+    ON = 3,
+    #[doc = "2: SPI signals from BLE Core to/from MCU Core are not isolated. value."]
+    OFF = 2,
+    #[doc = "0: SPI signals from BLE Core to/from MCU Core are automatically isolated by the logic value."]
+    AUTO = 0,
+}
+impl From<SPIISOCTL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SPIISOCTL_A) -> Self {
+        variant as _
+    }
+}
+impl SPIISOCTL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SPIISOCTL_A> {
+        match self.bits {
+            3 => Some(SPIISOCTL_A::ON),
+            2 => Some(SPIISOCTL_A::OFF),
+            0 => Some(SPIISOCTL_A::AUTO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ON`"]
+    #[inline(always)]
+    pub fn is_on(&self) -> bool {
+        *self == SPIISOCTL_A::ON
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == SPIISOCTL_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `AUTO`"]
+    #[inline(always)]
+    pub fn is_auto(&self) -> bool {
+        *self == SPIISOCTL_A::AUTO
+    }
+}
+#[doc = "Field `SPIISOCTL` writer - Configuration of BLEH isolation controls for SPI related signals."]
+pub type SPIISOCTL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BLECFG_SPEC, u8, SPIISOCTL_A, 2, O>;
+impl<'a, const O: u8> SPIISOCTL_W<'a, O> {
+    #[doc = "SPI signals from BLE Core to/from MCU Core are isolated. value."]
+    #[inline(always)]
+    pub fn on(self) -> &'a mut W {
+        self.variant(SPIISOCTL_A::ON)
+    }
+    #[doc = "SPI signals from BLE Core to/from MCU Core are not isolated. value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(SPIISOCTL_A::OFF)
+    }
+    #[doc = "SPI signals from BLE Core to/from MCU Core are automatically isolated by the logic value."]
+    #[inline(always)]
+    pub fn auto(self) -> &'a mut W {
+        self.variant(SPIISOCTL_A::AUTO)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable the power state machine for automatic sequencing and control of power states of the BLE Core module."]
+    #[inline(always)]
+    pub fn pwrsmen(&self) -> PWRSMEN_R {
+        PWRSMEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core."]
+    #[inline(always)]
+    pub fn blerstn(&self) -> BLERSTN_R {
+        BLERSTN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 2:3 - WAKE signal override. Controls the source of the WAKE signal to the BLE Core."]
+    #[inline(always)]
+    pub fn wakeupctl(&self) -> WAKEUPCTL_R {
+        WAKEUPCTL_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bits 4:5 - DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+    #[inline(always)]
+    pub fn dcdcflgctl(&self) -> DCDCFLGCTL_R {
+        DCDCFLGCTL_R::new(((self.bits >> 4) & 3) as u8)
+    }
+    #[doc = "Bits 6:7 - BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+    #[inline(always)]
+    pub fn blehreqctl(&self) -> BLEHREQCTL_R {
+        BLEHREQCTL_R::new(((self.bits >> 6) & 3) as u8)
+    }
+    #[doc = "Bit 8 - Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for dcdc req from BLE Core."]
+    #[inline(always)]
+    pub fn wt4actoff(&self) -> WT4ACTOFF_R {
+        WT4ACTOFF_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine."]
+    #[inline(always)]
+    pub fn mcufrcslp(&self) -> MCUFRCSLP_R {
+        MCUFRCSLP_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Force the clock in the BLEIF to be always running"]
+    #[inline(always)]
+    pub fn frcclk(&self) -> FRCCLK_R {
+        FRCCLK_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state."]
+    #[inline(always)]
+    pub fn stayasleep(&self) -> STAYASLEEP_R {
+        STAYASLEEP_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bits 12:13 - Configuration of BLEH isolation control for power related signals."]
+    #[inline(always)]
+    pub fn pwrisoctl(&self) -> PWRISOCTL_R {
+        PWRISOCTL_R::new(((self.bits >> 12) & 3) as u8)
+    }
+    #[doc = "Bits 14:15 - Configuration of BLEH isolation controls for SPI related signals."]
+    #[inline(always)]
+    pub fn spiisoctl(&self) -> SPIISOCTL_R {
+        SPIISOCTL_R::new(((self.bits >> 14) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable the power state machine for automatic sequencing and control of power states of the BLE Core module."]
+    #[inline(always)]
+    pub fn pwrsmen(&mut self) -> PWRSMEN_W<0> {
+        PWRSMEN_W::new(self)
+    }
+    #[doc = "Bit 1 - Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core."]
+    #[inline(always)]
+    pub fn blerstn(&mut self) -> BLERSTN_W<1> {
+        BLERSTN_W::new(self)
+    }
+    #[doc = "Bits 2:3 - WAKE signal override. Controls the source of the WAKE signal to the BLE Core."]
+    #[inline(always)]
+    pub fn wakeupctl(&mut self) -> WAKEUPCTL_W<2> {
+        WAKEUPCTL_W::new(self)
+    }
+    #[doc = "Bits 4:5 - DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+    #[inline(always)]
+    pub fn dcdcflgctl(&mut self) -> DCDCFLGCTL_W<4> {
+        DCDCFLGCTL_W::new(self)
+    }
+    #[doc = "Bits 6:7 - BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic."]
+    #[inline(always)]
+    pub fn blehreqctl(&mut self) -> BLEHREQCTL_W<6> {
+        BLEHREQCTL_W::new(self)
+    }
+    #[doc = "Bit 8 - Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for dcdc req from BLE Core."]
+    #[inline(always)]
+    pub fn wt4actoff(&mut self) -> WT4ACTOFF_W<8> {
+        WT4ACTOFF_W::new(self)
+    }
+    #[doc = "Bit 9 - Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine."]
+    #[inline(always)]
+    pub fn mcufrcslp(&mut self) -> MCUFRCSLP_W<9> {
+        MCUFRCSLP_W::new(self)
+    }
+    #[doc = "Bit 10 - Force the clock in the BLEIF to be always running"]
+    #[inline(always)]
+    pub fn frcclk(&mut self) -> FRCCLK_W<10> {
+        FRCCLK_W::new(self)
+    }
+    #[doc = "Bit 11 - Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state."]
+    #[inline(always)]
+    pub fn stayasleep(&mut self) -> STAYASLEEP_W<11> {
+        STAYASLEEP_W::new(self)
+    }
+    #[doc = "Bits 12:13 - Configuration of BLEH isolation control for power related signals."]
+    #[inline(always)]
+    pub fn pwrisoctl(&mut self) -> PWRISOCTL_W<12> {
+        PWRISOCTL_W::new(self)
+    }
+    #[doc = "Bits 14:15 - Configuration of BLEH isolation controls for SPI related signals."]
+    #[inline(always)]
+    pub fn spiisoctl(&mut self) -> SPIISOCTL_W<14> {
+        SPIISOCTL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "BLE Core Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blecfg](index.html) module"]
+pub struct BLECFG_SPEC;
+impl crate::RegisterSpec for BLECFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [blecfg::R](R) reader structure"]
+impl crate::Readable for BLECFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [blecfg::W](W) writer structure"]
+impl crate::Writable for BLECFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets BLECFG to value 0"]
+impl crate::Resettable for BLECFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/bledbg.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `BLEDBG` reader"]
+pub struct R(crate::R<BLEDBG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BLEDBG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BLEDBG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BLEDBG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `BLEDBG` writer"]
+pub struct W(crate::W<BLEDBG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<BLEDBG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<BLEDBG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<BLEDBG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DBGEN` reader - Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings"]
+pub type DBGEN_R = crate::BitReader<bool>;
+#[doc = "Field `DBGEN` writer - Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings"]
+pub type DBGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLEDBG_SPEC, bool, O>;
+#[doc = "Field `IOCLKON` reader - IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+pub type IOCLKON_R = crate::BitReader<bool>;
+#[doc = "Field `IOCLKON` writer - IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+pub type IOCLKON_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLEDBG_SPEC, bool, O>;
+#[doc = "Field `APBCLKON` reader - APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+pub type APBCLKON_R = crate::BitReader<bool>;
+#[doc = "Field `APBCLKON` writer - APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+pub type APBCLKON_W<'a, const O: u8> = crate::BitWriter<'a, u32, BLEDBG_SPEC, bool, O>;
+#[doc = "Field `DBGDATA` reader - Debug data"]
+pub type DBGDATA_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DBGDATA` writer - Debug data"]
+pub type DBGDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLEDBG_SPEC, u32, u32, 29, O>;
+impl R {
+    #[doc = "Bit 0 - Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings"]
+    #[inline(always)]
+    pub fn dbgen(&self) -> DBGEN_R {
+        DBGEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+    #[inline(always)]
+    pub fn ioclkon(&self) -> IOCLKON_R {
+        IOCLKON_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+    #[inline(always)]
+    pub fn apbclkon(&self) -> APBCLKON_R {
+        APBCLKON_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bits 3:31 - Debug data"]
+    #[inline(always)]
+    pub fn dbgdata(&self) -> DBGDATA_R {
+        DBGDATA_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings"]
+    #[inline(always)]
+    pub fn dbgen(&mut self) -> DBGEN_W<0> {
+        DBGEN_W::new(self)
+    }
+    #[doc = "Bit 1 - IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+    #[inline(always)]
+    pub fn ioclkon(&mut self) -> IOCLKON_W<1> {
+        IOCLKON_W::new(self)
+    }
+    #[doc = "Bit 2 - APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed."]
+    #[inline(always)]
+    pub fn apbclkon(&mut self) -> APBCLKON_W<2> {
+        APBCLKON_W::new(self)
+    }
+    #[doc = "Bits 3:31 - Debug data"]
+    #[inline(always)]
+    pub fn dbgdata(&mut self) -> DBGDATA_W<3> {
+        DBGDATA_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "BLEIF Master Debug Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bledbg](index.html) module"]
+pub struct BLEDBG_SPEC;
+impl crate::RegisterSpec for BLEDBG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [bledbg::R](R) reader structure"]
+impl crate::Readable for BLEDBG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [bledbg::W](W) writer structure"]
+impl crate::Writable for BLEDBG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets BLEDBG to value 0"]
+impl crate::Resettable for BLEDBG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/bstatus.rs

@@ -0,0 +1,380 @@
+#[doc = "Register `BSTATUS` reader"]
+pub struct R(crate::R<BSTATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BSTATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BSTATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BSTATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `BSTATUS` writer"]
+pub struct W(crate::W<BSTATUS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<BSTATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<BSTATUS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<BSTATUS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `B2MSTATE` reader - State of the BLE Core logic."]
+pub type B2MSTATE_R = crate::FieldReader<u8, B2MSTATE_A>;
+#[doc = "State of the BLE Core logic.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum B2MSTATE_A {
+    #[doc = "0: Reset State value."]
+    RESET = 0,
+    #[doc = "1: Sleep state. value."]
+    SLEEP = 1,
+    #[doc = "2: Standby State value."]
+    STANDBY = 2,
+    #[doc = "3: Idle state value."]
+    IDLE = 3,
+    #[doc = "4: Active state. value."]
+    ACTIVE = 4,
+}
+impl From<B2MSTATE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: B2MSTATE_A) -> Self {
+        variant as _
+    }
+}
+impl B2MSTATE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<B2MSTATE_A> {
+        match self.bits {
+            0 => Some(B2MSTATE_A::RESET),
+            1 => Some(B2MSTATE_A::SLEEP),
+            2 => Some(B2MSTATE_A::STANDBY),
+            3 => Some(B2MSTATE_A::IDLE),
+            4 => Some(B2MSTATE_A::ACTIVE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RESET`"]
+    #[inline(always)]
+    pub fn is_reset(&self) -> bool {
+        *self == B2MSTATE_A::RESET
+    }
+    #[doc = "Checks if the value of the field is `SLEEP`"]
+    #[inline(always)]
+    pub fn is_sleep(&self) -> bool {
+        *self == B2MSTATE_A::SLEEP
+    }
+    #[doc = "Checks if the value of the field is `STANDBY`"]
+    #[inline(always)]
+    pub fn is_standby(&self) -> bool {
+        *self == B2MSTATE_A::STANDBY
+    }
+    #[doc = "Checks if the value of the field is `IDLE`"]
+    #[inline(always)]
+    pub fn is_idle(&self) -> bool {
+        *self == B2MSTATE_A::IDLE
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE`"]
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == B2MSTATE_A::ACTIVE
+    }
+}
+#[doc = "Field `B2MSTATE` writer - State of the BLE Core logic."]
+pub type B2MSTATE_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BSTATUS_SPEC, u8, B2MSTATE_A, 3, O>;
+impl<'a, const O: u8> B2MSTATE_W<'a, O> {
+    #[doc = "Reset State value."]
+    #[inline(always)]
+    pub fn reset(self) -> &'a mut W {
+        self.variant(B2MSTATE_A::RESET)
+    }
+    #[doc = "Sleep state. value."]
+    #[inline(always)]
+    pub fn sleep(self) -> &'a mut W {
+        self.variant(B2MSTATE_A::SLEEP)
+    }
+    #[doc = "Standby State value."]
+    #[inline(always)]
+    pub fn standby(self) -> &'a mut W {
+        self.variant(B2MSTATE_A::STANDBY)
+    }
+    #[doc = "Idle state value."]
+    #[inline(always)]
+    pub fn idle(self) -> &'a mut W {
+        self.variant(B2MSTATE_A::IDLE)
+    }
+    #[doc = "Active state. value."]
+    #[inline(always)]
+    pub fn active(self) -> &'a mut W {
+        self.variant(B2MSTATE_A::ACTIVE)
+    }
+}
+#[doc = "Field `SPISTATUS` reader - Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active."]
+pub type SPISTATUS_R = crate::BitReader<bool>;
+#[doc = "Field `SPISTATUS` writer - Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active."]
+pub type SPISTATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSTATUS_SPEC, bool, O>;
+#[doc = "Field `DCDCREQ` reader - Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1."]
+pub type DCDCREQ_R = crate::BitReader<bool>;
+#[doc = "Field `DCDCREQ` writer - Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1."]
+pub type DCDCREQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSTATUS_SPEC, bool, O>;
+#[doc = "Field `DCDCFLAG` reader - Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH ppower is active."]
+pub type DCDCFLAG_R = crate::BitReader<bool>;
+#[doc = "Field `DCDCFLAG` writer - Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH ppower is active."]
+pub type DCDCFLAG_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSTATUS_SPEC, bool, O>;
+#[doc = "Field `WAKEUP` reader - Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state."]
+pub type WAKEUP_R = crate::BitReader<bool>;
+#[doc = "Field `WAKEUP` writer - Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state."]
+pub type WAKEUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSTATUS_SPEC, bool, O>;
+#[doc = "Field `BLEIRQ` reader - Status of the BLEIRQ signal from the BLE Core. A value of 1 idicates that read data is available in the core and a read operation needs to be performed."]
+pub type BLEIRQ_R = crate::BitReader<bool>;
+#[doc = "Field `BLEIRQ` writer - Status of the BLEIRQ signal from the BLE Core. A value of 1 idicates that read data is available in the core and a read operation needs to be performed."]
+pub type BLEIRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSTATUS_SPEC, bool, O>;
+#[doc = "Field `PWRST` reader - Current status of the power state machine"]
+pub type PWRST_R = crate::FieldReader<u8, PWRST_A>;
+#[doc = "Current status of the power state machine\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PWRST_A {
+    #[doc = "0: Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals value."]
+    OFF = 0,
+    #[doc = "1: Initialization state. BLEH not powered value."]
+    INIT = 1,
+    #[doc = "2: Waiting for the powerup of the BLEH value."]
+    PWRON = 2,
+    #[doc = "3: The BLE Core is powered and active value."]
+    ACTIVE = 3,
+    #[doc = "6: The BLE Core has entered sleep mode and the power request is inactive value."]
+    SLEEP = 6,
+    #[doc = "4: The BLE Core is in shutdown mode value."]
+    SHUTDOWN = 4,
+}
+impl From<PWRST_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PWRST_A) -> Self {
+        variant as _
+    }
+}
+impl PWRST_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<PWRST_A> {
+        match self.bits {
+            0 => Some(PWRST_A::OFF),
+            1 => Some(PWRST_A::INIT),
+            2 => Some(PWRST_A::PWRON),
+            3 => Some(PWRST_A::ACTIVE),
+            6 => Some(PWRST_A::SLEEP),
+            4 => Some(PWRST_A::SHUTDOWN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OFF`"]
+    #[inline(always)]
+    pub fn is_off(&self) -> bool {
+        *self == PWRST_A::OFF
+    }
+    #[doc = "Checks if the value of the field is `INIT`"]
+    #[inline(always)]
+    pub fn is_init(&self) -> bool {
+        *self == PWRST_A::INIT
+    }
+    #[doc = "Checks if the value of the field is `PWRON`"]
+    #[inline(always)]
+    pub fn is_pwron(&self) -> bool {
+        *self == PWRST_A::PWRON
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE`"]
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == PWRST_A::ACTIVE
+    }
+    #[doc = "Checks if the value of the field is `SLEEP`"]
+    #[inline(always)]
+    pub fn is_sleep(&self) -> bool {
+        *self == PWRST_A::SLEEP
+    }
+    #[doc = "Checks if the value of the field is `SHUTDOWN`"]
+    #[inline(always)]
+    pub fn is_shutdown(&self) -> bool {
+        *self == PWRST_A::SHUTDOWN
+    }
+}
+#[doc = "Field `PWRST` writer - Current status of the power state machine"]
+pub type PWRST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BSTATUS_SPEC, u8, PWRST_A, 3, O>;
+impl<'a, const O: u8> PWRST_W<'a, O> {
+    #[doc = "Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals value."]
+    #[inline(always)]
+    pub fn off(self) -> &'a mut W {
+        self.variant(PWRST_A::OFF)
+    }
+    #[doc = "Initialization state. BLEH not powered value."]
+    #[inline(always)]
+    pub fn init(self) -> &'a mut W {
+        self.variant(PWRST_A::INIT)
+    }
+    #[doc = "Waiting for the powerup of the BLEH value."]
+    #[inline(always)]
+    pub fn pwron(self) -> &'a mut W {
+        self.variant(PWRST_A::PWRON)
+    }
+    #[doc = "The BLE Core is powered and active value."]
+    #[inline(always)]
+    pub fn active(self) -> &'a mut W {
+        self.variant(PWRST_A::ACTIVE)
+    }
+    #[doc = "The BLE Core has entered sleep mode and the power request is inactive value."]
+    #[inline(always)]
+    pub fn sleep(self) -> &'a mut W {
+        self.variant(PWRST_A::SLEEP)
+    }
+    #[doc = "The BLE Core is in shutdown mode value."]
+    #[inline(always)]
+    pub fn shutdown(self) -> &'a mut W {
+        self.variant(PWRST_A::SHUTDOWN)
+    }
+}
+#[doc = "Field `BLEHACK` reader - Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use."]
+pub type BLEHACK_R = crate::BitReader<bool>;
+#[doc = "Field `BLEHACK` writer - Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use."]
+pub type BLEHACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSTATUS_SPEC, bool, O>;
+#[doc = "Field `BLEHREQ` reader - Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use."]
+pub type BLEHREQ_R = crate::BitReader<bool>;
+#[doc = "Field `BLEHREQ` writer - Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use."]
+pub type BLEHREQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSTATUS_SPEC, bool, O>;
+impl R {
+    #[doc = "Bits 0:2 - State of the BLE Core logic."]
+    #[inline(always)]
+    pub fn b2mstate(&self) -> B2MSTATE_R {
+        B2MSTATE_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 3 - Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active."]
+    #[inline(always)]
+    pub fn spistatus(&self) -> SPISTATUS_R {
+        SPISTATUS_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1."]
+    #[inline(always)]
+    pub fn dcdcreq(&self) -> DCDCREQ_R {
+        DCDCREQ_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH ppower is active."]
+    #[inline(always)]
+    pub fn dcdcflag(&self) -> DCDCFLAG_R {
+        DCDCFLAG_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state."]
+    #[inline(always)]
+    pub fn wakeup(&self) -> WAKEUP_R {
+        WAKEUP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Status of the BLEIRQ signal from the BLE Core. A value of 1 idicates that read data is available in the core and a read operation needs to be performed."]
+    #[inline(always)]
+    pub fn bleirq(&self) -> BLEIRQ_R {
+        BLEIRQ_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bits 8:10 - Current status of the power state machine"]
+    #[inline(always)]
+    pub fn pwrst(&self) -> PWRST_R {
+        PWRST_R::new(((self.bits >> 8) & 7) as u8)
+    }
+    #[doc = "Bit 11 - Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use."]
+    #[inline(always)]
+    pub fn blehack(&self) -> BLEHACK_R {
+        BLEHACK_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use."]
+    #[inline(always)]
+    pub fn blehreq(&self) -> BLEHREQ_R {
+        BLEHREQ_R::new(((self.bits >> 12) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - State of the BLE Core logic."]
+    #[inline(always)]
+    pub fn b2mstate(&mut self) -> B2MSTATE_W<0> {
+        B2MSTATE_W::new(self)
+    }
+    #[doc = "Bit 3 - Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active."]
+    #[inline(always)]
+    pub fn spistatus(&mut self) -> SPISTATUS_W<3> {
+        SPISTATUS_W::new(self)
+    }
+    #[doc = "Bit 4 - Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1."]
+    #[inline(always)]
+    pub fn dcdcreq(&mut self) -> DCDCREQ_W<4> {
+        DCDCREQ_W::new(self)
+    }
+    #[doc = "Bit 5 - Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH ppower is active."]
+    #[inline(always)]
+    pub fn dcdcflag(&mut self) -> DCDCFLAG_W<5> {
+        DCDCFLAG_W::new(self)
+    }
+    #[doc = "Bit 6 - Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state."]
+    #[inline(always)]
+    pub fn wakeup(&mut self) -> WAKEUP_W<6> {
+        WAKEUP_W::new(self)
+    }
+    #[doc = "Bit 7 - Status of the BLEIRQ signal from the BLE Core. A value of 1 idicates that read data is available in the core and a read operation needs to be performed."]
+    #[inline(always)]
+    pub fn bleirq(&mut self) -> BLEIRQ_W<7> {
+        BLEIRQ_W::new(self)
+    }
+    #[doc = "Bits 8:10 - Current status of the power state machine"]
+    #[inline(always)]
+    pub fn pwrst(&mut self) -> PWRST_W<8> {
+        PWRST_W::new(self)
+    }
+    #[doc = "Bit 11 - Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use."]
+    #[inline(always)]
+    pub fn blehack(&mut self) -> BLEHACK_W<11> {
+        BLEHACK_W::new(self)
+    }
+    #[doc = "Bit 12 - Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use."]
+    #[inline(always)]
+    pub fn blehreq(&mut self) -> BLEHREQ_W<12> {
+        BLEHREQ_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "BLE Core status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bstatus](index.html) module"]
+pub struct BSTATUS_SPEC;
+impl crate::RegisterSpec for BSTATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [bstatus::R](R) reader structure"]
+impl crate::Readable for BSTATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [bstatus::W](W) writer structure"]
+impl crate::Writable for BSTATUS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets BSTATUS to value 0"]
+impl crate::Resettable for BSTATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/clkcfg.rs

@@ -0,0 +1,248 @@
+#[doc = "Register `CLKCFG` reader"]
+pub struct R(crate::R<CLKCFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CLKCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CLKCFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CLKCFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CLKCFG` writer"]
+pub struct W(crate::W<CLKCFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CLKCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CLKCFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CLKCFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `IOCLKEN` reader - Enable for the interface clock. Must be enabled prior to executing any IO operations."]
+pub type IOCLKEN_R = crate::BitReader<bool>;
+#[doc = "Field `IOCLKEN` writer - Enable for the interface clock. Must be enabled prior to executing any IO operations."]
+pub type IOCLKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCFG_SPEC, bool, O>;
+#[doc = "Field `FSEL` reader - Select the input clock frequency."]
+pub type FSEL_R = crate::FieldReader<u8, FSEL_A>;
+#[doc = "Select the input clock frequency.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum FSEL_A {
+    #[doc = "0: Selects the minimum power clock. This setting should be used whenever the IOM is not active. value."]
+    MIN_PWR = 0,
+    #[doc = "1: Selects the HFRC as the input clock. value."]
+    HFRC = 1,
+    #[doc = "2: Selects the HFRC / 2 as the input clock. value."]
+    HFRC_DIV2 = 2,
+    #[doc = "3: Selects the HFRC / 4 as the input clock. value."]
+    HFRC_DIV4 = 3,
+    #[doc = "4: Selects the HFRC / 8 as the input clock. value."]
+    HFRC_DIV8 = 4,
+    #[doc = "5: Selects the HFRC / 16 as the input clock. value."]
+    HFRC_DIV16 = 5,
+    #[doc = "6: Selects the HFRC / 32 as the input clock. value."]
+    HFRC_DIV32 = 6,
+    #[doc = "7: Selects the HFRC / 64 as the input clock. value."]
+    HFRC_DIV64 = 7,
+}
+impl From<FSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: FSEL_A) -> Self {
+        variant as _
+    }
+}
+impl FSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FSEL_A {
+        match self.bits {
+            0 => FSEL_A::MIN_PWR,
+            1 => FSEL_A::HFRC,
+            2 => FSEL_A::HFRC_DIV2,
+            3 => FSEL_A::HFRC_DIV4,
+            4 => FSEL_A::HFRC_DIV8,
+            5 => FSEL_A::HFRC_DIV16,
+            6 => FSEL_A::HFRC_DIV32,
+            7 => FSEL_A::HFRC_DIV64,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `MIN_PWR`"]
+    #[inline(always)]
+    pub fn is_min_pwr(&self) -> bool {
+        *self == FSEL_A::MIN_PWR
+    }
+    #[doc = "Checks if the value of the field is `HFRC`"]
+    #[inline(always)]
+    pub fn is_hfrc(&self) -> bool {
+        *self == FSEL_A::HFRC
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV2`"]
+    #[inline(always)]
+    pub fn is_hfrc_div2(&self) -> bool {
+        *self == FSEL_A::HFRC_DIV2
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV4`"]
+    #[inline(always)]
+    pub fn is_hfrc_div4(&self) -> bool {
+        *self == FSEL_A::HFRC_DIV4
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV8`"]
+    #[inline(always)]
+    pub fn is_hfrc_div8(&self) -> bool {
+        *self == FSEL_A::HFRC_DIV8
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV16`"]
+    #[inline(always)]
+    pub fn is_hfrc_div16(&self) -> bool {
+        *self == FSEL_A::HFRC_DIV16
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV32`"]
+    #[inline(always)]
+    pub fn is_hfrc_div32(&self) -> bool {
+        *self == FSEL_A::HFRC_DIV32
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV64`"]
+    #[inline(always)]
+    pub fn is_hfrc_div64(&self) -> bool {
+        *self == FSEL_A::HFRC_DIV64
+    }
+}
+#[doc = "Field `FSEL` writer - Select the input clock frequency."]
+pub type FSEL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CLKCFG_SPEC, u8, FSEL_A, 3, O>;
+impl<'a, const O: u8> FSEL_W<'a, O> {
+    #[doc = "Selects the minimum power clock. This setting should be used whenever the IOM is not active. value."]
+    #[inline(always)]
+    pub fn min_pwr(self) -> &'a mut W {
+        self.variant(FSEL_A::MIN_PWR)
+    }
+    #[doc = "Selects the HFRC as the input clock. value."]
+    #[inline(always)]
+    pub fn hfrc(self) -> &'a mut W {
+        self.variant(FSEL_A::HFRC)
+    }
+    #[doc = "Selects the HFRC / 2 as the input clock. value."]
+    #[inline(always)]
+    pub fn hfrc_div2(self) -> &'a mut W {
+        self.variant(FSEL_A::HFRC_DIV2)
+    }
+    #[doc = "Selects the HFRC / 4 as the input clock. value."]
+    #[inline(always)]
+    pub fn hfrc_div4(self) -> &'a mut W {
+        self.variant(FSEL_A::HFRC_DIV4)
+    }
+    #[doc = "Selects the HFRC / 8 as the input clock. value."]
+    #[inline(always)]
+    pub fn hfrc_div8(self) -> &'a mut W {
+        self.variant(FSEL_A::HFRC_DIV8)
+    }
+    #[doc = "Selects the HFRC / 16 as the input clock. value."]
+    #[inline(always)]
+    pub fn hfrc_div16(self) -> &'a mut W {
+        self.variant(FSEL_A::HFRC_DIV16)
+    }
+    #[doc = "Selects the HFRC / 32 as the input clock. value."]
+    #[inline(always)]
+    pub fn hfrc_div32(self) -> &'a mut W {
+        self.variant(FSEL_A::HFRC_DIV32)
+    }
+    #[doc = "Selects the HFRC / 64 as the input clock. value."]
+    #[inline(always)]
+    pub fn hfrc_div64(self) -> &'a mut W {
+        self.variant(FSEL_A::HFRC_DIV64)
+    }
+}
+#[doc = "Field `CLK32KEN` reader - Enable for the 32Khz clock to the BLE module"]
+pub type CLK32KEN_R = crate::BitReader<bool>;
+#[doc = "Field `CLK32KEN` writer - Enable for the 32Khz clock to the BLE module"]
+pub type CLK32KEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCFG_SPEC, bool, O>;
+#[doc = "Field `DIV3` reader - Enable of the divide by 3 of the source IOCLK."]
+pub type DIV3_R = crate::BitReader<bool>;
+#[doc = "Field `DIV3` writer - Enable of the divide by 3 of the source IOCLK."]
+pub type DIV3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCFG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Enable for the interface clock. Must be enabled prior to executing any IO operations."]
+    #[inline(always)]
+    pub fn ioclken(&self) -> IOCLKEN_R {
+        IOCLKEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 8:10 - Select the input clock frequency."]
+    #[inline(always)]
+    pub fn fsel(&self) -> FSEL_R {
+        FSEL_R::new(((self.bits >> 8) & 7) as u8)
+    }
+    #[doc = "Bit 11 - Enable for the 32Khz clock to the BLE module"]
+    #[inline(always)]
+    pub fn clk32ken(&self) -> CLK32KEN_R {
+        CLK32KEN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Enable of the divide by 3 of the source IOCLK."]
+    #[inline(always)]
+    pub fn div3(&self) -> DIV3_R {
+        DIV3_R::new(((self.bits >> 12) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable for the interface clock. Must be enabled prior to executing any IO operations."]
+    #[inline(always)]
+    pub fn ioclken(&mut self) -> IOCLKEN_W<0> {
+        IOCLKEN_W::new(self)
+    }
+    #[doc = "Bits 8:10 - Select the input clock frequency."]
+    #[inline(always)]
+    pub fn fsel(&mut self) -> FSEL_W<8> {
+        FSEL_W::new(self)
+    }
+    #[doc = "Bit 11 - Enable for the 32Khz clock to the BLE module"]
+    #[inline(always)]
+    pub fn clk32ken(&mut self) -> CLK32KEN_W<11> {
+        CLK32KEN_W::new(self)
+    }
+    #[doc = "Bit 12 - Enable of the divide by 3 of the source IOCLK."]
+    #[inline(always)]
+    pub fn div3(&mut self) -> DIV3_W<12> {
+        DIV3_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "I/O Clock Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkcfg](index.html) module"]
+pub struct CLKCFG_SPEC;
+impl crate::RegisterSpec for CLKCFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [clkcfg::R](R) reader structure"]
+impl crate::Readable for CLKCFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [clkcfg::W](W) writer structure"]
+impl crate::Writable for CLKCFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CLKCFG to value 0"]
+impl crate::Resettable for CLKCFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cmd.rs

@@ -0,0 +1,210 @@
+#[doc = "Register `CMD` reader"]
+pub struct R(crate::R<CMD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CMD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CMD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CMD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CMD` writer"]
+pub struct W(crate::W<CMD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CMD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CMD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CMD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CMD` reader - Command for submodule."]
+pub type CMD_R = crate::FieldReader<u8, CMD_A>;
+#[doc = "Command for submodule.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CMD_A {
+    #[doc = "1: Write command using count of offset bytes specified in the OFFSETCNT field value."]
+    WRITE = 1,
+    #[doc = "2: Read command using count of offset bytes specified in the OFFSETCNT field value."]
+    READ = 2,
+}
+impl From<CMD_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CMD_A) -> Self {
+        variant as _
+    }
+}
+impl CMD_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CMD_A> {
+        match self.bits {
+            1 => Some(CMD_A::WRITE),
+            2 => Some(CMD_A::READ),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `WRITE`"]
+    #[inline(always)]
+    pub fn is_write(&self) -> bool {
+        *self == CMD_A::WRITE
+    }
+    #[doc = "Checks if the value of the field is `READ`"]
+    #[inline(always)]
+    pub fn is_read(&self) -> bool {
+        *self == CMD_A::READ
+    }
+}
+#[doc = "Field `CMD` writer - Command for submodule."]
+pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMD_SPEC, u8, CMD_A, 5, O>;
+impl<'a, const O: u8> CMD_W<'a, O> {
+    #[doc = "Write command using count of offset bytes specified in the OFFSETCNT field value."]
+    #[inline(always)]
+    pub fn write(self) -> &'a mut W {
+        self.variant(CMD_A::WRITE)
+    }
+    #[doc = "Read command using count of offset bytes specified in the OFFSETCNT field value."]
+    #[inline(always)]
+    pub fn read(self) -> &'a mut W {
+        self.variant(CMD_A::READ)
+    }
+}
+#[doc = "Field `OFFSETCNT` reader - Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI\\[15:8\\]
+will be transmitted first, then OFFSETHI\\[7:0\\]
+then OFFSETLO. If offsetcnt == 2, OFFSETHI\\[7:0\\]
+will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration."]
+pub type OFFSETCNT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `OFFSETCNT` writer - Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI\\[15:8\\]
+will be transmitted first, then OFFSETHI\\[7:0\\]
+then OFFSETLO. If offsetcnt == 2, OFFSETHI\\[7:0\\]
+will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration."]
+pub type OFFSETCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMD_SPEC, u8, u8, 2, O>;
+#[doc = "Field `CONT` reader - Contine to hold the bus after the current transaction if set to a 1 with a new command issued."]
+pub type CONT_R = crate::BitReader<bool>;
+#[doc = "Field `CONT` writer - Contine to hold the bus after the current transaction if set to a 1 with a new command issued."]
+pub type CONT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMD_SPEC, bool, O>;
+#[doc = "Field `TSIZE` reader - Defines the transaction size in bytes. The offset transfer is not included in this size."]
+pub type TSIZE_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `TSIZE` writer - Defines the transaction size in bytes. The offset transfer is not included in this size."]
+pub type TSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMD_SPEC, u16, u16, 12, O>;
+#[doc = "Field `CMDSEL` reader - Command Specific selection information"]
+pub type CMDSEL_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CMDSEL` writer - Command Specific selection information"]
+pub type CMDSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMD_SPEC, u8, u8, 2, O>;
+#[doc = "Field `OFFSETLO` reader - This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first."]
+pub type OFFSETLO_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `OFFSETLO` writer - This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first."]
+pub type OFFSETLO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMD_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:4 - Command for submodule."]
+    #[inline(always)]
+    pub fn cmd(&self) -> CMD_R {
+        CMD_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bits 5:6 - Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI\\[15:8\\]
+will be transmitted first, then OFFSETHI\\[7:0\\]
+then OFFSETLO. If offsetcnt == 2, OFFSETHI\\[7:0\\]
+will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration."]
+    #[inline(always)]
+    pub fn offsetcnt(&self) -> OFFSETCNT_R {
+        OFFSETCNT_R::new(((self.bits >> 5) & 3) as u8)
+    }
+    #[doc = "Bit 7 - Contine to hold the bus after the current transaction if set to a 1 with a new command issued."]
+    #[inline(always)]
+    pub fn cont(&self) -> CONT_R {
+        CONT_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bits 8:19 - Defines the transaction size in bytes. The offset transfer is not included in this size."]
+    #[inline(always)]
+    pub fn tsize(&self) -> TSIZE_R {
+        TSIZE_R::new(((self.bits >> 8) & 0x0fff) as u16)
+    }
+    #[doc = "Bits 20:21 - Command Specific selection information"]
+    #[inline(always)]
+    pub fn cmdsel(&self) -> CMDSEL_R {
+        CMDSEL_R::new(((self.bits >> 20) & 3) as u8)
+    }
+    #[doc = "Bits 24:31 - This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first."]
+    #[inline(always)]
+    pub fn offsetlo(&self) -> OFFSETLO_R {
+        OFFSETLO_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Command for submodule."]
+    #[inline(always)]
+    pub fn cmd(&mut self) -> CMD_W<0> {
+        CMD_W::new(self)
+    }
+    #[doc = "Bits 5:6 - Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI\\[15:8\\]
+will be transmitted first, then OFFSETHI\\[7:0\\]
+then OFFSETLO. If offsetcnt == 2, OFFSETHI\\[7:0\\]
+will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration."]
+    #[inline(always)]
+    pub fn offsetcnt(&mut self) -> OFFSETCNT_W<5> {
+        OFFSETCNT_W::new(self)
+    }
+    #[doc = "Bit 7 - Contine to hold the bus after the current transaction if set to a 1 with a new command issued."]
+    #[inline(always)]
+    pub fn cont(&mut self) -> CONT_W<7> {
+        CONT_W::new(self)
+    }
+    #[doc = "Bits 8:19 - Defines the transaction size in bytes. The offset transfer is not included in this size."]
+    #[inline(always)]
+    pub fn tsize(&mut self) -> TSIZE_W<8> {
+        TSIZE_W::new(self)
+    }
+    #[doc = "Bits 20:21 - Command Specific selection information"]
+    #[inline(always)]
+    pub fn cmdsel(&mut self) -> CMDSEL_W<20> {
+        CMDSEL_W::new(self)
+    }
+    #[doc = "Bits 24:31 - This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first."]
+    #[inline(always)]
+    pub fn offsetlo(&mut self) -> OFFSETLO_W<24> {
+        OFFSETLO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command and offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmd](index.html) module"]
+pub struct CMD_SPEC;
+impl crate::RegisterSpec for CMD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cmd::R](R) reader structure"]
+impl crate::Readable for CMD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cmd::W](W) writer structure"]
+impl crate::Writable for CMD_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CMD to value 0"]
+impl crate::Resettable for CMD_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cmdrpt.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CMDRPT` reader"]
+pub struct R(crate::R<CMDRPT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CMDRPT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CMDRPT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CMDRPT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CMDRPT` writer"]
+pub struct W(crate::W<CMDRPT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CMDRPT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CMDRPT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CMDRPT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CMDRPT` reader - Count of number of times to repeat the next command."]
+pub type CMDRPT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CMDRPT` writer - Count of number of times to repeat the next command."]
+pub type CMDRPT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDRPT_SPEC, u8, u8, 5, O>;
+impl R {
+    #[doc = "Bits 0:4 - Count of number of times to repeat the next command."]
+    #[inline(always)]
+    pub fn cmdrpt(&self) -> CMDRPT_R {
+        CMDRPT_R::new((self.bits & 0x1f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Count of number of times to repeat the next command."]
+    #[inline(always)]
+    pub fn cmdrpt(&mut self) -> CMDRPT_W<0> {
+        CMDRPT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command Repeat Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdrpt](index.html) module"]
+pub struct CMDRPT_SPEC;
+impl crate::RegisterSpec for CMDRPT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cmdrpt::R](R) reader structure"]
+impl crate::Readable for CMDRPT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cmdrpt::W](W) writer structure"]
+impl crate::Writable for CMDRPT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CMDRPT to value 0"]
+impl crate::Resettable for CMDRPT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cmdstat.rs

@@ -0,0 +1,183 @@
+#[doc = "Register `CMDSTAT` reader"]
+pub struct R(crate::R<CMDSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CMDSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CMDSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CMDSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CMDSTAT` writer"]
+pub struct W(crate::W<CMDSTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CMDSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CMDSTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CMDSTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CCMD` reader - current command that is being executed"]
+pub type CCMD_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CCMD` writer - current command that is being executed"]
+pub type CCMD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDSTAT_SPEC, u8, u8, 5, O>;
+#[doc = "Field `CMDSTAT` reader - The current status of the command execution."]
+pub type CMDSTAT_R = crate::FieldReader<u8, CMDSTAT_A>;
+#[doc = "The current status of the command execution.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CMDSTAT_A {
+    #[doc = "1: Error encountered with command value."]
+    ERR = 1,
+    #[doc = "2: Actively processing command value."]
+    ACTIVE = 2,
+    #[doc = "4: Idle state, no active command, no error value."]
+    IDLE = 4,
+    #[doc = "6: Command in progress, but waiting on data from host value."]
+    WAIT = 6,
+}
+impl From<CMDSTAT_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CMDSTAT_A) -> Self {
+        variant as _
+    }
+}
+impl CMDSTAT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CMDSTAT_A> {
+        match self.bits {
+            1 => Some(CMDSTAT_A::ERR),
+            2 => Some(CMDSTAT_A::ACTIVE),
+            4 => Some(CMDSTAT_A::IDLE),
+            6 => Some(CMDSTAT_A::WAIT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ERR`"]
+    #[inline(always)]
+    pub fn is_err(&self) -> bool {
+        *self == CMDSTAT_A::ERR
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE`"]
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == CMDSTAT_A::ACTIVE
+    }
+    #[doc = "Checks if the value of the field is `IDLE`"]
+    #[inline(always)]
+    pub fn is_idle(&self) -> bool {
+        *self == CMDSTAT_A::IDLE
+    }
+    #[doc = "Checks if the value of the field is `WAIT`"]
+    #[inline(always)]
+    pub fn is_wait(&self) -> bool {
+        *self == CMDSTAT_A::WAIT
+    }
+}
+#[doc = "Field `CMDSTAT` writer - The current status of the command execution."]
+pub type CMDSTAT_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, CMDSTAT_SPEC, u8, CMDSTAT_A, 3, O>;
+impl<'a, const O: u8> CMDSTAT_W<'a, O> {
+    #[doc = "Error encountered with command value."]
+    #[inline(always)]
+    pub fn err(self) -> &'a mut W {
+        self.variant(CMDSTAT_A::ERR)
+    }
+    #[doc = "Actively processing command value."]
+    #[inline(always)]
+    pub fn active(self) -> &'a mut W {
+        self.variant(CMDSTAT_A::ACTIVE)
+    }
+    #[doc = "Idle state, no active command, no error value."]
+    #[inline(always)]
+    pub fn idle(self) -> &'a mut W {
+        self.variant(CMDSTAT_A::IDLE)
+    }
+    #[doc = "Command in progress, but waiting on data from host value."]
+    #[inline(always)]
+    pub fn wait(self) -> &'a mut W {
+        self.variant(CMDSTAT_A::WAIT)
+    }
+}
+#[doc = "Field `CTSIZE` reader - The current number of bytes still to be transferred with this command. This field will count down to zero."]
+pub type CTSIZE_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `CTSIZE` writer - The current number of bytes still to be transferred with this command. This field will count down to zero."]
+pub type CTSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDSTAT_SPEC, u16, u16, 12, O>;
+impl R {
+    #[doc = "Bits 0:4 - current command that is being executed"]
+    #[inline(always)]
+    pub fn ccmd(&self) -> CCMD_R {
+        CCMD_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bits 5:7 - The current status of the command execution."]
+    #[inline(always)]
+    pub fn cmdstat(&self) -> CMDSTAT_R {
+        CMDSTAT_R::new(((self.bits >> 5) & 7) as u8)
+    }
+    #[doc = "Bits 8:19 - The current number of bytes still to be transferred with this command. This field will count down to zero."]
+    #[inline(always)]
+    pub fn ctsize(&self) -> CTSIZE_R {
+        CTSIZE_R::new(((self.bits >> 8) & 0x0fff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - current command that is being executed"]
+    #[inline(always)]
+    pub fn ccmd(&mut self) -> CCMD_W<0> {
+        CCMD_W::new(self)
+    }
+    #[doc = "Bits 5:7 - The current status of the command execution."]
+    #[inline(always)]
+    pub fn cmdstat(&mut self) -> CMDSTAT_W<5> {
+        CMDSTAT_W::new(self)
+    }
+    #[doc = "Bits 8:19 - The current number of bytes still to be transferred with this command. This field will count down to zero."]
+    #[inline(always)]
+    pub fn ctsize(&mut self) -> CTSIZE_W<8> {
+        CTSIZE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdstat](index.html) module"]
+pub struct CMDSTAT_SPEC;
+impl crate::RegisterSpec for CMDSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cmdstat::R](R) reader structure"]
+impl crate::Readable for CMDSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cmdstat::W](W) writer structure"]
+impl crate::Writable for CMDSTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CMDSTAT to value 0"]
+impl crate::Resettable for CMDSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqaddr.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `CQADDR` reader"]
+pub struct R(crate::R<CQADDR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQADDR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQADDR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQADDR` writer"]
+pub struct W(crate::W<CQADDR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQADDR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQADDR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQADDR` reader - Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary"]
+pub type CQADDR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `CQADDR` writer - Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary"]
+pub type CQADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQADDR_SPEC, u32, u32, 18, O>;
+#[doc = "Field `CQADDR28` reader - Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access"]
+pub type CQADDR28_R = crate::BitReader<bool>;
+#[doc = "Field `CQADDR28` writer - Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access"]
+pub type CQADDR28_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQADDR_SPEC, bool, O>;
+impl R {
+    #[doc = "Bits 2:19 - Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary"]
+    #[inline(always)]
+    pub fn cqaddr(&self) -> CQADDR_R {
+        CQADDR_R::new(((self.bits >> 2) & 0x0003_ffff) as u32)
+    }
+    #[doc = "Bit 28 - Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access"]
+    #[inline(always)]
+    pub fn cqaddr28(&self) -> CQADDR28_R {
+        CQADDR28_R::new(((self.bits >> 28) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 2:19 - Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary"]
+    #[inline(always)]
+    pub fn cqaddr(&mut self) -> CQADDR_W<2> {
+        CQADDR_W::new(self)
+    }
+    #[doc = "Bit 28 - Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access"]
+    #[inline(always)]
+    pub fn cqaddr28(&mut self) -> CQADDR28_W<28> {
+        CQADDR28_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "CQ Target Read Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqaddr](index.html) module"]
+pub struct CQADDR_SPEC;
+impl crate::RegisterSpec for CQADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqaddr::R](R) reader structure"]
+impl crate::Readable for CQADDR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqaddr::W](W) writer structure"]
+impl crate::Writable for CQADDR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQADDR to value 0"]
+impl crate::Resettable for CQADDR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqcfg.rs

@@ -0,0 +1,186 @@
+#[doc = "Register `CQCFG` reader"]
+pub struct R(crate::R<CQCFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQCFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQCFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQCFG` writer"]
+pub struct W(crate::W<CQCFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQCFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQCFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQEN` reader - Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well."]
+pub type CQEN_R = crate::BitReader<CQEN_A>;
+#[doc = "Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CQEN_A {
+    #[doc = "0: Disable CQ Function value."]
+    DIS = 0,
+    #[doc = "1: Enable CQ Function value."]
+    EN = 1,
+}
+impl From<CQEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: CQEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CQEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CQEN_A {
+        match self.bits {
+            false => CQEN_A::DIS,
+            true => CQEN_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == CQEN_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == CQEN_A::EN
+    }
+}
+#[doc = "Field `CQEN` writer - Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well."]
+pub type CQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQCFG_SPEC, CQEN_A, O>;
+impl<'a, const O: u8> CQEN_W<'a, O> {
+    #[doc = "Disable CQ Function value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(CQEN_A::DIS)
+    }
+    #[doc = "Enable CQ Function value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(CQEN_A::EN)
+    }
+}
+#[doc = "Field `CQPRI` reader - Sets the Priority of the command queue dma request."]
+pub type CQPRI_R = crate::BitReader<CQPRI_A>;
+#[doc = "Sets the Priority of the command queue dma request.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CQPRI_A {
+    #[doc = "0: Low Priority (service as best effort) value."]
+    LOW = 0,
+    #[doc = "1: High Priority (service immediately) value."]
+    HIGH = 1,
+}
+impl From<CQPRI_A> for bool {
+    #[inline(always)]
+    fn from(variant: CQPRI_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CQPRI_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CQPRI_A {
+        match self.bits {
+            false => CQPRI_A::LOW,
+            true => CQPRI_A::HIGH,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOW`"]
+    #[inline(always)]
+    pub fn is_low(&self) -> bool {
+        *self == CQPRI_A::LOW
+    }
+    #[doc = "Checks if the value of the field is `HIGH`"]
+    #[inline(always)]
+    pub fn is_high(&self) -> bool {
+        *self == CQPRI_A::HIGH
+    }
+}
+#[doc = "Field `CQPRI` writer - Sets the Priority of the command queue dma request."]
+pub type CQPRI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQCFG_SPEC, CQPRI_A, O>;
+impl<'a, const O: u8> CQPRI_W<'a, O> {
+    #[doc = "Low Priority (service as best effort) value."]
+    #[inline(always)]
+    pub fn low(self) -> &'a mut W {
+        self.variant(CQPRI_A::LOW)
+    }
+    #[doc = "High Priority (service immediately) value."]
+    #[inline(always)]
+    pub fn high(self) -> &'a mut W {
+        self.variant(CQPRI_A::HIGH)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well."]
+    #[inline(always)]
+    pub fn cqen(&self) -> CQEN_R {
+        CQEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Sets the Priority of the command queue dma request."]
+    #[inline(always)]
+    pub fn cqpri(&self) -> CQPRI_R {
+        CQPRI_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well."]
+    #[inline(always)]
+    pub fn cqen(&mut self) -> CQEN_W<0> {
+        CQEN_W::new(self)
+    }
+    #[doc = "Bit 1 - Sets the Priority of the command queue dma request."]
+    #[inline(always)]
+    pub fn cqpri(&mut self) -> CQPRI_W<1> {
+        CQPRI_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command Queue Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqcfg](index.html) module"]
+pub struct CQCFG_SPEC;
+impl crate::RegisterSpec for CQCFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqcfg::R](R) reader structure"]
+impl crate::Readable for CQCFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqcfg::W](W) writer structure"]
+impl crate::Writable for CQCFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQCFG to value 0"]
+impl crate::Resettable for CQCFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqcuridx.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CQCURIDX` reader"]
+pub struct R(crate::R<CQCURIDX_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQCURIDX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQCURIDX_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQCURIDX_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQCURIDX` writer"]
+pub struct W(crate::W<CQCURIDX_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQCURIDX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQCURIDX_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQCURIDX_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQCURIDX` reader - Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+pub type CQCURIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CQCURIDX` writer - Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+pub type CQCURIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQCURIDX_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+    #[inline(always)]
+    pub fn cqcuridx(&self) -> CQCURIDX_R {
+        CQCURIDX_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+    #[inline(always)]
+    pub fn cqcuridx(&mut self) -> CQCURIDX_W<0> {
+        CQCURIDX_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqcuridx](index.html) module"]
+pub struct CQCURIDX_SPEC;
+impl crate::RegisterSpec for CQCURIDX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqcuridx::R](R) reader structure"]
+impl crate::Readable for CQCURIDX_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqcuridx::W](W) writer structure"]
+impl crate::Writable for CQCURIDX_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQCURIDX to value 0"]
+impl crate::Resettable for CQCURIDX_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqendidx.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CQENDIDX` reader"]
+pub struct R(crate::R<CQENDIDX_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQENDIDX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQENDIDX_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQENDIDX_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQENDIDX` writer"]
+pub struct W(crate::W<CQENDIDX_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQENDIDX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQENDIDX_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQENDIDX_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQENDIDX` reader - Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+pub type CQENDIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CQENDIDX` writer - Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+pub type CQENDIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQENDIDX_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+    #[inline(always)]
+    pub fn cqendidx(&self) -> CQENDIDX_R {
+        CQENDIDX_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."]
+    #[inline(always)]
+    pub fn cqendidx(&mut self) -> CQENDIDX_W<0> {
+        CQENDIDX_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqendidx](index.html) module"]
+pub struct CQENDIDX_SPEC;
+impl crate::RegisterSpec for CQENDIDX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqendidx::R](R) reader structure"]
+impl crate::Readable for CQENDIDX_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqendidx::W](W) writer structure"]
+impl crate::Writable for CQENDIDX_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQENDIDX to value 0"]
+impl crate::Resettable for CQENDIDX_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqflags.rs

@@ -0,0 +1,102 @@
+#[doc = "Register `CQFLAGS` reader"]
+pub struct R(crate::R<CQFLAGS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQFLAGS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQFLAGS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQFLAGS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQFLAGS` writer"]
+pub struct W(crate::W<CQFLAGS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQFLAGS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQFLAGS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQFLAGS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQFLAGS` reader - Current flag status (read-only). Bits \\[7:0\\]
+are software controllable and bits \\[15:8\\]
+are hardware status."]
+pub type CQFLAGS_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `CQFLAGS` writer - Current flag status (read-only). Bits \\[7:0\\]
+are software controllable and bits \\[15:8\\]
+are hardware status."]
+pub type CQFLAGS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQFLAGS_SPEC, u16, u16, 16, O>;
+#[doc = "Field `CQIRQMASK` reader - Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"]
+pub type CQIRQMASK_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `CQIRQMASK` writer - Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"]
+pub type CQIRQMASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQFLAGS_SPEC, u16, u16, 16, O>;
+impl R {
+    #[doc = "Bits 0:15 - Current flag status (read-only). Bits \\[7:0\\]
+are software controllable and bits \\[15:8\\]
+are hardware status."]
+    #[inline(always)]
+    pub fn cqflags(&self) -> CQFLAGS_R {
+        CQFLAGS_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"]
+    #[inline(always)]
+    pub fn cqirqmask(&self) -> CQIRQMASK_R {
+        CQIRQMASK_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Current flag status (read-only). Bits \\[7:0\\]
+are software controllable and bits \\[15:8\\]
+are hardware status."]
+    #[inline(always)]
+    pub fn cqflags(&mut self) -> CQFLAGS_W<0> {
+        CQFLAGS_W::new(self)
+    }
+    #[doc = "Bits 16:31 - Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"]
+    #[inline(always)]
+    pub fn cqirqmask(&mut self) -> CQIRQMASK_W<16> {
+        CQIRQMASK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command Queue Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqflags](index.html) module"]
+pub struct CQFLAGS_SPEC;
+impl crate::RegisterSpec for CQFLAGS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqflags::R](R) reader structure"]
+impl crate::Readable for CQFLAGS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqflags::W](W) writer structure"]
+impl crate::Writable for CQFLAGS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQFLAGS to value 0"]
+impl crate::Resettable for CQFLAGS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqpauseen.rs

@@ -0,0 +1,311 @@
+#[doc = "Register `CQPAUSEEN` reader"]
+pub struct R(crate::R<CQPAUSEEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQPAUSEEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQPAUSEEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQPAUSEEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQPAUSEEN` writer"]
+pub struct W(crate::W<CQPAUSEEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQPAUSEEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQPAUSEEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQPAUSEEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQPEN` reader - Enables the specified event to pause command processing when active"]
+pub type CQPEN_R = crate::FieldReader<u16, CQPEN_A>;
+#[doc = "Enables the specified event to pause command processing when active\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u16)]
+pub enum CQPEN_A {
+    #[doc = "32768: Pauses command queue processing when HWCNT matches SWCNT value."]
+    CNTEQ = 32768,
+    #[doc = "16384: Pause command queue when input BLE bit XORed with SWFLAG4 is '1' value."]
+    BLEXOREN = 16384,
+    #[doc = "8192: Pause command queue when input IOM bit XORed with SWFLAG3 is '1' value."]
+    IOMXOREN = 8192,
+    #[doc = "4096: Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1' value."]
+    GPIOXOREN = 4096,
+    #[doc = "2048: Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1' value."]
+    MSPI1XNOREN = 2048,
+    #[doc = "1024: Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1' value."]
+    MSPI0XNOREN = 1024,
+    #[doc = "512: Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1' value."]
+    MSPI1XOREN = 512,
+    #[doc = "256: Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1' value."]
+    MSPI0XOREN = 256,
+    #[doc = "128: Pause the command queue when software flag bit 7 is '1'. value."]
+    SWFLAGEN7 = 128,
+    #[doc = "64: Pause the command queue when software flag bit 7 is '1' value."]
+    SWFLAGEN6 = 64,
+    #[doc = "32: Pause the command queue when software flag bit 7 is '1' value."]
+    SWFLAGEN5 = 32,
+    #[doc = "16: Pause the command queue when software flag bit 7 is '1' value."]
+    SWFLAGEN4 = 16,
+    #[doc = "8: Pause the command queue when software flag bit 7 is '1' value."]
+    SWFLAGEN3 = 8,
+    #[doc = "4: Pause the command queue when software flag bit 7 is '1' value."]
+    SWFLAGEN2 = 4,
+    #[doc = "2: Pause the command queue when software flag bit 7 is '1' value."]
+    SWFLAGEN1 = 2,
+    #[doc = "1: Pause the command queue when software flag bit 7 is '1' value."]
+    SWFLGEN0 = 1,
+}
+impl From<CQPEN_A> for u16 {
+    #[inline(always)]
+    fn from(variant: CQPEN_A) -> Self {
+        variant as _
+    }
+}
+impl CQPEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CQPEN_A> {
+        match self.bits {
+            32768 => Some(CQPEN_A::CNTEQ),
+            16384 => Some(CQPEN_A::BLEXOREN),
+            8192 => Some(CQPEN_A::IOMXOREN),
+            4096 => Some(CQPEN_A::GPIOXOREN),
+            2048 => Some(CQPEN_A::MSPI1XNOREN),
+            1024 => Some(CQPEN_A::MSPI0XNOREN),
+            512 => Some(CQPEN_A::MSPI1XOREN),
+            256 => Some(CQPEN_A::MSPI0XOREN),
+            128 => Some(CQPEN_A::SWFLAGEN7),
+            64 => Some(CQPEN_A::SWFLAGEN6),
+            32 => Some(CQPEN_A::SWFLAGEN5),
+            16 => Some(CQPEN_A::SWFLAGEN4),
+            8 => Some(CQPEN_A::SWFLAGEN3),
+            4 => Some(CQPEN_A::SWFLAGEN2),
+            2 => Some(CQPEN_A::SWFLAGEN1),
+            1 => Some(CQPEN_A::SWFLGEN0),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CNTEQ`"]
+    #[inline(always)]
+    pub fn is_cnteq(&self) -> bool {
+        *self == CQPEN_A::CNTEQ
+    }
+    #[doc = "Checks if the value of the field is `BLEXOREN`"]
+    #[inline(always)]
+    pub fn is_blexoren(&self) -> bool {
+        *self == CQPEN_A::BLEXOREN
+    }
+    #[doc = "Checks if the value of the field is `IOMXOREN`"]
+    #[inline(always)]
+    pub fn is_iomxoren(&self) -> bool {
+        *self == CQPEN_A::IOMXOREN
+    }
+    #[doc = "Checks if the value of the field is `GPIOXOREN`"]
+    #[inline(always)]
+    pub fn is_gpioxoren(&self) -> bool {
+        *self == CQPEN_A::GPIOXOREN
+    }
+    #[doc = "Checks if the value of the field is `MSPI1XNOREN`"]
+    #[inline(always)]
+    pub fn is_mspi1xnoren(&self) -> bool {
+        *self == CQPEN_A::MSPI1XNOREN
+    }
+    #[doc = "Checks if the value of the field is `MSPI0XNOREN`"]
+    #[inline(always)]
+    pub fn is_mspi0xnoren(&self) -> bool {
+        *self == CQPEN_A::MSPI0XNOREN
+    }
+    #[doc = "Checks if the value of the field is `MSPI1XOREN`"]
+    #[inline(always)]
+    pub fn is_mspi1xoren(&self) -> bool {
+        *self == CQPEN_A::MSPI1XOREN
+    }
+    #[doc = "Checks if the value of the field is `MSPI0XOREN`"]
+    #[inline(always)]
+    pub fn is_mspi0xoren(&self) -> bool {
+        *self == CQPEN_A::MSPI0XOREN
+    }
+    #[doc = "Checks if the value of the field is `SWFLAGEN7`"]
+    #[inline(always)]
+    pub fn is_swflagen7(&self) -> bool {
+        *self == CQPEN_A::SWFLAGEN7
+    }
+    #[doc = "Checks if the value of the field is `SWFLAGEN6`"]
+    #[inline(always)]
+    pub fn is_swflagen6(&self) -> bool {
+        *self == CQPEN_A::SWFLAGEN6
+    }
+    #[doc = "Checks if the value of the field is `SWFLAGEN5`"]
+    #[inline(always)]
+    pub fn is_swflagen5(&self) -> bool {
+        *self == CQPEN_A::SWFLAGEN5
+    }
+    #[doc = "Checks if the value of the field is `SWFLAGEN4`"]
+    #[inline(always)]
+    pub fn is_swflagen4(&self) -> bool {
+        *self == CQPEN_A::SWFLAGEN4
+    }
+    #[doc = "Checks if the value of the field is `SWFLAGEN3`"]
+    #[inline(always)]
+    pub fn is_swflagen3(&self) -> bool {
+        *self == CQPEN_A::SWFLAGEN3
+    }
+    #[doc = "Checks if the value of the field is `SWFLAGEN2`"]
+    #[inline(always)]
+    pub fn is_swflagen2(&self) -> bool {
+        *self == CQPEN_A::SWFLAGEN2
+    }
+    #[doc = "Checks if the value of the field is `SWFLAGEN1`"]
+    #[inline(always)]
+    pub fn is_swflagen1(&self) -> bool {
+        *self == CQPEN_A::SWFLAGEN1
+    }
+    #[doc = "Checks if the value of the field is `SWFLGEN0`"]
+    #[inline(always)]
+    pub fn is_swflgen0(&self) -> bool {
+        *self == CQPEN_A::SWFLGEN0
+    }
+}
+#[doc = "Field `CQPEN` writer - Enables the specified event to pause command processing when active"]
+pub type CQPEN_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, CQPAUSEEN_SPEC, u16, CQPEN_A, 16, O>;
+impl<'a, const O: u8> CQPEN_W<'a, O> {
+    #[doc = "Pauses command queue processing when HWCNT matches SWCNT value."]
+    #[inline(always)]
+    pub fn cnteq(self) -> &'a mut W {
+        self.variant(CQPEN_A::CNTEQ)
+    }
+    #[doc = "Pause command queue when input BLE bit XORed with SWFLAG4 is '1' value."]
+    #[inline(always)]
+    pub fn blexoren(self) -> &'a mut W {
+        self.variant(CQPEN_A::BLEXOREN)
+    }
+    #[doc = "Pause command queue when input IOM bit XORed with SWFLAG3 is '1' value."]
+    #[inline(always)]
+    pub fn iomxoren(self) -> &'a mut W {
+        self.variant(CQPEN_A::IOMXOREN)
+    }
+    #[doc = "Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1' value."]
+    #[inline(always)]
+    pub fn gpioxoren(self) -> &'a mut W {
+        self.variant(CQPEN_A::GPIOXOREN)
+    }
+    #[doc = "Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1' value."]
+    #[inline(always)]
+    pub fn mspi1xnoren(self) -> &'a mut W {
+        self.variant(CQPEN_A::MSPI1XNOREN)
+    }
+    #[doc = "Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1' value."]
+    #[inline(always)]
+    pub fn mspi0xnoren(self) -> &'a mut W {
+        self.variant(CQPEN_A::MSPI0XNOREN)
+    }
+    #[doc = "Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1' value."]
+    #[inline(always)]
+    pub fn mspi1xoren(self) -> &'a mut W {
+        self.variant(CQPEN_A::MSPI1XOREN)
+    }
+    #[doc = "Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1' value."]
+    #[inline(always)]
+    pub fn mspi0xoren(self) -> &'a mut W {
+        self.variant(CQPEN_A::MSPI0XOREN)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1'. value."]
+    #[inline(always)]
+    pub fn swflagen7(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLAGEN7)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1' value."]
+    #[inline(always)]
+    pub fn swflagen6(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLAGEN6)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1' value."]
+    #[inline(always)]
+    pub fn swflagen5(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLAGEN5)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1' value."]
+    #[inline(always)]
+    pub fn swflagen4(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLAGEN4)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1' value."]
+    #[inline(always)]
+    pub fn swflagen3(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLAGEN3)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1' value."]
+    #[inline(always)]
+    pub fn swflagen2(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLAGEN2)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1' value."]
+    #[inline(always)]
+    pub fn swflagen1(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLAGEN1)
+    }
+    #[doc = "Pause the command queue when software flag bit 7 is '1' value."]
+    #[inline(always)]
+    pub fn swflgen0(self) -> &'a mut W {
+        self.variant(CQPEN_A::SWFLGEN0)
+    }
+}
+impl R {
+    #[doc = "Bits 0:15 - Enables the specified event to pause command processing when active"]
+    #[inline(always)]
+    pub fn cqpen(&self) -> CQPEN_R {
+        CQPEN_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Enables the specified event to pause command processing when active"]
+    #[inline(always)]
+    pub fn cqpen(&mut self) -> CQPEN_W<0> {
+        CQPEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command Queue Pause Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqpauseen](index.html) module"]
+pub struct CQPAUSEEN_SPEC;
+impl crate::RegisterSpec for CQPAUSEEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqpauseen::R](R) reader structure"]
+impl crate::Readable for CQPAUSEEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqpauseen::W](W) writer structure"]
+impl crate::Writable for CQPAUSEEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQPAUSEEN to value 0"]
+impl crate::Resettable for CQPAUSEEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqsetclear.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `CQSETCLEAR` reader"]
+pub struct R(crate::R<CQSETCLEAR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQSETCLEAR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQSETCLEAR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQSETCLEAR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQSETCLEAR` writer"]
+pub struct W(crate::W<CQSETCLEAR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQSETCLEAR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQSETCLEAR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQSETCLEAR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQFSET` reader - Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+pub type CQFSET_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CQFSET` writer - Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+pub type CQFSET_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQSETCLEAR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `CQFTGL` reader - Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+pub type CQFTGL_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CQFTGL` writer - Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+pub type CQFTGL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQSETCLEAR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `CQFCLR` reader - Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"]
+pub type CQFCLR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CQFCLR` writer - Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"]
+pub type CQFCLR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CQSETCLEAR_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+    #[inline(always)]
+    pub fn cqfset(&self) -> CQFSET_R {
+        CQFSET_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+    #[inline(always)]
+    pub fn cqftgl(&self) -> CQFTGL_R {
+        CQFTGL_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"]
+    #[inline(always)]
+    pub fn cqfclr(&self) -> CQFCLR_R {
+        CQFCLR_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+    #[inline(always)]
+    pub fn cqfset(&mut self) -> CQFSET_W<0> {
+        CQFSET_W::new(self)
+    }
+    #[doc = "Bits 8:15 - Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"]
+    #[inline(always)]
+    pub fn cqftgl(&mut self) -> CQFTGL_W<8> {
+        CQFTGL_W::new(self)
+    }
+    #[doc = "Bits 16:23 - Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"]
+    #[inline(always)]
+    pub fn cqfclr(&mut self) -> CQFCLR_W<16> {
+        CQFCLR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command Queue Flag Set/Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqsetclear](index.html) module"]
+pub struct CQSETCLEAR_SPEC;
+impl crate::RegisterSpec for CQSETCLEAR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqsetclear::R](R) reader structure"]
+impl crate::Readable for CQSETCLEAR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqsetclear::W](W) writer structure"]
+impl crate::Writable for CQSETCLEAR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQSETCLEAR to value 0"]
+impl crate::Resettable for CQSETCLEAR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/cqstat.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `CQSTAT` reader"]
+pub struct R(crate::R<CQSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CQSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CQSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CQSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CQSTAT` writer"]
+pub struct W(crate::W<CQSTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CQSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CQSTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CQSTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CQTIP` reader - Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event."]
+pub type CQTIP_R = crate::BitReader<bool>;
+#[doc = "Field `CQTIP` writer - Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event."]
+pub type CQTIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQSTAT_SPEC, bool, O>;
+#[doc = "Field `CQPAUSED` reader - Command queue operation is currently paused."]
+pub type CQPAUSED_R = crate::BitReader<bool>;
+#[doc = "Field `CQPAUSED` writer - Command queue operation is currently paused."]
+pub type CQPAUSED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQSTAT_SPEC, bool, O>;
+#[doc = "Field `CQERR` reader - Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation."]
+pub type CQERR_R = crate::BitReader<bool>;
+#[doc = "Field `CQERR` writer - Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation."]
+pub type CQERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQSTAT_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event."]
+    #[inline(always)]
+    pub fn cqtip(&self) -> CQTIP_R {
+        CQTIP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Command queue operation is currently paused."]
+    #[inline(always)]
+    pub fn cqpaused(&self) -> CQPAUSED_R {
+        CQPAUSED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation."]
+    #[inline(always)]
+    pub fn cqerr(&self) -> CQERR_R {
+        CQERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event."]
+    #[inline(always)]
+    pub fn cqtip(&mut self) -> CQTIP_W<0> {
+        CQTIP_W::new(self)
+    }
+    #[doc = "Bit 1 - Command queue operation is currently paused."]
+    #[inline(always)]
+    pub fn cqpaused(&mut self) -> CQPAUSED_W<1> {
+        CQPAUSED_W::new(self)
+    }
+    #[doc = "Bit 2 - Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation."]
+    #[inline(always)]
+    pub fn cqerr(&mut self) -> CQERR_W<2> {
+        CQERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command Queue Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqstat](index.html) module"]
+pub struct CQSTAT_SPEC;
+impl crate::RegisterSpec for CQSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cqstat::R](R) reader structure"]
+impl crate::Readable for CQSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cqstat::W](W) writer structure"]
+impl crate::Writable for CQSTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CQSTAT to value 0"]
+impl crate::Resettable for CQSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/dmacfg.rs

@@ -0,0 +1,306 @@
+#[doc = "Register `DMACFG` reader"]
+pub struct R(crate::R<DMACFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMACFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMACFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMACFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMACFG` writer"]
+pub struct W(crate::W<DMACFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMACFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMACFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMACFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DMAEN` reader - DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command"]
+pub type DMAEN_R = crate::BitReader<DMAEN_A>;
+#[doc = "DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAEN_A {
+    #[doc = "0: Disable DMA Function value."]
+    DIS = 0,
+    #[doc = "1: Enable DMA Function value."]
+    EN = 1,
+}
+impl From<DMAEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMAEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMAEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMAEN_A {
+        match self.bits {
+            false => DMAEN_A::DIS,
+            true => DMAEN_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == DMAEN_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == DMAEN_A::EN
+    }
+}
+#[doc = "Field `DMAEN` writer - DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command"]
+pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMAEN_A, O>;
+impl<'a, const O: u8> DMAEN_W<'a, O> {
+    #[doc = "Disable DMA Function value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(DMAEN_A::DIS)
+    }
+    #[doc = "Enable DMA Function value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(DMAEN_A::EN)
+    }
+}
+#[doc = "Field `DMADIR` reader - Direction"]
+pub type DMADIR_R = crate::BitReader<DMADIR_A>;
+#[doc = "Direction\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMADIR_A {
+    #[doc = "0: Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices. value."]
+    P2M = 0,
+    #[doc = "1: Memory to Peripheral transaction. To be set when doing IOM write operations, ie writing data to external devices. value."]
+    M2P = 1,
+}
+impl From<DMADIR_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMADIR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMADIR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMADIR_A {
+        match self.bits {
+            false => DMADIR_A::P2M,
+            true => DMADIR_A::M2P,
+        }
+    }
+    #[doc = "Checks if the value of the field is `P2M`"]
+    #[inline(always)]
+    pub fn is_p2m(&self) -> bool {
+        *self == DMADIR_A::P2M
+    }
+    #[doc = "Checks if the value of the field is `M2P`"]
+    #[inline(always)]
+    pub fn is_m2p(&self) -> bool {
+        *self == DMADIR_A::M2P
+    }
+}
+#[doc = "Field `DMADIR` writer - Direction"]
+pub type DMADIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMADIR_A, O>;
+impl<'a, const O: u8> DMADIR_W<'a, O> {
+    #[doc = "Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices. value."]
+    #[inline(always)]
+    pub fn p2m(self) -> &'a mut W {
+        self.variant(DMADIR_A::P2M)
+    }
+    #[doc = "Memory to Peripheral transaction. To be set when doing IOM write operations, ie writing data to external devices. value."]
+    #[inline(always)]
+    pub fn m2p(self) -> &'a mut W {
+        self.variant(DMADIR_A::M2P)
+    }
+}
+#[doc = "Field `DMAPRI` reader - Sets the Priority of the DMA request"]
+pub type DMAPRI_R = crate::BitReader<DMAPRI_A>;
+#[doc = "Sets the Priority of the DMA request\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAPRI_A {
+    #[doc = "0: Low Priority (service as best effort) value."]
+    LOW = 0,
+    #[doc = "1: High Priority (service immediately) value."]
+    HIGH = 1,
+}
+impl From<DMAPRI_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMAPRI_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMAPRI_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMAPRI_A {
+        match self.bits {
+            false => DMAPRI_A::LOW,
+            true => DMAPRI_A::HIGH,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOW`"]
+    #[inline(always)]
+    pub fn is_low(&self) -> bool {
+        *self == DMAPRI_A::LOW
+    }
+    #[doc = "Checks if the value of the field is `HIGH`"]
+    #[inline(always)]
+    pub fn is_high(&self) -> bool {
+        *self == DMAPRI_A::HIGH
+    }
+}
+#[doc = "Field `DMAPRI` writer - Sets the Priority of the DMA request"]
+pub type DMAPRI_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DMAPRI_A, O>;
+impl<'a, const O: u8> DMAPRI_W<'a, O> {
+    #[doc = "Low Priority (service as best effort) value."]
+    #[inline(always)]
+    pub fn low(self) -> &'a mut W {
+        self.variant(DMAPRI_A::LOW)
+    }
+    #[doc = "High Priority (service immediately) value."]
+    #[inline(always)]
+    pub fn high(self) -> &'a mut W {
+        self.variant(DMAPRI_A::HIGH)
+    }
+}
+#[doc = "Field `DPWROFF` reader - Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed."]
+pub type DPWROFF_R = crate::BitReader<DPWROFF_A>;
+#[doc = "Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DPWROFF_A {
+    #[doc = "0: Power off disabled value."]
+    DIS = 0,
+    #[doc = "1: Power off enabled value."]
+    EN = 1,
+}
+impl From<DPWROFF_A> for bool {
+    #[inline(always)]
+    fn from(variant: DPWROFF_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DPWROFF_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DPWROFF_A {
+        match self.bits {
+            false => DPWROFF_A::DIS,
+            true => DPWROFF_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == DPWROFF_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == DPWROFF_A::EN
+    }
+}
+#[doc = "Field `DPWROFF` writer - Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed."]
+pub type DPWROFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACFG_SPEC, DPWROFF_A, O>;
+impl<'a, const O: u8> DPWROFF_W<'a, O> {
+    #[doc = "Power off disabled value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(DPWROFF_A::DIS)
+    }
+    #[doc = "Power off enabled value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(DPWROFF_A::EN)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command"]
+    #[inline(always)]
+    pub fn dmaen(&self) -> DMAEN_R {
+        DMAEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Direction"]
+    #[inline(always)]
+    pub fn dmadir(&self) -> DMADIR_R {
+        DMADIR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Sets the Priority of the DMA request"]
+    #[inline(always)]
+    pub fn dmapri(&self) -> DMAPRI_R {
+        DMAPRI_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed."]
+    #[inline(always)]
+    pub fn dpwroff(&self) -> DPWROFF_R {
+        DPWROFF_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command"]
+    #[inline(always)]
+    pub fn dmaen(&mut self) -> DMAEN_W<0> {
+        DMAEN_W::new(self)
+    }
+    #[doc = "Bit 1 - Direction"]
+    #[inline(always)]
+    pub fn dmadir(&mut self) -> DMADIR_W<1> {
+        DMADIR_W::new(self)
+    }
+    #[doc = "Bit 8 - Sets the Priority of the DMA request"]
+    #[inline(always)]
+    pub fn dmapri(&mut self) -> DMAPRI_W<8> {
+        DMAPRI_W::new(self)
+    }
+    #[doc = "Bit 9 - Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed."]
+    #[inline(always)]
+    pub fn dpwroff(&mut self) -> DPWROFF_W<9> {
+        DPWROFF_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacfg](index.html) module"]
+pub struct DMACFG_SPEC;
+impl crate::RegisterSpec for DMACFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmacfg::R](R) reader structure"]
+impl crate::Readable for DMACFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmacfg::W](W) writer structure"]
+impl crate::Writable for DMACFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMACFG to value 0"]
+impl crate::Resettable for DMACFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/dmastat.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `DMASTAT` reader"]
+pub struct R(crate::R<DMASTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMASTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMASTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMASTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMASTAT` writer"]
+pub struct W(crate::W<DMASTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMASTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMASTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMASTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DMATIP` reader - DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only."]
+pub type DMATIP_R = crate::BitReader<bool>;
+#[doc = "Field `DMATIP` writer - DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only."]
+pub type DMATIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMASTAT_SPEC, bool, O>;
+#[doc = "Field `DMACPL` reader - DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0."]
+pub type DMACPL_R = crate::BitReader<bool>;
+#[doc = "Field `DMACPL` writer - DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0."]
+pub type DMACPL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMASTAT_SPEC, bool, O>;
+#[doc = "Field `DMAERR` reader - DMA Error. This active high bit signals that an error was encountered during the DMA operation."]
+pub type DMAERR_R = crate::BitReader<bool>;
+#[doc = "Field `DMAERR` writer - DMA Error. This active high bit signals that an error was encountered during the DMA operation."]
+pub type DMAERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMASTAT_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only."]
+    #[inline(always)]
+    pub fn dmatip(&self) -> DMATIP_R {
+        DMATIP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0."]
+    #[inline(always)]
+    pub fn dmacpl(&self) -> DMACPL_R {
+        DMACPL_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA Error. This active high bit signals that an error was encountered during the DMA operation."]
+    #[inline(always)]
+    pub fn dmaerr(&self) -> DMAERR_R {
+        DMAERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only."]
+    #[inline(always)]
+    pub fn dmatip(&mut self) -> DMATIP_W<0> {
+        DMATIP_W::new(self)
+    }
+    #[doc = "Bit 1 - DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0."]
+    #[inline(always)]
+    pub fn dmacpl(&mut self) -> DMACPL_W<1> {
+        DMACPL_W::new(self)
+    }
+    #[doc = "Bit 2 - DMA Error. This active high bit signals that an error was encountered during the DMA operation."]
+    #[inline(always)]
+    pub fn dmaerr(&mut self) -> DMAERR_W<2> {
+        DMAERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmastat](index.html) module"]
+pub struct DMASTAT_SPEC;
+impl crate::RegisterSpec for DMASTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmastat::R](R) reader structure"]
+impl crate::Readable for DMASTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmastat::W](W) writer structure"]
+impl crate::Writable for DMASTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMASTAT to value 0"]
+impl crate::Resettable for DMASTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/dmatargaddr.rs

@@ -0,0 +1,99 @@
+#[doc = "Register `DMATARGADDR` reader"]
+pub struct R(crate::R<DMATARGADDR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATARGADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATARGADDR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATARGADDR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATARGADDR` writer"]
+pub struct W(crate::W<DMATARGADDR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATARGADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATARGADDR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATARGADDR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TARGADDR` reader - Bits \\[19:0\\]
+of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written."]
+pub type TARGADDR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `TARGADDR` writer - Bits \\[19:0\\]
+of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written."]
+pub type TARGADDR_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DMATARGADDR_SPEC, u32, u32, 20, O>;
+#[doc = "Field `TARGADDR28` reader - Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash"]
+pub type TARGADDR28_R = crate::BitReader<bool>;
+#[doc = "Field `TARGADDR28` writer - Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash"]
+pub type TARGADDR28_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATARGADDR_SPEC, bool, O>;
+impl R {
+    #[doc = "Bits 0:19 - Bits \\[19:0\\]
+of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written."]
+    #[inline(always)]
+    pub fn targaddr(&self) -> TARGADDR_R {
+        TARGADDR_R::new((self.bits & 0x000f_ffff) as u32)
+    }
+    #[doc = "Bit 28 - Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash"]
+    #[inline(always)]
+    pub fn targaddr28(&self) -> TARGADDR28_R {
+        TARGADDR28_R::new(((self.bits >> 28) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - Bits \\[19:0\\]
+of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written."]
+    #[inline(always)]
+    pub fn targaddr(&mut self) -> TARGADDR_W<0> {
+        TARGADDR_W::new(self)
+    }
+    #[doc = "Bit 28 - Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash"]
+    #[inline(always)]
+    pub fn targaddr28(&mut self) -> TARGADDR28_W<28> {
+        TARGADDR28_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Target Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatargaddr](index.html) module"]
+pub struct DMATARGADDR_SPEC;
+impl crate::RegisterSpec for DMATARGADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatargaddr::R](R) reader structure"]
+impl crate::Readable for DMATARGADDR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatargaddr::W](W) writer structure"]
+impl crate::Writable for DMATARGADDR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATARGADDR to value 0"]
+impl crate::Resettable for DMATARGADDR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/dmatotcount.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `DMATOTCOUNT` reader"]
+pub struct R(crate::R<DMATOTCOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATOTCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATOTCOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATOTCOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATOTCOUNT` writer"]
+pub struct W(crate::W<DMATOTCOUNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATOTCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATOTCOUNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATOTCOUNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TOTCOUNT` reader - Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+pub type TOTCOUNT_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `TOTCOUNT` writer - Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+pub type TOTCOUNT_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DMATOTCOUNT_SPEC, u16, u16, 12, O>;
+impl R {
+    #[doc = "Bits 0:11 - Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+    #[inline(always)]
+    pub fn totcount(&self) -> TOTCOUNT_R {
+        TOTCOUNT_R::new((self.bits & 0x0fff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:11 - Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+    #[inline(always)]
+    pub fn totcount(&mut self) -> TOTCOUNT_W<0> {
+        TOTCOUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Total Transfer Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatotcount](index.html) module"]
+pub struct DMATOTCOUNT_SPEC;
+impl crate::RegisterSpec for DMATOTCOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatotcount::R](R) reader structure"]
+impl crate::Readable for DMATOTCOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatotcount::W](W) writer structure"]
+impl crate::Writable for DMATOTCOUNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATOTCOUNT to value 0"]
+impl crate::Resettable for DMATOTCOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/dmatrigen.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `DMATRIGEN` reader"]
+pub struct R(crate::R<DMATRIGEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATRIGEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATRIGEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATRIGEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATRIGEN` writer"]
+pub struct W(crate::W<DMATRIGEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATRIGEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATRIGEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATRIGEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DCMDCMPEN` reader - Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed."]
+pub type DCMDCMPEN_R = crate::BitReader<bool>;
+#[doc = "Field `DCMDCMPEN` writer - Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed."]
+pub type DCMDCMPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGEN_SPEC, bool, O>;
+#[doc = "Field `DTHREN` reader - Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the commmand. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete."]
+pub type DTHREN_R = crate::BitReader<bool>;
+#[doc = "Field `DTHREN` writer - Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the commmand. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete."]
+pub type DTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGEN_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed."]
+    #[inline(always)]
+    pub fn dcmdcmpen(&self) -> DCMDCMPEN_R {
+        DCMDCMPEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the commmand. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete."]
+    #[inline(always)]
+    pub fn dthren(&self) -> DTHREN_R {
+        DTHREN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed."]
+    #[inline(always)]
+    pub fn dcmdcmpen(&mut self) -> DCMDCMPEN_W<0> {
+        DCMDCMPEN_W::new(self)
+    }
+    #[doc = "Bit 1 - Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the commmand. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete."]
+    #[inline(always)]
+    pub fn dthren(&mut self) -> DTHREN_W<1> {
+        DTHREN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Trigger Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatrigen](index.html) module"]
+pub struct DMATRIGEN_SPEC;
+impl crate::RegisterSpec for DMATRIGEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatrigen::R](R) reader structure"]
+impl crate::Readable for DMATRIGEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatrigen::W](W) writer structure"]
+impl crate::Writable for DMATRIGEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATRIGEN to value 0"]
+impl crate::Resettable for DMATRIGEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/dmatrigstat.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `DMATRIGSTAT` reader"]
+pub struct R(crate::R<DMATRIGSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMATRIGSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMATRIGSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMATRIGSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMATRIGSTAT` writer"]
+pub struct W(crate::W<DMATRIGSTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMATRIGSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMATRIGSTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMATRIGSTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DCMDCMP` reader - Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA."]
+pub type DCMDCMP_R = crate::BitReader<bool>;
+#[doc = "Field `DCMDCMP` writer - Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA."]
+pub type DCMDCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGSTAT_SPEC, bool, O>;
+#[doc = "Field `DTHR` reader - Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+pub type DTHR_R = crate::BitReader<bool>;
+#[doc = "Field `DTHR` writer - Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+pub type DTHR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGSTAT_SPEC, bool, O>;
+#[doc = "Field `DTOTCMP` reader - DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation."]
+pub type DTOTCMP_R = crate::BitReader<bool>;
+#[doc = "Field `DTOTCMP` writer - DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation."]
+pub type DTOTCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMATRIGSTAT_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA."]
+    #[inline(always)]
+    pub fn dcmdcmp(&self) -> DCMDCMP_R {
+        DCMDCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+    #[inline(always)]
+    pub fn dthr(&self) -> DTHR_R {
+        DTHR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation."]
+    #[inline(always)]
+    pub fn dtotcmp(&self) -> DTOTCMP_R {
+        DTOTCMP_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA."]
+    #[inline(always)]
+    pub fn dcmdcmp(&mut self) -> DCMDCMP_W<0> {
+        DCMDCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."]
+    #[inline(always)]
+    pub fn dthr(&mut self) -> DTHR_W<1> {
+        DTHR_W::new(self)
+    }
+    #[doc = "Bit 2 - DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation."]
+    #[inline(always)]
+    pub fn dtotcmp(&mut self) -> DTOTCMP_W<2> {
+        DTOTCMP_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DMA Trigger Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatrigstat](index.html) module"]
+pub struct DMATRIGSTAT_SPEC;
+impl crate::RegisterSpec for DMATRIGSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmatrigstat::R](R) reader structure"]
+impl crate::Readable for DMATRIGSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmatrigstat::W](W) writer structure"]
+impl crate::Writable for DMATRIGSTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMATRIGSTAT to value 0"]
+impl crate::Resettable for DMATRIGSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/fifo.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `FIFO` reader"]
+pub struct R(crate::R<FIFO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFO` writer"]
+pub struct W(crate::W<FIFO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FIFO` reader - FIFO direct access. Only locations 0 - 3F will return valid information."]
+pub type FIFO_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `FIFO` writer - FIFO direct access. Only locations 0 - 3F will return valid information."]
+pub type FIFO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - FIFO direct access. Only locations 0 - 3F will return valid information."]
+    #[inline(always)]
+    pub fn fifo(&self) -> FIFO_R {
+        FIFO_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - FIFO direct access. Only locations 0 - 3F will return valid information."]
+    #[inline(always)]
+    pub fn fifo(&mut self) -> FIFO_W<0> {
+        FIFO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO Access Port\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"]
+pub struct FIFO_SPEC;
+impl crate::RegisterSpec for FIFO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifo::R](R) reader structure"]
+impl crate::Readable for FIFO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"]
+impl crate::Writable for FIFO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFO to value 0"]
+impl crate::Resettable for FIFO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/fifoctrl.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `FIFOCTRL` reader"]
+pub struct R(crate::R<FIFOCTRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFOCTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFOCTRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFOCTRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFOCTRL` writer"]
+pub struct W(crate::W<FIFOCTRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFOCTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFOCTRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFOCTRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POPWR` reader - Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode."]
+pub type POPWR_R = crate::BitReader<bool>;
+#[doc = "Field `POPWR` writer - Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode."]
+pub type POPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCTRL_SPEC, bool, O>;
+#[doc = "Field `FIFORSTN` reader - Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset."]
+pub type FIFORSTN_R = crate::BitReader<bool>;
+#[doc = "Field `FIFORSTN` writer - Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset."]
+pub type FIFORSTN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCTRL_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode."]
+    #[inline(always)]
+    pub fn popwr(&self) -> POPWR_R {
+        POPWR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset."]
+    #[inline(always)]
+    pub fn fiforstn(&self) -> FIFORSTN_R {
+        FIFORSTN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode."]
+    #[inline(always)]
+    pub fn popwr(&mut self) -> POPWR_W<0> {
+        POPWR_W::new(self)
+    }
+    #[doc = "Bit 1 - Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset."]
+    #[inline(always)]
+    pub fn fiforstn(&mut self) -> FIFORSTN_W<1> {
+        FIFORSTN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifoctrl](index.html) module"]
+pub struct FIFOCTRL_SPEC;
+impl crate::RegisterSpec for FIFOCTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifoctrl::R](R) reader structure"]
+impl crate::Readable for FIFOCTRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifoctrl::W](W) writer structure"]
+impl crate::Writable for FIFOCTRL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFOCTRL to value 0x02"]
+impl crate::Resettable for FIFOCTRL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x02
+    }
+}

apollo3-pac/src/bleif/fifoloc.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `FIFOLOC` reader"]
+pub struct R(crate::R<FIFOLOC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFOLOC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFOLOC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFOLOC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFOLOC` writer"]
+pub struct W(crate::W<FIFOLOC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFOLOC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFOLOC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFOLOC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FIFOWPTR` reader - Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices."]
+pub type FIFOWPTR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFOWPTR` writer - Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices."]
+pub type FIFOWPTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOLOC_SPEC, u8, u8, 4, O>;
+#[doc = "Field `FIFORPTR` reader - Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation."]
+pub type FIFORPTR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFORPTR` writer - Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation."]
+pub type FIFORPTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOLOC_SPEC, u8, u8, 4, O>;
+impl R {
+    #[doc = "Bits 0:3 - Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices."]
+    #[inline(always)]
+    pub fn fifowptr(&self) -> FIFOWPTR_R {
+        FIFOWPTR_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 8:11 - Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation."]
+    #[inline(always)]
+    pub fn fiforptr(&self) -> FIFORPTR_R {
+        FIFORPTR_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices."]
+    #[inline(always)]
+    pub fn fifowptr(&mut self) -> FIFOWPTR_W<0> {
+        FIFOWPTR_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation."]
+    #[inline(always)]
+    pub fn fiforptr(&mut self) -> FIFORPTR_W<8> {
+        FIFORPTR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO Pointers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifoloc](index.html) module"]
+pub struct FIFOLOC_SPEC;
+impl crate::RegisterSpec for FIFOLOC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifoloc::R](R) reader structure"]
+impl crate::Readable for FIFOLOC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifoloc::W](W) writer structure"]
+impl crate::Writable for FIFOLOC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFOLOC to value 0"]
+impl crate::Resettable for FIFOLOC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/fifopop.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `FIFOPOP` reader"]
+pub struct R(crate::R<FIFOPOP_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFOPOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFOPOP_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFOPOP_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFOPOP` writer"]
+pub struct W(crate::W<FIFOPOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFOPOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFOPOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFOPOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FIFODOUT` reader - This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word."]
+pub type FIFODOUT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `FIFODOUT` writer - This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word."]
+pub type FIFODOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPOP_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word."]
+    #[inline(always)]
+    pub fn fifodout(&self) -> FIFODOUT_R {
+        FIFODOUT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word."]
+    #[inline(always)]
+    pub fn fifodout(&mut self) -> FIFODOUT_W<0> {
+        FIFODOUT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO POP register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifopop](index.html) module"]
+pub struct FIFOPOP_SPEC;
+impl crate::RegisterSpec for FIFOPOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifopop::R](R) reader structure"]
+impl crate::Readable for FIFOPOP_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifopop::W](W) writer structure"]
+impl crate::Writable for FIFOPOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFOPOP to value 0"]
+impl crate::Resettable for FIFOPOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/fifoptr.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `FIFOPTR` reader"]
+pub struct R(crate::R<FIFOPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFOPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFOPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFOPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFOPTR` writer"]
+pub struct W(crate::W<FIFOPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFOPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFOPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFOPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FIFO0SIZ` reader - The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)"]
+pub type FIFO0SIZ_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFO0SIZ` writer - The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)"]
+pub type FIFO0SIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPTR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `FIFO0REM` reader - The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)"]
+pub type FIFO0REM_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFO0REM` writer - The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)"]
+pub type FIFO0REM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPTR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `FIFO1SIZ` reader - The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)"]
+pub type FIFO1SIZ_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFO1SIZ` writer - The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)"]
+pub type FIFO1SIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPTR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `FIFO1REM` reader - The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)"]
+pub type FIFO1REM_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFO1REM` writer - The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)"]
+pub type FIFO1REM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPTR_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)"]
+    #[inline(always)]
+    pub fn fifo0siz(&self) -> FIFO0SIZ_R {
+        FIFO0SIZ_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)"]
+    #[inline(always)]
+    pub fn fifo0rem(&self) -> FIFO0REM_R {
+        FIFO0REM_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)"]
+    #[inline(always)]
+    pub fn fifo1siz(&self) -> FIFO1SIZ_R {
+        FIFO1SIZ_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)"]
+    #[inline(always)]
+    pub fn fifo1rem(&self) -> FIFO1REM_R {
+        FIFO1REM_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)"]
+    #[inline(always)]
+    pub fn fifo0siz(&mut self) -> FIFO0SIZ_W<0> {
+        FIFO0SIZ_W::new(self)
+    }
+    #[doc = "Bits 8:15 - The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)"]
+    #[inline(always)]
+    pub fn fifo0rem(&mut self) -> FIFO0REM_W<8> {
+        FIFO0REM_W::new(self)
+    }
+    #[doc = "Bits 16:23 - The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)"]
+    #[inline(always)]
+    pub fn fifo1siz(&mut self) -> FIFO1SIZ_W<16> {
+        FIFO1SIZ_W::new(self)
+    }
+    #[doc = "Bits 24:31 - The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)"]
+    #[inline(always)]
+    pub fn fifo1rem(&mut self) -> FIFO1REM_W<24> {
+        FIFO1REM_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO size and remaining slots open values\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifoptr](index.html) module"]
+pub struct FIFOPTR_SPEC;
+impl crate::RegisterSpec for FIFOPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifoptr::R](R) reader structure"]
+impl crate::Readable for FIFOPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifoptr::W](W) writer structure"]
+impl crate::Writable for FIFOPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFOPTR to value 0"]
+impl crate::Resettable for FIFOPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/fifopush.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `FIFOPUSH` reader"]
+pub struct R(crate::R<FIFOPUSH_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFOPUSH_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFOPUSH_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFOPUSH_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFOPUSH` writer"]
+pub struct W(crate::W<FIFOPUSH_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFOPUSH_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFOPUSH_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFOPUSH_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FIFODIN` reader - This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."]
+pub type FIFODIN_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `FIFODIN` writer - This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."]
+pub type FIFODIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOPUSH_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."]
+    #[inline(always)]
+    pub fn fifodin(&self) -> FIFODIN_R {
+        FIFODIN_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."]
+    #[inline(always)]
+    pub fn fifodin(&mut self) -> FIFODIN_W<0> {
+        FIFODIN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO PUSH register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifopush](index.html) module"]
+pub struct FIFOPUSH_SPEC;
+impl crate::RegisterSpec for FIFOPUSH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifopush::R](R) reader structure"]
+impl crate::Readable for FIFOPUSH_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifopush::W](W) writer structure"]
+impl crate::Writable for FIFOPUSH_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFOPUSH to value 0"]
+impl crate::Resettable for FIFOPUSH_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/fifothr.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `FIFOTHR` reader"]
+pub struct R(crate::R<FIFOTHR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FIFOTHR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FIFOTHR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FIFOTHR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FIFOTHR` writer"]
+pub struct W(crate::W<FIFOTHR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFOTHR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFOTHR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFOTHR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FIFORTHR` reader - FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations."]
+pub type FIFORTHR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFORTHR` writer - FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations."]
+pub type FIFORTHR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOTHR_SPEC, u8, u8, 6, O>;
+#[doc = "Field `FIFOWTHR` reader - FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations."]
+pub type FIFOWTHR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `FIFOWTHR` writer - FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations."]
+pub type FIFOWTHR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOTHR_SPEC, u8, u8, 6, O>;
+impl R {
+    #[doc = "Bits 0:5 - FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations."]
+    #[inline(always)]
+    pub fn fiforthr(&self) -> FIFORTHR_R {
+        FIFORTHR_R::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bits 8:13 - FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations."]
+    #[inline(always)]
+    pub fn fifowthr(&self) -> FIFOWTHR_R {
+        FIFOWTHR_R::new(((self.bits >> 8) & 0x3f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations."]
+    #[inline(always)]
+    pub fn fiforthr(&mut self) -> FIFORTHR_W<0> {
+        FIFORTHR_W::new(self)
+    }
+    #[doc = "Bits 8:13 - FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations."]
+    #[inline(always)]
+    pub fn fifowthr(&mut self) -> FIFOWTHR_W<8> {
+        FIFOWTHR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "FIFO Threshold Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifothr](index.html) module"]
+pub struct FIFOTHR_SPEC;
+impl crate::RegisterSpec for FIFOTHR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [fifothr::R](R) reader structure"]
+impl crate::Readable for FIFOTHR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [fifothr::W](W) writer structure"]
+impl crate::Writable for FIFOTHR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFOTHR to value 0"]
+impl crate::Resettable for FIFOTHR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/intclr.rs

@@ -0,0 +1,304 @@
+#[doc = "Register `INTCLR` reader"]
+pub struct R(crate::R<INTCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTCLR` writer"]
+pub struct W(crate::W<INTCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CMDCMP` reader - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_R = crate::BitReader<bool>;
+#[doc = "Field `CMDCMP` writer - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `THR` reader - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_R = crate::BitReader<bool>;
+#[doc = "Field `THR` writer - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `FUNDFL` reader - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_R = crate::BitReader<bool>;
+#[doc = "Field `FUNDFL` writer - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `FOVFL` reader - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_R = crate::BitReader<bool>;
+#[doc = "Field `FOVFL` writer - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `B2MST` reader - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_R = crate::BitReader<bool>;
+#[doc = "Field `B2MST` writer - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `IACC` reader - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_R = crate::BitReader<bool>;
+#[doc = "Field `IACC` writer - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `ICMD` reader - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_R = crate::BitReader<bool>;
+#[doc = "Field `ICMD` writer - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `BLECIRQ` reader - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_R = crate::BitReader<bool>;
+#[doc = "Field `BLECIRQ` writer - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `BLECSSTAT` reader - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_R = crate::BitReader<bool>;
+#[doc = "Field `BLECSSTAT` writer - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `DCMP` reader - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_R = crate::BitReader<bool>;
+#[doc = "Field `DCMP` writer - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `DERR` reader - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_R = crate::BitReader<bool>;
+#[doc = "Field `DERR` writer - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `CQPAUSED` reader - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_R = crate::BitReader<bool>;
+#[doc = "Field `CQPAUSED` writer - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `CQUPD` reader - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_R = crate::BitReader<bool>;
+#[doc = "Field `CQUPD` writer - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `CQERR` reader - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_R = crate::BitReader<bool>;
+#[doc = "Field `CQERR` writer - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `B2MSLEEP` reader - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSLEEP` writer - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `B2MACTIVE` reader - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_R = crate::BitReader<bool>;
+#[doc = "Field `B2MACTIVE` writer - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+#[doc = "Field `B2MSHUTDN` reader - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSHUTDN` writer - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTCLR_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&self) -> CMDCMP_R {
+        CMDCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&self) -> THR_R {
+        THR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&self) -> FUNDFL_R {
+        FUNDFL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&self) -> FOVFL_R {
+        FOVFL_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&self) -> B2MST_R {
+        B2MST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&self) -> IACC_R {
+        IACC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&self) -> ICMD_R {
+        ICMD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&self) -> BLECIRQ_R {
+        BLECIRQ_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&self) -> BLECSSTAT_R {
+        BLECSSTAT_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&self) -> CQPAUSED_R {
+        CQPAUSED_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&self) -> CQUPD_R {
+        CQUPD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&self) -> CQERR_R {
+        CQERR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&self) -> B2MSLEEP_R {
+        B2MSLEEP_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&self) -> B2MACTIVE_R {
+        B2MACTIVE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&self) -> B2MSHUTDN_R {
+        B2MSHUTDN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&mut self) -> CMDCMP_W<0> {
+        CMDCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&mut self) -> THR_W<1> {
+        THR_W::new(self)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&mut self) -> FUNDFL_W<2> {
+        FUNDFL_W::new(self)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&mut self) -> FOVFL_W<3> {
+        FOVFL_W::new(self)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&mut self) -> B2MST_W<4> {
+        B2MST_W::new(self)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&mut self) -> IACC_W<5> {
+        IACC_W::new(self)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&mut self) -> ICMD_W<6> {
+        ICMD_W::new(self)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&mut self) -> BLECIRQ_W<7> {
+        BLECIRQ_W::new(self)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&mut self) -> BLECSSTAT_W<8> {
+        BLECSSTAT_W::new(self)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<9> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<10> {
+        DERR_W::new(self)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&mut self) -> CQPAUSED_W<11> {
+        CQPAUSED_W::new(self)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&mut self) -> CQUPD_W<12> {
+        CQUPD_W::new(self)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&mut self) -> CQERR_W<13> {
+        CQERR_W::new(self)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&mut self) -> B2MSLEEP_W<14> {
+        B2MSLEEP_W::new(self)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&mut self) -> B2MACTIVE_W<15> {
+        B2MACTIVE_W::new(self)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W<16> {
+        B2MSHUTDN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "IO Master Interrupts: Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intclr](index.html) module"]
+pub struct INTCLR_SPEC;
+impl crate::RegisterSpec for INTCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intclr::R](R) reader structure"]
+impl crate::Readable for INTCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intclr::W](W) writer structure"]
+impl crate::Writable for INTCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTCLR to value 0"]
+impl crate::Resettable for INTCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/inten.rs

@@ -0,0 +1,304 @@
+#[doc = "Register `INTEN` reader"]
+pub struct R(crate::R<INTEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTEN` writer"]
+pub struct W(crate::W<INTEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CMDCMP` reader - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_R = crate::BitReader<bool>;
+#[doc = "Field `CMDCMP` writer - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `THR` reader - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_R = crate::BitReader<bool>;
+#[doc = "Field `THR` writer - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `FUNDFL` reader - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_R = crate::BitReader<bool>;
+#[doc = "Field `FUNDFL` writer - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `FOVFL` reader - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_R = crate::BitReader<bool>;
+#[doc = "Field `FOVFL` writer - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `B2MST` reader - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_R = crate::BitReader<bool>;
+#[doc = "Field `B2MST` writer - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `IACC` reader - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_R = crate::BitReader<bool>;
+#[doc = "Field `IACC` writer - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `ICMD` reader - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_R = crate::BitReader<bool>;
+#[doc = "Field `ICMD` writer - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `BLECIRQ` reader - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_R = crate::BitReader<bool>;
+#[doc = "Field `BLECIRQ` writer - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `BLECSSTAT` reader - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_R = crate::BitReader<bool>;
+#[doc = "Field `BLECSSTAT` writer - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `DCMP` reader - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_R = crate::BitReader<bool>;
+#[doc = "Field `DCMP` writer - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `DERR` reader - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_R = crate::BitReader<bool>;
+#[doc = "Field `DERR` writer - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `CQPAUSED` reader - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_R = crate::BitReader<bool>;
+#[doc = "Field `CQPAUSED` writer - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `CQUPD` reader - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_R = crate::BitReader<bool>;
+#[doc = "Field `CQUPD` writer - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `CQERR` reader - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_R = crate::BitReader<bool>;
+#[doc = "Field `CQERR` writer - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `B2MSLEEP` reader - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSLEEP` writer - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `B2MACTIVE` reader - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_R = crate::BitReader<bool>;
+#[doc = "Field `B2MACTIVE` writer - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+#[doc = "Field `B2MSHUTDN` reader - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSHUTDN` writer - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&self) -> CMDCMP_R {
+        CMDCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&self) -> THR_R {
+        THR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&self) -> FUNDFL_R {
+        FUNDFL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&self) -> FOVFL_R {
+        FOVFL_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&self) -> B2MST_R {
+        B2MST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&self) -> IACC_R {
+        IACC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&self) -> ICMD_R {
+        ICMD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&self) -> BLECIRQ_R {
+        BLECIRQ_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&self) -> BLECSSTAT_R {
+        BLECSSTAT_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&self) -> CQPAUSED_R {
+        CQPAUSED_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&self) -> CQUPD_R {
+        CQUPD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&self) -> CQERR_R {
+        CQERR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&self) -> B2MSLEEP_R {
+        B2MSLEEP_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&self) -> B2MACTIVE_R {
+        B2MACTIVE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&self) -> B2MSHUTDN_R {
+        B2MSHUTDN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&mut self) -> CMDCMP_W<0> {
+        CMDCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&mut self) -> THR_W<1> {
+        THR_W::new(self)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&mut self) -> FUNDFL_W<2> {
+        FUNDFL_W::new(self)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&mut self) -> FOVFL_W<3> {
+        FOVFL_W::new(self)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&mut self) -> B2MST_W<4> {
+        B2MST_W::new(self)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&mut self) -> IACC_W<5> {
+        IACC_W::new(self)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&mut self) -> ICMD_W<6> {
+        ICMD_W::new(self)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&mut self) -> BLECIRQ_W<7> {
+        BLECIRQ_W::new(self)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&mut self) -> BLECSSTAT_W<8> {
+        BLECSSTAT_W::new(self)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<9> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<10> {
+        DERR_W::new(self)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&mut self) -> CQPAUSED_W<11> {
+        CQPAUSED_W::new(self)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&mut self) -> CQUPD_W<12> {
+        CQUPD_W::new(self)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&mut self) -> CQERR_W<13> {
+        CQERR_W::new(self)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&mut self) -> B2MSLEEP_W<14> {
+        B2MSLEEP_W::new(self)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&mut self) -> B2MACTIVE_W<15> {
+        B2MACTIVE_W::new(self)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W<16> {
+        B2MSHUTDN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "IO Master Interrupts: Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
+pub struct INTEN_SPEC;
+impl crate::RegisterSpec for INTEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [inten::R](R) reader structure"]
+impl crate::Readable for INTEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
+impl crate::Writable for INTEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTEN to value 0"]
+impl crate::Resettable for INTEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/intset.rs

@@ -0,0 +1,304 @@
+#[doc = "Register `INTSET` reader"]
+pub struct R(crate::R<INTSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTSET` writer"]
+pub struct W(crate::W<INTSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CMDCMP` reader - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_R = crate::BitReader<bool>;
+#[doc = "Field `CMDCMP` writer - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `THR` reader - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_R = crate::BitReader<bool>;
+#[doc = "Field `THR` writer - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `FUNDFL` reader - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_R = crate::BitReader<bool>;
+#[doc = "Field `FUNDFL` writer - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `FOVFL` reader - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_R = crate::BitReader<bool>;
+#[doc = "Field `FOVFL` writer - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `B2MST` reader - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_R = crate::BitReader<bool>;
+#[doc = "Field `B2MST` writer - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `IACC` reader - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_R = crate::BitReader<bool>;
+#[doc = "Field `IACC` writer - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `ICMD` reader - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_R = crate::BitReader<bool>;
+#[doc = "Field `ICMD` writer - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `BLECIRQ` reader - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_R = crate::BitReader<bool>;
+#[doc = "Field `BLECIRQ` writer - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `BLECSSTAT` reader - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_R = crate::BitReader<bool>;
+#[doc = "Field `BLECSSTAT` writer - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `DCMP` reader - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_R = crate::BitReader<bool>;
+#[doc = "Field `DCMP` writer - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `DERR` reader - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_R = crate::BitReader<bool>;
+#[doc = "Field `DERR` writer - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `CQPAUSED` reader - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_R = crate::BitReader<bool>;
+#[doc = "Field `CQPAUSED` writer - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `CQUPD` reader - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_R = crate::BitReader<bool>;
+#[doc = "Field `CQUPD` writer - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `CQERR` reader - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_R = crate::BitReader<bool>;
+#[doc = "Field `CQERR` writer - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `B2MSLEEP` reader - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSLEEP` writer - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `B2MACTIVE` reader - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_R = crate::BitReader<bool>;
+#[doc = "Field `B2MACTIVE` writer - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+#[doc = "Field `B2MSHUTDN` reader - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSHUTDN` writer - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSET_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&self) -> CMDCMP_R {
+        CMDCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&self) -> THR_R {
+        THR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&self) -> FUNDFL_R {
+        FUNDFL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&self) -> FOVFL_R {
+        FOVFL_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&self) -> B2MST_R {
+        B2MST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&self) -> IACC_R {
+        IACC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&self) -> ICMD_R {
+        ICMD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&self) -> BLECIRQ_R {
+        BLECIRQ_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&self) -> BLECSSTAT_R {
+        BLECSSTAT_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&self) -> CQPAUSED_R {
+        CQPAUSED_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&self) -> CQUPD_R {
+        CQUPD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&self) -> CQERR_R {
+        CQERR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&self) -> B2MSLEEP_R {
+        B2MSLEEP_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&self) -> B2MACTIVE_R {
+        B2MACTIVE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&self) -> B2MSHUTDN_R {
+        B2MSHUTDN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&mut self) -> CMDCMP_W<0> {
+        CMDCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&mut self) -> THR_W<1> {
+        THR_W::new(self)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&mut self) -> FUNDFL_W<2> {
+        FUNDFL_W::new(self)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&mut self) -> FOVFL_W<3> {
+        FOVFL_W::new(self)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&mut self) -> B2MST_W<4> {
+        B2MST_W::new(self)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&mut self) -> IACC_W<5> {
+        IACC_W::new(self)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&mut self) -> ICMD_W<6> {
+        ICMD_W::new(self)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&mut self) -> BLECIRQ_W<7> {
+        BLECIRQ_W::new(self)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&mut self) -> BLECSSTAT_W<8> {
+        BLECSSTAT_W::new(self)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<9> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<10> {
+        DERR_W::new(self)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&mut self) -> CQPAUSED_W<11> {
+        CQPAUSED_W::new(self)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&mut self) -> CQUPD_W<12> {
+        CQUPD_W::new(self)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&mut self) -> CQERR_W<13> {
+        CQERR_W::new(self)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&mut self) -> B2MSLEEP_W<14> {
+        B2MSLEEP_W::new(self)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&mut self) -> B2MACTIVE_W<15> {
+        B2MACTIVE_W::new(self)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W<16> {
+        B2MSHUTDN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "IO Master Interrupts: Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intset](index.html) module"]
+pub struct INTSET_SPEC;
+impl crate::RegisterSpec for INTSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intset::R](R) reader structure"]
+impl crate::Readable for INTSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intset::W](W) writer structure"]
+impl crate::Writable for INTSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTSET to value 0"]
+impl crate::Resettable for INTSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/intstat.rs

@@ -0,0 +1,304 @@
+#[doc = "Register `INTSTAT` reader"]
+pub struct R(crate::R<INTSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTSTAT` writer"]
+pub struct W(crate::W<INTSTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTSTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTSTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CMDCMP` reader - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_R = crate::BitReader<bool>;
+#[doc = "Field `CMDCMP` writer - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+pub type CMDCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `THR` reader - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_R = crate::BitReader<bool>;
+#[doc = "Field `THR` writer - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+pub type THR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `FUNDFL` reader - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_R = crate::BitReader<bool>;
+#[doc = "Field `FUNDFL` writer - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+pub type FUNDFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `FOVFL` reader - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_R = crate::BitReader<bool>;
+#[doc = "Field `FOVFL` writer - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+pub type FOVFL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `B2MST` reader - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_R = crate::BitReader<bool>;
+#[doc = "Field `B2MST` writer - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+pub type B2MST_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `IACC` reader - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_R = crate::BitReader<bool>;
+#[doc = "Field `IACC` writer - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+pub type IACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `ICMD` reader - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_R = crate::BitReader<bool>;
+#[doc = "Field `ICMD` writer - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+pub type ICMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `BLECIRQ` reader - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_R = crate::BitReader<bool>;
+#[doc = "Field `BLECIRQ` writer - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+pub type BLECIRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `BLECSSTAT` reader - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_R = crate::BitReader<bool>;
+#[doc = "Field `BLECSSTAT` writer - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+pub type BLECSSTAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `DCMP` reader - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_R = crate::BitReader<bool>;
+#[doc = "Field `DCMP` writer - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+pub type DCMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `DERR` reader - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_R = crate::BitReader<bool>;
+#[doc = "Field `DERR` writer - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+pub type DERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `CQPAUSED` reader - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_R = crate::BitReader<bool>;
+#[doc = "Field `CQPAUSED` writer - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+pub type CQPAUSED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `CQUPD` reader - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_R = crate::BitReader<bool>;
+#[doc = "Field `CQUPD` writer - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+pub type CQUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `CQERR` reader - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_R = crate::BitReader<bool>;
+#[doc = "Field `CQERR` writer - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+pub type CQERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `B2MSLEEP` reader - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSLEEP` writer - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+pub type B2MSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `B2MACTIVE` reader - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_R = crate::BitReader<bool>;
+#[doc = "Field `B2MACTIVE` writer - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+#[doc = "Field `B2MSHUTDN` reader - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_R = crate::BitReader<bool>;
+#[doc = "Field `B2MSHUTDN` writer - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+pub type B2MSHUTDN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTSTAT_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&self) -> CMDCMP_R {
+        CMDCMP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&self) -> THR_R {
+        THR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&self) -> FUNDFL_R {
+        FUNDFL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&self) -> FOVFL_R {
+        FOVFL_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&self) -> B2MST_R {
+        B2MST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&self) -> IACC_R {
+        IACC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&self) -> ICMD_R {
+        ICMD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&self) -> BLECIRQ_R {
+        BLECIRQ_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&self) -> BLECSSTAT_R {
+        BLECSSTAT_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&self) -> DCMP_R {
+        DCMP_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&self) -> DERR_R {
+        DERR_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&self) -> CQPAUSED_R {
+        CQPAUSED_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&self) -> CQUPD_R {
+        CQUPD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&self) -> CQERR_R {
+        CQERR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&self) -> B2MSLEEP_R {
+        B2MSLEEP_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&self) -> B2MACTIVE_R {
+        B2MACTIVE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&self) -> B2MSHUTDN_R {
+        B2MSHUTDN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
+    #[inline(always)]
+    pub fn cmdcmp(&mut self) -> CMDCMP_W<0> {
+        CMDCMP_W::new(self)
+    }
+    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
+    #[inline(always)]
+    pub fn thr(&mut self) -> THR_W<1> {
+        THR_W::new(self)
+    }
+    #[doc = "Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO."]
+    #[inline(always)]
+    pub fn fundfl(&mut self) -> FUNDFL_W<2> {
+        FUNDFL_W::new(self)
+    }
+    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
+    #[inline(always)]
+    pub fn fovfl(&mut self) -> FOVFL_W<3> {
+        FOVFL_W::new(self)
+    }
+    #[doc = "Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core."]
+    #[inline(always)]
+    pub fn b2mst(&mut self) -> B2MST_W<4> {
+        B2MST_W::new(self)
+    }
+    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
+    #[inline(always)]
+    pub fn iacc(&mut self) -> IACC_W<5> {
+        IACC_W::new(self)
+    }
+    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
+    #[inline(always)]
+    pub fn icmd(&mut self) -> ICMD_W<6> {
+        ICMD_W::new(self)
+    }
+    #[doc = "Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core."]
+    #[inline(always)]
+    pub fn blecirq(&mut self) -> BLECIRQ_W<7> {
+        BLECIRQ_W::new(self)
+    }
+    #[doc = "Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high."]
+    #[inline(always)]
+    pub fn blecsstat(&mut self) -> BLECSSTAT_W<8> {
+        BLECSSTAT_W::new(self)
+    }
+    #[doc = "Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
+    #[inline(always)]
+    pub fn dcmp(&mut self) -> DCMP_W<9> {
+        DCMP_W::new(self)
+    }
+    #[doc = "Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
+    #[inline(always)]
+    pub fn derr(&mut self) -> DERR_W<10> {
+        DERR_W::new(self)
+    }
+    #[doc = "Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
+    #[inline(always)]
+    pub fn cqpaused(&mut self) -> CQPAUSED_W<11> {
+        CQPAUSED_W::new(self)
+    }
+    #[doc = "Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
+    #[inline(always)]
+    pub fn cqupd(&mut self) -> CQUPD_W<12> {
+        CQUPD_W::new(self)
+    }
+    #[doc = "Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions"]
+    #[inline(always)]
+    pub fn cqerr(&mut self) -> CQERR_W<13> {
+        CQERR_W::new(self)
+    }
+    #[doc = "Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state"]
+    #[inline(always)]
+    pub fn b2msleep(&mut self) -> B2MSLEEP_W<14> {
+        B2MSLEEP_W::new(self)
+    }
+    #[doc = "Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mactive(&mut self) -> B2MACTIVE_W<15> {
+        B2MACTIVE_W::new(self)
+    }
+    #[doc = "Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)"]
+    #[inline(always)]
+    pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W<16> {
+        B2MSHUTDN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "IO Master Interrupts: Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstat](index.html) module"]
+pub struct INTSTAT_SPEC;
+impl crate::RegisterSpec for INTSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intstat::R](R) reader structure"]
+impl crate::Readable for INTSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intstat::W](W) writer structure"]
+impl crate::Writable for INTSTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTSTAT to value 0"]
+impl crate::Resettable for INTSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/mspicfg.rs

@@ -0,0 +1,542 @@
+#[doc = "Register `MSPICFG` reader"]
+pub struct R(crate::R<MSPICFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MSPICFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MSPICFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MSPICFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MSPICFG` writer"]
+pub struct W(crate::W<MSPICFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MSPICFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MSPICFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MSPICFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SPOL` reader - This bit selects SPI polarity."]
+pub type SPOL_R = crate::BitReader<SPOL_A>;
+#[doc = "This bit selects SPI polarity.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SPOL_A {
+    #[doc = "0: The initial value of the clock is 0. value."]
+    CLK_BASE_0 = 0,
+    #[doc = "1: The initial value of the clock is 1. value."]
+    CLK_BASE_1 = 1,
+}
+impl From<SPOL_A> for bool {
+    #[inline(always)]
+    fn from(variant: SPOL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SPOL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SPOL_A {
+        match self.bits {
+            false => SPOL_A::CLK_BASE_0,
+            true => SPOL_A::CLK_BASE_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CLK_BASE_0`"]
+    #[inline(always)]
+    pub fn is_clk_base_0(&self) -> bool {
+        *self == SPOL_A::CLK_BASE_0
+    }
+    #[doc = "Checks if the value of the field is `CLK_BASE_1`"]
+    #[inline(always)]
+    pub fn is_clk_base_1(&self) -> bool {
+        *self == SPOL_A::CLK_BASE_1
+    }
+}
+#[doc = "Field `SPOL` writer - This bit selects SPI polarity."]
+pub type SPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, SPOL_A, O>;
+impl<'a, const O: u8> SPOL_W<'a, O> {
+    #[doc = "The initial value of the clock is 0. value."]
+    #[inline(always)]
+    pub fn clk_base_0(self) -> &'a mut W {
+        self.variant(SPOL_A::CLK_BASE_0)
+    }
+    #[doc = "The initial value of the clock is 1. value."]
+    #[inline(always)]
+    pub fn clk_base_1(self) -> &'a mut W {
+        self.variant(SPOL_A::CLK_BASE_1)
+    }
+}
+#[doc = "Field `SPHA` reader - Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock."]
+pub type SPHA_R = crate::BitReader<SPHA_A>;
+#[doc = "Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SPHA_A {
+    #[doc = "0: Sample on the leading (first) clock edge, rising or falling dependant on the value of SPOL value."]
+    SAMPLE_LEADING_EDGE = 0,
+    #[doc = "1: Sample on the trailing (second) clock edge, rising of falling dependant on the value of SPOL value."]
+    SAMPLE_TRAILING_EDGE = 1,
+}
+impl From<SPHA_A> for bool {
+    #[inline(always)]
+    fn from(variant: SPHA_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SPHA_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SPHA_A {
+        match self.bits {
+            false => SPHA_A::SAMPLE_LEADING_EDGE,
+            true => SPHA_A::SAMPLE_TRAILING_EDGE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SAMPLE_LEADING_EDGE`"]
+    #[inline(always)]
+    pub fn is_sample_leading_edge(&self) -> bool {
+        *self == SPHA_A::SAMPLE_LEADING_EDGE
+    }
+    #[doc = "Checks if the value of the field is `SAMPLE_TRAILING_EDGE`"]
+    #[inline(always)]
+    pub fn is_sample_trailing_edge(&self) -> bool {
+        *self == SPHA_A::SAMPLE_TRAILING_EDGE
+    }
+}
+#[doc = "Field `SPHA` writer - Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock."]
+pub type SPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, SPHA_A, O>;
+impl<'a, const O: u8> SPHA_W<'a, O> {
+    #[doc = "Sample on the leading (first) clock edge, rising or falling dependant on the value of SPOL value."]
+    #[inline(always)]
+    pub fn sample_leading_edge(self) -> &'a mut W {
+        self.variant(SPHA_A::SAMPLE_LEADING_EDGE)
+    }
+    #[doc = "Sample on the trailing (second) clock edge, rising of falling dependant on the value of SPOL value."]
+    #[inline(always)]
+    pub fn sample_trailing_edge(self) -> &'a mut W {
+        self.variant(SPHA_A::SAMPLE_TRAILING_EDGE)
+    }
+}
+#[doc = "Field `FULLDUP` reader - Full Duplex mode. Capture read data during writes operations"]
+pub type FULLDUP_R = crate::BitReader<bool>;
+#[doc = "Field `FULLDUP` writer - Full Duplex mode. Capture read data during writes operations"]
+pub type FULLDUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, bool, O>;
+#[doc = "Field `WTFC` reader - Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core."]
+pub type WTFC_R = crate::BitReader<WTFC_A>;
+#[doc = "Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WTFC_A {
+    #[doc = "0: Write mode flow control disabled. value."]
+    DIS = 0,
+    #[doc = "1: Write mode flow control enabled. value."]
+    EN = 1,
+}
+impl From<WTFC_A> for bool {
+    #[inline(always)]
+    fn from(variant: WTFC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WTFC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WTFC_A {
+        match self.bits {
+            false => WTFC_A::DIS,
+            true => WTFC_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == WTFC_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == WTFC_A::EN
+    }
+}
+#[doc = "Field `WTFC` writer - Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core."]
+pub type WTFC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, WTFC_A, O>;
+impl<'a, const O: u8> WTFC_W<'a, O> {
+    #[doc = "Write mode flow control disabled. value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(WTFC_A::DIS)
+    }
+    #[doc = "Write mode flow control enabled. value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(WTFC_A::EN)
+    }
+}
+#[doc = "Field `RDFC` reader - Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core."]
+pub type RDFC_R = crate::BitReader<RDFC_A>;
+#[doc = "Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RDFC_A {
+    #[doc = "0: Read mode flow control disabled. value."]
+    DIS = 0,
+    #[doc = "1: Read mode flow control enabled. value."]
+    EN = 1,
+}
+impl From<RDFC_A> for bool {
+    #[inline(always)]
+    fn from(variant: RDFC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RDFC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RDFC_A {
+        match self.bits {
+            false => RDFC_A::DIS,
+            true => RDFC_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == RDFC_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == RDFC_A::EN
+    }
+}
+#[doc = "Field `RDFC` writer - Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core."]
+pub type RDFC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, RDFC_A, O>;
+impl<'a, const O: u8> RDFC_W<'a, O> {
+    #[doc = "Read mode flow control disabled. value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(RDFC_A::DIS)
+    }
+    #[doc = "Read mode flow control enabled. value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(RDFC_A::EN)
+    }
+}
+#[doc = "Field `WTFCPOL` reader - Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers)."]
+pub type WTFCPOL_R = crate::BitReader<WTFCPOL_A>;
+#[doc = "Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers).\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WTFCPOL_A {
+    #[doc = "0: SPI_STATUS signal from BLE Core high(1) creates flow control and new write spi transactions will not be started until the signal goes low.(default) value."]
+    NORMAL = 0,
+    #[doc = "1: SPI_STATUS signal from BLE Core high(1) creates low(0) control and new write spi transactions will not be started until the signal goes high. value."]
+    INVERTED = 1,
+}
+impl From<WTFCPOL_A> for bool {
+    #[inline(always)]
+    fn from(variant: WTFCPOL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WTFCPOL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WTFCPOL_A {
+        match self.bits {
+            false => WTFCPOL_A::NORMAL,
+            true => WTFCPOL_A::INVERTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NORMAL`"]
+    #[inline(always)]
+    pub fn is_normal(&self) -> bool {
+        *self == WTFCPOL_A::NORMAL
+    }
+    #[doc = "Checks if the value of the field is `INVERTED`"]
+    #[inline(always)]
+    pub fn is_inverted(&self) -> bool {
+        *self == WTFCPOL_A::INVERTED
+    }
+}
+#[doc = "Field `WTFCPOL` writer - Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers)."]
+pub type WTFCPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, WTFCPOL_A, O>;
+impl<'a, const O: u8> WTFCPOL_W<'a, O> {
+    #[doc = "SPI_STATUS signal from BLE Core high(1) creates flow control and new write spi transactions will not be started until the signal goes low.(default) value."]
+    #[inline(always)]
+    pub fn normal(self) -> &'a mut W {
+        self.variant(WTFCPOL_A::NORMAL)
+    }
+    #[doc = "SPI_STATUS signal from BLE Core high(1) creates low(0) control and new write spi transactions will not be started until the signal goes high. value."]
+    #[inline(always)]
+    pub fn inverted(self) -> &'a mut W {
+        self.variant(WTFCPOL_A::INVERTED)
+    }
+}
+#[doc = "Field `RDFCPOL` reader - Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted."]
+pub type RDFCPOL_R = crate::BitReader<RDFCPOL_A>;
+#[doc = "Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RDFCPOL_A {
+    #[doc = "0: SPI_STATUS signal from BLE Core high(1) creates flow control and new read spi transactions will not be started until the signal goes low.(default) value."]
+    NORMAL = 0,
+    #[doc = "1: SPI_STATUS signal from BLE Core low(0) creates flow control and new read spi transactions will not be started until the signal goes high. value."]
+    INVERTED = 1,
+}
+impl From<RDFCPOL_A> for bool {
+    #[inline(always)]
+    fn from(variant: RDFCPOL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RDFCPOL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RDFCPOL_A {
+        match self.bits {
+            false => RDFCPOL_A::NORMAL,
+            true => RDFCPOL_A::INVERTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NORMAL`"]
+    #[inline(always)]
+    pub fn is_normal(&self) -> bool {
+        *self == RDFCPOL_A::NORMAL
+    }
+    #[doc = "Checks if the value of the field is `INVERTED`"]
+    #[inline(always)]
+    pub fn is_inverted(&self) -> bool {
+        *self == RDFCPOL_A::INVERTED
+    }
+}
+#[doc = "Field `RDFCPOL` writer - Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted."]
+pub type RDFCPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, RDFCPOL_A, O>;
+impl<'a, const O: u8> RDFCPOL_W<'a, O> {
+    #[doc = "SPI_STATUS signal from BLE Core high(1) creates flow control and new read spi transactions will not be started until the signal goes low.(default) value."]
+    #[inline(always)]
+    pub fn normal(self) -> &'a mut W {
+        self.variant(RDFCPOL_A::NORMAL)
+    }
+    #[doc = "SPI_STATUS signal from BLE Core low(0) creates flow control and new read spi transactions will not be started until the signal goes high. value."]
+    #[inline(always)]
+    pub fn inverted(self) -> &'a mut W {
+        self.variant(RDFCPOL_A::INVERTED)
+    }
+}
+#[doc = "Field `SPILSB` reader - Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first."]
+pub type SPILSB_R = crate::BitReader<SPILSB_A>;
+#[doc = "Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SPILSB_A {
+    #[doc = "0: Send and receive MSB bit first value."]
+    MSB = 0,
+    #[doc = "1: Send and receive LSB bit first value."]
+    LSB = 1,
+}
+impl From<SPILSB_A> for bool {
+    #[inline(always)]
+    fn from(variant: SPILSB_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SPILSB_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SPILSB_A {
+        match self.bits {
+            false => SPILSB_A::MSB,
+            true => SPILSB_A::LSB,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MSB`"]
+    #[inline(always)]
+    pub fn is_msb(&self) -> bool {
+        *self == SPILSB_A::MSB
+    }
+    #[doc = "Checks if the value of the field is `LSB`"]
+    #[inline(always)]
+    pub fn is_lsb(&self) -> bool {
+        *self == SPILSB_A::LSB
+    }
+}
+#[doc = "Field `SPILSB` writer - Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first."]
+pub type SPILSB_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, SPILSB_A, O>;
+impl<'a, const O: u8> SPILSB_W<'a, O> {
+    #[doc = "Send and receive MSB bit first value."]
+    #[inline(always)]
+    pub fn msb(self) -> &'a mut W {
+        self.variant(SPILSB_A::MSB)
+    }
+    #[doc = "Send and receive LSB bit first value."]
+    #[inline(always)]
+    pub fn lsb(self) -> &'a mut W {
+        self.variant(SPILSB_A::LSB)
+    }
+}
+#[doc = "Field `DINDLY` reader - Delay tap to use for the input signal (MISO). This gives more hold time on the input data."]
+pub type DINDLY_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `DINDLY` writer - Delay tap to use for the input signal (MISO). This gives more hold time on the input data."]
+pub type DINDLY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MSPICFG_SPEC, u8, u8, 3, O>;
+#[doc = "Field `DOUTDLY` reader - Delay tap to use for the output signal (MOSI). This give more hold time on the output data."]
+pub type DOUTDLY_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `DOUTDLY` writer - Delay tap to use for the output signal (MOSI). This give more hold time on the output data."]
+pub type DOUTDLY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MSPICFG_SPEC, u8, u8, 3, O>;
+#[doc = "Field `MSPIRST` reader - Bit is deprecated. setting it will have no effect."]
+pub type MSPIRST_R = crate::BitReader<bool>;
+#[doc = "Field `MSPIRST` writer - Bit is deprecated. setting it will have no effect."]
+pub type MSPIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSPICFG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - This bit selects SPI polarity."]
+    #[inline(always)]
+    pub fn spol(&self) -> SPOL_R {
+        SPOL_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock."]
+    #[inline(always)]
+    pub fn spha(&self) -> SPHA_R {
+        SPHA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Full Duplex mode. Capture read data during writes operations"]
+    #[inline(always)]
+    pub fn fulldup(&self) -> FULLDUP_R {
+        FULLDUP_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core."]
+    #[inline(always)]
+    pub fn wtfc(&self) -> WTFC_R {
+        WTFC_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core."]
+    #[inline(always)]
+    pub fn rdfc(&self) -> RDFC_R {
+        RDFC_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers)."]
+    #[inline(always)]
+    pub fn wtfcpol(&self) -> WTFCPOL_R {
+        WTFCPOL_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted."]
+    #[inline(always)]
+    pub fn rdfcpol(&self) -> RDFCPOL_R {
+        RDFCPOL_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first."]
+    #[inline(always)]
+    pub fn spilsb(&self) -> SPILSB_R {
+        SPILSB_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bits 24:26 - Delay tap to use for the input signal (MISO). This gives more hold time on the input data."]
+    #[inline(always)]
+    pub fn dindly(&self) -> DINDLY_R {
+        DINDLY_R::new(((self.bits >> 24) & 7) as u8)
+    }
+    #[doc = "Bits 27:29 - Delay tap to use for the output signal (MOSI). This give more hold time on the output data."]
+    #[inline(always)]
+    pub fn doutdly(&self) -> DOUTDLY_R {
+        DOUTDLY_R::new(((self.bits >> 27) & 7) as u8)
+    }
+    #[doc = "Bit 30 - Bit is deprecated. setting it will have no effect."]
+    #[inline(always)]
+    pub fn mspirst(&self) -> MSPIRST_R {
+        MSPIRST_R::new(((self.bits >> 30) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit selects SPI polarity."]
+    #[inline(always)]
+    pub fn spol(&mut self) -> SPOL_W<0> {
+        SPOL_W::new(self)
+    }
+    #[doc = "Bit 1 - Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock."]
+    #[inline(always)]
+    pub fn spha(&mut self) -> SPHA_W<1> {
+        SPHA_W::new(self)
+    }
+    #[doc = "Bit 2 - Full Duplex mode. Capture read data during writes operations"]
+    #[inline(always)]
+    pub fn fulldup(&mut self) -> FULLDUP_W<2> {
+        FULLDUP_W::new(self)
+    }
+    #[doc = "Bit 16 - Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core."]
+    #[inline(always)]
+    pub fn wtfc(&mut self) -> WTFC_W<16> {
+        WTFC_W::new(self)
+    }
+    #[doc = "Bit 17 - Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core."]
+    #[inline(always)]
+    pub fn rdfc(&mut self) -> RDFC_W<17> {
+        RDFC_W::new(self)
+    }
+    #[doc = "Bit 21 - Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers)."]
+    #[inline(always)]
+    pub fn wtfcpol(&mut self) -> WTFCPOL_W<21> {
+        WTFCPOL_W::new(self)
+    }
+    #[doc = "Bit 22 - Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted."]
+    #[inline(always)]
+    pub fn rdfcpol(&mut self) -> RDFCPOL_W<22> {
+        RDFCPOL_W::new(self)
+    }
+    #[doc = "Bit 23 - Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first."]
+    #[inline(always)]
+    pub fn spilsb(&mut self) -> SPILSB_W<23> {
+        SPILSB_W::new(self)
+    }
+    #[doc = "Bits 24:26 - Delay tap to use for the input signal (MISO). This gives more hold time on the input data."]
+    #[inline(always)]
+    pub fn dindly(&mut self) -> DINDLY_W<24> {
+        DINDLY_W::new(self)
+    }
+    #[doc = "Bits 27:29 - Delay tap to use for the output signal (MOSI). This give more hold time on the output data."]
+    #[inline(always)]
+    pub fn doutdly(&mut self) -> DOUTDLY_W<27> {
+        DOUTDLY_W::new(self)
+    }
+    #[doc = "Bit 30 - Bit is deprecated. setting it will have no effect."]
+    #[inline(always)]
+    pub fn mspirst(&mut self) -> MSPIRST_W<30> {
+        MSPIRST_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "SPI module master configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mspicfg](index.html) module"]
+pub struct MSPICFG_SPEC;
+impl crate::RegisterSpec for MSPICFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mspicfg::R](R) reader structure"]
+impl crate::Readable for MSPICFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [mspicfg::W](W) writer structure"]
+impl crate::Writable for MSPICFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MSPICFG to value 0x4000_0000"]
+impl crate::Resettable for MSPICFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x4000_0000
+    }
+}

apollo3-pac/src/bleif/offsethi.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `OFFSETHI` reader"]
+pub struct R(crate::R<OFFSETHI_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<OFFSETHI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<OFFSETHI_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<OFFSETHI_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `OFFSETHI` writer"]
+pub struct W(crate::W<OFFSETHI_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<OFFSETHI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<OFFSETHI_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<OFFSETHI_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `OFFSETHI` reader - Holds the high order bytes of the 2 or 3 byte offset phase of a transaction."]
+pub type OFFSETHI_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `OFFSETHI` writer - Holds the high order bytes of the 2 or 3 byte offset phase of a transaction."]
+pub type OFFSETHI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OFFSETHI_SPEC, u16, u16, 16, O>;
+impl R {
+    #[doc = "Bits 0:15 - Holds the high order bytes of the 2 or 3 byte offset phase of a transaction."]
+    #[inline(always)]
+    pub fn offsethi(&self) -> OFFSETHI_R {
+        OFFSETHI_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Holds the high order bytes of the 2 or 3 byte offset phase of a transaction."]
+    #[inline(always)]
+    pub fn offsethi(&mut self) -> OFFSETHI_W<0> {
+        OFFSETHI_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "High order offset bytes\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsethi](index.html) module"]
+pub struct OFFSETHI_SPEC;
+impl crate::RegisterSpec for OFFSETHI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [offsethi::R](R) reader structure"]
+impl crate::Readable for OFFSETHI_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [offsethi::W](W) writer structure"]
+impl crate::Writable for OFFSETHI_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets OFFSETHI to value 0"]
+impl crate::Resettable for OFFSETHI_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/pwrcmd.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `PWRCMD` reader"]
+pub struct R(crate::R<PWRCMD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PWRCMD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PWRCMD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PWRCMD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PWRCMD` writer"]
+pub struct W(crate::W<PWRCMD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PWRCMD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PWRCMD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PWRCMD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `WAKEREQ` reader - Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state"]
+pub type WAKEREQ_R = crate::BitReader<bool>;
+#[doc = "Field `WAKEREQ` writer - Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state"]
+pub type WAKEREQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, PWRCMD_SPEC, bool, O>;
+#[doc = "Field `RESTART` reader - Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state."]
+pub type RESTART_R = crate::BitReader<bool>;
+#[doc = "Field `RESTART` writer - Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state."]
+pub type RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, PWRCMD_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state"]
+    #[inline(always)]
+    pub fn wakereq(&self) -> WAKEREQ_R {
+        WAKEREQ_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state."]
+    #[inline(always)]
+    pub fn restart(&self) -> RESTART_R {
+        RESTART_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state"]
+    #[inline(always)]
+    pub fn wakereq(&mut self) -> WAKEREQ_W<0> {
+        WAKEREQ_W::new(self)
+    }
+    #[doc = "Bit 1 - Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state."]
+    #[inline(always)]
+    pub fn restart(&mut self) -> RESTART_W<1> {
+        RESTART_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "BLE Power command interface\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwrcmd](index.html) module"]
+pub struct PWRCMD_SPEC;
+impl crate::RegisterSpec for PWRCMD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [pwrcmd::R](R) reader structure"]
+impl crate::Readable for PWRCMD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pwrcmd::W](W) writer structure"]
+impl crate::Writable for PWRCMD_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PWRCMD to value 0"]
+impl crate::Resettable for PWRCMD_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/bleif/status.rs

@@ -0,0 +1,210 @@
+#[doc = "Register `STATUS` reader"]
+pub struct R(crate::R<STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `STATUS` writer"]
+pub struct W(crate::W<STATUS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<STATUS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<STATUS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ERR` reader - Bit has been deprecated. Please refer to the other error indicators. This will always return 0."]
+pub type ERR_R = crate::BitReader<ERR_A>;
+#[doc = "Bit has been deprecated. Please refer to the other error indicators. This will always return 0.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERR_A {
+    #[doc = "1: Bit has been deprecated and will always return 0. value."]
+    ERROR = 1,
+}
+impl From<ERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: ERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<ERR_A> {
+        match self.bits {
+            true => Some(ERR_A::ERROR),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ERROR`"]
+    #[inline(always)]
+    pub fn is_error(&self) -> bool {
+        *self == ERR_A::ERROR
+    }
+}
+#[doc = "Field `ERR` writer - Bit has been deprecated. Please refer to the other error indicators. This will always return 0."]
+pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, ERR_A, O>;
+impl<'a, const O: u8> ERR_W<'a, O> {
+    #[doc = "Bit has been deprecated and will always return 0. value."]
+    #[inline(always)]
+    pub fn error(self) -> &'a mut W {
+        self.variant(ERR_A::ERROR)
+    }
+}
+#[doc = "Field `CMDACT` reader - Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized."]
+pub type CMDACT_R = crate::BitReader<CMDACT_A>;
+#[doc = "Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CMDACT_A {
+    #[doc = "1: An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed. value."]
+    ACTIVE = 1,
+}
+impl From<CMDACT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CMDACT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CMDACT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CMDACT_A> {
+        match self.bits {
+            true => Some(CMDACT_A::ACTIVE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE`"]
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == CMDACT_A::ACTIVE
+    }
+}
+#[doc = "Field `CMDACT` writer - Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized."]
+pub type CMDACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, CMDACT_A, O>;
+impl<'a, const O: u8> CMDACT_W<'a, O> {
+    #[doc = "An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed. value."]
+    #[inline(always)]
+    pub fn active(self) -> &'a mut W {
+        self.variant(CMDACT_A::ACTIVE)
+    }
+}
+#[doc = "Field `IDLEST` reader - indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers."]
+pub type IDLEST_R = crate::BitReader<IDLEST_A>;
+#[doc = "indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IDLEST_A {
+    #[doc = "1: The I/O state machine is in the idle state. value."]
+    IDLE = 1,
+}
+impl From<IDLEST_A> for bool {
+    #[inline(always)]
+    fn from(variant: IDLEST_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IDLEST_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<IDLEST_A> {
+        match self.bits {
+            true => Some(IDLEST_A::IDLE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `IDLE`"]
+    #[inline(always)]
+    pub fn is_idle(&self) -> bool {
+        *self == IDLEST_A::IDLE
+    }
+}
+#[doc = "Field `IDLEST` writer - indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers."]
+pub type IDLEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, IDLEST_A, O>;
+impl<'a, const O: u8> IDLEST_W<'a, O> {
+    #[doc = "The I/O state machine is in the idle state. value."]
+    #[inline(always)]
+    pub fn idle(self) -> &'a mut W {
+        self.variant(IDLEST_A::IDLE)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Bit has been deprecated. Please refer to the other error indicators. This will always return 0."]
+    #[inline(always)]
+    pub fn err(&self) -> ERR_R {
+        ERR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized."]
+    #[inline(always)]
+    pub fn cmdact(&self) -> CMDACT_R {
+        CMDACT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers."]
+    #[inline(always)]
+    pub fn idlest(&self) -> IDLEST_R {
+        IDLEST_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Bit has been deprecated. Please refer to the other error indicators. This will always return 0."]
+    #[inline(always)]
+    pub fn err(&mut self) -> ERR_W<0> {
+        ERR_W::new(self)
+    }
+    #[doc = "Bit 1 - Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized."]
+    #[inline(always)]
+    pub fn cmdact(&mut self) -> CMDACT_W<1> {
+        CMDACT_W::new(self)
+    }
+    #[doc = "Bit 2 - indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers."]
+    #[inline(always)]
+    pub fn idlest(&mut self) -> IDLEST_W<2> {
+        IDLEST_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "IOM Module Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
+pub struct STATUS_SPEC;
+impl crate::RegisterSpec for STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [status::R](R) reader structure"]
+impl crate::Readable for STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"]
+impl crate::Writable for STATUS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for STATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl.rs

@@ -0,0 +1,96 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Flash Cache Control Register"]
+    pub cachecfg: CACHECFG,
+    #[doc = "0x04 - Flash Control Register"]
+    pub flashcfg: FLASHCFG,
+    #[doc = "0x08 - Cache Control"]
+    pub ctrl: CTRL,
+    _reserved3: [u8; 0x04],
+    #[doc = "0x10 - Flash Cache Noncachable Region 0 Start"]
+    pub ncr0start: NCR0START,
+    #[doc = "0x14 - Flash Cache Noncachable Region 0 End"]
+    pub ncr0end: NCR0END,
+    #[doc = "0x18 - Flash Cache Noncachable Region 1 Start"]
+    pub ncr1start: NCR1START,
+    #[doc = "0x1c - Flash Cache Noncachable Region 1 End"]
+    pub ncr1end: NCR1END,
+    _reserved7: [u8; 0x20],
+    #[doc = "0x40 - Data Cache Total Accesses"]
+    pub dmon0: DMON0,
+    #[doc = "0x44 - Data Cache Tag Lookups"]
+    pub dmon1: DMON1,
+    #[doc = "0x48 - Data Cache Hits"]
+    pub dmon2: DMON2,
+    #[doc = "0x4c - Data Cache Line Hits"]
+    pub dmon3: DMON3,
+    #[doc = "0x50 - Instruction Cache Total Accesses"]
+    pub imon0: IMON0,
+    #[doc = "0x54 - Instruction Cache Tag Lookups"]
+    pub imon1: IMON1,
+    #[doc = "0x58 - Instruction Cache Hits"]
+    pub imon2: IMON2,
+    #[doc = "0x5c - Instruction Cache Line Hits"]
+    pub imon3: IMON3,
+}
+#[doc = "CACHECFG (rw) register accessor: an alias for `Reg<CACHECFG_SPEC>`"]
+pub type CACHECFG = crate::Reg<cachecfg::CACHECFG_SPEC>;
+#[doc = "Flash Cache Control Register"]
+pub mod cachecfg;
+#[doc = "FLASHCFG (rw) register accessor: an alias for `Reg<FLASHCFG_SPEC>`"]
+pub type FLASHCFG = crate::Reg<flashcfg::FLASHCFG_SPEC>;
+#[doc = "Flash Control Register"]
+pub mod flashcfg;
+#[doc = "CTRL (rw) register accessor: an alias for `Reg<CTRL_SPEC>`"]
+pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
+#[doc = "Cache Control"]
+pub mod ctrl;
+#[doc = "NCR0START (rw) register accessor: an alias for `Reg<NCR0START_SPEC>`"]
+pub type NCR0START = crate::Reg<ncr0start::NCR0START_SPEC>;
+#[doc = "Flash Cache Noncachable Region 0 Start"]
+pub mod ncr0start;
+#[doc = "NCR0END (rw) register accessor: an alias for `Reg<NCR0END_SPEC>`"]
+pub type NCR0END = crate::Reg<ncr0end::NCR0END_SPEC>;
+#[doc = "Flash Cache Noncachable Region 0 End"]
+pub mod ncr0end;
+#[doc = "NCR1START (rw) register accessor: an alias for `Reg<NCR1START_SPEC>`"]
+pub type NCR1START = crate::Reg<ncr1start::NCR1START_SPEC>;
+#[doc = "Flash Cache Noncachable Region 1 Start"]
+pub mod ncr1start;
+#[doc = "NCR1END (rw) register accessor: an alias for `Reg<NCR1END_SPEC>`"]
+pub type NCR1END = crate::Reg<ncr1end::NCR1END_SPEC>;
+#[doc = "Flash Cache Noncachable Region 1 End"]
+pub mod ncr1end;
+#[doc = "DMON0 (rw) register accessor: an alias for `Reg<DMON0_SPEC>`"]
+pub type DMON0 = crate::Reg<dmon0::DMON0_SPEC>;
+#[doc = "Data Cache Total Accesses"]
+pub mod dmon0;
+#[doc = "DMON1 (rw) register accessor: an alias for `Reg<DMON1_SPEC>`"]
+pub type DMON1 = crate::Reg<dmon1::DMON1_SPEC>;
+#[doc = "Data Cache Tag Lookups"]
+pub mod dmon1;
+#[doc = "DMON2 (rw) register accessor: an alias for `Reg<DMON2_SPEC>`"]
+pub type DMON2 = crate::Reg<dmon2::DMON2_SPEC>;
+#[doc = "Data Cache Hits"]
+pub mod dmon2;
+#[doc = "DMON3 (rw) register accessor: an alias for `Reg<DMON3_SPEC>`"]
+pub type DMON3 = crate::Reg<dmon3::DMON3_SPEC>;
+#[doc = "Data Cache Line Hits"]
+pub mod dmon3;
+#[doc = "IMON0 (rw) register accessor: an alias for `Reg<IMON0_SPEC>`"]
+pub type IMON0 = crate::Reg<imon0::IMON0_SPEC>;
+#[doc = "Instruction Cache Total Accesses"]
+pub mod imon0;
+#[doc = "IMON1 (rw) register accessor: an alias for `Reg<IMON1_SPEC>`"]
+pub type IMON1 = crate::Reg<imon1::IMON1_SPEC>;
+#[doc = "Instruction Cache Tag Lookups"]
+pub mod imon1;
+#[doc = "IMON2 (rw) register accessor: an alias for `Reg<IMON2_SPEC>`"]
+pub type IMON2 = crate::Reg<imon2::IMON2_SPEC>;
+#[doc = "Instruction Cache Hits"]
+pub mod imon2;
+#[doc = "IMON3 (rw) register accessor: an alias for `Reg<IMON3_SPEC>`"]
+pub type IMON3 = crate::Reg<imon3::IMON3_SPEC>;
+#[doc = "Instruction Cache Line Hits"]
+pub mod imon3;

apollo3-pac/src/cachectrl/cachecfg.rs

@@ -0,0 +1,281 @@
+#[doc = "Register `CACHECFG` reader"]
+pub struct R(crate::R<CACHECFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CACHECFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CACHECFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CACHECFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CACHECFG` writer"]
+pub struct W(crate::W<CACHECFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CACHECFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CACHECFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CACHECFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access."]
+pub type ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `ENABLE` writer - Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access."]
+pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `LRU` reader - Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM."]
+pub type LRU_R = crate::BitReader<bool>;
+#[doc = "Field `LRU` writer - Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM."]
+pub type LRU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `ENABLE_NC0` reader - Enable Non-cacheable region 0. See NCR0 registers to define the region."]
+pub type ENABLE_NC0_R = crate::BitReader<bool>;
+#[doc = "Field `ENABLE_NC0` writer - Enable Non-cacheable region 0. See NCR0 registers to define the region."]
+pub type ENABLE_NC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `ENABLE_NC1` reader - Enable Non-cacheable region 1. See NCR1 registers to define the region."]
+pub type ENABLE_NC1_R = crate::BitReader<bool>;
+#[doc = "Field `ENABLE_NC1` writer - Enable Non-cacheable region 1. See NCR1 registers to define the region."]
+pub type ENABLE_NC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `CONFIG` reader - Sets the cache configuration"]
+pub type CONFIG_R = crate::FieldReader<u8, CONFIG_A>;
+#[doc = "Sets the cache configuration\n\nValue on reset: 5"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CONFIG_A {
+    #[doc = "4: Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) value."]
+    W1_128B_512E = 4,
+    #[doc = "5: Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active) value."]
+    W2_128B_512E = 5,
+    #[doc = "8: Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active) value."]
+    W1_128B_1024E = 8,
+}
+impl From<CONFIG_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CONFIG_A) -> Self {
+        variant as _
+    }
+}
+impl CONFIG_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CONFIG_A> {
+        match self.bits {
+            4 => Some(CONFIG_A::W1_128B_512E),
+            5 => Some(CONFIG_A::W2_128B_512E),
+            8 => Some(CONFIG_A::W1_128B_1024E),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `W1_128B_512E`"]
+    #[inline(always)]
+    pub fn is_w1_128b_512e(&self) -> bool {
+        *self == CONFIG_A::W1_128B_512E
+    }
+    #[doc = "Checks if the value of the field is `W2_128B_512E`"]
+    #[inline(always)]
+    pub fn is_w2_128b_512e(&self) -> bool {
+        *self == CONFIG_A::W2_128B_512E
+    }
+    #[doc = "Checks if the value of the field is `W1_128B_1024E`"]
+    #[inline(always)]
+    pub fn is_w1_128b_1024e(&self) -> bool {
+        *self == CONFIG_A::W1_128B_1024E
+    }
+}
+#[doc = "Field `CONFIG` writer - Sets the cache configuration"]
+pub type CONFIG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CACHECFG_SPEC, u8, CONFIG_A, 4, O>;
+impl<'a, const O: u8> CONFIG_W<'a, O> {
+    #[doc = "Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) value."]
+    #[inline(always)]
+    pub fn w1_128b_512e(self) -> &'a mut W {
+        self.variant(CONFIG_A::W1_128B_512E)
+    }
+    #[doc = "Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active) value."]
+    #[inline(always)]
+    pub fn w2_128b_512e(self) -> &'a mut W {
+        self.variant(CONFIG_A::W2_128B_512E)
+    }
+    #[doc = "Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active) value."]
+    #[inline(always)]
+    pub fn w1_128b_1024e(self) -> &'a mut W {
+        self.variant(CONFIG_A::W1_128B_1024E)
+    }
+}
+#[doc = "Field `ICACHE_ENABLE` reader - Enable Flash Instruction Caching"]
+pub type ICACHE_ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `ICACHE_ENABLE` writer - Enable Flash Instruction Caching"]
+pub type ICACHE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `DCACHE_ENABLE` reader - Enable Flash Data Caching."]
+pub type DCACHE_ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `DCACHE_ENABLE` writer - Enable Flash Data Caching."]
+pub type DCACHE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `CACHE_CLKGATE` reader - Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency."]
+pub type CACHE_CLKGATE_R = crate::BitReader<bool>;
+#[doc = "Field `CACHE_CLKGATE` writer - Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency."]
+pub type CACHE_CLKGATE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `CACHE_LS` reader - Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage."]
+pub type CACHE_LS_R = crate::BitReader<bool>;
+#[doc = "Field `CACHE_LS` writer - Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage."]
+pub type CACHE_LS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `DATA_CLKGATE` reader - Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency."]
+pub type DATA_CLKGATE_R = crate::BitReader<bool>;
+#[doc = "Field `DATA_CLKGATE` writer - Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency."]
+pub type DATA_CLKGATE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+#[doc = "Field `ENABLE_MONITOR` reader - Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments."]
+pub type ENABLE_MONITOR_R = crate::BitReader<bool>;
+#[doc = "Field `ENABLE_MONITOR` writer - Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments."]
+pub type ENABLE_MONITOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CACHECFG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access."]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM."]
+    #[inline(always)]
+    pub fn lru(&self) -> LRU_R {
+        LRU_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Enable Non-cacheable region 0. See NCR0 registers to define the region."]
+    #[inline(always)]
+    pub fn enable_nc0(&self) -> ENABLE_NC0_R {
+        ENABLE_NC0_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Enable Non-cacheable region 1. See NCR1 registers to define the region."]
+    #[inline(always)]
+    pub fn enable_nc1(&self) -> ENABLE_NC1_R {
+        ENABLE_NC1_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:7 - Sets the cache configuration"]
+    #[inline(always)]
+    pub fn config(&self) -> CONFIG_R {
+        CONFIG_R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bit 8 - Enable Flash Instruction Caching"]
+    #[inline(always)]
+    pub fn icache_enable(&self) -> ICACHE_ENABLE_R {
+        ICACHE_ENABLE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Enable Flash Data Caching."]
+    #[inline(always)]
+    pub fn dcache_enable(&self) -> DCACHE_ENABLE_R {
+        DCACHE_ENABLE_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency."]
+    #[inline(always)]
+    pub fn cache_clkgate(&self) -> CACHE_CLKGATE_R {
+        CACHE_CLKGATE_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage."]
+    #[inline(always)]
+    pub fn cache_ls(&self) -> CACHE_LS_R {
+        CACHE_LS_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 20 - Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency."]
+    #[inline(always)]
+    pub fn data_clkgate(&self) -> DATA_CLKGATE_R {
+        DATA_CLKGATE_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 24 - Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments."]
+    #[inline(always)]
+    pub fn enable_monitor(&self) -> ENABLE_MONITOR_R {
+        ENABLE_MONITOR_R::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access."]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Bit 1 - Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM."]
+    #[inline(always)]
+    pub fn lru(&mut self) -> LRU_W<1> {
+        LRU_W::new(self)
+    }
+    #[doc = "Bit 2 - Enable Non-cacheable region 0. See NCR0 registers to define the region."]
+    #[inline(always)]
+    pub fn enable_nc0(&mut self) -> ENABLE_NC0_W<2> {
+        ENABLE_NC0_W::new(self)
+    }
+    #[doc = "Bit 3 - Enable Non-cacheable region 1. See NCR1 registers to define the region."]
+    #[inline(always)]
+    pub fn enable_nc1(&mut self) -> ENABLE_NC1_W<3> {
+        ENABLE_NC1_W::new(self)
+    }
+    #[doc = "Bits 4:7 - Sets the cache configuration"]
+    #[inline(always)]
+    pub fn config(&mut self) -> CONFIG_W<4> {
+        CONFIG_W::new(self)
+    }
+    #[doc = "Bit 8 - Enable Flash Instruction Caching"]
+    #[inline(always)]
+    pub fn icache_enable(&mut self) -> ICACHE_ENABLE_W<8> {
+        ICACHE_ENABLE_W::new(self)
+    }
+    #[doc = "Bit 9 - Enable Flash Data Caching."]
+    #[inline(always)]
+    pub fn dcache_enable(&mut self) -> DCACHE_ENABLE_W<9> {
+        DCACHE_ENABLE_W::new(self)
+    }
+    #[doc = "Bit 10 - Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency."]
+    #[inline(always)]
+    pub fn cache_clkgate(&mut self) -> CACHE_CLKGATE_W<10> {
+        CACHE_CLKGATE_W::new(self)
+    }
+    #[doc = "Bit 11 - Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage."]
+    #[inline(always)]
+    pub fn cache_ls(&mut self) -> CACHE_LS_W<11> {
+        CACHE_LS_W::new(self)
+    }
+    #[doc = "Bit 20 - Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency."]
+    #[inline(always)]
+    pub fn data_clkgate(&mut self) -> DATA_CLKGATE_W<20> {
+        DATA_CLKGATE_W::new(self)
+    }
+    #[doc = "Bit 24 - Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments."]
+    #[inline(always)]
+    pub fn enable_monitor(&mut self) -> ENABLE_MONITOR_W<24> {
+        ENABLE_MONITOR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash Cache Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cachecfg](index.html) module"]
+pub struct CACHECFG_SPEC;
+impl crate::RegisterSpec for CACHECFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cachecfg::R](R) reader structure"]
+impl crate::Readable for CACHECFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cachecfg::W](W) writer structure"]
+impl crate::Writable for CACHECFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CACHECFG to value 0x0010_0c50"]
+impl crate::Resettable for CACHECFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0010_0c50
+    }
+}

apollo3-pac/src/cachectrl/ctrl.rs

@@ -0,0 +1,226 @@
+#[doc = "Register `CTRL` reader"]
+pub struct R(crate::R<CTRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CTRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CTRL` writer"]
+pub struct W(crate::W<CTRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CTRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `INVALIDATE` reader - Writing a 1 to this bitfield invalidates the flash cache contents."]
+pub type INVALIDATE_R = crate::BitReader<bool>;
+#[doc = "Field `INVALIDATE` writer - Writing a 1 to this bitfield invalidates the flash cache contents."]
+pub type INVALIDATE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+#[doc = "Field `RESET_STAT` reader - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
+pub type RESET_STAT_R = crate::BitReader<RESET_STAT_A>;
+#[doc = "Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RESET_STAT_A {
+    #[doc = "1: Clear Cache Stats value."]
+    CLEAR = 1,
+}
+impl From<RESET_STAT_A> for bool {
+    #[inline(always)]
+    fn from(variant: RESET_STAT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RESET_STAT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<RESET_STAT_A> {
+        match self.bits {
+            true => Some(RESET_STAT_A::CLEAR),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CLEAR`"]
+    #[inline(always)]
+    pub fn is_clear(&self) -> bool {
+        *self == RESET_STAT_A::CLEAR
+    }
+}
+#[doc = "Field `RESET_STAT` writer - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
+pub type RESET_STAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, RESET_STAT_A, O>;
+impl<'a, const O: u8> RESET_STAT_W<'a, O> {
+    #[doc = "Clear Cache Stats value."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(RESET_STAT_A::CLEAR)
+    }
+}
+#[doc = "Field `CACHE_READY` reader - Cache Ready Status (enabled and not processing an invalidate operation)"]
+pub type CACHE_READY_R = crate::BitReader<bool>;
+#[doc = "Field `CACHE_READY` writer - Cache Ready Status (enabled and not processing an invalidate operation)"]
+pub type CACHE_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+#[doc = "Field `FLASH0_SLM_STATUS` reader - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
+pub type FLASH0_SLM_STATUS_R = crate::BitReader<bool>;
+#[doc = "Field `FLASH0_SLM_STATUS` writer - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
+pub type FLASH0_SLM_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+#[doc = "Field `FLASH0_SLM_DISABLE` reader - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
+pub type FLASH0_SLM_DISABLE_R = crate::BitReader<bool>;
+#[doc = "Field `FLASH0_SLM_DISABLE` writer - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
+pub type FLASH0_SLM_DISABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+#[doc = "Field `FLASH0_SLM_ENABLE` reader - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+pub type FLASH0_SLM_ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `FLASH0_SLM_ENABLE` writer - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+pub type FLASH0_SLM_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+#[doc = "Field `FLASH1_SLM_STATUS` reader - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
+pub type FLASH1_SLM_STATUS_R = crate::BitReader<bool>;
+#[doc = "Field `FLASH1_SLM_STATUS` writer - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
+pub type FLASH1_SLM_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+#[doc = "Field `FLASH1_SLM_DISABLE` reader - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
+pub type FLASH1_SLM_DISABLE_R = crate::BitReader<bool>;
+#[doc = "Field `FLASH1_SLM_DISABLE` writer - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
+pub type FLASH1_SLM_DISABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+#[doc = "Field `FLASH1_SLM_ENABLE` reader - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+pub type FLASH1_SLM_ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `FLASH1_SLM_ENABLE` writer - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+pub type FLASH1_SLM_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents."]
+    #[inline(always)]
+    pub fn invalidate(&self) -> INVALIDATE_R {
+        INVALIDATE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
+    #[inline(always)]
+    pub fn reset_stat(&self) -> RESET_STAT_R {
+        RESET_STAT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)"]
+    #[inline(always)]
+    pub fn cache_ready(&self) -> CACHE_READY_R {
+        CACHE_READY_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
+    #[inline(always)]
+    pub fn flash0_slm_status(&self) -> FLASH0_SLM_STATUS_R {
+        FLASH0_SLM_STATUS_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
+    #[inline(always)]
+    pub fn flash0_slm_disable(&self) -> FLASH0_SLM_DISABLE_R {
+        FLASH0_SLM_DISABLE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+    #[inline(always)]
+    pub fn flash0_slm_enable(&self) -> FLASH0_SLM_ENABLE_R {
+        FLASH0_SLM_ENABLE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
+    #[inline(always)]
+    pub fn flash1_slm_status(&self) -> FLASH1_SLM_STATUS_R {
+        FLASH1_SLM_STATUS_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
+    #[inline(always)]
+    pub fn flash1_slm_disable(&self) -> FLASH1_SLM_DISABLE_R {
+        FLASH1_SLM_DISABLE_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+    #[inline(always)]
+    pub fn flash1_slm_enable(&self) -> FLASH1_SLM_ENABLE_R {
+        FLASH1_SLM_ENABLE_R::new(((self.bits >> 10) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents."]
+    #[inline(always)]
+    pub fn invalidate(&mut self) -> INVALIDATE_W<0> {
+        INVALIDATE_W::new(self)
+    }
+    #[doc = "Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
+    #[inline(always)]
+    pub fn reset_stat(&mut self) -> RESET_STAT_W<1> {
+        RESET_STAT_W::new(self)
+    }
+    #[doc = "Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)"]
+    #[inline(always)]
+    pub fn cache_ready(&mut self) -> CACHE_READY_W<2> {
+        CACHE_READY_W::new(self)
+    }
+    #[doc = "Bit 4 - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
+    #[inline(always)]
+    pub fn flash0_slm_status(&mut self) -> FLASH0_SLM_STATUS_W<4> {
+        FLASH0_SLM_STATUS_W::new(self)
+    }
+    #[doc = "Bit 5 - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
+    #[inline(always)]
+    pub fn flash0_slm_disable(&mut self) -> FLASH0_SLM_DISABLE_W<5> {
+        FLASH0_SLM_DISABLE_W::new(self)
+    }
+    #[doc = "Bit 6 - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+    #[inline(always)]
+    pub fn flash0_slm_enable(&mut self) -> FLASH0_SLM_ENABLE_W<6> {
+        FLASH0_SLM_ENABLE_W::new(self)
+    }
+    #[doc = "Bit 8 - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
+    #[inline(always)]
+    pub fn flash1_slm_status(&mut self) -> FLASH1_SLM_STATUS_W<8> {
+        FLASH1_SLM_STATUS_W::new(self)
+    }
+    #[doc = "Bit 9 - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
+    #[inline(always)]
+    pub fn flash1_slm_disable(&mut self) -> FLASH1_SLM_DISABLE_W<9> {
+        FLASH1_SLM_DISABLE_W::new(self)
+    }
+    #[doc = "Bit 10 - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
+    #[inline(always)]
+    pub fn flash1_slm_enable(&mut self) -> FLASH1_SLM_ENABLE_W<10> {
+        FLASH1_SLM_ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Cache Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
+pub struct CTRL_SPEC;
+impl crate::RegisterSpec for CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
+impl crate::Readable for CTRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
+impl crate::Writable for CTRL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CTRL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/dmon0.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `DMON0` reader"]
+pub struct R(crate::R<DMON0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMON0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMON0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMON0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMON0` writer"]
+pub struct W(crate::W<DMON0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMON0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMON0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMON0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DACCESS_COUNT` reader - Total accesses to data cache. All performance metrics should be relative to the number of accesses performed."]
+pub type DACCESS_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DACCESS_COUNT` writer - Total accesses to data cache. All performance metrics should be relative to the number of accesses performed."]
+pub type DACCESS_COUNT_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DMON0_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Total accesses to data cache. All performance metrics should be relative to the number of accesses performed."]
+    #[inline(always)]
+    pub fn daccess_count(&self) -> DACCESS_COUNT_R {
+        DACCESS_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Total accesses to data cache. All performance metrics should be relative to the number of accesses performed."]
+    #[inline(always)]
+    pub fn daccess_count(&mut self) -> DACCESS_COUNT_W<0> {
+        DACCESS_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Cache Total Accesses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmon0](index.html) module"]
+pub struct DMON0_SPEC;
+impl crate::RegisterSpec for DMON0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmon0::R](R) reader structure"]
+impl crate::Readable for DMON0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmon0::W](W) writer structure"]
+impl crate::Writable for DMON0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMON0 to value 0"]
+impl crate::Resettable for DMON0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/dmon1.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `DMON1` reader"]
+pub struct R(crate::R<DMON1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMON1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMON1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMON1` writer"]
+pub struct W(crate::W<DMON1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMON1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMON1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DLOOKUP_COUNT` reader - Total tag lookups from data cache."]
+pub type DLOOKUP_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DLOOKUP_COUNT` writer - Total tag lookups from data cache."]
+pub type DLOOKUP_COUNT_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, DMON1_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Total tag lookups from data cache."]
+    #[inline(always)]
+    pub fn dlookup_count(&self) -> DLOOKUP_COUNT_R {
+        DLOOKUP_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Total tag lookups from data cache."]
+    #[inline(always)]
+    pub fn dlookup_count(&mut self) -> DLOOKUP_COUNT_W<0> {
+        DLOOKUP_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Cache Tag Lookups\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmon1](index.html) module"]
+pub struct DMON1_SPEC;
+impl crate::RegisterSpec for DMON1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmon1::R](R) reader structure"]
+impl crate::Readable for DMON1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmon1::W](W) writer structure"]
+impl crate::Writable for DMON1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMON1 to value 0"]
+impl crate::Resettable for DMON1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/dmon2.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `DMON2` reader"]
+pub struct R(crate::R<DMON2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMON2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMON2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMON2` writer"]
+pub struct W(crate::W<DMON2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMON2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMON2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DHIT_COUNT` reader - Cache hits from lookup operations."]
+pub type DHIT_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DHIT_COUNT` writer - Cache hits from lookup operations."]
+pub type DHIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMON2_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Cache hits from lookup operations."]
+    #[inline(always)]
+    pub fn dhit_count(&self) -> DHIT_COUNT_R {
+        DHIT_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Cache hits from lookup operations."]
+    #[inline(always)]
+    pub fn dhit_count(&mut self) -> DHIT_COUNT_W<0> {
+        DHIT_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Cache Hits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmon2](index.html) module"]
+pub struct DMON2_SPEC;
+impl crate::RegisterSpec for DMON2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmon2::R](R) reader structure"]
+impl crate::Readable for DMON2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmon2::W](W) writer structure"]
+impl crate::Writable for DMON2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMON2 to value 0"]
+impl crate::Resettable for DMON2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/dmon3.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `DMON3` reader"]
+pub struct R(crate::R<DMON3_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DMON3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DMON3_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DMON3_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DMON3` writer"]
+pub struct W(crate::W<DMON3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DMON3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DMON3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DMON3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DLINE_COUNT` reader - Cache hits from line cache"]
+pub type DLINE_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DLINE_COUNT` writer - Cache hits from line cache"]
+pub type DLINE_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMON3_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Cache hits from line cache"]
+    #[inline(always)]
+    pub fn dline_count(&self) -> DLINE_COUNT_R {
+        DLINE_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Cache hits from line cache"]
+    #[inline(always)]
+    pub fn dline_count(&mut self) -> DLINE_COUNT_W<0> {
+        DLINE_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Cache Line Hits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmon3](index.html) module"]
+pub struct DMON3_SPEC;
+impl crate::RegisterSpec for DMON3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dmon3::R](R) reader structure"]
+impl crate::Readable for DMON3_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dmon3::W](W) writer structure"]
+impl crate::Writable for DMON3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DMON3 to value 0"]
+impl crate::Resettable for DMON3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/flashcfg.rs

@@ -0,0 +1,184 @@
+#[doc = "Register `FLASHCFG` reader"]
+pub struct R(crate::R<FLASHCFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FLASHCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FLASHCFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FLASHCFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FLASHCFG` writer"]
+pub struct W(crate::W<FLASHCFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FLASHCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FLASHCFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FLASHCFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RD_WAIT` reader - Sets read waitstates for normal (fast) operation. A value of 1 is recommended."]
+pub type RD_WAIT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RD_WAIT` writer - Sets read waitstates for normal (fast) operation. A value of 1 is recommended."]
+pub type RD_WAIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLASHCFG_SPEC, u8, u8, 4, O>;
+#[doc = "Field `SEDELAY` reader - Sets SE delay (flash address setup). A value of 5 is recommended."]
+pub type SEDELAY_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `SEDELAY` writer - Sets SE delay (flash address setup). A value of 5 is recommended."]
+pub type SEDELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLASHCFG_SPEC, u8, u8, 3, O>;
+#[doc = "Field `LPM_RD_WAIT` reader - Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"]
+pub type LPM_RD_WAIT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `LPM_RD_WAIT` writer - Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"]
+pub type LPM_RD_WAIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLASHCFG_SPEC, u8, u8, 4, O>;
+#[doc = "Field `LPMMODE` reader - Controls flash low power modes (control of LPM pin)."]
+pub type LPMMODE_R = crate::FieldReader<u8, LPMMODE_A>;
+#[doc = "Controls flash low power modes (control of LPM pin).\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LPMMODE_A {
+    #[doc = "0: High power mode (LPM not used). value."]
+    NEVER = 0,
+    #[doc = "1: Fast Standby mode. LPM deasserted for read operations, but asserted while flash IDLE. value."]
+    STANDBY = 1,
+    #[doc = "2: Low Power mode. LPM always asserted for reads. LPM_RD_WAIT must be programmed to accomodate longer read access times. value."]
+    ALWAYS = 2,
+}
+impl From<LPMMODE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LPMMODE_A) -> Self {
+        variant as _
+    }
+}
+impl LPMMODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LPMMODE_A> {
+        match self.bits {
+            0 => Some(LPMMODE_A::NEVER),
+            1 => Some(LPMMODE_A::STANDBY),
+            2 => Some(LPMMODE_A::ALWAYS),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NEVER`"]
+    #[inline(always)]
+    pub fn is_never(&self) -> bool {
+        *self == LPMMODE_A::NEVER
+    }
+    #[doc = "Checks if the value of the field is `STANDBY`"]
+    #[inline(always)]
+    pub fn is_standby(&self) -> bool {
+        *self == LPMMODE_A::STANDBY
+    }
+    #[doc = "Checks if the value of the field is `ALWAYS`"]
+    #[inline(always)]
+    pub fn is_always(&self) -> bool {
+        *self == LPMMODE_A::ALWAYS
+    }
+}
+#[doc = "Field `LPMMODE` writer - Controls flash low power modes (control of LPM pin)."]
+pub type LPMMODE_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, FLASHCFG_SPEC, u8, LPMMODE_A, 2, O>;
+impl<'a, const O: u8> LPMMODE_W<'a, O> {
+    #[doc = "High power mode (LPM not used). value."]
+    #[inline(always)]
+    pub fn never(self) -> &'a mut W {
+        self.variant(LPMMODE_A::NEVER)
+    }
+    #[doc = "Fast Standby mode. LPM deasserted for read operations, but asserted while flash IDLE. value."]
+    #[inline(always)]
+    pub fn standby(self) -> &'a mut W {
+        self.variant(LPMMODE_A::STANDBY)
+    }
+    #[doc = "Low Power mode. LPM always asserted for reads. LPM_RD_WAIT must be programmed to accomodate longer read access times. value."]
+    #[inline(always)]
+    pub fn always(self) -> &'a mut W {
+        self.variant(LPMMODE_A::ALWAYS)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Sets read waitstates for normal (fast) operation. A value of 1 is recommended."]
+    #[inline(always)]
+    pub fn rd_wait(&self) -> RD_WAIT_R {
+        RD_WAIT_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:6 - Sets SE delay (flash address setup). A value of 5 is recommended."]
+    #[inline(always)]
+    pub fn sedelay(&self) -> SEDELAY_R {
+        SEDELAY_R::new(((self.bits >> 4) & 7) as u8)
+    }
+    #[doc = "Bits 8:11 - Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"]
+    #[inline(always)]
+    pub fn lpm_rd_wait(&self) -> LPM_RD_WAIT_R {
+        LPM_RD_WAIT_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:13 - Controls flash low power modes (control of LPM pin)."]
+    #[inline(always)]
+    pub fn lpmmode(&self) -> LPMMODE_R {
+        LPMMODE_R::new(((self.bits >> 12) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Sets read waitstates for normal (fast) operation. A value of 1 is recommended."]
+    #[inline(always)]
+    pub fn rd_wait(&mut self) -> RD_WAIT_W<0> {
+        RD_WAIT_W::new(self)
+    }
+    #[doc = "Bits 4:6 - Sets SE delay (flash address setup). A value of 5 is recommended."]
+    #[inline(always)]
+    pub fn sedelay(&mut self) -> SEDELAY_W<4> {
+        SEDELAY_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"]
+    #[inline(always)]
+    pub fn lpm_rd_wait(&mut self) -> LPM_RD_WAIT_W<8> {
+        LPM_RD_WAIT_W::new(self)
+    }
+    #[doc = "Bits 12:13 - Controls flash low power modes (control of LPM pin)."]
+    #[inline(always)]
+    pub fn lpmmode(&mut self) -> LPMMODE_W<12> {
+        LPMMODE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flashcfg](index.html) module"]
+pub struct FLASHCFG_SPEC;
+impl crate::RegisterSpec for FLASHCFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [flashcfg::R](R) reader structure"]
+impl crate::Readable for FLASHCFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [flashcfg::W](W) writer structure"]
+impl crate::Writable for FLASHCFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FLASHCFG to value 0x0873"]
+impl crate::Resettable for FLASHCFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0873
+    }
+}

apollo3-pac/src/cachectrl/imon0.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `IMON0` reader"]
+pub struct R(crate::R<IMON0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IMON0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IMON0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IMON0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IMON0` writer"]
+pub struct W(crate::W<IMON0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IMON0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IMON0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IMON0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `IACCESS_COUNT` reader - Total accesses to Instruction cache"]
+pub type IACCESS_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `IACCESS_COUNT` writer - Total accesses to Instruction cache"]
+pub type IACCESS_COUNT_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, IMON0_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Total accesses to Instruction cache"]
+    #[inline(always)]
+    pub fn iaccess_count(&self) -> IACCESS_COUNT_R {
+        IACCESS_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Total accesses to Instruction cache"]
+    #[inline(always)]
+    pub fn iaccess_count(&mut self) -> IACCESS_COUNT_W<0> {
+        IACCESS_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Instruction Cache Total Accesses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imon0](index.html) module"]
+pub struct IMON0_SPEC;
+impl crate::RegisterSpec for IMON0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [imon0::R](R) reader structure"]
+impl crate::Readable for IMON0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [imon0::W](W) writer structure"]
+impl crate::Writable for IMON0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IMON0 to value 0"]
+impl crate::Resettable for IMON0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/imon1.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `IMON1` reader"]
+pub struct R(crate::R<IMON1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IMON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IMON1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IMON1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IMON1` writer"]
+pub struct W(crate::W<IMON1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IMON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IMON1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IMON1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ILOOKUP_COUNT` reader - Total tag lookups from Instruction cache"]
+pub type ILOOKUP_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ILOOKUP_COUNT` writer - Total tag lookups from Instruction cache"]
+pub type ILOOKUP_COUNT_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, IMON1_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Total tag lookups from Instruction cache"]
+    #[inline(always)]
+    pub fn ilookup_count(&self) -> ILOOKUP_COUNT_R {
+        ILOOKUP_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Total tag lookups from Instruction cache"]
+    #[inline(always)]
+    pub fn ilookup_count(&mut self) -> ILOOKUP_COUNT_W<0> {
+        ILOOKUP_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Instruction Cache Tag Lookups\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imon1](index.html) module"]
+pub struct IMON1_SPEC;
+impl crate::RegisterSpec for IMON1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [imon1::R](R) reader structure"]
+impl crate::Readable for IMON1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [imon1::W](W) writer structure"]
+impl crate::Writable for IMON1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IMON1 to value 0"]
+impl crate::Resettable for IMON1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/imon2.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `IMON2` reader"]
+pub struct R(crate::R<IMON2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IMON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IMON2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IMON2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IMON2` writer"]
+pub struct W(crate::W<IMON2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IMON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IMON2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IMON2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `IHIT_COUNT` reader - Cache hits from lookup operations"]
+pub type IHIT_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `IHIT_COUNT` writer - Cache hits from lookup operations"]
+pub type IHIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMON2_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Cache hits from lookup operations"]
+    #[inline(always)]
+    pub fn ihit_count(&self) -> IHIT_COUNT_R {
+        IHIT_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Cache hits from lookup operations"]
+    #[inline(always)]
+    pub fn ihit_count(&mut self) -> IHIT_COUNT_W<0> {
+        IHIT_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Instruction Cache Hits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imon2](index.html) module"]
+pub struct IMON2_SPEC;
+impl crate::RegisterSpec for IMON2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [imon2::R](R) reader structure"]
+impl crate::Readable for IMON2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [imon2::W](W) writer structure"]
+impl crate::Writable for IMON2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IMON2 to value 0"]
+impl crate::Resettable for IMON2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/imon3.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `IMON3` reader"]
+pub struct R(crate::R<IMON3_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IMON3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IMON3_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IMON3_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IMON3` writer"]
+pub struct W(crate::W<IMON3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IMON3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IMON3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IMON3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ILINE_COUNT` reader - Cache hits from line cache"]
+pub type ILINE_COUNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ILINE_COUNT` writer - Cache hits from line cache"]
+pub type ILINE_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMON3_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Cache hits from line cache"]
+    #[inline(always)]
+    pub fn iline_count(&self) -> ILINE_COUNT_R {
+        ILINE_COUNT_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Cache hits from line cache"]
+    #[inline(always)]
+    pub fn iline_count(&mut self) -> ILINE_COUNT_W<0> {
+        ILINE_COUNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Instruction Cache Line Hits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imon3](index.html) module"]
+pub struct IMON3_SPEC;
+impl crate::RegisterSpec for IMON3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [imon3::R](R) reader structure"]
+impl crate::Readable for IMON3_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [imon3::W](W) writer structure"]
+impl crate::Writable for IMON3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IMON3 to value 0"]
+impl crate::Resettable for IMON3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/ncr0end.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `NCR0END` reader"]
+pub struct R(crate::R<NCR0END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NCR0END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NCR0END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NCR0END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `NCR0END` writer"]
+pub struct W(crate::W<NCR0END_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NCR0END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NCR0END_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NCR0END_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDR` reader - End address for non-cacheable region 0"]
+pub type ADDR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ADDR` writer - End address for non-cacheable region 0"]
+pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NCR0END_SPEC, u32, u32, 23, O>;
+impl R {
+    #[doc = "Bits 4:26 - End address for non-cacheable region 0"]
+    #[inline(always)]
+    pub fn addr(&self) -> ADDR_R {
+        ADDR_R::new(((self.bits >> 4) & 0x007f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 4:26 - End address for non-cacheable region 0"]
+    #[inline(always)]
+    pub fn addr(&mut self) -> ADDR_W<4> {
+        ADDR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash Cache Noncachable Region 0 End\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ncr0end](index.html) module"]
+pub struct NCR0END_SPEC;
+impl crate::RegisterSpec for NCR0END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ncr0end::R](R) reader structure"]
+impl crate::Readable for NCR0END_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ncr0end::W](W) writer structure"]
+impl crate::Writable for NCR0END_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NCR0END to value 0"]
+impl crate::Resettable for NCR0END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/ncr0start.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `NCR0START` reader"]
+pub struct R(crate::R<NCR0START_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NCR0START_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NCR0START_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NCR0START_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `NCR0START` writer"]
+pub struct W(crate::W<NCR0START_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NCR0START_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NCR0START_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NCR0START_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDR` reader - Start address for non-cacheable region 0"]
+pub type ADDR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ADDR` writer - Start address for non-cacheable region 0"]
+pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NCR0START_SPEC, u32, u32, 23, O>;
+impl R {
+    #[doc = "Bits 4:26 - Start address for non-cacheable region 0"]
+    #[inline(always)]
+    pub fn addr(&self) -> ADDR_R {
+        ADDR_R::new(((self.bits >> 4) & 0x007f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 4:26 - Start address for non-cacheable region 0"]
+    #[inline(always)]
+    pub fn addr(&mut self) -> ADDR_W<4> {
+        ADDR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash Cache Noncachable Region 0 Start\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ncr0start](index.html) module"]
+pub struct NCR0START_SPEC;
+impl crate::RegisterSpec for NCR0START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ncr0start::R](R) reader structure"]
+impl crate::Readable for NCR0START_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ncr0start::W](W) writer structure"]
+impl crate::Writable for NCR0START_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NCR0START to value 0"]
+impl crate::Resettable for NCR0START_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/ncr1end.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `NCR1END` reader"]
+pub struct R(crate::R<NCR1END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NCR1END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NCR1END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NCR1END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `NCR1END` writer"]
+pub struct W(crate::W<NCR1END_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NCR1END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NCR1END_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NCR1END_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDR` reader - End address for non-cacheable region 1"]
+pub type ADDR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ADDR` writer - End address for non-cacheable region 1"]
+pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NCR1END_SPEC, u32, u32, 23, O>;
+impl R {
+    #[doc = "Bits 4:26 - End address for non-cacheable region 1"]
+    #[inline(always)]
+    pub fn addr(&self) -> ADDR_R {
+        ADDR_R::new(((self.bits >> 4) & 0x007f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 4:26 - End address for non-cacheable region 1"]
+    #[inline(always)]
+    pub fn addr(&mut self) -> ADDR_W<4> {
+        ADDR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash Cache Noncachable Region 1 End\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ncr1end](index.html) module"]
+pub struct NCR1END_SPEC;
+impl crate::RegisterSpec for NCR1END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ncr1end::R](R) reader structure"]
+impl crate::Readable for NCR1END_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ncr1end::W](W) writer structure"]
+impl crate::Writable for NCR1END_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NCR1END to value 0"]
+impl crate::Resettable for NCR1END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/cachectrl/ncr1start.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `NCR1START` reader"]
+pub struct R(crate::R<NCR1START_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NCR1START_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NCR1START_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NCR1START_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `NCR1START` writer"]
+pub struct W(crate::W<NCR1START_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NCR1START_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NCR1START_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NCR1START_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDR` reader - Start address for non-cacheable region 1"]
+pub type ADDR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ADDR` writer - Start address for non-cacheable region 1"]
+pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NCR1START_SPEC, u32, u32, 23, O>;
+impl R {
+    #[doc = "Bits 4:26 - Start address for non-cacheable region 1"]
+    #[inline(always)]
+    pub fn addr(&self) -> ADDR_R {
+        ADDR_R::new(((self.bits >> 4) & 0x007f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 4:26 - Start address for non-cacheable region 1"]
+    #[inline(always)]
+    pub fn addr(&mut self) -> ADDR_W<4> {
+        ADDR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash Cache Noncachable Region 1 Start\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ncr1start](index.html) module"]
+pub struct NCR1START_SPEC;
+impl crate::RegisterSpec for NCR1START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ncr1start::R](R) reader structure"]
+impl crate::Readable for NCR1START_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ncr1start::W](W) writer structure"]
+impl crate::Writable for NCR1START_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NCR1START to value 0"]
+impl crate::Resettable for NCR1START_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/clkgen.rs

@@ -0,0 +1,115 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - XT Oscillator Control"]
+    pub calxt: CALXT,
+    #[doc = "0x04 - RC Oscillator Control"]
+    pub calrc: CALRC,
+    #[doc = "0x08 - Autocalibration Counter"]
+    pub acalctr: ACALCTR,
+    #[doc = "0x0c - Oscillator Control"]
+    pub octrl: OCTRL,
+    #[doc = "0x10 - CLKOUT Frequency Select"]
+    pub clkout: CLKOUT,
+    #[doc = "0x14 - Key Register for Clock Control Register"]
+    pub clkkey: CLKKEY,
+    #[doc = "0x18 - HFRC Clock Control"]
+    pub cctrl: CCTRL,
+    #[doc = "0x1c - Clock Generator Status"]
+    pub status: STATUS,
+    #[doc = "0x20 - HFRC Adjustment"]
+    pub hfadj: HFADJ,
+    _reserved9: [u8; 0x04],
+    #[doc = "0x28 - Clock Enable Status"]
+    pub clockenstat: CLOCKENSTAT,
+    #[doc = "0x2c - Clock Enable Status"]
+    pub clocken2stat: CLOCKEN2STAT,
+    #[doc = "0x30 - Clock Enable Status"]
+    pub clocken3stat: CLOCKEN3STAT,
+    #[doc = "0x34 - HFRC Frequency Control register"]
+    pub freqctrl: FREQCTRL,
+    _reserved13: [u8; 0x04],
+    #[doc = "0x3c - BLE BUCK TON ADJUST"]
+    pub blebucktonadj: BLEBUCKTONADJ,
+    _reserved14: [u8; 0xc0],
+    #[doc = "0x100 - CLKGEN Interrupt Register: Enable"]
+    pub intrpten: INTRPTEN,
+    #[doc = "0x104 - CLKGEN Interrupt Register: Status"]
+    pub intrptstat: INTRPTSTAT,
+    #[doc = "0x108 - CLKGEN Interrupt Register: Clear"]
+    pub intrptclr: INTRPTCLR,
+    #[doc = "0x10c - CLKGEN Interrupt Register: Set"]
+    pub intrptset: INTRPTSET,
+}
+#[doc = "CALXT (rw) register accessor: an alias for `Reg<CALXT_SPEC>`"]
+pub type CALXT = crate::Reg<calxt::CALXT_SPEC>;
+#[doc = "XT Oscillator Control"]
+pub mod calxt;
+#[doc = "CALRC (rw) register accessor: an alias for `Reg<CALRC_SPEC>`"]
+pub type CALRC = crate::Reg<calrc::CALRC_SPEC>;
+#[doc = "RC Oscillator Control"]
+pub mod calrc;
+#[doc = "ACALCTR (rw) register accessor: an alias for `Reg<ACALCTR_SPEC>`"]
+pub type ACALCTR = crate::Reg<acalctr::ACALCTR_SPEC>;
+#[doc = "Autocalibration Counter"]
+pub mod acalctr;
+#[doc = "OCTRL (rw) register accessor: an alias for `Reg<OCTRL_SPEC>`"]
+pub type OCTRL = crate::Reg<octrl::OCTRL_SPEC>;
+#[doc = "Oscillator Control"]
+pub mod octrl;
+#[doc = "CLKOUT (rw) register accessor: an alias for `Reg<CLKOUT_SPEC>`"]
+pub type CLKOUT = crate::Reg<clkout::CLKOUT_SPEC>;
+#[doc = "CLKOUT Frequency Select"]
+pub mod clkout;
+#[doc = "CLKKEY (rw) register accessor: an alias for `Reg<CLKKEY_SPEC>`"]
+pub type CLKKEY = crate::Reg<clkkey::CLKKEY_SPEC>;
+#[doc = "Key Register for Clock Control Register"]
+pub mod clkkey;
+#[doc = "CCTRL (rw) register accessor: an alias for `Reg<CCTRL_SPEC>`"]
+pub type CCTRL = crate::Reg<cctrl::CCTRL_SPEC>;
+#[doc = "HFRC Clock Control"]
+pub mod cctrl;
+#[doc = "STATUS (rw) register accessor: an alias for `Reg<STATUS_SPEC>`"]
+pub type STATUS = crate::Reg<status::STATUS_SPEC>;
+#[doc = "Clock Generator Status"]
+pub mod status;
+#[doc = "HFADJ (rw) register accessor: an alias for `Reg<HFADJ_SPEC>`"]
+pub type HFADJ = crate::Reg<hfadj::HFADJ_SPEC>;
+#[doc = "HFRC Adjustment"]
+pub mod hfadj;
+#[doc = "CLOCKENSTAT (rw) register accessor: an alias for `Reg<CLOCKENSTAT_SPEC>`"]
+pub type CLOCKENSTAT = crate::Reg<clockenstat::CLOCKENSTAT_SPEC>;
+#[doc = "Clock Enable Status"]
+pub mod clockenstat;
+#[doc = "CLOCKEN2STAT (rw) register accessor: an alias for `Reg<CLOCKEN2STAT_SPEC>`"]
+pub type CLOCKEN2STAT = crate::Reg<clocken2stat::CLOCKEN2STAT_SPEC>;
+#[doc = "Clock Enable Status"]
+pub mod clocken2stat;
+#[doc = "CLOCKEN3STAT (rw) register accessor: an alias for `Reg<CLOCKEN3STAT_SPEC>`"]
+pub type CLOCKEN3STAT = crate::Reg<clocken3stat::CLOCKEN3STAT_SPEC>;
+#[doc = "Clock Enable Status"]
+pub mod clocken3stat;
+#[doc = "FREQCTRL (rw) register accessor: an alias for `Reg<FREQCTRL_SPEC>`"]
+pub type FREQCTRL = crate::Reg<freqctrl::FREQCTRL_SPEC>;
+#[doc = "HFRC Frequency Control register"]
+pub mod freqctrl;
+#[doc = "BLEBUCKTONADJ (rw) register accessor: an alias for `Reg<BLEBUCKTONADJ_SPEC>`"]
+pub type BLEBUCKTONADJ = crate::Reg<blebucktonadj::BLEBUCKTONADJ_SPEC>;
+#[doc = "BLE BUCK TON ADJUST"]
+pub mod blebucktonadj;
+#[doc = "INTRPTEN (rw) register accessor: an alias for `Reg<INTRPTEN_SPEC>`"]
+pub type INTRPTEN = crate::Reg<intrpten::INTRPTEN_SPEC>;
+#[doc = "CLKGEN Interrupt Register: Enable"]
+pub mod intrpten;
+#[doc = "INTRPTSTAT (rw) register accessor: an alias for `Reg<INTRPTSTAT_SPEC>`"]
+pub type INTRPTSTAT = crate::Reg<intrptstat::INTRPTSTAT_SPEC>;
+#[doc = "CLKGEN Interrupt Register: Status"]
+pub mod intrptstat;
+#[doc = "INTRPTCLR (rw) register accessor: an alias for `Reg<INTRPTCLR_SPEC>`"]
+pub type INTRPTCLR = crate::Reg<intrptclr::INTRPTCLR_SPEC>;
+#[doc = "CLKGEN Interrupt Register: Clear"]
+pub mod intrptclr;
+#[doc = "INTRPTSET (rw) register accessor: an alias for `Reg<INTRPTSET_SPEC>`"]
+pub type INTRPTSET = crate::Reg<intrptset::INTRPTSET_SPEC>;
+#[doc = "CLKGEN Interrupt Register: Set"]
+pub mod intrptset;

apollo3-pac/src/clkgen/acalctr.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `ACALCTR` reader"]
+pub struct R(crate::R<ACALCTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ACALCTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ACALCTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ACALCTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ACALCTR` writer"]
+pub struct W(crate::W<ACALCTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ACALCTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ACALCTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ACALCTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ACALCTR` reader - Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC."]
+pub type ACALCTR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `ACALCTR` writer - Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC."]
+pub type ACALCTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACALCTR_SPEC, u32, u32, 24, O>;
+impl R {
+    #[doc = "Bits 0:23 - Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC."]
+    #[inline(always)]
+    pub fn acalctr(&self) -> ACALCTR_R {
+        ACALCTR_R::new((self.bits & 0x00ff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC."]
+    #[inline(always)]
+    pub fn acalctr(&mut self) -> ACALCTR_W<0> {
+        ACALCTR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Autocalibration Counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acalctr](index.html) module"]
+pub struct ACALCTR_SPEC;
+impl crate::RegisterSpec for ACALCTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [acalctr::R](R) reader structure"]
+impl crate::Readable for ACALCTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [acalctr::W](W) writer structure"]
+impl crate::Writable for ACALCTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ACALCTR to value 0"]
+impl crate::Resettable for ACALCTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/clkgen/blebucktonadj.rs

@@ -0,0 +1,552 @@
+#[doc = "Register `BLEBUCKTONADJ` reader"]
+pub struct R(crate::R<BLEBUCKTONADJ_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BLEBUCKTONADJ_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BLEBUCKTONADJ_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BLEBUCKTONADJ_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `BLEBUCKTONADJ` writer"]
+pub struct W(crate::W<BLEBUCKTONADJ_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<BLEBUCKTONADJ_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<BLEBUCKTONADJ_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<BLEBUCKTONADJ_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TONLOWTHRESHOLD` reader - TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)"]
+pub type TONLOWTHRESHOLD_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `TONLOWTHRESHOLD` writer - TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)"]
+pub type TONLOWTHRESHOLD_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BLEBUCKTONADJ_SPEC, u16, u16, 10, O>;
+#[doc = "Field `TONHIGHTHRESHOLD` reader - TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)"]
+pub type TONHIGHTHRESHOLD_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `TONHIGHTHRESHOLD` writer - TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)"]
+pub type TONHIGHTHRESHOLD_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, BLEBUCKTONADJ_SPEC, u16, u16, 10, O>;
+#[doc = "Field `TONADJUSTPERIOD` reader - TON ADJUST PERIOD"]
+pub type TONADJUSTPERIOD_R = crate::FieldReader<u8, TONADJUSTPERIOD_A>;
+#[doc = "TON ADJUST PERIOD\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum TONADJUSTPERIOD_A {
+    #[doc = "3: Adjust done for every 1 3KHz period value."]
+    HFRC_3KHZ = 3,
+    #[doc = "2: Adjust done for every 1 12KHz period value."]
+    HFRC_12KHZ = 2,
+    #[doc = "1: Adjust done for every 1 47KHz period value."]
+    HFRC_47KHZ = 1,
+    #[doc = "0: Adjust done for every 1 94KHz period value."]
+    HFRC_94KHZ = 0,
+}
+impl From<TONADJUSTPERIOD_A> for u8 {
+    #[inline(always)]
+    fn from(variant: TONADJUSTPERIOD_A) -> Self {
+        variant as _
+    }
+}
+impl TONADJUSTPERIOD_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TONADJUSTPERIOD_A {
+        match self.bits {
+            3 => TONADJUSTPERIOD_A::HFRC_3KHZ,
+            2 => TONADJUSTPERIOD_A::HFRC_12KHZ,
+            1 => TONADJUSTPERIOD_A::HFRC_47KHZ,
+            0 => TONADJUSTPERIOD_A::HFRC_94KHZ,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFRC_3KHZ`"]
+    #[inline(always)]
+    pub fn is_hfrc_3khz(&self) -> bool {
+        *self == TONADJUSTPERIOD_A::HFRC_3KHZ
+    }
+    #[doc = "Checks if the value of the field is `HFRC_12KHZ`"]
+    #[inline(always)]
+    pub fn is_hfrc_12khz(&self) -> bool {
+        *self == TONADJUSTPERIOD_A::HFRC_12KHZ
+    }
+    #[doc = "Checks if the value of the field is `HFRC_47KHZ`"]
+    #[inline(always)]
+    pub fn is_hfrc_47khz(&self) -> bool {
+        *self == TONADJUSTPERIOD_A::HFRC_47KHZ
+    }
+    #[doc = "Checks if the value of the field is `HFRC_94KHZ`"]
+    #[inline(always)]
+    pub fn is_hfrc_94khz(&self) -> bool {
+        *self == TONADJUSTPERIOD_A::HFRC_94KHZ
+    }
+}
+#[doc = "Field `TONADJUSTPERIOD` writer - TON ADJUST PERIOD"]
+pub type TONADJUSTPERIOD_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, BLEBUCKTONADJ_SPEC, u8, TONADJUSTPERIOD_A, 2, O>;
+impl<'a, const O: u8> TONADJUSTPERIOD_W<'a, O> {
+    #[doc = "Adjust done for every 1 3KHz period value."]
+    #[inline(always)]
+    pub fn hfrc_3khz(self) -> &'a mut W {
+        self.variant(TONADJUSTPERIOD_A::HFRC_3KHZ)
+    }
+    #[doc = "Adjust done for every 1 12KHz period value."]
+    #[inline(always)]
+    pub fn hfrc_12khz(self) -> &'a mut W {
+        self.variant(TONADJUSTPERIOD_A::HFRC_12KHZ)
+    }
+    #[doc = "Adjust done for every 1 47KHz period value."]
+    #[inline(always)]
+    pub fn hfrc_47khz(self) -> &'a mut W {
+        self.variant(TONADJUSTPERIOD_A::HFRC_47KHZ)
+    }
+    #[doc = "Adjust done for every 1 94KHz period value."]
+    #[inline(always)]
+    pub fn hfrc_94khz(self) -> &'a mut W {
+        self.variant(TONADJUSTPERIOD_A::HFRC_94KHZ)
+    }
+}
+#[doc = "Field `TONADJUSTEN` reader - TON ADJUST ENABLE"]
+pub type TONADJUSTEN_R = crate::BitReader<TONADJUSTEN_A>;
+#[doc = "TON ADJUST ENABLE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TONADJUSTEN_A {
+    #[doc = "0: Disable Adjust for BLE BUCK TON trim value."]
+    DIS = 0,
+    #[doc = "1: Enable Adjust for BLE BUCK TON trim value."]
+    EN = 1,
+}
+impl From<TONADJUSTEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: TONADJUSTEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl TONADJUSTEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TONADJUSTEN_A {
+        match self.bits {
+            false => TONADJUSTEN_A::DIS,
+            true => TONADJUSTEN_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == TONADJUSTEN_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == TONADJUSTEN_A::EN
+    }
+}
+#[doc = "Field `TONADJUSTEN` writer - TON ADJUST ENABLE"]
+pub type TONADJUSTEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, BLEBUCKTONADJ_SPEC, TONADJUSTEN_A, O>;
+impl<'a, const O: u8> TONADJUSTEN_W<'a, O> {
+    #[doc = "Disable Adjust for BLE BUCK TON trim value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(TONADJUSTEN_A::DIS)
+    }
+    #[doc = "Enable Adjust for BLE BUCK TON trim value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(TONADJUSTEN_A::EN)
+    }
+}
+#[doc = "Field `ZEROLENDETECTTRIM` reader - BLEBUCK ZERO LENGTH DETECT TRIM"]
+pub type ZEROLENDETECTTRIM_R = crate::FieldReader<u8, ZEROLENDETECTTRIM_A>;
+#[doc = "BLEBUCK ZERO LENGTH DETECT TRIM\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ZEROLENDETECTTRIM_A {
+    #[doc = "15: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 81us (10 percent margin of error) or more value."]
+    SET_F = 15,
+    #[doc = "14: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 75.6us (10 percent margin of error) or more value."]
+    SET_E = 14,
+    #[doc = "13: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 70.2us (10 percent margin of error) or more value."]
+    SET_D = 13,
+    #[doc = "12: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 64.8us (10 percent margin of error) or more value."]
+    SET_C = 12,
+    #[doc = "11: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 59.4us (10 percent margin of error) or more value."]
+    SET_B = 11,
+    #[doc = "10: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 54.0us (10 percent margin of error) or more value."]
+    SET_A = 10,
+    #[doc = "9: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 48.6us (10 percent margin of error) or more value."]
+    SET9 = 9,
+    #[doc = "8: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 43.2us (10 percent margin of error) or more value."]
+    SET8 = 8,
+    #[doc = "7: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 37.8us (10 percent margin of error) or more value."]
+    SET7 = 7,
+    #[doc = "6: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 32.4us (10 percent margin of error) or more value."]
+    SET6 = 6,
+    #[doc = "5: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 27.0us (10 percent margin of error) or more value."]
+    SET5 = 5,
+    #[doc = "4: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 21.6us (10 percent margin of error) or more value."]
+    SET4 = 4,
+    #[doc = "3: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 16.2us (10 percent margin of error) or more value."]
+    SET3 = 3,
+    #[doc = "2: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 10.8us (10 percent margin of error) or more value."]
+    SET2 = 2,
+    #[doc = "1: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 5.4us (10 percent margin of error) or more value."]
+    SET1 = 1,
+    #[doc = "0: Indicator send when the BLE BUCK asserts blebuck_comp1 for about 2.0us (10 percent margin of error) or more value."]
+    SET0 = 0,
+}
+impl From<ZEROLENDETECTTRIM_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ZEROLENDETECTTRIM_A) -> Self {
+        variant as _
+    }
+}
+impl ZEROLENDETECTTRIM_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ZEROLENDETECTTRIM_A {
+        match self.bits {
+            15 => ZEROLENDETECTTRIM_A::SET_F,
+            14 => ZEROLENDETECTTRIM_A::SET_E,
+            13 => ZEROLENDETECTTRIM_A::SET_D,
+            12 => ZEROLENDETECTTRIM_A::SET_C,
+            11 => ZEROLENDETECTTRIM_A::SET_B,
+            10 => ZEROLENDETECTTRIM_A::SET_A,
+            9 => ZEROLENDETECTTRIM_A::SET9,
+            8 => ZEROLENDETECTTRIM_A::SET8,
+            7 => ZEROLENDETECTTRIM_A::SET7,
+            6 => ZEROLENDETECTTRIM_A::SET6,
+            5 => ZEROLENDETECTTRIM_A::SET5,
+            4 => ZEROLENDETECTTRIM_A::SET4,
+            3 => ZEROLENDETECTTRIM_A::SET3,
+            2 => ZEROLENDETECTTRIM_A::SET2,
+            1 => ZEROLENDETECTTRIM_A::SET1,
+            0 => ZEROLENDETECTTRIM_A::SET0,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `SET_F`"]
+    #[inline(always)]
+    pub fn is_set_f(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET_F
+    }
+    #[doc = "Checks if the value of the field is `SET_E`"]
+    #[inline(always)]
+    pub fn is_set_e(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET_E
+    }
+    #[doc = "Checks if the value of the field is `SET_D`"]
+    #[inline(always)]
+    pub fn is_set_d(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET_D
+    }
+    #[doc = "Checks if the value of the field is `SET_C`"]
+    #[inline(always)]
+    pub fn is_set_c(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET_C
+    }
+    #[doc = "Checks if the value of the field is `SET_B`"]
+    #[inline(always)]
+    pub fn is_set_b(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET_B
+    }
+    #[doc = "Checks if the value of the field is `SET_A`"]
+    #[inline(always)]
+    pub fn is_set_a(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET_A
+    }
+    #[doc = "Checks if the value of the field is `SET9`"]
+    #[inline(always)]
+    pub fn is_set9(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET9
+    }
+    #[doc = "Checks if the value of the field is `SET8`"]
+    #[inline(always)]
+    pub fn is_set8(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET8
+    }
+    #[doc = "Checks if the value of the field is `SET7`"]
+    #[inline(always)]
+    pub fn is_set7(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET7
+    }
+    #[doc = "Checks if the value of the field is `SET6`"]
+    #[inline(always)]
+    pub fn is_set6(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET6
+    }
+    #[doc = "Checks if the value of the field is `SET5`"]
+    #[inline(always)]
+    pub fn is_set5(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET5
+    }
+    #[doc = "Checks if the value of the field is `SET4`"]
+    #[inline(always)]
+    pub fn is_set4(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET4
+    }
+    #[doc = "Checks if the value of the field is `SET3`"]
+    #[inline(always)]
+    pub fn is_set3(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET3
+    }
+    #[doc = "Checks if the value of the field is `SET2`"]
+    #[inline(always)]
+    pub fn is_set2(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET2
+    }
+    #[doc = "Checks if the value of the field is `SET1`"]
+    #[inline(always)]
+    pub fn is_set1(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET1
+    }
+    #[doc = "Checks if the value of the field is `SET0`"]
+    #[inline(always)]
+    pub fn is_set0(&self) -> bool {
+        *self == ZEROLENDETECTTRIM_A::SET0
+    }
+}
+#[doc = "Field `ZEROLENDETECTTRIM` writer - BLEBUCK ZERO LENGTH DETECT TRIM"]
+pub type ZEROLENDETECTTRIM_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, BLEBUCKTONADJ_SPEC, u8, ZEROLENDETECTTRIM_A, 4, O>;
+impl<'a, const O: u8> ZEROLENDETECTTRIM_W<'a, O> {
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 81us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set_f(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET_F)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 75.6us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set_e(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET_E)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 70.2us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set_d(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET_D)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 64.8us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set_c(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET_C)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 59.4us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set_b(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET_B)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 54.0us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set_a(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET_A)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 48.6us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set9(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET9)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 43.2us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set8(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET8)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 37.8us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set7(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET7)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 32.4us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set6(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET6)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 27.0us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set5(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET5)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 21.6us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set4(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET4)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 16.2us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set3(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET3)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 10.8us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set2(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET2)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 5.4us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set1(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET1)
+    }
+    #[doc = "Indicator send when the BLE BUCK asserts blebuck_comp1 for about 2.0us (10 percent margin of error) or more value."]
+    #[inline(always)]
+    pub fn set0(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTTRIM_A::SET0)
+    }
+}
+#[doc = "Field `ZEROLENDETECTEN` reader - BLEBUCK ZERO LENGTH DETECT ENABLE"]
+pub type ZEROLENDETECTEN_R = crate::BitReader<ZEROLENDETECTEN_A>;
+#[doc = "BLEBUCK ZERO LENGTH DETECT ENABLE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ZEROLENDETECTEN_A {
+    #[doc = "0: Disable Zero Length Detect value."]
+    DIS = 0,
+    #[doc = "1: Enable Zero Length Detect value."]
+    EN = 1,
+}
+impl From<ZEROLENDETECTEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: ZEROLENDETECTEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ZEROLENDETECTEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ZEROLENDETECTEN_A {
+        match self.bits {
+            false => ZEROLENDETECTEN_A::DIS,
+            true => ZEROLENDETECTEN_A::EN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIS`"]
+    #[inline(always)]
+    pub fn is_dis(&self) -> bool {
+        *self == ZEROLENDETECTEN_A::DIS
+    }
+    #[doc = "Checks if the value of the field is `EN`"]
+    #[inline(always)]
+    pub fn is_en(&self) -> bool {
+        *self == ZEROLENDETECTEN_A::EN
+    }
+}
+#[doc = "Field `ZEROLENDETECTEN` writer - BLEBUCK ZERO LENGTH DETECT ENABLE"]
+pub type ZEROLENDETECTEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, BLEBUCKTONADJ_SPEC, ZEROLENDETECTEN_A, O>;
+impl<'a, const O: u8> ZEROLENDETECTEN_W<'a, O> {
+    #[doc = "Disable Zero Length Detect value."]
+    #[inline(always)]
+    pub fn dis(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTEN_A::DIS)
+    }
+    #[doc = "Enable Zero Length Detect value."]
+    #[inline(always)]
+    pub fn en(self) -> &'a mut W {
+        self.variant(ZEROLENDETECTEN_A::EN)
+    }
+}
+impl R {
+    #[doc = "Bits 0:9 - TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)"]
+    #[inline(always)]
+    pub fn tonlowthreshold(&self) -> TONLOWTHRESHOLD_R {
+        TONLOWTHRESHOLD_R::new((self.bits & 0x03ff) as u16)
+    }
+    #[doc = "Bits 10:19 - TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)"]
+    #[inline(always)]
+    pub fn tonhighthreshold(&self) -> TONHIGHTHRESHOLD_R {
+        TONHIGHTHRESHOLD_R::new(((self.bits >> 10) & 0x03ff) as u16)
+    }
+    #[doc = "Bits 20:21 - TON ADJUST PERIOD"]
+    #[inline(always)]
+    pub fn tonadjustperiod(&self) -> TONADJUSTPERIOD_R {
+        TONADJUSTPERIOD_R::new(((self.bits >> 20) & 3) as u8)
+    }
+    #[doc = "Bit 22 - TON ADJUST ENABLE"]
+    #[inline(always)]
+    pub fn tonadjusten(&self) -> TONADJUSTEN_R {
+        TONADJUSTEN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bits 23:26 - BLEBUCK ZERO LENGTH DETECT TRIM"]
+    #[inline(always)]
+    pub fn zerolendetecttrim(&self) -> ZEROLENDETECTTRIM_R {
+        ZEROLENDETECTTRIM_R::new(((self.bits >> 23) & 0x0f) as u8)
+    }
+    #[doc = "Bit 27 - BLEBUCK ZERO LENGTH DETECT ENABLE"]
+    #[inline(always)]
+    pub fn zerolendetecten(&self) -> ZEROLENDETECTEN_R {
+        ZEROLENDETECTEN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:9 - TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)"]
+    #[inline(always)]
+    pub fn tonlowthreshold(&mut self) -> TONLOWTHRESHOLD_W<0> {
+        TONLOWTHRESHOLD_W::new(self)
+    }
+    #[doc = "Bits 10:19 - TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)"]
+    #[inline(always)]
+    pub fn tonhighthreshold(&mut self) -> TONHIGHTHRESHOLD_W<10> {
+        TONHIGHTHRESHOLD_W::new(self)
+    }
+    #[doc = "Bits 20:21 - TON ADJUST PERIOD"]
+    #[inline(always)]
+    pub fn tonadjustperiod(&mut self) -> TONADJUSTPERIOD_W<20> {
+        TONADJUSTPERIOD_W::new(self)
+    }
+    #[doc = "Bit 22 - TON ADJUST ENABLE"]
+    #[inline(always)]
+    pub fn tonadjusten(&mut self) -> TONADJUSTEN_W<22> {
+        TONADJUSTEN_W::new(self)
+    }
+    #[doc = "Bits 23:26 - BLEBUCK ZERO LENGTH DETECT TRIM"]
+    #[inline(always)]
+    pub fn zerolendetecttrim(&mut self) -> ZEROLENDETECTTRIM_W<23> {
+        ZEROLENDETECTTRIM_W::new(self)
+    }
+    #[doc = "Bit 27 - BLEBUCK ZERO LENGTH DETECT ENABLE"]
+    #[inline(always)]
+    pub fn zerolendetecten(&mut self) -> ZEROLENDETECTEN_W<27> {
+        ZEROLENDETECTEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "BLE BUCK TON ADJUST\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blebucktonadj](index.html) module"]
+pub struct BLEBUCKTONADJ_SPEC;
+impl crate::RegisterSpec for BLEBUCKTONADJ_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [blebucktonadj::R](R) reader structure"]
+impl crate::Readable for BLEBUCKTONADJ_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [blebucktonadj::W](W) writer structure"]
+impl crate::Writable for BLEBUCKTONADJ_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets BLEBUCKTONADJ to value 0"]
+impl crate::Resettable for BLEBUCKTONADJ_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/clkgen/calrc.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CALRC` reader"]
+pub struct R(crate::R<CALRC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CALRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CALRC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CALRC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CALRC` writer"]
+pub struct W(crate::W<CALRC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CALRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CALRC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CALRC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CALRC` reader - LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjuction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock."]
+pub type CALRC_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `CALRC` writer - LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjuction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock."]
+pub type CALRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CALRC_SPEC, u32, u32, 18, O>;
+impl R {
+    #[doc = "Bits 0:17 - LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjuction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock."]
+    #[inline(always)]
+    pub fn calrc(&self) -> CALRC_R {
+        CALRC_R::new((self.bits & 0x0003_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:17 - LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjuction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock."]
+    #[inline(always)]
+    pub fn calrc(&mut self) -> CALRC_W<0> {
+        CALRC_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RC Oscillator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calrc](index.html) module"]
+pub struct CALRC_SPEC;
+impl crate::RegisterSpec for CALRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [calrc::R](R) reader structure"]
+impl crate::Readable for CALRC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [calrc::W](W) writer structure"]
+impl crate::Writable for CALRC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CALRC to value 0"]
+impl crate::Resettable for CALRC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/clkgen/calxt.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CALXT` reader"]
+pub struct R(crate::R<CALXT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CALXT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CALXT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CALXT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CALXT` writer"]
+pub struct W(crate::W<CALXT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CALXT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CALXT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CALXT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CALXT` reader - XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023."]
+pub type CALXT_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `CALXT` writer - XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023."]
+pub type CALXT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CALXT_SPEC, u16, u16, 11, O>;
+impl R {
+    #[doc = "Bits 0:10 - XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023."]
+    #[inline(always)]
+    pub fn calxt(&self) -> CALXT_R {
+        CALXT_R::new((self.bits & 0x07ff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:10 - XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023."]
+    #[inline(always)]
+    pub fn calxt(&mut self) -> CALXT_W<0> {
+        CALXT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "XT Oscillator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calxt](index.html) module"]
+pub struct CALXT_SPEC;
+impl crate::RegisterSpec for CALXT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [calxt::R](R) reader structure"]
+impl crate::Readable for CALXT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [calxt::W](W) writer structure"]
+impl crate::Writable for CALXT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CALXT to value 0"]
+impl crate::Resettable for CALXT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

apollo3-pac/src/clkgen/cctrl.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `CCTRL` reader"]
+pub struct R(crate::R<CCTRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CCTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CCTRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CCTRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CCTRL` writer"]
+pub struct W(crate::W<CCTRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CCTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CCTRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CCTRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CORESEL` reader - Core Clock divisor"]
+pub type CORESEL_R = crate::BitReader<CORESEL_A>;
+#[doc = "Core Clock divisor\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CORESEL_A {
+    #[doc = "0: Core Clock is HFRC value."]
+    HFRC = 0,
+    #[doc = "1: Core Clock is HFRC / 2 value."]
+    HFRC_DIV2 = 1,
+}
+impl From<CORESEL_A> for bool {
+    #[inline(always)]
+    fn from(variant: CORESEL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CORESEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CORESEL_A {
+        match self.bits {
+            false => CORESEL_A::HFRC,
+            true => CORESEL_A::HFRC_DIV2,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFRC`"]
+    #[inline(always)]
+    pub fn is_hfrc(&self) -> bool {
+        *self == CORESEL_A::HFRC
+    }
+    #[doc = "Checks if the value of the field is `HFRC_DIV2`"]
+    #[inline(always)]
+    pub fn is_hfrc_div2(&self) -> bool {
+        *self == CORESEL_A::HFRC_DIV2
+    }
+}
+#[doc = "Field `CORESEL` writer - Core Clock divisor"]
+pub type CORESEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCTRL_SPEC, CORESEL_A, O>;
+impl<'a, const O: u8> CORESEL_W<'a, O> {
+    #[doc = "Core Clock is HFRC value."]
+    #[inline(always)]
+    pub fn hfrc(self) -> &'a mut W {
+        self.variant(CORESEL_A::HFRC)
+    }
+    #[doc = "Core Clock is HFRC / 2 value."]
+    #[inline(always)]
+    pub fn hfrc_div2(self) -> &'a mut W {
+        self.variant(CORESEL_A::HFRC_DIV2)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Core Clock divisor"]
+    #[inline(always)]
+    pub fn coresel(&self) -> CORESEL_R {
+        CORESEL_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core Clock divisor"]
+    #[inline(always)]
+    pub fn coresel(&mut self) -> CORESEL_W<0> {
+        CORESEL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "HFRC Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cctrl](index.html) module"]
+pub struct CCTRL_SPEC;
+impl crate::RegisterSpec for CCTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cctrl::R](R) reader structure"]
+impl crate::Readable for CCTRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cctrl::W](W) writer structure"]
+impl crate::Writable for CCTRL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CCTRL to value 0x01"]
+impl crate::Resettable for CCTRL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

apollo3-pac/src/clkgen/clkkey.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `CLKKEY` reader"]
+pub struct R(crate::R<CLKKEY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CLKKEY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CLKKEY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CLKKEY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CLKKEY` writer"]
+pub struct W(crate::W<CLKKEY_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CLKKEY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CLKKEY_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CLKKEY_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CLKKEY` reader - Key register value."]
+pub type CLKKEY_R = crate::FieldReader<u32, CLKKEY_A>;
+#[doc = "Key register value.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum CLKKEY_A {
+    #[doc = "71: Key value."]
+    KEY = 71,
+}
+impl From<CLKKEY_A> for u32 {
+    #[inline(always)]
+    fn from(variant: CLKKEY_A) -> Self {
+        variant as _
+    }
+}
+impl CLKKEY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CLKKEY_A> {
+        match self.bits {
+            71 => Some(CLKKEY_A::KEY),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `KEY`"]
+    #[inline(always)]
+    pub fn is_key(&self) -> bool {
+        *self == CLKKEY_A::KEY
+    }
+}
+#[doc = "Field `CLKKEY` writer - Key register value."]
+pub type CLKKEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKKEY_SPEC, u32, CLKKEY_A, 32, O>;
+impl<'a, const O: u8> CLKKEY_W<'a, O> {
+    #[doc = "Key value."]
+    #[inline(always)]
+    pub fn key(self) -> &'a mut W {
+        self.variant(CLKKEY_A::KEY)
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Key register value."]
+    #[inline(always)]
+    pub fn clkkey(&self) -> CLKKEY_R {
+        CLKKEY_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Key register value."]
+    #[inline(always)]
+    pub fn clkkey(&mut self) -> CLKKEY_W<0> {
+        CLKKEY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Key Register for Clock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkkey](index.html) module"]
+pub struct CLKKEY_SPEC;
+impl crate::RegisterSpec for CLKKEY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [clkkey::R](R) reader structure"]
+impl crate::Readable for CLKKEY_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [clkkey::W](W) writer structure"]
+impl crate::Writable for CLKKEY_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CLKKEY to value 0"]
+impl crate::Resettable for CLKKEY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}