vance/vos
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
vance
2022-10-23 23:45:43 -07:00
commit e190fa5193
6450 changed files with 8626944 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo3p/regs/am_reg.h
+281
View File
@@ -0,0 +1,281 @@
//*****************************************************************************
//
// am_reg.h
//! @file
//!
//! @brief Apollo4 register macros
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_H
#define AM_REG_H
//*****************************************************************************
//
// ADC
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_ADC_NUM_MODULES 1
#define AM_REG_ADCn(n) \
(REG_ADC_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// APBDMA
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_APBDMA_NUM_MODULES 1
#define AM_REG_APBDMAn(n) \
(REG_APBDMA_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// BLEIF
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_BLEIF_NUM_MODULES 1
#define AM_REG_BLEIFn(n) \
(REG_BLEIF_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// CACHECTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_CACHECTRL_NUM_MODULES 1
#define AM_REG_CACHECTRLn(n) \
(REG_CACHECTRL_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// CLKGEN
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_CLKGEN_NUM_MODULES 1
#define AM_REG_CLKGENn(n) \
(REG_CLKGEN_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// CTIMER
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_CTIMER_NUM_MODULES 1
#define AM_REG_CTIMERn(n) \
(REG_CTIMER_BASEADDR + 0x00000020 * n)
//*****************************************************************************
//
// FLASHCTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_FLASHCTRL_NUM_MODULES 1
#define AM_REG_FLASHCTRLn(n) \
(REG_FLASHCTRL_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// GPIO
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_GPIO_NUM_MODULES 1
#define AM_REG_GPIOn(n) \
(REG_GPIO_BASEADDR + 0x00000004 * n)
//*****************************************************************************
//
// IOM
// Instance finder. (6 instance(s) available)
//
//*****************************************************************************
#define AM_REG_IOM_NUM_MODULES 6
#define AM_REG_IOMn(n) \
(REG_IOM_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// IOSLAVE
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_IOSLAVE_NUM_MODULES 1
#define AM_REG_IOSLAVEn(n) \
(REG_IOSLAVE_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// MCUCTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_MCUCTRL_NUM_MODULES 1
#define AM_REG_MCUCTRLn(n) \
(REG_MCUCTRL_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// MSPI
// Instance finder. (3 instance(s) available)
//
//*****************************************************************************
#define AM_REG_MSPI_NUM_MODULES 3
#define AM_REG_MSPIn(n) \
(REG_MSPI_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// PDM
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_PDM_NUM_MODULES 1
#define AM_REG_PDMn(n) \
(REG_PDM_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// PWRCTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_PWRCTRL_NUM_MODULES 1
#define AM_REG_PWRCTRLn(n) \
(REG_PWRCTRL_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// RSTGEN
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_RSTGEN_NUM_MODULES 1
#define AM_REG_RSTGENn(n) \
(REG_RSTGEN_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// RTC
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_RTC_NUM_MODULES 1
#define AM_REG_RTCn(n) \
(REG_RTC_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// SCARD
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_SCARD_NUM_MODULES 1
#define AM_REG_SCARDn(n) \
(REG_SCARD_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// SECURITY
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_SECURITY_NUM_MODULES 1
#define AM_REG_SECURITYn(n) \
(REG_SECURITY_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// UART
// Instance finder. (2 instance(s) available)
//
//*****************************************************************************
#define AM_REG_UART_NUM_MODULES 2
#define AM_REG_UARTn(n) \
(REG_UART_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// VCOMP
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_VCOMP_NUM_MODULES 1
#define AM_REG_VCOMPn(n) \
(REG_VCOMP_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// WDT
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_WDT_NUM_MODULES 1
#define AM_REG_WDTn(n) \
(REG_WDT_BASEADDR + 0x00000000 * n)
#endif // AM_REG_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo3p/regs/am_reg_base_addresses.h
+108
View File
@@ -0,0 +1,108 @@
//*****************************************************************************
//
// am_reg_base_addresses.h
//! @file
//!
//! @brief Register defines for all module base addresses
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_BASE_ADDRESSES_H
#define AM_REG_BASE_ADDRESSES_H
#include "stdint.h"
//
// ARM standard register space (needed for macros)
//
#define REG_ITM_BASEADDR (0x00000000UL)
#define REG_JEDEC_BASEADDR (0x00000000UL)
#define REG_NVIC_BASEADDR (0x00000000UL)
#define REG_SYSCTRL_BASEADDR (0x00000000UL)
#define REG_SYSTICK_BASEADDR (0x00000000UL)
#define REG_TPIU_BASEADDR (0x00000000UL)
//
// Peripheral register space
//
#define REG_ADC_BASEADDR (0x50010000UL)
#define REG_APBDMA_BASEADDR (0x40011000UL)
#define REG_BLEIF_BASEADDR (0x5000C000UL)
#define REG_CACHECTRL_BASEADDR (0x40018000UL)
#define REG_CLKGEN_BASEADDR (0x40004000UL)
#define REG_CTIMER_BASEADDR (0x40008000UL)
#define REG_GPIO_BASEADDR (0x40010000UL)
//#define REG_IOMSTR_BASEADDR (0x50004000UL)
#define REG_IOM_BASEADDR (0x50004000UL)
#define REG_IOSLAVE_BASEADDR (0x50000000UL)
#define REG_MCUCTRL_BASEADDR (0x40020000UL)
#define REG_MSPI_BASEADDR (0x50014000UL)
#define REG_PDM_BASEADDR (0x50011000UL)
#define REG_PWRCTRL_BASEADDR (0x40021000UL)
#define REG_RSTGEN_BASEADDR (0x40000000UL)
#define REG_RTC_BASEADDR (0x40004200UL)
#define REG_SCARD_BASEADDR (0x40080000UL)
#define REG_SECURITY_BASEADDR (0x40030000UL)
#define REG_UART_BASEADDR (0x4001C000UL)
#define REG_VCOMP_BASEADDR (0x4000C000UL)
#define REG_WDT_BASEADDR (0x40024000UL)
//
// SRAM address space
//
#define SRAM_BASEADDR (0x10000000UL)
//
// Flash address space
//
#define FLASH_BASEADDR (0x00000000UL)
//
// MSPI XIP & XIPMM addresses
//
#define MSPI0_XIP_BASEADDR (0x02000000UL)
#define MSPI0_XIPMM_BASEADDR (0x52000000UL)
#define MSPI1_XIP_BASEADDR (0x04000000UL)
#define MSPI1_XIPMM_BASEADDR (0x54000000UL)
#define MSPI2_XIP_BASEADDR (0x06000000UL)
#define MSPI2_XIPMM_BASEADDR (0x56000000UL)
#endif // AM_REG_BASE_ADDRESSES_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo3p/regs/am_reg_iomstr_cmd.h
+76
View File
@@ -0,0 +1,76 @@
//*****************************************************************************
//
// am_reg_iomstr_cmd.h
//! @file
//!
//! @brief Register macros for the IOMSTR module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_IOMSTR_CMD_H
#define AM_REG_IOMSTR_CMD_H
#if AM_PART_APOLLO2
//*****************************************************************************
//
// IOMSTR_CMD - Command Register
//
//*****************************************************************************
#define AM_REG_IOMSTR_CMD_CMD_POS_LENGTH 0x00000000
#define AM_REG_IOMSTR_CMD_CMD_POS_OFFSET 0x00000008
#define AM_REG_IOMSTR_CMD_CMD_POS_ADDRESS 0x00000010
#define AM_REG_IOMSTR_CMD_CMD_POS_CHNL 0x00000010
#define AM_REG_IOMSTR_CMD_CMD_POS_UPLNGTH 0x00000017
#define AM_REG_IOMSTR_CMD_CMD_POS_10BIT 0x0000001A
#define AM_REG_IOMSTR_CMD_CMD_POS_LSB 0x0000001B
#define AM_REG_IOMSTR_CMD_CMD_POS_CONT 0x0000001C
#define AM_REG_IOMSTR_CMD_CMD_POS_OPER 0x0000001D
#define AM_REG_IOMSTR_CMD_CMD_MSK_LENGTH 0x000000FF
#define AM_REG_IOMSTR_CMD_CMD_MSK_OFFSET 0x0000FF00
#define AM_REG_IOMSTR_CMD_CMD_MSK_ADDRESS 0x00FF0000
#define AM_REG_IOMSTR_CMD_CMD_MSK_CHNL 0x00070000
#define AM_REG_IOMSTR_CMD_CMD_MSK_UPLNGTH 0x07800000
#define AM_REG_IOMSTR_CMD_CMD_MSK_10BIT 0x04000000
#define AM_REG_IOMSTR_CMD_CMD_MSK_LSB 0x08000000
#define AM_REG_IOMSTR_CMD_CMD_MSK_CONT 0x10000000
#define AM_REG_IOMSTR_CMD_CMD_MSK_OPER 0xE0000000
#endif // AM_PART_APOLLO2
#endif // AM_REG_IOMSTR_CMD_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo3p/regs/am_reg_jedec.h
+369
View File
@@ -0,0 +1,369 @@
//*****************************************************************************
//
// am_reg_jedec.h
//! @file
//!
//! @brief Register macros for the ARM JEDEC module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_JEDEC_H
#define AM_REG_JEDEC_H
//*****************************************************************************
//
// JEDEC
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_JEDEC_NUM_MODULES 1
#define AM_REG_JEDECn(n) \
(REG_JEDEC_BASEADDR + 0x00000000 * n)
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language = extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/**
\brief Structure type to access the Apollo CM4 JEDEC registers.
*/
typedef struct
{
uint32_t RESERVED0[52U]; /* 0xF00 - 0xFCF */
union
{
__IM uint32_t PID4; /*!< 0xF0000FD0 (R/ ) PID4 Register */
struct
{
__IM uint32_t JEPCONT : 4; /* [3..0] Contains the JEP Continuation bits. */
} PID4_b;
};
union
{
__IM uint32_t PID5; /*!< 0xF0000FD4 (R/ ) PID5 Register */
struct
{
__IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */
} PID5_b;
};
union
{
__IM uint32_t PID6; /*!< 0xF0000FD8 (R/ ) PID6 Register */
struct
{
__IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */
} PID6_b;
};
union
{
__IM uint32_t PID7; /*!< 0xF0000FDC (R/ ) PID7 Register */
struct
{
__IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */
} PID7_b;
};
union
{
__IM uint32_t PID0; /*!< 0xF0000FE0 (R/ ) PID0 Register */
struct
{
__IM uint32_t PNL8 : 8; /* [7..0] Contains the low 8 bits of the Ambiq Micro device part number. */
} PID0_b;
};
union
{
__IM uint32_t PID1; /*!< 0xF0000FE4 (R/ ) PID1 Register */
struct
{
__IM uint32_t PNH4 : 4; /* [3..0] Contains the high 4 bits of the Ambiq Micro device part number. */
__IM uint32_t JEPIDL : 4; /* [7..4] Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID is therefore 0x9B. */
} PID1_b;
};
union
{
__IM uint32_t PID2; /*!< 0xF0000FE8 (R/ ) PID2 Register */
struct
{
__IM uint32_t JEPIDH : 4; /* [3..0] Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this field is hard-coded to 1. The full JEPID is therefore 0x9B. */
__IM uint32_t CHIPREVH4 : 4; /* [7..4] Contains the high 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */
} PID2_b;
};
union
{
__IM uint32_t PID3; /*!< 0xF0000FEC (R/ ) PID3 Register */
struct
{
__IM uint32_t ZERO : 4; /* [3..0] This field is hard-coded to 0x0. */
__IM uint32_t CHIPREVL4 : 4; /* [7..0] Contains the low 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */
} PID3_b;
};
union
{
__IM uint32_t CID0; /*!< 0xF0000FE0 (R/ ) CID0 Register */
struct
{
__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID0. */
} CID0_b;
};
union
{
__IM uint32_t CID1; /*!< 0xF0000FE4 (R/ ) CID1 Register */
struct
{
__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID1. */
} CID1_b;
};
union
{
__IM uint32_t CID2; /*!< 0xF0000FE8 (R/ ) CID2 Register */
struct
{
__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID2. */
} CID2_b;
};
union
{
__IM uint32_t CID3; /*!< 0xF0000FEC (R/ ) CID3 Register */
struct
{
__IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID3. */
} CID3_b;
};
} JEDEC_Type;
//*****************************************************************************
//
// JEDEC_PID4 - JEP Continuation Register
//
//*****************************************************************************
// Contains the JEP Continuation bits.
#define JEDEC_PID4_JEPCONT_Pos 0U
#define JEDEC_PID4_JEPCONT_Msk (0x0000000FUL)
//*****************************************************************************
//
// JEDEC_PID5 - JEP reserved Register
//
//*****************************************************************************
// Contains the value of 0x00000000.
#define JEDEC_PID5_VALUE_Pos 0U
#define JEDEC_PID5_VALUE_Msk (0xFFFFFFFFUL)
//*****************************************************************************
//
// JEDEC_PID6 - JEP reserved Register
//
//*****************************************************************************
// Contains the value of 0x00000000.
#define JEDEC_PID6_VALUE_Pos 0U
#define JEDEC_PID6_VALUE_Msk (0xFFFFFFFFUL)
//*****************************************************************************
//
// JEDEC_PID7 - JEP reserved Register
//
//*****************************************************************************
// Contains the value of 0x00000000.
#define JEDEC_PID7_VALUE_Pos 0U
#define JEDEC_PID7_VALUE_Msk (0xFFFFFFFFUL)
//*****************************************************************************
//
// JEDEC_PID0 - Ambiq Partnum low byte
//
//*****************************************************************************
// Contains the low 8 bits of the Ambiq Micro device part number.
#define JEDEC_PID0_PNL8_Pos 0U
#define JEDEC_PID0_PNL8_Msk (0x000000FFUL)
//*****************************************************************************
//
// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble.
//
//*****************************************************************************
// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID
// is therefore 0x9B.
#define JEDEC_PID1_JEPIDL_Pos 4U
#define JEDEC_PID1_JEPIDL_Msk (0x000000F0UL)
// Contains the high 4 bits of the Ambiq Micro device part number.
#define JEDEC_PID1_PNH4_Pos 0U
#define JEDEC_PID1_PNH4_Msk (0x0000000FUL)
//*****************************************************************************
//
// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble
//
//*****************************************************************************
// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also
// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
// chip.
#define JEDEC_PID2_CHIPREVH4_Pos 4U
#define JEDEC_PID2_CHIPREVH4_Msk (0x000000F0UL)
// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this
// field is hard-coded to 1. The full JEPID is therefore 0x9B.
#define JEDEC_PID2_JEPIDH_Pos 0U
#define JEDEC_PID2_JEPIDH_Msk (0x0000000FUL)
//*****************************************************************************
//
// JEDEC_PID3 - Ambiq chip revision high-nibble.
//
//*****************************************************************************
// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also
// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
// chip.
#define JEDEC_PID3_CHIPREVL4_Pos 4U
#define JEDEC_PID3_CHIPREVL4_Msk (0x000000F0UL)
// This field is hard-coded to 0x0.
#define JEDEC_PID3_ZERO_Pos 0U
#define JEDEC_PID3_ZERO_Msk (0x0000000FUL)
//*****************************************************************************
//
// JEDEC_CID0 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID0.
#define JEDEC_CID0_CID_Pos 0U
#define JEDEC_CID0_CID_Msk (0x000000FFUL)
//*****************************************************************************
//
// JEDEC_CID1 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID1.
#define JEDEC_CID1_CID_Pos 0U
#define JEDEC_CID1_CID_Msk (0x000000FFUL)
//*****************************************************************************
//
// JEDEC_CID2 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID2.
#define JEDEC_CID2_CID_Pos 0U
#define JEDEC_CID2_CID_Msk (0x000000FFUL)
//*****************************************************************************
//
// JEDEC_CID3 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID3.
#define JEDEC_CID3_CID_Pos 0U
#define JEDEC_CID3_CID_Msk (0x000000FFUL)
#define JEDEC_BASE (0xF0000F00UL) /*!< JEDEC Base Address */
#define JEDEC ((JEDEC_Type *) JEDEC_BASE ) /*!< JEDEC configuration struct */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#endif
#endif // AM_REG_JEDEC_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo3p/regs/am_reg_m4.h
+92
View File
@@ -0,0 +1,92 @@
//*****************************************************************************
//
// am_reg_m4.h
//! @file
//!
//! @brief A collection of a few CMSIS-style macros that are not automatically
//! generated in their respective core files.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_CM4_H
#define AM_REG_CM4_H
//*****************************************************************************
//
// am_reg_itm.h
// CMSIS-style defines.
//
//*****************************************************************************
#define ITM_LAR_KEYVAL 0xC5ACCE55
//*****************************************************************************
//
// am_reg_sysctrl.h
// CMSIS-style defines.
//
//*****************************************************************************
#define SCB_CPACR_CP11_Pos 22
#define SCB_CPACR_CP11_Msk 0x00C00000
#define SCB_CPACR_CP10_Pos 20
#define SCB_CPACR_CP10_Msk 0x00300000
//*****************************************************************************
//
// am_reg_tpiu.h
// CMSIS-style defines.
//
//*****************************************************************************
#define TPI_CSPSR_CWIDTH_1BIT 1
#define TPI_SPPR_TXMODE_UART 2
#define TPI_ITCTRL_Mode_NORMAL 0
#ifndef TPI_ACPR_SWOSCALER_Pos
//
// In the CMSIS 5.6.0 version of core_cm4.h, the SWOSCALER field was no longer
// defined, while the PRESCALER field was left intact even though previous CMSIS
// versions PRESCALER as deprecated. On the off chance that future versions
// make a correction and remove PRESCALER, define SWOSCALER here (per 5.3.0).
//
#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
#endif
#endif // AM_REG_CM4_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo3p/regs/am_reg_macros.h
+138
View File
@@ -0,0 +1,138 @@
//*****************************************************************************
//
// am_reg_macros.h
//! @file
//!
//! @brief Helper macros for using hardware registers.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_MACROS_H
#define AM_REG_MACROS_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// For direct 32-bit access to a register or memory location, use AM_REGVAL:
// AM_REGVAL(0x1234567) |= 0xDEADBEEF;
//
//*****************************************************************************
#define AM_REGVAL(x) (*((volatile uint32_t *)(x)))
#define AM_REGVAL_FLOAT(x) (*((volatile float *)(x)))
//*****************************************************************************
//
// AM_REGADDR()
// One thing CMSIS does not do well natively is to provide for static register
// address computation. The address-of operator (e.g. &periph->reg) is helpful,
// but does run into problems, such as when attempting to cast the resulting
// pointer to a uint32_t. The standard C macro, offsetof() can help.
//
// Use AM_REGADDR() for single-module peripherals.
// Use AM_REGADDRn() for multi-module peripherals (e.g. IOM, UART).
//
//*****************************************************************************
#define AM_REGADDR(periph, reg) ( periph##_BASE + offsetof(periph##_Type, reg) )
#define AM_REGADDRn(periph, n, reg) ( periph##0_BASE + \
offsetof(periph##0_Type, reg) + \
(n * (periph##1_BASE - periph##0_BASE)) )
//*****************************************************************************
//
// Critical section assembly macros
//
// These macros call functions that implement critical section protection using
// inline assembly for various compilers. They are intended to be used in other
// register macros or directly in sections of code.
//
// Important usage note: These macros create a local scope and therefore MUST
// be used in pairs.
//
//*****************************************************************************
#define AM_CRITICAL_BEGIN \
if ( 1 ) \
{ \
volatile uint32_t ui32Primask_04172010; \
ui32Primask_04172010 = am_hal_interrupt_master_disable();
#define AM_CRITICAL_END \
am_hal_interrupt_master_set(ui32Primask_04172010); \
}
//*****************************************************************************
//
// Compiler-specific macros.
//
// Macros that accomplish compiler-specific tasks.
// For example, suppression of certain compiler warnings.
//
//*****************************************************************************
#if defined(__IAR_SYSTEMS_ICC__)
/* Suppress IAR compiler warning about volatile ordering */
#define DIAG_SUPPRESS_VOLATILE_ORDER() _Pragma("diag_suppress=Pa082")
/* Restore IAR compiler warning to default */
#define DIAG_DEFAULT_VOLATILE_ORDER() _Pragma("diag_default=Pa082")
#else
#define DIAG_SUPPRESS_VOLATILE_ORDER()
#define DIAG_DEFAULT_VOLATILE_ORDER()
#endif
//
// The intrinsic for IAR's CLZ instruction is different than other compilers.
//
#ifdef __IAR_SYSTEMS_ICC__
#define AM_ASM_CLZ(ui32val) __CLZ(ui32val)
#else
#define AM_ASM_CLZ(ui32val) __builtin_clz(ui32val)
#endif
#ifdef __cplusplus
}
#endif
#endif // AM_REG_MACROS_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo3p/regs/am_reg_macros_asm.h
+63
View File
@@ -0,0 +1,63 @@
//*****************************************************************************
//
// am_reg_macros_asm.h
//! @file
//!
//! @brief Inline assembly macros. Initially for critical section handling in
//! protecting hardware registers.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_MACROS_ASM_H
#define AM_REG_MACROS_ASM_H
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif // AM_REG_MACROS_ASM_H