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ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_adc.h
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//*****************************************************************************
//
// am_reg_adc.h
//! @file
//!
//! @brief Register macros for the ADC module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_ADC_H
#define AM_REG_ADC_H
//*****************************************************************************
//
// ADC
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_ADC_NUM_MODULES 1
#define AM_REG_ADCn(n) \
(REG_ADC_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_ADC_CFG_O 0x00000000
#define AM_REG_ADC_STAT_O 0x00000004
#define AM_REG_ADC_SWT_O 0x00000008
#define AM_REG_ADC_SL0CFG_O 0x0000000C
#define AM_REG_ADC_SL1CFG_O 0x00000010
#define AM_REG_ADC_SL2CFG_O 0x00000014
#define AM_REG_ADC_SL3CFG_O 0x00000018
#define AM_REG_ADC_SL4CFG_O 0x0000001C
#define AM_REG_ADC_SL5CFG_O 0x00000020
#define AM_REG_ADC_SL6CFG_O 0x00000024
#define AM_REG_ADC_SL7CFG_O 0x00000028
#define AM_REG_ADC_WULIM_O 0x0000002C
#define AM_REG_ADC_WLLIM_O 0x00000030
#define AM_REG_ADC_FIFO_O 0x00000038
#define AM_REG_ADC_INTEN_O 0x00000200
#define AM_REG_ADC_INTSTAT_O 0x00000204
#define AM_REG_ADC_INTCLR_O 0x00000208
#define AM_REG_ADC_INTSET_O 0x0000020C
//*****************************************************************************
//
// ADC_INTEN - ADC Interrupt registers: Enable
//
//*****************************************************************************
// Window comparator voltage incursion interrupt.
#define AM_REG_ADC_INTEN_WCINC_S 5
#define AM_REG_ADC_INTEN_WCINC_M 0x00000020
#define AM_REG_ADC_INTEN_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_ADC_INTEN_WCINC_WCINCINT 0x00000020
// Window comparator voltage excursion interrupt.
#define AM_REG_ADC_INTEN_WCEXC_S 4
#define AM_REG_ADC_INTEN_WCEXC_M 0x00000010
#define AM_REG_ADC_INTEN_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_ADC_INTEN_WCEXC_WCEXCINT 0x00000010
// FIFO 100 percent full interrupt.
#define AM_REG_ADC_INTEN_FIFOOVR2_S 3
#define AM_REG_ADC_INTEN_FIFOOVR2_M 0x00000008
#define AM_REG_ADC_INTEN_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_ADC_INTEN_FIFOOVR2_FIFOFULLINT 0x00000008
// FIFO 75 percent full interrupt.
#define AM_REG_ADC_INTEN_FIFOOVR1_S 2
#define AM_REG_ADC_INTEN_FIFOOVR1_M 0x00000004
#define AM_REG_ADC_INTEN_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_ADC_INTEN_FIFOOVR1_FIFO75INT 0x00000004
// ADC scan complete interrupt.
#define AM_REG_ADC_INTEN_SCNCMP_S 1
#define AM_REG_ADC_INTEN_SCNCMP_M 0x00000002
#define AM_REG_ADC_INTEN_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_INTEN_SCNCMP_SCNCMPINT 0x00000002
// ADC conversion complete interrupt.
#define AM_REG_ADC_INTEN_CNVCMP_S 0
#define AM_REG_ADC_INTEN_CNVCMP_M 0x00000001
#define AM_REG_ADC_INTEN_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_INTEN_CNVCMP_CNVCMPINT 0x00000001
//*****************************************************************************
//
// ADC_INTSTAT - ADC Interrupt registers: Status
//
//*****************************************************************************
// Window comparator voltage incursion interrupt.
#define AM_REG_ADC_INTSTAT_WCINC_S 5
#define AM_REG_ADC_INTSTAT_WCINC_M 0x00000020
#define AM_REG_ADC_INTSTAT_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_ADC_INTSTAT_WCINC_WCINCINT 0x00000020
// Window comparator voltage excursion interrupt.
#define AM_REG_ADC_INTSTAT_WCEXC_S 4
#define AM_REG_ADC_INTSTAT_WCEXC_M 0x00000010
#define AM_REG_ADC_INTSTAT_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_ADC_INTSTAT_WCEXC_WCEXCINT 0x00000010
// FIFO 100 percent full interrupt.
#define AM_REG_ADC_INTSTAT_FIFOOVR2_S 3
#define AM_REG_ADC_INTSTAT_FIFOOVR2_M 0x00000008
#define AM_REG_ADC_INTSTAT_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_ADC_INTSTAT_FIFOOVR2_FIFOFULLINT 0x00000008
// FIFO 75 percent full interrupt.
#define AM_REG_ADC_INTSTAT_FIFOOVR1_S 2
#define AM_REG_ADC_INTSTAT_FIFOOVR1_M 0x00000004
#define AM_REG_ADC_INTSTAT_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_ADC_INTSTAT_FIFOOVR1_FIFO75INT 0x00000004
// ADC scan complete interrupt.
#define AM_REG_ADC_INTSTAT_SCNCMP_S 1
#define AM_REG_ADC_INTSTAT_SCNCMP_M 0x00000002
#define AM_REG_ADC_INTSTAT_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_INTSTAT_SCNCMP_SCNCMPINT 0x00000002
// ADC conversion complete interrupt.
#define AM_REG_ADC_INTSTAT_CNVCMP_S 0
#define AM_REG_ADC_INTSTAT_CNVCMP_M 0x00000001
#define AM_REG_ADC_INTSTAT_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_INTSTAT_CNVCMP_CNVCMPINT 0x00000001
//*****************************************************************************
//
// ADC_INTCLR - ADC Interrupt registers: Clear
//
//*****************************************************************************
// Window comparator voltage incursion interrupt.
#define AM_REG_ADC_INTCLR_WCINC_S 5
#define AM_REG_ADC_INTCLR_WCINC_M 0x00000020
#define AM_REG_ADC_INTCLR_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_ADC_INTCLR_WCINC_WCINCINT 0x00000020
// Window comparator voltage excursion interrupt.
#define AM_REG_ADC_INTCLR_WCEXC_S 4
#define AM_REG_ADC_INTCLR_WCEXC_M 0x00000010
#define AM_REG_ADC_INTCLR_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_ADC_INTCLR_WCEXC_WCEXCINT 0x00000010
// FIFO 100 percent full interrupt.
#define AM_REG_ADC_INTCLR_FIFOOVR2_S 3
#define AM_REG_ADC_INTCLR_FIFOOVR2_M 0x00000008
#define AM_REG_ADC_INTCLR_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_ADC_INTCLR_FIFOOVR2_FIFOFULLINT 0x00000008
// FIFO 75 percent full interrupt.
#define AM_REG_ADC_INTCLR_FIFOOVR1_S 2
#define AM_REG_ADC_INTCLR_FIFOOVR1_M 0x00000004
#define AM_REG_ADC_INTCLR_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_ADC_INTCLR_FIFOOVR1_FIFO75INT 0x00000004
// ADC scan complete interrupt.
#define AM_REG_ADC_INTCLR_SCNCMP_S 1
#define AM_REG_ADC_INTCLR_SCNCMP_M 0x00000002
#define AM_REG_ADC_INTCLR_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_INTCLR_SCNCMP_SCNCMPINT 0x00000002
// ADC conversion complete interrupt.
#define AM_REG_ADC_INTCLR_CNVCMP_S 0
#define AM_REG_ADC_INTCLR_CNVCMP_M 0x00000001
#define AM_REG_ADC_INTCLR_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_INTCLR_CNVCMP_CNVCMPINT 0x00000001
//*****************************************************************************
//
// ADC_INTSET - ADC Interrupt registers: Set
//
//*****************************************************************************
// Window comparator voltage incursion interrupt.
#define AM_REG_ADC_INTSET_WCINC_S 5
#define AM_REG_ADC_INTSET_WCINC_M 0x00000020
#define AM_REG_ADC_INTSET_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_ADC_INTSET_WCINC_WCINCINT 0x00000020
// Window comparator voltage excursion interrupt.
#define AM_REG_ADC_INTSET_WCEXC_S 4
#define AM_REG_ADC_INTSET_WCEXC_M 0x00000010
#define AM_REG_ADC_INTSET_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_ADC_INTSET_WCEXC_WCEXCINT 0x00000010
// FIFO 100 percent full interrupt.
#define AM_REG_ADC_INTSET_FIFOOVR2_S 3
#define AM_REG_ADC_INTSET_FIFOOVR2_M 0x00000008
#define AM_REG_ADC_INTSET_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_ADC_INTSET_FIFOOVR2_FIFOFULLINT 0x00000008
// FIFO 75 percent full interrupt.
#define AM_REG_ADC_INTSET_FIFOOVR1_S 2
#define AM_REG_ADC_INTSET_FIFOOVR1_M 0x00000004
#define AM_REG_ADC_INTSET_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_ADC_INTSET_FIFOOVR1_FIFO75INT 0x00000004
// ADC scan complete interrupt.
#define AM_REG_ADC_INTSET_SCNCMP_S 1
#define AM_REG_ADC_INTSET_SCNCMP_M 0x00000002
#define AM_REG_ADC_INTSET_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_INTSET_SCNCMP_SCNCMPINT 0x00000002
// ADC conversion complete interrupt.
#define AM_REG_ADC_INTSET_CNVCMP_S 0
#define AM_REG_ADC_INTSET_CNVCMP_M 0x00000001
#define AM_REG_ADC_INTSET_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_INTSET_CNVCMP_CNVCMPINT 0x00000001
//*****************************************************************************
//
// ADC_CFG - Configuration Register
//
//*****************************************************************************
// Select the source and frequency for the ADC clock. All values not enumerated
// below are undefined.
#define AM_REG_ADC_CFG_CLKSEL_S 24
#define AM_REG_ADC_CFG_CLKSEL_M 0x03000000
#define AM_REG_ADC_CFG_CLKSEL(n) (((uint32_t)(n) << 24) & 0x03000000)
#define AM_REG_ADC_CFG_CLKSEL_OFF 0x00000000
#define AM_REG_ADC_CFG_CLKSEL_HFRC 0x01000000
#define AM_REG_ADC_CFG_CLKSEL_HFRC_DIV2 0x02000000
// This bit selects the ADC trigger polarity for external off chip triggers.
#define AM_REG_ADC_CFG_TRIGPOL_S 19
#define AM_REG_ADC_CFG_TRIGPOL_M 0x00080000
#define AM_REG_ADC_CFG_TRIGPOL(n) (((uint32_t)(n) << 19) & 0x00080000)
#define AM_REG_ADC_CFG_TRIGPOL_RISING_EDGE 0x00000000
#define AM_REG_ADC_CFG_TRIGPOL_FALLING_EDGE 0x00080000
// Select the ADC trigger source.
#define AM_REG_ADC_CFG_TRIGSEL_S 16
#define AM_REG_ADC_CFG_TRIGSEL_M 0x00070000
#define AM_REG_ADC_CFG_TRIGSEL(n) (((uint32_t)(n) << 16) & 0x00070000)
#define AM_REG_ADC_CFG_TRIGSEL_EXT0 0x00000000
#define AM_REG_ADC_CFG_TRIGSEL_EXT1 0x00010000
#define AM_REG_ADC_CFG_TRIGSEL_EXT2 0x00020000
#define AM_REG_ADC_CFG_TRIGSEL_EXT3 0x00030000
#define AM_REG_ADC_CFG_TRIGSEL_VCOMP 0x00040000
#define AM_REG_ADC_CFG_TRIGSEL_SWT 0x00070000
// Select the ADC reference voltage.
#define AM_REG_ADC_CFG_REFSEL_S 8
#define AM_REG_ADC_CFG_REFSEL_M 0x00000300
#define AM_REG_ADC_CFG_REFSEL(n) (((uint32_t)(n) << 8) & 0x00000300)
#define AM_REG_ADC_CFG_REFSEL_INT2P0 0x00000000
#define AM_REG_ADC_CFG_REFSEL_INT1P5 0x00000100
#define AM_REG_ADC_CFG_REFSEL_EXT2P0 0x00000200
#define AM_REG_ADC_CFG_REFSEL_EXT1P5 0x00000300
// Clock mode register
#define AM_REG_ADC_CFG_CKMODE_S 4
#define AM_REG_ADC_CFG_CKMODE_M 0x00000010
#define AM_REG_ADC_CFG_CKMODE(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_ADC_CFG_CKMODE_LPCKMODE 0x00000000
#define AM_REG_ADC_CFG_CKMODE_LLCKMODE 0x00000010
// Select power mode to enter between active scans.
#define AM_REG_ADC_CFG_LPMODE_S 3
#define AM_REG_ADC_CFG_LPMODE_M 0x00000008
#define AM_REG_ADC_CFG_LPMODE(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_ADC_CFG_LPMODE_MODE0 0x00000000
#define AM_REG_ADC_CFG_LPMODE_MODE1 0x00000008
// This bit enables Repeating Scan Mode.
#define AM_REG_ADC_CFG_RPTEN_S 2
#define AM_REG_ADC_CFG_RPTEN_M 0x00000004
#define AM_REG_ADC_CFG_RPTEN(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_ADC_CFG_RPTEN_SINGLE_SCAN 0x00000000
#define AM_REG_ADC_CFG_RPTEN_REPEATING_SCAN 0x00000004
// This bit enables the ADC module. While the ADC is enabled, the ADCCFG and
// SLOT Configuration regsiter settings must remain stable and unchanged. All
// configuration register settings, slot configuration settings and window
// comparison settings should be written prior to setting the ADCEN bit to '1'.
#define AM_REG_ADC_CFG_ADCEN_S 0
#define AM_REG_ADC_CFG_ADCEN_M 0x00000001
#define AM_REG_ADC_CFG_ADCEN(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_CFG_ADCEN_DIS 0x00000000
#define AM_REG_ADC_CFG_ADCEN_EN 0x00000001
//*****************************************************************************
//
// ADC_STAT - ADC Power Status
//
//*****************************************************************************
// Indicates the power-status of the ADC.
#define AM_REG_ADC_STAT_PWDSTAT_S 0
#define AM_REG_ADC_STAT_PWDSTAT_M 0x00000001
#define AM_REG_ADC_STAT_PWDSTAT(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_STAT_PWDSTAT_ON 0x00000000
#define AM_REG_ADC_STAT_PWDSTAT_POWERED_DOWN 0x00000001
//*****************************************************************************
//
// ADC_SWT - Software trigger
//
//*****************************************************************************
// Writing 0x37 to this register generates a software trigger.
#define AM_REG_ADC_SWT_SWT_S 0
#define AM_REG_ADC_SWT_SWT_M 0x000000FF
#define AM_REG_ADC_SWT_SWT(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_ADC_SWT_SWT_GEN_SW_TRIGGER 0x00000037
//*****************************************************************************
//
// ADC_SL0CFG - Slot 0 Configuration Register
//
//*****************************************************************************
// Select the number of measurements to average in the accumulate divide module
// for this slot.
#define AM_REG_ADC_SL0CFG_ADSEL0_S 24
#define AM_REG_ADC_SL0CFG_ADSEL0_M 0x07000000
#define AM_REG_ADC_SL0CFG_ADSEL0(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL0CFG_PRMODE0_S 16
#define AM_REG_ADC_SL0CFG_PRMODE0_M 0x00030000
#define AM_REG_ADC_SL0CFG_PRMODE0(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL0CFG_PRMODE0_P14B 0x00000000
#define AM_REG_ADC_SL0CFG_PRMODE0_P12B 0x00010000
#define AM_REG_ADC_SL0CFG_PRMODE0_P10B 0x00020000
#define AM_REG_ADC_SL0CFG_PRMODE0_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL0CFG_CHSEL0_S 8
#define AM_REG_ADC_SL0CFG_CHSEL0_M 0x00000F00
#define AM_REG_ADC_SL0CFG_CHSEL0(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL0CFG_CHSEL0_SE0 0x00000000
#define AM_REG_ADC_SL0CFG_CHSEL0_SE1 0x00000100
#define AM_REG_ADC_SL0CFG_CHSEL0_SE2 0x00000200
#define AM_REG_ADC_SL0CFG_CHSEL0_SE3 0x00000300
#define AM_REG_ADC_SL0CFG_CHSEL0_SE4 0x00000400
#define AM_REG_ADC_SL0CFG_CHSEL0_SE5 0x00000500
#define AM_REG_ADC_SL0CFG_CHSEL0_SE6 0x00000600
#define AM_REG_ADC_SL0CFG_CHSEL0_SE7 0x00000700
#define AM_REG_ADC_SL0CFG_CHSEL0_SE8 0x00000800
#define AM_REG_ADC_SL0CFG_CHSEL0_SE9 0x00000900
#define AM_REG_ADC_SL0CFG_CHSEL0_DF0 0x00000A00
#define AM_REG_ADC_SL0CFG_CHSEL0_DF1 0x00000B00
#define AM_REG_ADC_SL0CFG_CHSEL0_TEMP 0x00000C00
#define AM_REG_ADC_SL0CFG_CHSEL0_BATT 0x00000D00
#define AM_REG_ADC_SL0CFG_CHSEL0_VSS 0x00000E00
// This bit enables the window compare function for slot 0.
#define AM_REG_ADC_SL0CFG_WCEN0_S 1
#define AM_REG_ADC_SL0CFG_WCEN0_M 0x00000002
#define AM_REG_ADC_SL0CFG_WCEN0(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL0CFG_WCEN0_WCEN 0x00000002
// This bit enables slot 0 for ADC conversions.
#define AM_REG_ADC_SL0CFG_SLEN0_S 0
#define AM_REG_ADC_SL0CFG_SLEN0_M 0x00000001
#define AM_REG_ADC_SL0CFG_SLEN0(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL0CFG_SLEN0_SLEN 0x00000001
//*****************************************************************************
//
// ADC_SL1CFG - Slot 1 Configuration Register
//
//*****************************************************************************
// Select the number of measurements to average in the accumulate divide module
// for this slot.
#define AM_REG_ADC_SL1CFG_ADSEL1_S 24
#define AM_REG_ADC_SL1CFG_ADSEL1_M 0x07000000
#define AM_REG_ADC_SL1CFG_ADSEL1(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL1CFG_PRMODE1_S 16
#define AM_REG_ADC_SL1CFG_PRMODE1_M 0x00030000
#define AM_REG_ADC_SL1CFG_PRMODE1(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL1CFG_PRMODE1_P14B 0x00000000
#define AM_REG_ADC_SL1CFG_PRMODE1_P12B 0x00010000
#define AM_REG_ADC_SL1CFG_PRMODE1_P10B 0x00020000
#define AM_REG_ADC_SL1CFG_PRMODE1_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL1CFG_CHSEL1_S 8
#define AM_REG_ADC_SL1CFG_CHSEL1_M 0x00000F00
#define AM_REG_ADC_SL1CFG_CHSEL1(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL1CFG_CHSEL1_SE0 0x00000000
#define AM_REG_ADC_SL1CFG_CHSEL1_SE1 0x00000100
#define AM_REG_ADC_SL1CFG_CHSEL1_SE2 0x00000200
#define AM_REG_ADC_SL1CFG_CHSEL1_SE3 0x00000300
#define AM_REG_ADC_SL1CFG_CHSEL1_SE4 0x00000400
#define AM_REG_ADC_SL1CFG_CHSEL1_SE5 0x00000500
#define AM_REG_ADC_SL1CFG_CHSEL1_SE6 0x00000600
#define AM_REG_ADC_SL1CFG_CHSEL1_SE7 0x00000700
#define AM_REG_ADC_SL1CFG_CHSEL1_SE8 0x00000800
#define AM_REG_ADC_SL1CFG_CHSEL1_SE9 0x00000900
#define AM_REG_ADC_SL1CFG_CHSEL1_DF0 0x00000A00
#define AM_REG_ADC_SL1CFG_CHSEL1_DF1 0x00000B00
#define AM_REG_ADC_SL1CFG_CHSEL1_TEMP 0x00000C00
#define AM_REG_ADC_SL1CFG_CHSEL1_BATT 0x00000D00
#define AM_REG_ADC_SL1CFG_CHSEL1_VSS 0x00000E00
// This bit enables the window compare function for slot 1.
#define AM_REG_ADC_SL1CFG_WCEN1_S 1
#define AM_REG_ADC_SL1CFG_WCEN1_M 0x00000002
#define AM_REG_ADC_SL1CFG_WCEN1(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL1CFG_WCEN1_WCEN 0x00000002
// This bit enables slot 1 for ADC conversions.
#define AM_REG_ADC_SL1CFG_SLEN1_S 0
#define AM_REG_ADC_SL1CFG_SLEN1_M 0x00000001
#define AM_REG_ADC_SL1CFG_SLEN1(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL1CFG_SLEN1_SLEN 0x00000001
//*****************************************************************************
//
// ADC_SL2CFG - Slot 2 Configuration Register
//
//*****************************************************************************
// Select the number of measurements to average in the accumulate divide module
// for this slot.
#define AM_REG_ADC_SL2CFG_ADSEL2_S 24
#define AM_REG_ADC_SL2CFG_ADSEL2_M 0x07000000
#define AM_REG_ADC_SL2CFG_ADSEL2(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL2CFG_PRMODE2_S 16
#define AM_REG_ADC_SL2CFG_PRMODE2_M 0x00030000
#define AM_REG_ADC_SL2CFG_PRMODE2(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL2CFG_PRMODE2_P14B 0x00000000
#define AM_REG_ADC_SL2CFG_PRMODE2_P12B 0x00010000
#define AM_REG_ADC_SL2CFG_PRMODE2_P10B 0x00020000
#define AM_REG_ADC_SL2CFG_PRMODE2_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL2CFG_CHSEL2_S 8
#define AM_REG_ADC_SL2CFG_CHSEL2_M 0x00000F00
#define AM_REG_ADC_SL2CFG_CHSEL2(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL2CFG_CHSEL2_SE0 0x00000000
#define AM_REG_ADC_SL2CFG_CHSEL2_SE1 0x00000100
#define AM_REG_ADC_SL2CFG_CHSEL2_SE2 0x00000200
#define AM_REG_ADC_SL2CFG_CHSEL2_SE3 0x00000300
#define AM_REG_ADC_SL2CFG_CHSEL2_SE4 0x00000400
#define AM_REG_ADC_SL2CFG_CHSEL2_SE5 0x00000500
#define AM_REG_ADC_SL2CFG_CHSEL2_SE6 0x00000600
#define AM_REG_ADC_SL2CFG_CHSEL2_SE7 0x00000700
#define AM_REG_ADC_SL2CFG_CHSEL2_SE8 0x00000800
#define AM_REG_ADC_SL2CFG_CHSEL2_SE9 0x00000900
#define AM_REG_ADC_SL2CFG_CHSEL2_DF0 0x00000A00
#define AM_REG_ADC_SL2CFG_CHSEL2_DF1 0x00000B00
#define AM_REG_ADC_SL2CFG_CHSEL2_TEMP 0x00000C00
#define AM_REG_ADC_SL2CFG_CHSEL2_BATT 0x00000D00
#define AM_REG_ADC_SL2CFG_CHSEL2_VSS 0x00000E00
// This bit enables the window compare function for slot 2.
#define AM_REG_ADC_SL2CFG_WCEN2_S 1
#define AM_REG_ADC_SL2CFG_WCEN2_M 0x00000002
#define AM_REG_ADC_SL2CFG_WCEN2(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL2CFG_WCEN2_WCEN 0x00000002
// This bit enables slot 2 for ADC conversions.
#define AM_REG_ADC_SL2CFG_SLEN2_S 0
#define AM_REG_ADC_SL2CFG_SLEN2_M 0x00000001
#define AM_REG_ADC_SL2CFG_SLEN2(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL2CFG_SLEN2_SLEN 0x00000001
//*****************************************************************************
//
// ADC_SL3CFG - Slot 3 Configuration Register
//
//*****************************************************************************
// Select the number of measurements to average in the accumulate divide module
// for this slot.
#define AM_REG_ADC_SL3CFG_ADSEL3_S 24
#define AM_REG_ADC_SL3CFG_ADSEL3_M 0x07000000
#define AM_REG_ADC_SL3CFG_ADSEL3(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL3CFG_PRMODE3_S 16
#define AM_REG_ADC_SL3CFG_PRMODE3_M 0x00030000
#define AM_REG_ADC_SL3CFG_PRMODE3(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL3CFG_PRMODE3_P14B 0x00000000
#define AM_REG_ADC_SL3CFG_PRMODE3_P12B 0x00010000
#define AM_REG_ADC_SL3CFG_PRMODE3_P10B 0x00020000
#define AM_REG_ADC_SL3CFG_PRMODE3_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL3CFG_CHSEL3_S 8
#define AM_REG_ADC_SL3CFG_CHSEL3_M 0x00000F00
#define AM_REG_ADC_SL3CFG_CHSEL3(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL3CFG_CHSEL3_SE0 0x00000000
#define AM_REG_ADC_SL3CFG_CHSEL3_SE1 0x00000100
#define AM_REG_ADC_SL3CFG_CHSEL3_SE2 0x00000200
#define AM_REG_ADC_SL3CFG_CHSEL3_SE3 0x00000300
#define AM_REG_ADC_SL3CFG_CHSEL3_SE4 0x00000400
#define AM_REG_ADC_SL3CFG_CHSEL3_SE5 0x00000500
#define AM_REG_ADC_SL3CFG_CHSEL3_SE6 0x00000600
#define AM_REG_ADC_SL3CFG_CHSEL3_SE7 0x00000700
#define AM_REG_ADC_SL3CFG_CHSEL3_SE8 0x00000800
#define AM_REG_ADC_SL3CFG_CHSEL3_SE9 0x00000900
#define AM_REG_ADC_SL3CFG_CHSEL3_DF0 0x00000A00
#define AM_REG_ADC_SL3CFG_CHSEL3_DF1 0x00000B00
#define AM_REG_ADC_SL3CFG_CHSEL3_TEMP 0x00000C00
#define AM_REG_ADC_SL3CFG_CHSEL3_BATT 0x00000D00
#define AM_REG_ADC_SL3CFG_CHSEL3_VSS 0x00000E00
// This bit enables the window compare function for slot 3.
#define AM_REG_ADC_SL3CFG_WCEN3_S 1
#define AM_REG_ADC_SL3CFG_WCEN3_M 0x00000002
#define AM_REG_ADC_SL3CFG_WCEN3(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL3CFG_WCEN3_WCEN 0x00000002
// This bit enables slot 3 for ADC conversions.
#define AM_REG_ADC_SL3CFG_SLEN3_S 0
#define AM_REG_ADC_SL3CFG_SLEN3_M 0x00000001
#define AM_REG_ADC_SL3CFG_SLEN3(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL3CFG_SLEN3_SLEN 0x00000001
//*****************************************************************************
//
// ADC_SL4CFG - Slot 4 Configuration Register
//
//*****************************************************************************
// Select the number of measurements to average in the accumulate divide module
// for this slot.
#define AM_REG_ADC_SL4CFG_ADSEL4_S 24
#define AM_REG_ADC_SL4CFG_ADSEL4_M 0x07000000
#define AM_REG_ADC_SL4CFG_ADSEL4(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL4CFG_PRMODE4_S 16
#define AM_REG_ADC_SL4CFG_PRMODE4_M 0x00030000
#define AM_REG_ADC_SL4CFG_PRMODE4(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL4CFG_PRMODE4_P14B 0x00000000
#define AM_REG_ADC_SL4CFG_PRMODE4_P12B 0x00010000
#define AM_REG_ADC_SL4CFG_PRMODE4_P10B 0x00020000
#define AM_REG_ADC_SL4CFG_PRMODE4_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL4CFG_CHSEL4_S 8
#define AM_REG_ADC_SL4CFG_CHSEL4_M 0x00000F00
#define AM_REG_ADC_SL4CFG_CHSEL4(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL4CFG_CHSEL4_SE0 0x00000000
#define AM_REG_ADC_SL4CFG_CHSEL4_SE1 0x00000100
#define AM_REG_ADC_SL4CFG_CHSEL4_SE2 0x00000200
#define AM_REG_ADC_SL4CFG_CHSEL4_SE3 0x00000300
#define AM_REG_ADC_SL4CFG_CHSEL4_SE4 0x00000400
#define AM_REG_ADC_SL4CFG_CHSEL4_SE5 0x00000500
#define AM_REG_ADC_SL4CFG_CHSEL4_SE6 0x00000600
#define AM_REG_ADC_SL4CFG_CHSEL4_SE7 0x00000700
#define AM_REG_ADC_SL4CFG_CHSEL4_SE8 0x00000800
#define AM_REG_ADC_SL4CFG_CHSEL4_SE9 0x00000900
#define AM_REG_ADC_SL4CFG_CHSEL4_DF0 0x00000A00
#define AM_REG_ADC_SL4CFG_CHSEL4_DF1 0x00000B00
#define AM_REG_ADC_SL4CFG_CHSEL4_TEMP 0x00000C00
#define AM_REG_ADC_SL4CFG_CHSEL4_BATT 0x00000D00
#define AM_REG_ADC_SL4CFG_CHSEL4_VSS 0x00000E00
// This bit enables the window compare function for slot 4.
#define AM_REG_ADC_SL4CFG_WCEN4_S 1
#define AM_REG_ADC_SL4CFG_WCEN4_M 0x00000002
#define AM_REG_ADC_SL4CFG_WCEN4(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL4CFG_WCEN4_WCEN 0x00000002
// This bit enables slot 4 for ADC conversions.
#define AM_REG_ADC_SL4CFG_SLEN4_S 0
#define AM_REG_ADC_SL4CFG_SLEN4_M 0x00000001
#define AM_REG_ADC_SL4CFG_SLEN4(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL4CFG_SLEN4_SLEN 0x00000001
//*****************************************************************************
//
// ADC_SL5CFG - Slot 5 Configuration Register
//
//*****************************************************************************
// Select number of measurements to average in the accumulate divide module for
// this slot.
#define AM_REG_ADC_SL5CFG_ADSEL5_S 24
#define AM_REG_ADC_SL5CFG_ADSEL5_M 0x07000000
#define AM_REG_ADC_SL5CFG_ADSEL5(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL5CFG_PRMODE5_S 16
#define AM_REG_ADC_SL5CFG_PRMODE5_M 0x00030000
#define AM_REG_ADC_SL5CFG_PRMODE5(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL5CFG_PRMODE5_P14B 0x00000000
#define AM_REG_ADC_SL5CFG_PRMODE5_P12B 0x00010000
#define AM_REG_ADC_SL5CFG_PRMODE5_P10B 0x00020000
#define AM_REG_ADC_SL5CFG_PRMODE5_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL5CFG_CHSEL5_S 8
#define AM_REG_ADC_SL5CFG_CHSEL5_M 0x00000F00
#define AM_REG_ADC_SL5CFG_CHSEL5(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL5CFG_CHSEL5_SE0 0x00000000
#define AM_REG_ADC_SL5CFG_CHSEL5_SE1 0x00000100
#define AM_REG_ADC_SL5CFG_CHSEL5_SE2 0x00000200
#define AM_REG_ADC_SL5CFG_CHSEL5_SE3 0x00000300
#define AM_REG_ADC_SL5CFG_CHSEL5_SE4 0x00000400
#define AM_REG_ADC_SL5CFG_CHSEL5_SE5 0x00000500
#define AM_REG_ADC_SL5CFG_CHSEL5_SE6 0x00000600
#define AM_REG_ADC_SL5CFG_CHSEL5_SE7 0x00000700
#define AM_REG_ADC_SL5CFG_CHSEL5_SE8 0x00000800
#define AM_REG_ADC_SL5CFG_CHSEL5_SE9 0x00000900
#define AM_REG_ADC_SL5CFG_CHSEL5_DF0 0x00000A00
#define AM_REG_ADC_SL5CFG_CHSEL5_DF1 0x00000B00
#define AM_REG_ADC_SL5CFG_CHSEL5_TEMP 0x00000C00
#define AM_REG_ADC_SL5CFG_CHSEL5_BATT 0x00000D00
#define AM_REG_ADC_SL5CFG_CHSEL5_VSS 0x00000E00
// This bit enables the window compare function for slot 5.
#define AM_REG_ADC_SL5CFG_WCEN5_S 1
#define AM_REG_ADC_SL5CFG_WCEN5_M 0x00000002
#define AM_REG_ADC_SL5CFG_WCEN5(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL5CFG_WCEN5_WCEN 0x00000002
// This bit enables slot 5 for ADC conversions.
#define AM_REG_ADC_SL5CFG_SLEN5_S 0
#define AM_REG_ADC_SL5CFG_SLEN5_M 0x00000001
#define AM_REG_ADC_SL5CFG_SLEN5(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL5CFG_SLEN5_SLEN 0x00000001
//*****************************************************************************
//
// ADC_SL6CFG - Slot 6 Configuration Register
//
//*****************************************************************************
// Select the number of measurements to average in the accumulate divide module
// for this slot.
#define AM_REG_ADC_SL6CFG_ADSEL6_S 24
#define AM_REG_ADC_SL6CFG_ADSEL6_M 0x07000000
#define AM_REG_ADC_SL6CFG_ADSEL6(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL6CFG_PRMODE6_S 16
#define AM_REG_ADC_SL6CFG_PRMODE6_M 0x00030000
#define AM_REG_ADC_SL6CFG_PRMODE6(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL6CFG_PRMODE6_P14B 0x00000000
#define AM_REG_ADC_SL6CFG_PRMODE6_P12B 0x00010000
#define AM_REG_ADC_SL6CFG_PRMODE6_P10B 0x00020000
#define AM_REG_ADC_SL6CFG_PRMODE6_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL6CFG_CHSEL6_S 8
#define AM_REG_ADC_SL6CFG_CHSEL6_M 0x00000F00
#define AM_REG_ADC_SL6CFG_CHSEL6(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL6CFG_CHSEL6_SE0 0x00000000
#define AM_REG_ADC_SL6CFG_CHSEL6_SE1 0x00000100
#define AM_REG_ADC_SL6CFG_CHSEL6_SE2 0x00000200
#define AM_REG_ADC_SL6CFG_CHSEL6_SE3 0x00000300
#define AM_REG_ADC_SL6CFG_CHSEL6_SE4 0x00000400
#define AM_REG_ADC_SL6CFG_CHSEL6_SE5 0x00000500
#define AM_REG_ADC_SL6CFG_CHSEL6_SE6 0x00000600
#define AM_REG_ADC_SL6CFG_CHSEL6_SE7 0x00000700
#define AM_REG_ADC_SL6CFG_CHSEL6_SE8 0x00000800
#define AM_REG_ADC_SL6CFG_CHSEL6_SE9 0x00000900
#define AM_REG_ADC_SL6CFG_CHSEL6_DF0 0x00000A00
#define AM_REG_ADC_SL6CFG_CHSEL6_DF1 0x00000B00
#define AM_REG_ADC_SL6CFG_CHSEL6_TEMP 0x00000C00
#define AM_REG_ADC_SL6CFG_CHSEL6_BATT 0x00000D00
#define AM_REG_ADC_SL6CFG_CHSEL6_VSS 0x00000E00
// This bit enables the window compare function for slot 6.
#define AM_REG_ADC_SL6CFG_WCEN6_S 1
#define AM_REG_ADC_SL6CFG_WCEN6_M 0x00000002
#define AM_REG_ADC_SL6CFG_WCEN6(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL6CFG_WCEN6_WCEN 0x00000002
// This bit enables slot 6 for ADC conversions.
#define AM_REG_ADC_SL6CFG_SLEN6_S 0
#define AM_REG_ADC_SL6CFG_SLEN6_M 0x00000001
#define AM_REG_ADC_SL6CFG_SLEN6(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL6CFG_SLEN6_SLEN 0x00000001
//*****************************************************************************
//
// ADC_SL7CFG - Slot 7 Configuration Register
//
//*****************************************************************************
// Select the number of measurements to average in the accumulate divide module
// for this slot.
#define AM_REG_ADC_SL7CFG_ADSEL7_S 24
#define AM_REG_ADC_SL7CFG_ADSEL7_M 0x07000000
#define AM_REG_ADC_SL7CFG_ADSEL7(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_1_MSRMT 0x00000000
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS 0x01000000
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS 0x02000000
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_8_MSRMT 0x03000000
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS 0x04000000
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS 0x05000000
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS 0x06000000
#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS 0x07000000
// Set the Precision Mode For Slot.
#define AM_REG_ADC_SL7CFG_PRMODE7_S 16
#define AM_REG_ADC_SL7CFG_PRMODE7_M 0x00030000
#define AM_REG_ADC_SL7CFG_PRMODE7(n) (((uint32_t)(n) << 16) & 0x00030000)
#define AM_REG_ADC_SL7CFG_PRMODE7_P14B 0x00000000
#define AM_REG_ADC_SL7CFG_PRMODE7_P12B 0x00010000
#define AM_REG_ADC_SL7CFG_PRMODE7_P10B 0x00020000
#define AM_REG_ADC_SL7CFG_PRMODE7_P8B 0x00030000
// Select one of the 14 channel inputs for this slot.
#define AM_REG_ADC_SL7CFG_CHSEL7_S 8
#define AM_REG_ADC_SL7CFG_CHSEL7_M 0x00000F00
#define AM_REG_ADC_SL7CFG_CHSEL7(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_ADC_SL7CFG_CHSEL7_SE0 0x00000000
#define AM_REG_ADC_SL7CFG_CHSEL7_SE1 0x00000100
#define AM_REG_ADC_SL7CFG_CHSEL7_SE2 0x00000200
#define AM_REG_ADC_SL7CFG_CHSEL7_SE3 0x00000300
#define AM_REG_ADC_SL7CFG_CHSEL7_SE4 0x00000400
#define AM_REG_ADC_SL7CFG_CHSEL7_SE5 0x00000500
#define AM_REG_ADC_SL7CFG_CHSEL7_SE6 0x00000600
#define AM_REG_ADC_SL7CFG_CHSEL7_SE7 0x00000700
#define AM_REG_ADC_SL7CFG_CHSEL7_SE8 0x00000800
#define AM_REG_ADC_SL7CFG_CHSEL7_SE9 0x00000900
#define AM_REG_ADC_SL7CFG_CHSEL7_DF0 0x00000A00
#define AM_REG_ADC_SL7CFG_CHSEL7_DF1 0x00000B00
#define AM_REG_ADC_SL7CFG_CHSEL7_TEMP 0x00000C00
#define AM_REG_ADC_SL7CFG_CHSEL7_BATT 0x00000D00
#define AM_REG_ADC_SL7CFG_CHSEL7_VSS 0x00000E00
// This bit enables the window compare function for slot 7.
#define AM_REG_ADC_SL7CFG_WCEN7_S 1
#define AM_REG_ADC_SL7CFG_WCEN7_M 0x00000002
#define AM_REG_ADC_SL7CFG_WCEN7(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_ADC_SL7CFG_WCEN7_WCEN 0x00000002
// This bit enables slot 7 for ADC conversions.
#define AM_REG_ADC_SL7CFG_SLEN7_S 0
#define AM_REG_ADC_SL7CFG_SLEN7_M 0x00000001
#define AM_REG_ADC_SL7CFG_SLEN7(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_ADC_SL7CFG_SLEN7_SLEN 0x00000001
//*****************************************************************************
//
// ADC_WULIM - Window Comparator Upper Limits Register
//
//*****************************************************************************
// Sets the upper limit for the wondow comparator.
#define AM_REG_ADC_WULIM_ULIM_S 0
#define AM_REG_ADC_WULIM_ULIM_M 0x000FFFFF
#define AM_REG_ADC_WULIM_ULIM(n) (((uint32_t)(n) << 0) & 0x000FFFFF)
//*****************************************************************************
//
// ADC_WLLIM - Window Comparator Lower Limits Register
//
//*****************************************************************************
// Sets the lower limit for the wondow comparator.
#define AM_REG_ADC_WLLIM_LLIM_S 0
#define AM_REG_ADC_WLLIM_LLIM_M 0x000FFFFF
#define AM_REG_ADC_WLLIM_LLIM(n) (((uint32_t)(n) << 0) & 0x000FFFFF)
//*****************************************************************************
//
// ADC_FIFO - FIFO Data and Valid Count Register
//
//*****************************************************************************
// RESERVED.
#define AM_REG_ADC_FIFO_RSVD_S 31
#define AM_REG_ADC_FIFO_RSVD_M 0x80000000
#define AM_REG_ADC_FIFO_RSVD(n) (((uint32_t)(n) << 31) & 0x80000000)
// Slot number associated with this FIFO data.
#define AM_REG_ADC_FIFO_SLOTNUM_S 28
#define AM_REG_ADC_FIFO_SLOTNUM_M 0x70000000
#define AM_REG_ADC_FIFO_SLOTNUM(n) (((uint32_t)(n) << 28) & 0x70000000)
// Number of valid entries in the ADC FIFO.
#define AM_REG_ADC_FIFO_COUNT_S 20
#define AM_REG_ADC_FIFO_COUNT_M 0x0FF00000
#define AM_REG_ADC_FIFO_COUNT(n) (((uint32_t)(n) << 20) & 0x0FF00000)
// Oldest data in the FIFO.
#define AM_REG_ADC_FIFO_DATA_S 0
#define AM_REG_ADC_FIFO_DATA_M 0x000FFFFF
#define AM_REG_ADC_FIFO_DATA(n) (((uint32_t)(n) << 0) & 0x000FFFFF)
#endif // AM_REG_ADC_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_base_addresses.h
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//*****************************************************************************
//
//! @file am_reg_base_addresses.h
//!
//! @brief Register defines for all module base addresses
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_BASE_ADDRESSES_H
#define AM_REG_BASE_ADDRESSES_H
#include "stdint.h"
// ARM standard register space (needed for macros)
#define REG_ITM_BASEADDR (0x00000000UL)
#define REG_JEDEC_BASEADDR (0x00000000UL)
#define REG_NVIC_BASEADDR (0x00000000UL)
#define REG_SYSCTRL_BASEADDR (0x00000000UL)
#define REG_SYSTICK_BASEADDR (0x00000000UL)
#define REG_TPIU_BASEADDR (0x00000000UL)
// Peripheral register space
#define REG_ADC_BASEADDR (0x50010000UL)
#define REG_CACHECTRL_BASEADDR (0x40018000UL)
#define REG_CLKGEN_BASEADDR (0x40004000UL)
#define REG_CTIMER_BASEADDR (0x40008000UL)
#define REG_GPIO_BASEADDR (0x40010000UL)
#define REG_IOMSTR_BASEADDR (0x50004000UL)
#define REG_IOSLAVE_BASEADDR (0x50000000UL)
#define REG_MCUCTRL_BASEADDR (0x40020000UL)
#define REG_PDM_BASEADDR (0x50011000UL)
#define REG_PWRCTRL_BASEADDR (0x40021000UL)
#define REG_RSTGEN_BASEADDR (0x40000000UL)
#define REG_RTC_BASEADDR (0x40004040UL)
#define REG_UART_BASEADDR (0x4001C000UL)
#define REG_VCOMP_BASEADDR (0x4000C000UL)
#define REG_WDT_BASEADDR (0x40024000UL)
// SRAM address space
#define SRAM_BASEADDR (0x10000000UL)
#endif // AM_REG_BASE_ADDRESSES_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_cachectrl.h
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//*****************************************************************************
//
// am_reg_cachectrl.h
//! @file
//!
//! @brief Register macros for the CACHECTRL module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_CACHECTRL_H
#define AM_REG_CACHECTRL_H
//*****************************************************************************
//
// CACHECTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_CACHECTRL_NUM_MODULES 1
#define AM_REG_CACHECTRLn(n) \
(REG_CACHECTRL_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_CACHECTRL_CACHECFG_O 0x00000000
#define AM_REG_CACHECTRL_FLASHCFG_O 0x00000004
#define AM_REG_CACHECTRL_CTRL_O 0x00000008
#define AM_REG_CACHECTRL_NCR0START_O 0x00000010
#define AM_REG_CACHECTRL_NCR0END_O 0x00000014
#define AM_REG_CACHECTRL_NCR1START_O 0x00000018
#define AM_REG_CACHECTRL_NCR1END_O 0x0000001C
#define AM_REG_CACHECTRL_CACHEMODE_O 0x00000030
#define AM_REG_CACHECTRL_DMON0_O 0x00000040
#define AM_REG_CACHECTRL_DMON1_O 0x00000044
#define AM_REG_CACHECTRL_DMON2_O 0x00000048
#define AM_REG_CACHECTRL_DMON3_O 0x0000004C
#define AM_REG_CACHECTRL_IMON0_O 0x00000050
#define AM_REG_CACHECTRL_IMON1_O 0x00000054
#define AM_REG_CACHECTRL_IMON2_O 0x00000058
#define AM_REG_CACHECTRL_IMON3_O 0x0000005C
//*****************************************************************************
//
// CACHECTRL_CACHECFG - Flash Cache Control Register
//
//*****************************************************************************
// Enable Cache Monitoring Stats. Only enable this for debug/performance
// analysis since it will consume additional power. See IMON/DMON registers for
// data.
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_S 24
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M 0x01000000
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(n) (((uint32_t)(n) << 24) & 0x01000000)
// Enable clock gating of entire cache data array subsystem. This should be
// enabled for normal operation.
#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_S 20
#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M 0x00100000
#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(n) (((uint32_t)(n) << 20) & 0x00100000)
// Unused. Should be left at default value.
#define AM_REG_CACHECTRL_CACHECFG_SMDLY_S 16
#define AM_REG_CACHECTRL_CACHECFG_SMDLY_M 0x000F0000
#define AM_REG_CACHECTRL_CACHECFG_SMDLY(n) (((uint32_t)(n) << 16) & 0x000F0000)
// Unused. Should be left at default value.
#define AM_REG_CACHECTRL_CACHECFG_DLY_S 12
#define AM_REG_CACHECTRL_CACHECFG_DLY_M 0x0000F000
#define AM_REG_CACHECTRL_CACHECFG_DLY(n) (((uint32_t)(n) << 12) & 0x0000F000)
// Enable LS (light sleep) of cache RAMs. This should not be enabled for normal
// operation. When this bit is set, the cache's RAMS will be put into light
// sleep mode while inactive. NOTE: if the cache is actively used, this may
// have an adverse affect on power since entering/exiting LS mode may consume
// more power than would be saved.
#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_S 11
#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M 0x00000800
#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS(n) (((uint32_t)(n) << 11) & 0x00000800)
// Enable clock gating of individual cache RAMs. This bit should be enabled for
// normal operation for lowest power consumption.
#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_S 10
#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M 0x00000400
#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE(n) (((uint32_t)(n) << 10) & 0x00000400)
// Enable Flash Data Caching. When set to 1, all instruction accesses to flash
// will be cached.
#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_S 9
#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M 0x00000200
#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(n) (((uint32_t)(n) << 9) & 0x00000200)
// Enable Flash Instruction Caching. When set to 1, all instruction accesses to
// flash will be cached.
#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_S 8
#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M 0x00000100
#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(n) (((uint32_t)(n) << 8) & 0x00000100)
// Bitfield should always be programmed to 0.
#define AM_REG_CACHECTRL_CACHECFG_SERIAL_S 7
#define AM_REG_CACHECTRL_CACHECFG_SERIAL_M 0x00000080
#define AM_REG_CACHECTRL_CACHECFG_SERIAL(n) (((uint32_t)(n) << 7) & 0x00000080)
// Sets the cache configuration. Only a single configuration of 0x5 is valid.
#define AM_REG_CACHECTRL_CACHECFG_CONFIG_S 4
#define AM_REG_CACHECTRL_CACHECFG_CONFIG_M 0x00000070
#define AM_REG_CACHECTRL_CACHECFG_CONFIG(n) (((uint32_t)(n) << 4) & 0x00000070)
#define AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E 0x00000050
// Enable Non-cacheable region 1. See the NCR1 registers to set the region
// boundaries and size.
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_S 3
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M 0x00000008
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1(n) (((uint32_t)(n) << 3) & 0x00000008)
// Enable Non-cacheable region 0. See the NCR0 registers to set the region
// boundaries and size.
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_S 2
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M 0x00000004
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0(n) (((uint32_t)(n) << 2) & 0x00000004)
// Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU
// (least recently used). LRR minimizes writes to the TAG SRAM and is
// recommended.
#define AM_REG_CACHECTRL_CACHECFG_LRU_S 1
#define AM_REG_CACHECTRL_CACHECFG_LRU_M 0x00000002
#define AM_REG_CACHECTRL_CACHECFG_LRU(n) (((uint32_t)(n) << 1) & 0x00000002)
// Enables the main flash cache controller logic and enables power to the cache
// RAMs. Instruction and Data caching need to be enabled independently using
// the ICACHE_ENABLE and DCACHE_ENABLE bits.
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_S 0
#define AM_REG_CACHECTRL_CACHECFG_ENABLE_M 0x00000001
#define AM_REG_CACHECTRL_CACHECFG_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// CACHECTRL_FLASHCFG - Flash Control Register
//
//*****************************************************************************
// Sets read waitstates for flash accesses (in clock cycles). This should be
// left at the default value for normal flash operation.
#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_S 0
#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_M 0x00000007
#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(n) (((uint32_t)(n) << 0) & 0x00000007)
//*****************************************************************************
//
// CACHECTRL_CTRL - Cache Control
//
//*****************************************************************************
// Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will
// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash
// access occurs. Wake from SLM requires ~5us, so this should only be set if
// the flash will not be accessed for reasonably long time.
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE_S 10
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE_M 0x00000400
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE(n) (((uint32_t)(n) << 10) & 0x00000400)
// Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode.
// Performing a flash read will also wake the array.
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE_S 9
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE_M 0x00000200
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE(n) (((uint32_t)(n) << 9) & 0x00000200)
// Flash Sleep Mode Status. When 1, flash instance 1 is asleep.
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS_S 8
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS_M 0x00000100
#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS(n) (((uint32_t)(n) << 8) & 0x00000100)
// Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will
// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash
// access occurs. Wake from SLM requires ~5us, so this should only be set if
// the flash will not be accessed for reasonably long time.
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE_S 6
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE_M 0x00000040
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE(n) (((uint32_t)(n) << 6) & 0x00000040)
// Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode.
// Performing a flash read will also wake the array.
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE_S 5
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE_M 0x00000020
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE(n) (((uint32_t)(n) << 5) & 0x00000020)
// Flash Sleep Mode Status. When 1, flash instance 0 is asleep.
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS_S 4
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS_M 0x00000010
#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS(n) (((uint32_t)(n) << 4) & 0x00000010)
// Cache Ready Status. A value of 1 indicates the cache is enabled and not
// processing an invalidate operation.
#define AM_REG_CACHECTRL_CTRL_CACHE_READY_S 2
#define AM_REG_CACHECTRL_CTRL_CACHE_READY_M 0x00000004
#define AM_REG_CACHECTRL_CTRL_CACHE_READY(n) (((uint32_t)(n) << 2) & 0x00000004)
// Writing a 1 to this bitfield will reset the cache monitor statistics
// (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling
// the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values
// until the stats are reset by writing this bitfield.
#define AM_REG_CACHECTRL_CTRL_RESET_STAT_S 1
#define AM_REG_CACHECTRL_CTRL_RESET_STAT_M 0x00000002
#define AM_REG_CACHECTRL_CTRL_RESET_STAT(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_CACHECTRL_CTRL_RESET_STAT_CLEAR 0x00000002
// Writing a 1 to this bitfield invalidates the flash cache contents.
#define AM_REG_CACHECTRL_CTRL_INVALIDATE_S 0
#define AM_REG_CACHECTRL_CTRL_INVALIDATE_M 0x00000001
#define AM_REG_CACHECTRL_CTRL_INVALIDATE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_CACHECTRL_CTRL_INVALIDATE_GO 0x00000001
//*****************************************************************************
//
// CACHECTRL_NCR0START - Flash Cache Noncachable Region 0 Start Address.
//
//*****************************************************************************
// Start address for non-cacheable region 0. The physical address of the start
// of this region should be programmed to this register and must be aligned to a
// 16-byte boundary (thus the lower 4 address bits are unused).
#define AM_REG_CACHECTRL_NCR0START_ADDR_S 4
#define AM_REG_CACHECTRL_NCR0START_ADDR_M 0x000FFFF0
#define AM_REG_CACHECTRL_NCR0START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
//*****************************************************************************
//
// CACHECTRL_NCR0END - Flash Cache Noncachable Region 0 End
//
//*****************************************************************************
// End address for non-cacheable region 0. The physical address of the end of
// this region should be programmed to this register and must be aligned to a
// 16-byte boundary (thus the lower 4 address bits are unused).
#define AM_REG_CACHECTRL_NCR0END_ADDR_S 4
#define AM_REG_CACHECTRL_NCR0END_ADDR_M 0x000FFFF0
#define AM_REG_CACHECTRL_NCR0END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
//*****************************************************************************
//
// CACHECTRL_NCR1START - Flash Cache Noncachable Region 1 Start
//
//*****************************************************************************
// Start address for non-cacheable region 1. The physical address of the start
// of this region should be programmed to this register and must be aligned to a
// 16-byte boundary (thus the lower 4 address bits are unused).
#define AM_REG_CACHECTRL_NCR1START_ADDR_S 4
#define AM_REG_CACHECTRL_NCR1START_ADDR_M 0x000FFFF0
#define AM_REG_CACHECTRL_NCR1START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
//*****************************************************************************
//
// CACHECTRL_NCR1END - Flash Cache Noncachable Region 1 End
//
//*****************************************************************************
// End address for non-cacheable region 1. The physical address of the end of
// this region should be programmed to this register and must be aligned to a
// 16-byte boundary (thus the lower 4 address bits are unused).
#define AM_REG_CACHECTRL_NCR1END_ADDR_S 4
#define AM_REG_CACHECTRL_NCR1END_ADDR_M 0x000FFFF0
#define AM_REG_CACHECTRL_NCR1END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
//*****************************************************************************
//
// CACHECTRL_CACHEMODE - Flash Cache Mode Register. Used to trim
// performance/power.
//
//*****************************************************************************
// Disallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value
// should be left at zero for optimal performance.
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_S 5
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_M 0x00000020
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6(n) (((uint32_t)(n) << 5) & 0x00000020)
// Disallow Data RAM reads (from line hits) during lookup read ops. Value
// should be left at zero for optimal performance.
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_S 4
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_M 0x00000010
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5(n) (((uint32_t)(n) << 4) & 0x00000010)
// Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should
// be left at zero for optimal performance.
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_S 3
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_M 0x00000008
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4(n) (((uint32_t)(n) << 3) & 0x00000008)
// Disallow cache data RAM writes on data RAM read cycles. Value should be left
// at zero for optimal performance.
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_S 2
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_M 0x00000004
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3(n) (((uint32_t)(n) << 2) & 0x00000004)
// Disallow cache data RAM writes on tag RAM read cycles. Value should be left
// at zero for optimal performance.
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_S 1
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_M 0x00000002
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2(n) (((uint32_t)(n) << 1) & 0x00000002)
// Disallow cache data RAM writes on tag RAM fill cycles. Value should be left
// at zero for optimal performance.
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_S 0
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_M 0x00000001
#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// CACHECTRL_DMON0 - Data Cache Total Accesses
//
//*****************************************************************************
// Total accesses to data cache
#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_S 0
#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// CACHECTRL_DMON1 - Data Cache Tag Lookups
//
//*****************************************************************************
// Total tag lookups from data cache
#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_S 0
#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// CACHECTRL_DMON2 - Data Cache Hits
//
//*****************************************************************************
// Cache hits from lookup operations
#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_S 0
#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// CACHECTRL_DMON3 - Data Cache Line Hits
//
//*****************************************************************************
// Cache hits from line cache
#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_S 0
#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// CACHECTRL_IMON0 - Instruction Cache Total Accesses
//
//*****************************************************************************
// Total accesses to Instruction cache
#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_S 0
#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// CACHECTRL_IMON1 - Instruction Cache Tag Lookups
//
//*****************************************************************************
// Total tag lookups from Instruction cache
#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_S 0
#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// CACHECTRL_IMON2 - Instruction Cache Hits
//
//*****************************************************************************
// Cache hits from lookup operations
#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_S 0
#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// CACHECTRL_IMON3 - Instruction Cache Line Hits
//
//*****************************************************************************
// Cache hits from line cache
#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_S 0
#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_M 0xFFFFFFFF
#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#endif // AM_REG_CACHECTRL_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_clkgen.h
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//*****************************************************************************
//
// am_reg_clkgen.h
//! @file
//!
//! @brief Register macros for the CLKGEN module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_CLKGEN_H
#define AM_REG_CLKGEN_H
//*****************************************************************************
//
// CLKGEN
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_CLKGEN_NUM_MODULES 1
#define AM_REG_CLKGENn(n) \
(REG_CLKGEN_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_CLKGEN_CALXT_O 0x00000000
#define AM_REG_CLKGEN_CALRC_O 0x00000004
#define AM_REG_CLKGEN_ACALCTR_O 0x00000008
#define AM_REG_CLKGEN_OCTRL_O 0x0000000C
#define AM_REG_CLKGEN_CLKOUT_O 0x00000010
#define AM_REG_CLKGEN_CCTRL_O 0x00000018
#define AM_REG_CLKGEN_STATUS_O 0x0000001C
#define AM_REG_CLKGEN_HFADJ_O 0x00000020
#define AM_REG_CLKGEN_CLOCKEN_O 0x00000028
#define AM_REG_CLKGEN_CLOCKEN2_O 0x0000002C
#define AM_REG_CLKGEN_CLOCKEN3_O 0x00000030
#define AM_REG_CLKGEN_UARTEN_O 0x00000034
#define AM_REG_CLKGEN_CLKKEY_O 0x00000014
#define AM_REG_CLKGEN_INTEN_O 0x00000100
#define AM_REG_CLKGEN_INTSTAT_O 0x00000104
#define AM_REG_CLKGEN_INTCLR_O 0x00000108
#define AM_REG_CLKGEN_INTSET_O 0x0000010C
//*****************************************************************************
//
// Key values.
//
//*****************************************************************************
#define AM_REG_CLKGEN_CLKKEY_KEYVAL 0x00000047
//*****************************************************************************
//
// CLKGEN_INTEN - CLKGEN Interrupt Register: Enable
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_CLKGEN_INTEN_ALM_S 3
#define AM_REG_CLKGEN_INTEN_ALM_M 0x00000008
#define AM_REG_CLKGEN_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_CLKGEN_INTEN_OF_S 2
#define AM_REG_CLKGEN_INTEN_OF_M 0x00000004
#define AM_REG_CLKGEN_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_CLKGEN_INTEN_ACC_S 1
#define AM_REG_CLKGEN_INTEN_ACC_M 0x00000002
#define AM_REG_CLKGEN_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_CLKGEN_INTEN_ACF_S 0
#define AM_REG_CLKGEN_INTEN_ACF_M 0x00000001
#define AM_REG_CLKGEN_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// CLKGEN_INTSTAT - CLKGEN Interrupt Register: Status
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_CLKGEN_INTSTAT_ALM_S 3
#define AM_REG_CLKGEN_INTSTAT_ALM_M 0x00000008
#define AM_REG_CLKGEN_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_CLKGEN_INTSTAT_OF_S 2
#define AM_REG_CLKGEN_INTSTAT_OF_M 0x00000004
#define AM_REG_CLKGEN_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_CLKGEN_INTSTAT_ACC_S 1
#define AM_REG_CLKGEN_INTSTAT_ACC_M 0x00000002
#define AM_REG_CLKGEN_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_CLKGEN_INTSTAT_ACF_S 0
#define AM_REG_CLKGEN_INTSTAT_ACF_M 0x00000001
#define AM_REG_CLKGEN_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// CLKGEN_INTCLR - CLKGEN Interrupt Register: Clear
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_CLKGEN_INTCLR_ALM_S 3
#define AM_REG_CLKGEN_INTCLR_ALM_M 0x00000008
#define AM_REG_CLKGEN_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_CLKGEN_INTCLR_OF_S 2
#define AM_REG_CLKGEN_INTCLR_OF_M 0x00000004
#define AM_REG_CLKGEN_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_CLKGEN_INTCLR_ACC_S 1
#define AM_REG_CLKGEN_INTCLR_ACC_M 0x00000002
#define AM_REG_CLKGEN_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_CLKGEN_INTCLR_ACF_S 0
#define AM_REG_CLKGEN_INTCLR_ACF_M 0x00000001
#define AM_REG_CLKGEN_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// CLKGEN_INTSET - CLKGEN Interrupt Register: Set
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_CLKGEN_INTSET_ALM_S 3
#define AM_REG_CLKGEN_INTSET_ALM_M 0x00000008
#define AM_REG_CLKGEN_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_CLKGEN_INTSET_OF_S 2
#define AM_REG_CLKGEN_INTSET_OF_M 0x00000004
#define AM_REG_CLKGEN_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_CLKGEN_INTSET_ACC_S 1
#define AM_REG_CLKGEN_INTSET_ACC_M 0x00000002
#define AM_REG_CLKGEN_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_CLKGEN_INTSET_ACF_S 0
#define AM_REG_CLKGEN_INTSET_ACF_M 0x00000001
#define AM_REG_CLKGEN_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// CLKGEN_CALXT - XT Oscillator Control
//
//*****************************************************************************
// XT Oscillator calibration value
#define AM_REG_CLKGEN_CALXT_CALXT_S 0
#define AM_REG_CLKGEN_CALXT_CALXT_M 0x000007FF
#define AM_REG_CLKGEN_CALXT_CALXT(n) (((uint32_t)(n) << 0) & 0x000007FF)
//*****************************************************************************
//
// CLKGEN_CALRC - RC Oscillator Control
//
//*****************************************************************************
// LFRC Oscillator calibration value
#define AM_REG_CLKGEN_CALRC_CALRC_S 0
#define AM_REG_CLKGEN_CALRC_CALRC_M 0x0003FFFF
#define AM_REG_CLKGEN_CALRC_CALRC(n) (((uint32_t)(n) << 0) & 0x0003FFFF)
//*****************************************************************************
//
// CLKGEN_ACALCTR - Autocalibration Counter
//
//*****************************************************************************
// Autocalibration Counter result.
#define AM_REG_CLKGEN_ACALCTR_ACALCTR_S 0
#define AM_REG_CLKGEN_ACALCTR_ACALCTR_M 0x00FFFFFF
#define AM_REG_CLKGEN_ACALCTR_ACALCTR(n) (((uint32_t)(n) << 0) & 0x00FFFFFF)
//*****************************************************************************
//
// CLKGEN_OCTRL - Oscillator Control
//
//*****************************************************************************
// Autocalibration control
#define AM_REG_CLKGEN_OCTRL_ACAL_S 8
#define AM_REG_CLKGEN_OCTRL_ACAL_M 0x00000700
#define AM_REG_CLKGEN_OCTRL_ACAL(n) (((uint32_t)(n) << 8) & 0x00000700)
#define AM_REG_CLKGEN_OCTRL_ACAL_DIS 0x00000000
#define AM_REG_CLKGEN_OCTRL_ACAL_1024SEC 0x00000200
#define AM_REG_CLKGEN_OCTRL_ACAL_512SEC 0x00000300
#define AM_REG_CLKGEN_OCTRL_ACAL_XTFREQ 0x00000600
#define AM_REG_CLKGEN_OCTRL_ACAL_EXTFREQ 0x00000700
// Selects the RTC oscillator (1 => LFRC, 0 => XT)
#define AM_REG_CLKGEN_OCTRL_OSEL_S 7
#define AM_REG_CLKGEN_OCTRL_OSEL_M 0x00000080
#define AM_REG_CLKGEN_OCTRL_OSEL(n) (((uint32_t)(n) << 7) & 0x00000080)
#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_XT 0x00000000
#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_LFRC 0x00000080
// Oscillator switch on failure function
#define AM_REG_CLKGEN_OCTRL_FOS_S 6
#define AM_REG_CLKGEN_OCTRL_FOS_M 0x00000040
#define AM_REG_CLKGEN_OCTRL_FOS(n) (((uint32_t)(n) << 6) & 0x00000040)
#define AM_REG_CLKGEN_OCTRL_FOS_DIS 0x00000000
#define AM_REG_CLKGEN_OCTRL_FOS_EN 0x00000040
// Stop the LFRC Oscillator to the RTC
#define AM_REG_CLKGEN_OCTRL_STOPRC_S 1
#define AM_REG_CLKGEN_OCTRL_STOPRC_M 0x00000002
#define AM_REG_CLKGEN_OCTRL_STOPRC(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_CLKGEN_OCTRL_STOPRC_EN 0x00000000
#define AM_REG_CLKGEN_OCTRL_STOPRC_STOP 0x00000002
// Stop the XT Oscillator to the RTC
#define AM_REG_CLKGEN_OCTRL_STOPXT_S 0
#define AM_REG_CLKGEN_OCTRL_STOPXT_M 0x00000001
#define AM_REG_CLKGEN_OCTRL_STOPXT(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_CLKGEN_OCTRL_STOPXT_EN 0x00000000
#define AM_REG_CLKGEN_OCTRL_STOPXT_STOP 0x00000001
//*****************************************************************************
//
// CLKGEN_CLKOUT - CLKOUT Frequency Select
//
//*****************************************************************************
// Enable the CLKOUT signal
#define AM_REG_CLKGEN_CLKOUT_CKEN_S 7
#define AM_REG_CLKGEN_CLKOUT_CKEN_M 0x00000080
#define AM_REG_CLKGEN_CLKOUT_CKEN(n) (((uint32_t)(n) << 7) & 0x00000080)
#define AM_REG_CLKGEN_CLKOUT_CKEN_DIS 0x00000000
#define AM_REG_CLKGEN_CLKOUT_CKEN_EN 0x00000080
// CLKOUT signal select. Note that HIGH_DRIVE should be selected if any high
// frequencies (such as from HFRC) are selected for CLKOUT.
#define AM_REG_CLKGEN_CLKOUT_CKSEL_S 0
#define AM_REG_CLKGEN_CLKOUT_CKSEL_M 0x0000003F
#define AM_REG_CLKGEN_CLKOUT_CKSEL(n) (((uint32_t)(n) << 0) & 0x0000003F)
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC 0x00000000
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2 0x00000001
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4 0x00000002
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8 0x00000003
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16 0x00000004
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32 0x00000005
#define AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_1Hz 0x00000010
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M 0x00000016
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT 0x00000017
#define AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz 0x00000018
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC 0x00000019
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 0x0000001A
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 0x0000001B
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 0x0000001C
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 0x0000001D
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 0x0000001E
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 0x0000001F
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 0x00000020
#define AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK 0x00000022
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 0x00000023
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 0x00000024
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 0x00000025
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K 0x00000026
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256 0x00000027
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K 0x00000028
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K 0x00000029
#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 0x0000002A
#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 0x0000002B
#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz 0x0000002C
#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K 0x0000002D
#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M 0x0000002E
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K 0x0000002F
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M 0x00000030
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M 0x00000031
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE 0x00000032
#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 0x00000033
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE 0x00000035
#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 0x00000036
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 0x00000037
#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE 0x00000039
//*****************************************************************************
//
// CLKGEN_CCTRL - HFRC Clock Control
//
//*****************************************************************************
// Core Clock divisor
#define AM_REG_CLKGEN_CCTRL_CORESEL_S 0
#define AM_REG_CLKGEN_CCTRL_CORESEL_M 0x00000001
#define AM_REG_CLKGEN_CCTRL_CORESEL(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC 0x00000000
#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2 0x00000001
//*****************************************************************************
//
// CLKGEN_STATUS - Clock Generator Status
//
//*****************************************************************************
// XT Oscillator is enabled but not oscillating
#define AM_REG_CLKGEN_STATUS_OSCF_S 1
#define AM_REG_CLKGEN_STATUS_OSCF_M 0x00000002
#define AM_REG_CLKGEN_STATUS_OSCF(n) (((uint32_t)(n) << 1) & 0x00000002)
// Current RTC oscillator (1 => LFRC, 0 => XT)
#define AM_REG_CLKGEN_STATUS_OMODE_S 0
#define AM_REG_CLKGEN_STATUS_OMODE_M 0x00000001
#define AM_REG_CLKGEN_STATUS_OMODE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// CLKGEN_HFADJ - HFRC Adjustment
//
//*****************************************************************************
// Gain control for HFRC adjustment
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_S 21
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_M 0x00E00000
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN(n) (((uint32_t)(n) << 21) & 0x00E00000)
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1 0x00000000
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 0x00200000
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_4 0x00400000
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_8 0x00600000
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_16 0x00800000
#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_32 0x00A00000
// XT warmup period for HFRC adjustment
#define AM_REG_CLKGEN_HFADJ_HFWARMUP_S 20
#define AM_REG_CLKGEN_HFADJ_HFWARMUP_M 0x00100000
#define AM_REG_CLKGEN_HFADJ_HFWARMUP(n) (((uint32_t)(n) << 20) & 0x00100000)
#define AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC 0x00000000
#define AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC 0x00100000
// Target HFRC adjustment value.
#define AM_REG_CLKGEN_HFADJ_HFXTADJ_S 8
#define AM_REG_CLKGEN_HFADJ_HFXTADJ_M 0x000FFF00
#define AM_REG_CLKGEN_HFADJ_HFXTADJ(n) (((uint32_t)(n) << 8) & 0x000FFF00)
// Repeat period for HFRC adjustment
#define AM_REG_CLKGEN_HFADJ_HFADJCK_S 1
#define AM_REG_CLKGEN_HFADJ_HFADJCK_M 0x0000000E
#define AM_REG_CLKGEN_HFADJ_HFADJCK(n) (((uint32_t)(n) << 1) & 0x0000000E)
#define AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC 0x00000000
#define AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC 0x00000002
#define AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC 0x00000004
#define AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC 0x00000006
#define AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC 0x00000008
#define AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC 0x0000000A
#define AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC 0x0000000C
#define AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC 0x0000000E
// HFRC adjustment control
#define AM_REG_CLKGEN_HFADJ_HFADJEN_S 0
#define AM_REG_CLKGEN_HFADJ_HFADJEN_M 0x00000001
#define AM_REG_CLKGEN_HFADJ_HFADJEN(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS 0x00000000
#define AM_REG_CLKGEN_HFADJ_HFADJEN_EN 0x00000001
//*****************************************************************************
//
// CLKGEN_CLOCKEN - Clock Enable Status
//
//*****************************************************************************
// Clock enable status
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_S 0
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_M 0xFFFFFFFF
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_ADC_CLKEN 0x00000001
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER_CLKEN 0x00000002
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0A_CLKEN 0x00000004
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0B_CLKEN 0x00000008
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1A_CLKEN 0x00000010
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1B_CLKEN 0x00000020
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2A_CLKEN 0x00000040
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2B_CLKEN 0x00000080
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3A_CLKEN 0x00000100
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3B_CLKEN 0x00000200
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR0_CLKEN 0x00000400
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR1_CLKEN 0x00000800
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR2_CLKEN 0x00001000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR3_CLKEN 0x00002000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR4_CLKEN 0x00004000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR5_CLKEN 0x00008000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC0_CLKEN 0x00010000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC1_CLKEN 0x00020000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC2_CLKEN 0x00040000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC3_CLKEN 0x00080000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC4_CLKEN 0x00100000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC5_CLKEN 0x00200000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOSLAVE_CLKEN 0x00400000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDM_CLKEN 0x00800000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDMIFC_CLKEN 0x01000000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_RSTGEN_CLKEN 0x02000000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_SRAM_WIPE_CLKEN 0x04000000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CLKEN 0x08000000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CNT_CLKEN 0x10000000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_TPIU_CLKEN 0x20000000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0_HCLK_CLKEN 0x40000000
#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0HF_CLKEN 0x80000000
//*****************************************************************************
//
// CLKGEN_CLOCKEN2 - Clock Enable Status
//
//*****************************************************************************
// Clock enable status 2
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_S 0
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_M 0xFFFFFFFF
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1_HCLK_CLKEN 0x00000001
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1HF_CLKEN 0x00000002
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_WDT_CLKEN 0x00000004
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_XT_32KHz_EN 0x40000000
#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_FRCHFRC 0x80000000
//*****************************************************************************
//
// CLKGEN_CLOCKEN3 - Clock Enable Status
//
//*****************************************************************************
// Clock enable status 3
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_S 0
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_M 0xFFFFFFFF
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_xtal_en 0x01000000
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_hfrc_en 0x02000000
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFADJEN 0x04000000
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_en_out 0x08000000
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_RTC_SOURCE 0x10000000
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_XTAL_EN 0x20000000
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_EN 0x40000000
#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_FLASHCLK_EN 0x80000000
//*****************************************************************************
//
// CLKGEN_UARTEN - UART Enable
//
//*****************************************************************************
// UART1 system clock control
#define AM_REG_CLKGEN_UARTEN_UART1EN_S 8
#define AM_REG_CLKGEN_UARTEN_UART1EN_M 0x00000300
#define AM_REG_CLKGEN_UARTEN_UART1EN(n) (((uint32_t)(n) << 8) & 0x00000300)
#define AM_REG_CLKGEN_UARTEN_UART1EN_DIS 0x00000000
#define AM_REG_CLKGEN_UARTEN_UART1EN_EN 0x00000100
#define AM_REG_CLKGEN_UARTEN_UART1EN_REDUCE_FREQ 0x00000200
#define AM_REG_CLKGEN_UARTEN_UART1EN_EN_POWER_SAV 0x00000300
// UART0 system clock control
#define AM_REG_CLKGEN_UARTEN_UART0EN_S 0
#define AM_REG_CLKGEN_UARTEN_UART0EN_M 0x00000003
#define AM_REG_CLKGEN_UARTEN_UART0EN(n) (((uint32_t)(n) << 0) & 0x00000003)
#define AM_REG_CLKGEN_UARTEN_UART0EN_DIS 0x00000000
#define AM_REG_CLKGEN_UARTEN_UART0EN_EN 0x00000001
#define AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ 0x00000002
#define AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV 0x00000003
#endif // AM_REG_CLKGEN_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_ctimer.h
+1919
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ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_flashctrl.h
+72
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@@ -0,0 +1,72 @@
//*****************************************************************************
//
// am_reg_flashctrl.h
//! @file
//!
//! @brief Register macros for the FLASHCTRL module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_FLASHCTRL_H
#define AM_REG_FLASHCTRL_H
//*****************************************************************************
//
// FLASHCTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_FLASHCTRL_NUM_MODULES 1
#define AM_REG_FLASHCTRLn(n) \
(REG_FLASHCTRL_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
//*****************************************************************************
//
// Key values.
//
//*****************************************************************************
#endif // AM_REG_FLASHCTRL_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_gpio.h
+5222
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ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_iomstr.h
+591
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//*****************************************************************************
//
// am_reg_iomstr.h
//! @file
//!
//! @brief Register macros for the IOMSTR module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_IOMSTR_H
#define AM_REG_IOMSTR_H
//*****************************************************************************
//
// IOMSTR
// Instance finder. (6 instance(s) available)
//
//*****************************************************************************
#define AM_REG_IOMSTR_NUM_MODULES 6
#define AM_REG_IOMSTRn(n) \
(REG_IOMSTR_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_IOMSTR_FIFO_O 0x00000000
#define AM_REG_IOMSTR_FIFOPTR_O 0x00000100
#define AM_REG_IOMSTR_TLNGTH_O 0x00000104
#define AM_REG_IOMSTR_FIFOTHR_O 0x00000108
#define AM_REG_IOMSTR_CLKCFG_O 0x0000010C
#define AM_REG_IOMSTR_CMD_O 0x00000110
#define AM_REG_IOMSTR_CMDRPT_O 0x00000114
#define AM_REG_IOMSTR_STATUS_O 0x00000118
#define AM_REG_IOMSTR_CFG_O 0x0000011C
#define AM_REG_IOMSTR_INTEN_O 0x00000200
#define AM_REG_IOMSTR_INTSTAT_O 0x00000204
#define AM_REG_IOMSTR_INTCLR_O 0x00000208
#define AM_REG_IOMSTR_INTSET_O 0x0000020C
//*****************************************************************************
//
// IOMSTR_INTEN - IO Master Interrupts: Enable
//
//*****************************************************************************
// This is the arbitration loss interrupt. This error occurs if another master
// collides with an IO Master transfer. Generally, the IOM started an operation
// but found SDA already low.
#define AM_REG_IOMSTR_INTEN_ARB_S 10
#define AM_REG_IOMSTR_INTEN_ARB_M 0x00000400
#define AM_REG_IOMSTR_INTEN_ARB(n) (((uint32_t)(n) << 10) & 0x00000400)
// This is the STOP command interrupt. A STOP bit was detected by the IOM.
#define AM_REG_IOMSTR_INTEN_STOP_S 9
#define AM_REG_IOMSTR_INTEN_STOP_M 0x00000200
#define AM_REG_IOMSTR_INTEN_STOP(n) (((uint32_t)(n) << 9) & 0x00000200)
// This is the START command interrupt. A START from another master was
// detected. Software must wait for a STOP before proceeding.
#define AM_REG_IOMSTR_INTEN_START_S 8
#define AM_REG_IOMSTR_INTEN_START_M 0x00000100
#define AM_REG_IOMSTR_INTEN_START(n) (((uint32_t)(n) << 8) & 0x00000100)
// This is the illegal command interrupt. Software attempted to issue a CMD
// while another CMD was already in progress. Or an attempt was made to issue a
// non-zero-length write CMD with an empty FIFO.
#define AM_REG_IOMSTR_INTEN_ICMD_S 7
#define AM_REG_IOMSTR_INTEN_ICMD_M 0x00000080
#define AM_REG_IOMSTR_INTEN_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080)
// This is the illegal FIFO access interrupt. An attempt was made to read the
// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
// CMD.
#define AM_REG_IOMSTR_INTEN_IACC_S 6
#define AM_REG_IOMSTR_INTEN_IACC_M 0x00000040
#define AM_REG_IOMSTR_INTEN_IACC(n) (((uint32_t)(n) << 6) & 0x00000040)
// This is the WTLEN interrupt.
#define AM_REG_IOMSTR_INTEN_WTLEN_S 5
#define AM_REG_IOMSTR_INTEN_WTLEN_M 0x00000020
#define AM_REG_IOMSTR_INTEN_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020)
// This is the I2C NAK interrupt. The expected ACK from the slave was not
// received by the IOM.
#define AM_REG_IOMSTR_INTEN_NAK_S 4
#define AM_REG_IOMSTR_INTEN_NAK_M 0x00000010
#define AM_REG_IOMSTR_INTEN_NAK(n) (((uint32_t)(n) << 4) & 0x00000010)
// This is the Write FIFO Overflow interrupt. An attempt was made to write the
// FIFO while it was full (i.e. while FIFOSIZ > 124).
#define AM_REG_IOMSTR_INTEN_FOVFL_S 3
#define AM_REG_IOMSTR_INTEN_FOVFL_M 0x00000008
#define AM_REG_IOMSTR_INTEN_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008)
// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
// when empty (i.e. while FIFOSIZ less than 4).
#define AM_REG_IOMSTR_INTEN_FUNDFL_S 2
#define AM_REG_IOMSTR_INTEN_FUNDFL_M 0x00000004
#define AM_REG_IOMSTR_INTEN_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO Threshold interrupt.
#define AM_REG_IOMSTR_INTEN_THR_S 1
#define AM_REG_IOMSTR_INTEN_THR_M 0x00000002
#define AM_REG_IOMSTR_INTEN_THR(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the Command Complete interrupt.
#define AM_REG_IOMSTR_INTEN_CMDCMP_S 0
#define AM_REG_IOMSTR_INTEN_CMDCMP_M 0x00000001
#define AM_REG_IOMSTR_INTEN_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOMSTR_INTSTAT - IO Master Interrupts: Status
//
//*****************************************************************************
// This is the arbitration loss interrupt. This error occurs if another master
// collides with an IO Master transfer. Generally, the IOM started an operation
// but found SDA already low.
#define AM_REG_IOMSTR_INTSTAT_ARB_S 10
#define AM_REG_IOMSTR_INTSTAT_ARB_M 0x00000400
#define AM_REG_IOMSTR_INTSTAT_ARB(n) (((uint32_t)(n) << 10) & 0x00000400)
// This is the STOP command interrupt. A STOP bit was detected by the IOM.
#define AM_REG_IOMSTR_INTSTAT_STOP_S 9
#define AM_REG_IOMSTR_INTSTAT_STOP_M 0x00000200
#define AM_REG_IOMSTR_INTSTAT_STOP(n) (((uint32_t)(n) << 9) & 0x00000200)
// This is the START command interrupt. A START from another master was
// detected. Software must wait for a STOP before proceeding.
#define AM_REG_IOMSTR_INTSTAT_START_S 8
#define AM_REG_IOMSTR_INTSTAT_START_M 0x00000100
#define AM_REG_IOMSTR_INTSTAT_START(n) (((uint32_t)(n) << 8) & 0x00000100)
// This is the illegal command interrupt. Software attempted to issue a CMD
// while another CMD was already in progress. Or an attempt was made to issue a
// non-zero-length write CMD with an empty FIFO.
#define AM_REG_IOMSTR_INTSTAT_ICMD_S 7
#define AM_REG_IOMSTR_INTSTAT_ICMD_M 0x00000080
#define AM_REG_IOMSTR_INTSTAT_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080)
// This is the illegal FIFO access interrupt. An attempt was made to read the
// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
// CMD.
#define AM_REG_IOMSTR_INTSTAT_IACC_S 6
#define AM_REG_IOMSTR_INTSTAT_IACC_M 0x00000040
#define AM_REG_IOMSTR_INTSTAT_IACC(n) (((uint32_t)(n) << 6) & 0x00000040)
// This is the WTLEN interrupt.
#define AM_REG_IOMSTR_INTSTAT_WTLEN_S 5
#define AM_REG_IOMSTR_INTSTAT_WTLEN_M 0x00000020
#define AM_REG_IOMSTR_INTSTAT_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020)
// This is the I2C NAK interrupt. The expected ACK from the slave was not
// received by the IOM.
#define AM_REG_IOMSTR_INTSTAT_NAK_S 4
#define AM_REG_IOMSTR_INTSTAT_NAK_M 0x00000010
#define AM_REG_IOMSTR_INTSTAT_NAK(n) (((uint32_t)(n) << 4) & 0x00000010)
// This is the Write FIFO Overflow interrupt. An attempt was made to write the
// FIFO while it was full (i.e. while FIFOSIZ > 124).
#define AM_REG_IOMSTR_INTSTAT_FOVFL_S 3
#define AM_REG_IOMSTR_INTSTAT_FOVFL_M 0x00000008
#define AM_REG_IOMSTR_INTSTAT_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008)
// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
// when empty (i.e. while FIFOSIZ less than 4).
#define AM_REG_IOMSTR_INTSTAT_FUNDFL_S 2
#define AM_REG_IOMSTR_INTSTAT_FUNDFL_M 0x00000004
#define AM_REG_IOMSTR_INTSTAT_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO Threshold interrupt.
#define AM_REG_IOMSTR_INTSTAT_THR_S 1
#define AM_REG_IOMSTR_INTSTAT_THR_M 0x00000002
#define AM_REG_IOMSTR_INTSTAT_THR(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the Command Complete interrupt.
#define AM_REG_IOMSTR_INTSTAT_CMDCMP_S 0
#define AM_REG_IOMSTR_INTSTAT_CMDCMP_M 0x00000001
#define AM_REG_IOMSTR_INTSTAT_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOMSTR_INTCLR - IO Master Interrupts: Clear
//
//*****************************************************************************
// This is the arbitration loss interrupt. This error occurs if another master
// collides with an IO Master transfer. Generally, the IOM started an operation
// but found SDA already low.
#define AM_REG_IOMSTR_INTCLR_ARB_S 10
#define AM_REG_IOMSTR_INTCLR_ARB_M 0x00000400
#define AM_REG_IOMSTR_INTCLR_ARB(n) (((uint32_t)(n) << 10) & 0x00000400)
// This is the STOP command interrupt. A STOP bit was detected by the IOM.
#define AM_REG_IOMSTR_INTCLR_STOP_S 9
#define AM_REG_IOMSTR_INTCLR_STOP_M 0x00000200
#define AM_REG_IOMSTR_INTCLR_STOP(n) (((uint32_t)(n) << 9) & 0x00000200)
// This is the START command interrupt. A START from another master was
// detected. Software must wait for a STOP before proceeding.
#define AM_REG_IOMSTR_INTCLR_START_S 8
#define AM_REG_IOMSTR_INTCLR_START_M 0x00000100
#define AM_REG_IOMSTR_INTCLR_START(n) (((uint32_t)(n) << 8) & 0x00000100)
// This is the illegal command interrupt. Software attempted to issue a CMD
// while another CMD was already in progress. Or an attempt was made to issue a
// non-zero-length write CMD with an empty FIFO.
#define AM_REG_IOMSTR_INTCLR_ICMD_S 7
#define AM_REG_IOMSTR_INTCLR_ICMD_M 0x00000080
#define AM_REG_IOMSTR_INTCLR_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080)
// This is the illegal FIFO access interrupt. An attempt was made to read the
// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
// CMD.
#define AM_REG_IOMSTR_INTCLR_IACC_S 6
#define AM_REG_IOMSTR_INTCLR_IACC_M 0x00000040
#define AM_REG_IOMSTR_INTCLR_IACC(n) (((uint32_t)(n) << 6) & 0x00000040)
// This is the WTLEN interrupt.
#define AM_REG_IOMSTR_INTCLR_WTLEN_S 5
#define AM_REG_IOMSTR_INTCLR_WTLEN_M 0x00000020
#define AM_REG_IOMSTR_INTCLR_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020)
// This is the I2C NAK interrupt. The expected ACK from the slave was not
// received by the IOM.
#define AM_REG_IOMSTR_INTCLR_NAK_S 4
#define AM_REG_IOMSTR_INTCLR_NAK_M 0x00000010
#define AM_REG_IOMSTR_INTCLR_NAK(n) (((uint32_t)(n) << 4) & 0x00000010)
// This is the Write FIFO Overflow interrupt. An attempt was made to write the
// FIFO while it was full (i.e. while FIFOSIZ > 124).
#define AM_REG_IOMSTR_INTCLR_FOVFL_S 3
#define AM_REG_IOMSTR_INTCLR_FOVFL_M 0x00000008
#define AM_REG_IOMSTR_INTCLR_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008)
// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
// when empty (i.e. while FIFOSIZ less than 4).
#define AM_REG_IOMSTR_INTCLR_FUNDFL_S 2
#define AM_REG_IOMSTR_INTCLR_FUNDFL_M 0x00000004
#define AM_REG_IOMSTR_INTCLR_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO Threshold interrupt.
#define AM_REG_IOMSTR_INTCLR_THR_S 1
#define AM_REG_IOMSTR_INTCLR_THR_M 0x00000002
#define AM_REG_IOMSTR_INTCLR_THR(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the Command Complete interrupt.
#define AM_REG_IOMSTR_INTCLR_CMDCMP_S 0
#define AM_REG_IOMSTR_INTCLR_CMDCMP_M 0x00000001
#define AM_REG_IOMSTR_INTCLR_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOMSTR_INTSET - IO Master Interrupts: Set
//
//*****************************************************************************
// This is the arbitration loss interrupt. This error occurs if another master
// collides with an IO Master transfer. Generally, the IOM started an operation
// but found SDA already low.
#define AM_REG_IOMSTR_INTSET_ARB_S 10
#define AM_REG_IOMSTR_INTSET_ARB_M 0x00000400
#define AM_REG_IOMSTR_INTSET_ARB(n) (((uint32_t)(n) << 10) & 0x00000400)
// This is the STOP command interrupt. A STOP bit was detected by the IOM.
#define AM_REG_IOMSTR_INTSET_STOP_S 9
#define AM_REG_IOMSTR_INTSET_STOP_M 0x00000200
#define AM_REG_IOMSTR_INTSET_STOP(n) (((uint32_t)(n) << 9) & 0x00000200)
// This is the START command interrupt. A START from another master was
// detected. Software must wait for a STOP before proceeding.
#define AM_REG_IOMSTR_INTSET_START_S 8
#define AM_REG_IOMSTR_INTSET_START_M 0x00000100
#define AM_REG_IOMSTR_INTSET_START(n) (((uint32_t)(n) << 8) & 0x00000100)
// This is the illegal command interrupt. Software attempted to issue a CMD
// while another CMD was already in progress. Or an attempt was made to issue a
// non-zero-length write CMD with an empty FIFO.
#define AM_REG_IOMSTR_INTSET_ICMD_S 7
#define AM_REG_IOMSTR_INTSET_ICMD_M 0x00000080
#define AM_REG_IOMSTR_INTSET_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080)
// This is the illegal FIFO access interrupt. An attempt was made to read the
// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
// CMD.
#define AM_REG_IOMSTR_INTSET_IACC_S 6
#define AM_REG_IOMSTR_INTSET_IACC_M 0x00000040
#define AM_REG_IOMSTR_INTSET_IACC(n) (((uint32_t)(n) << 6) & 0x00000040)
// This is the WTLEN interrupt.
#define AM_REG_IOMSTR_INTSET_WTLEN_S 5
#define AM_REG_IOMSTR_INTSET_WTLEN_M 0x00000020
#define AM_REG_IOMSTR_INTSET_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020)
// This is the I2C NAK interrupt. The expected ACK from the slave was not
// received by the IOM.
#define AM_REG_IOMSTR_INTSET_NAK_S 4
#define AM_REG_IOMSTR_INTSET_NAK_M 0x00000010
#define AM_REG_IOMSTR_INTSET_NAK(n) (((uint32_t)(n) << 4) & 0x00000010)
// This is the Write FIFO Overflow interrupt. An attempt was made to write the
// FIFO while it was full (i.e. while FIFOSIZ > 124).
#define AM_REG_IOMSTR_INTSET_FOVFL_S 3
#define AM_REG_IOMSTR_INTSET_FOVFL_M 0x00000008
#define AM_REG_IOMSTR_INTSET_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008)
// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
// when empty (i.e. while FIFOSIZ less than 4).
#define AM_REG_IOMSTR_INTSET_FUNDFL_S 2
#define AM_REG_IOMSTR_INTSET_FUNDFL_M 0x00000004
#define AM_REG_IOMSTR_INTSET_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO Threshold interrupt.
#define AM_REG_IOMSTR_INTSET_THR_S 1
#define AM_REG_IOMSTR_INTSET_THR_M 0x00000002
#define AM_REG_IOMSTR_INTSET_THR(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the Command Complete interrupt.
#define AM_REG_IOMSTR_INTSET_CMDCMP_S 0
#define AM_REG_IOMSTR_INTSET_CMDCMP_M 0x00000001
#define AM_REG_IOMSTR_INTSET_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOMSTR_FIFO - FIFO Access Port
//
//*****************************************************************************
// FIFO access port.
#define AM_REG_IOMSTR_FIFO_FIFO_S 0
#define AM_REG_IOMSTR_FIFO_FIFO_M 0xFFFFFFFF
#define AM_REG_IOMSTR_FIFO_FIFO(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// IOMSTR_FIFOPTR - Current FIFO Pointers
//
//*****************************************************************************
// The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or
// 64-FIFOSIZ if FULLDUP = 1)).
#define AM_REG_IOMSTR_FIFOPTR_FIFOREM_S 16
#define AM_REG_IOMSTR_FIFOPTR_FIFOREM_M 0x00FF0000
#define AM_REG_IOMSTR_FIFOPTR_FIFOREM(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// The number of bytes currently in the FIFO.
#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_S 0
#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_M 0x000000FF
#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// IOMSTR_TLNGTH - Transfer Length
//
//*****************************************************************************
// Remaining transfer length.
#define AM_REG_IOMSTR_TLNGTH_TLNGTH_S 0
#define AM_REG_IOMSTR_TLNGTH_TLNGTH_M 0x00000FFF
#define AM_REG_IOMSTR_TLNGTH_TLNGTH(n) (((uint32_t)(n) << 0) & 0x00000FFF)
//*****************************************************************************
//
// IOMSTR_FIFOTHR - FIFO Threshold Configuration
//
//*****************************************************************************
// FIFO write threshold.
#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_S 8
#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_M 0x00007F00
#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(n) (((uint32_t)(n) << 8) & 0x00007F00)
// FIFO read threshold.
#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_S 0
#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_M 0x0000007F
#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR(n) (((uint32_t)(n) << 0) & 0x0000007F)
//*****************************************************************************
//
// IOMSTR_CLKCFG - I/O Clock Configuration
//
//*****************************************************************************
// Clock total count minus 1.
#define AM_REG_IOMSTR_CLKCFG_TOTPER_S 24
#define AM_REG_IOMSTR_CLKCFG_TOTPER_M 0xFF000000
#define AM_REG_IOMSTR_CLKCFG_TOTPER(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Clock low count minus 1.
#define AM_REG_IOMSTR_CLKCFG_LOWPER_S 16
#define AM_REG_IOMSTR_CLKCFG_LOWPER_M 0x00FF0000
#define AM_REG_IOMSTR_CLKCFG_LOWPER(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Enable clock division by TOTPER.
#define AM_REG_IOMSTR_CLKCFG_DIVEN_S 12
#define AM_REG_IOMSTR_CLKCFG_DIVEN_M 0x00001000
#define AM_REG_IOMSTR_CLKCFG_DIVEN(n) (((uint32_t)(n) << 12) & 0x00001000)
#define AM_REG_IOMSTR_CLKCFG_DIVEN_DIS 0x00000000
#define AM_REG_IOMSTR_CLKCFG_DIVEN_EN 0x00001000
// Enable divide by 3.
#define AM_REG_IOMSTR_CLKCFG_DIV3_S 11
#define AM_REG_IOMSTR_CLKCFG_DIV3_M 0x00000800
#define AM_REG_IOMSTR_CLKCFG_DIV3(n) (((uint32_t)(n) << 11) & 0x00000800)
#define AM_REG_IOMSTR_CLKCFG_DIV3_DIS 0x00000000
#define AM_REG_IOMSTR_CLKCFG_DIV3_EN 0x00000800
// Select the input clock frequency.
#define AM_REG_IOMSTR_CLKCFG_FSEL_S 8
#define AM_REG_IOMSTR_CLKCFG_FSEL_M 0x00000700
#define AM_REG_IOMSTR_CLKCFG_FSEL(n) (((uint32_t)(n) << 8) & 0x00000700)
#define AM_REG_IOMSTR_CLKCFG_FSEL_MIN_PWR 0x00000000
#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC 0x00000100
#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV2 0x00000200
#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV4 0x00000300
#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV8 0x00000400
#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV16 0x00000500
#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV32 0x00000600
#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV64 0x00000700
//*****************************************************************************
//
// IOMSTR_CMD - Command Register
//
//*****************************************************************************
// This register holds the I/O Command
#define AM_REG_IOMSTR_CMD_CMD_S 0
#define AM_REG_IOMSTR_CMD_CMD_M 0xFFFFFFFF
#define AM_REG_IOMSTR_CMD_CMD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// IOMSTR_CMDRPT - Command Repeat Register
//
//*****************************************************************************
// These bits hold the Command repeat count.
#define AM_REG_IOMSTR_CMDRPT_CMDRPT_S 0
#define AM_REG_IOMSTR_CMDRPT_CMDRPT_M 0x0000001F
#define AM_REG_IOMSTR_CMDRPT_CMDRPT(n) (((uint32_t)(n) << 0) & 0x0000001F)
//*****************************************************************************
//
// IOMSTR_STATUS - Status Register
//
//*****************************************************************************
// This bit indicates if the I/O state machine is IDLE.
#define AM_REG_IOMSTR_STATUS_IDLEST_S 2
#define AM_REG_IOMSTR_STATUS_IDLEST_M 0x00000004
#define AM_REG_IOMSTR_STATUS_IDLEST(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_IOMSTR_STATUS_IDLEST_IDLE 0x00000004
// This bit indicates if the I/O Command is active.
#define AM_REG_IOMSTR_STATUS_CMDACT_S 1
#define AM_REG_IOMSTR_STATUS_CMDACT_M 0x00000002
#define AM_REG_IOMSTR_STATUS_CMDACT(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_IOMSTR_STATUS_CMDACT_ACTIVE 0x00000002
// This bit indicates if an error interrupt has occurred.
#define AM_REG_IOMSTR_STATUS_ERR_S 0
#define AM_REG_IOMSTR_STATUS_ERR_M 0x00000001
#define AM_REG_IOMSTR_STATUS_ERR(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_IOMSTR_STATUS_ERR_ERROR 0x00000001
//*****************************************************************************
//
// IOMSTR_CFG - I/O Master Configuration
//
//*****************************************************************************
// This bit enables the IO Master.
#define AM_REG_IOMSTR_CFG_IFCEN_S 31
#define AM_REG_IOMSTR_CFG_IFCEN_M 0x80000000
#define AM_REG_IOMSTR_CFG_IFCEN(n) (((uint32_t)(n) << 31) & 0x80000000)
#define AM_REG_IOMSTR_CFG_IFCEN_DIS 0x00000000
#define AM_REG_IOMSTR_CFG_IFCEN_EN 0x80000000
// This bit selects the read flow control signal polarity.
#define AM_REG_IOMSTR_CFG_RDFCPOL_S 14
#define AM_REG_IOMSTR_CFG_RDFCPOL_M 0x00004000
#define AM_REG_IOMSTR_CFG_RDFCPOL(n) (((uint32_t)(n) << 14) & 0x00004000)
#define AM_REG_IOMSTR_CFG_RDFCPOL_HIGH 0x00000000
#define AM_REG_IOMSTR_CFG_RDFCPOL_LOW 0x00004000
// This bit selects the write flow control signal polarity.
#define AM_REG_IOMSTR_CFG_WTFCPOL_S 13
#define AM_REG_IOMSTR_CFG_WTFCPOL_M 0x00002000
#define AM_REG_IOMSTR_CFG_WTFCPOL(n) (((uint32_t)(n) << 13) & 0x00002000)
#define AM_REG_IOMSTR_CFG_WTFCPOL_HIGH 0x00000000
#define AM_REG_IOMSTR_CFG_WTFCPOL_LOW 0x00002000
// This bit selects the write mode flow control signal.
#define AM_REG_IOMSTR_CFG_WTFCIRQ_S 12
#define AM_REG_IOMSTR_CFG_WTFCIRQ_M 0x00001000
#define AM_REG_IOMSTR_CFG_WTFCIRQ(n) (((uint32_t)(n) << 12) & 0x00001000)
#define AM_REG_IOMSTR_CFG_WTFCIRQ_MISO 0x00000000
#define AM_REG_IOMSTR_CFG_WTFCIRQ_IRQ 0x00001000
// This bit must be left at the default value of 0.
#define AM_REG_IOMSTR_CFG_FCDEL_S 11
#define AM_REG_IOMSTR_CFG_FCDEL_M 0x00000800
#define AM_REG_IOMSTR_CFG_FCDEL(n) (((uint32_t)(n) << 11) & 0x00000800)
// This bit invewrts MOSI when flow control is enabled.
#define AM_REG_IOMSTR_CFG_MOSIINV_S 10
#define AM_REG_IOMSTR_CFG_MOSIINV_M 0x00000400
#define AM_REG_IOMSTR_CFG_MOSIINV(n) (((uint32_t)(n) << 10) & 0x00000400)
#define AM_REG_IOMSTR_CFG_MOSIINV_NORMAL 0x00000000
#define AM_REG_IOMSTR_CFG_MOSIINV_INVERT 0x00000400
// This bit enables read mode flow control.
#define AM_REG_IOMSTR_CFG_RDFC_S 9
#define AM_REG_IOMSTR_CFG_RDFC_M 0x00000200
#define AM_REG_IOMSTR_CFG_RDFC(n) (((uint32_t)(n) << 9) & 0x00000200)
#define AM_REG_IOMSTR_CFG_RDFC_DIS 0x00000000
#define AM_REG_IOMSTR_CFG_RDFC_EN 0x00000200
// This bit enables write mode flow control.
#define AM_REG_IOMSTR_CFG_WTFC_S 8
#define AM_REG_IOMSTR_CFG_WTFC_M 0x00000100
#define AM_REG_IOMSTR_CFG_WTFC(n) (((uint32_t)(n) << 8) & 0x00000100)
#define AM_REG_IOMSTR_CFG_WTFC_DIS 0x00000000
#define AM_REG_IOMSTR_CFG_WTFC_EN 0x00000100
// This bit selects the preread timing.
#define AM_REG_IOMSTR_CFG_STARTRD_S 4
#define AM_REG_IOMSTR_CFG_STARTRD_M 0x00000030
#define AM_REG_IOMSTR_CFG_STARTRD(n) (((uint32_t)(n) << 4) & 0x00000030)
#define AM_REG_IOMSTR_CFG_STARTRD_PRERD0 0x00000000
#define AM_REG_IOMSTR_CFG_STARTRD_PRERD1 0x00000010
#define AM_REG_IOMSTR_CFG_STARTRD_PRERD2 0x00000020
#define AM_REG_IOMSTR_CFG_STARTRD_PRERD3 0x00000030
// This bit selects full duplex mode.
#define AM_REG_IOMSTR_CFG_FULLDUP_S 3
#define AM_REG_IOMSTR_CFG_FULLDUP_M 0x00000008
#define AM_REG_IOMSTR_CFG_FULLDUP(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_IOMSTR_CFG_FULLDUP_NORMAL 0x00000000
#define AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP 0x00000008
// This bit selects SPI phase.
#define AM_REG_IOMSTR_CFG_SPHA_S 2
#define AM_REG_IOMSTR_CFG_SPHA_M 0x00000004
#define AM_REG_IOMSTR_CFG_SPHA(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_LEADING_EDGE 0x00000000
#define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_TRAILING_EDGE 0x00000004
// This bit selects SPI polarity.
#define AM_REG_IOMSTR_CFG_SPOL_S 1
#define AM_REG_IOMSTR_CFG_SPOL_M 0x00000002
#define AM_REG_IOMSTR_CFG_SPOL(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_0 0x00000000
#define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_1 0x00000002
// This bit selects the I/O interface.
#define AM_REG_IOMSTR_CFG_IFCSEL_S 0
#define AM_REG_IOMSTR_CFG_IFCSEL_M 0x00000001
#define AM_REG_IOMSTR_CFG_IFCSEL(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_IOMSTR_CFG_IFCSEL_I2C 0x00000000
#define AM_REG_IOMSTR_CFG_IFCSEL_SPI 0x00000001
#endif // AM_REG_IOMSTR_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_ioslave.h
+518
View File
@@ -0,0 +1,518 @@
//*****************************************************************************
//
// am_reg_ioslave.h
//! @file
//!
//! @brief Register macros for the IOSLAVE module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_IOSLAVE_H
#define AM_REG_IOSLAVE_H
//*****************************************************************************
//
// IOSLAVE
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_IOSLAVE_NUM_MODULES 1
#define AM_REG_IOSLAVEn(n) \
(REG_IOSLAVE_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_IOSLAVE_FIFOPTR_O 0x00000100
#define AM_REG_IOSLAVE_FIFOCFG_O 0x00000104
#define AM_REG_IOSLAVE_FIFOTHR_O 0x00000108
#define AM_REG_IOSLAVE_FUPD_O 0x0000010C
#define AM_REG_IOSLAVE_FIFOCTR_O 0x00000110
#define AM_REG_IOSLAVE_FIFOINC_O 0x00000114
#define AM_REG_IOSLAVE_CFG_O 0x00000118
#define AM_REG_IOSLAVE_PRENC_O 0x0000011C
#define AM_REG_IOSLAVE_IOINTCTL_O 0x00000120
#define AM_REG_IOSLAVE_GENADD_O 0x00000124
#define AM_REG_IOSLAVE_INTEN_O 0x00000200
#define AM_REG_IOSLAVE_INTSTAT_O 0x00000204
#define AM_REG_IOSLAVE_INTCLR_O 0x00000208
#define AM_REG_IOSLAVE_INTSET_O 0x0000020C
#define AM_REG_IOSLAVE_REGACCINTEN_O 0x00000210
#define AM_REG_IOSLAVE_REGACCINTSTAT_O 0x00000214
#define AM_REG_IOSLAVE_REGACCINTCLR_O 0x00000218
#define AM_REG_IOSLAVE_REGACCINTSET_O 0x0000021C
//*****************************************************************************
//
// IOSLAVE_INTEN - IO Slave Interrupts: Enable
//
//*****************************************************************************
// Transfer complete interrupt, write to register space.
#define AM_REG_IOSLAVE_INTEN_XCMPWR_S 9
#define AM_REG_IOSLAVE_INTEN_XCMPWR_M 0x00000200
#define AM_REG_IOSLAVE_INTEN_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200)
// Transfer complete interrupt, write to FIFO space.
#define AM_REG_IOSLAVE_INTEN_XCMPWF_S 8
#define AM_REG_IOSLAVE_INTEN_XCMPWF_M 0x00000100
#define AM_REG_IOSLAVE_INTEN_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100)
// Transfer complete interrupt, read from register space.
#define AM_REG_IOSLAVE_INTEN_XCMPRR_S 7
#define AM_REG_IOSLAVE_INTEN_XCMPRR_M 0x00000080
#define AM_REG_IOSLAVE_INTEN_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080)
// Transfer complete interrupt, read from FIFO space.
#define AM_REG_IOSLAVE_INTEN_XCMPRF_S 6
#define AM_REG_IOSLAVE_INTEN_XCMPRF_M 0x00000040
#define AM_REG_IOSLAVE_INTEN_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040)
// I2C Interrupt Write interrupt.
#define AM_REG_IOSLAVE_INTEN_IOINTW_S 5
#define AM_REG_IOSLAVE_INTEN_IOINTW_M 0x00000020
#define AM_REG_IOSLAVE_INTEN_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020)
// I2C General Address interrupt.
#define AM_REG_IOSLAVE_INTEN_GENAD_S 4
#define AM_REG_IOSLAVE_INTEN_GENAD_M 0x00000010
#define AM_REG_IOSLAVE_INTEN_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010)
// FIFO Read Error interrupt.
#define AM_REG_IOSLAVE_INTEN_FRDERR_S 3
#define AM_REG_IOSLAVE_INTEN_FRDERR_M 0x00000008
#define AM_REG_IOSLAVE_INTEN_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008)
// FIFO Underflow interrupt.
#define AM_REG_IOSLAVE_INTEN_FUNDFL_S 2
#define AM_REG_IOSLAVE_INTEN_FUNDFL_M 0x00000004
#define AM_REG_IOSLAVE_INTEN_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// FIFO Overflow interrupt.
#define AM_REG_IOSLAVE_INTEN_FOVFL_S 1
#define AM_REG_IOSLAVE_INTEN_FOVFL_M 0x00000002
#define AM_REG_IOSLAVE_INTEN_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002)
// FIFO Size interrupt.
#define AM_REG_IOSLAVE_INTEN_FSIZE_S 0
#define AM_REG_IOSLAVE_INTEN_FSIZE_M 0x00000001
#define AM_REG_IOSLAVE_INTEN_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOSLAVE_INTSTAT - IO Slave Interrupts: Status
//
//*****************************************************************************
// Transfer complete interrupt, write to register space.
#define AM_REG_IOSLAVE_INTSTAT_XCMPWR_S 9
#define AM_REG_IOSLAVE_INTSTAT_XCMPWR_M 0x00000200
#define AM_REG_IOSLAVE_INTSTAT_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200)
// Transfer complete interrupt, write to FIFO space.
#define AM_REG_IOSLAVE_INTSTAT_XCMPWF_S 8
#define AM_REG_IOSLAVE_INTSTAT_XCMPWF_M 0x00000100
#define AM_REG_IOSLAVE_INTSTAT_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100)
// Transfer complete interrupt, read from register space.
#define AM_REG_IOSLAVE_INTSTAT_XCMPRR_S 7
#define AM_REG_IOSLAVE_INTSTAT_XCMPRR_M 0x00000080
#define AM_REG_IOSLAVE_INTSTAT_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080)
// Transfer complete interrupt, read from FIFO space.
#define AM_REG_IOSLAVE_INTSTAT_XCMPRF_S 6
#define AM_REG_IOSLAVE_INTSTAT_XCMPRF_M 0x00000040
#define AM_REG_IOSLAVE_INTSTAT_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040)
// I2C Interrupt Write interrupt.
#define AM_REG_IOSLAVE_INTSTAT_IOINTW_S 5
#define AM_REG_IOSLAVE_INTSTAT_IOINTW_M 0x00000020
#define AM_REG_IOSLAVE_INTSTAT_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020)
// I2C General Address interrupt.
#define AM_REG_IOSLAVE_INTSTAT_GENAD_S 4
#define AM_REG_IOSLAVE_INTSTAT_GENAD_M 0x00000010
#define AM_REG_IOSLAVE_INTSTAT_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010)
// FIFO Read Error interrupt.
#define AM_REG_IOSLAVE_INTSTAT_FRDERR_S 3
#define AM_REG_IOSLAVE_INTSTAT_FRDERR_M 0x00000008
#define AM_REG_IOSLAVE_INTSTAT_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008)
// FIFO Underflow interrupt.
#define AM_REG_IOSLAVE_INTSTAT_FUNDFL_S 2
#define AM_REG_IOSLAVE_INTSTAT_FUNDFL_M 0x00000004
#define AM_REG_IOSLAVE_INTSTAT_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// FIFO Overflow interrupt.
#define AM_REG_IOSLAVE_INTSTAT_FOVFL_S 1
#define AM_REG_IOSLAVE_INTSTAT_FOVFL_M 0x00000002
#define AM_REG_IOSLAVE_INTSTAT_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002)
// FIFO Size interrupt.
#define AM_REG_IOSLAVE_INTSTAT_FSIZE_S 0
#define AM_REG_IOSLAVE_INTSTAT_FSIZE_M 0x00000001
#define AM_REG_IOSLAVE_INTSTAT_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOSLAVE_INTCLR - IO Slave Interrupts: Clear
//
//*****************************************************************************
// Transfer complete interrupt, write to register space.
#define AM_REG_IOSLAVE_INTCLR_XCMPWR_S 9
#define AM_REG_IOSLAVE_INTCLR_XCMPWR_M 0x00000200
#define AM_REG_IOSLAVE_INTCLR_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200)
// Transfer complete interrupt, write to FIFO space.
#define AM_REG_IOSLAVE_INTCLR_XCMPWF_S 8
#define AM_REG_IOSLAVE_INTCLR_XCMPWF_M 0x00000100
#define AM_REG_IOSLAVE_INTCLR_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100)
// Transfer complete interrupt, read from register space.
#define AM_REG_IOSLAVE_INTCLR_XCMPRR_S 7
#define AM_REG_IOSLAVE_INTCLR_XCMPRR_M 0x00000080
#define AM_REG_IOSLAVE_INTCLR_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080)
// Transfer complete interrupt, read from FIFO space.
#define AM_REG_IOSLAVE_INTCLR_XCMPRF_S 6
#define AM_REG_IOSLAVE_INTCLR_XCMPRF_M 0x00000040
#define AM_REG_IOSLAVE_INTCLR_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040)
// I2C Interrupt Write interrupt.
#define AM_REG_IOSLAVE_INTCLR_IOINTW_S 5
#define AM_REG_IOSLAVE_INTCLR_IOINTW_M 0x00000020
#define AM_REG_IOSLAVE_INTCLR_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020)
// I2C General Address interrupt.
#define AM_REG_IOSLAVE_INTCLR_GENAD_S 4
#define AM_REG_IOSLAVE_INTCLR_GENAD_M 0x00000010
#define AM_REG_IOSLAVE_INTCLR_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010)
// FIFO Read Error interrupt.
#define AM_REG_IOSLAVE_INTCLR_FRDERR_S 3
#define AM_REG_IOSLAVE_INTCLR_FRDERR_M 0x00000008
#define AM_REG_IOSLAVE_INTCLR_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008)
// FIFO Underflow interrupt.
#define AM_REG_IOSLAVE_INTCLR_FUNDFL_S 2
#define AM_REG_IOSLAVE_INTCLR_FUNDFL_M 0x00000004
#define AM_REG_IOSLAVE_INTCLR_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// FIFO Overflow interrupt.
#define AM_REG_IOSLAVE_INTCLR_FOVFL_S 1
#define AM_REG_IOSLAVE_INTCLR_FOVFL_M 0x00000002
#define AM_REG_IOSLAVE_INTCLR_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002)
// FIFO Size interrupt.
#define AM_REG_IOSLAVE_INTCLR_FSIZE_S 0
#define AM_REG_IOSLAVE_INTCLR_FSIZE_M 0x00000001
#define AM_REG_IOSLAVE_INTCLR_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOSLAVE_INTSET - IO Slave Interrupts: Set
//
//*****************************************************************************
// Transfer complete interrupt, write to register space.
#define AM_REG_IOSLAVE_INTSET_XCMPWR_S 9
#define AM_REG_IOSLAVE_INTSET_XCMPWR_M 0x00000200
#define AM_REG_IOSLAVE_INTSET_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200)
// Transfer complete interrupt, write to FIFO space.
#define AM_REG_IOSLAVE_INTSET_XCMPWF_S 8
#define AM_REG_IOSLAVE_INTSET_XCMPWF_M 0x00000100
#define AM_REG_IOSLAVE_INTSET_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100)
// Transfer complete interrupt, read from register space.
#define AM_REG_IOSLAVE_INTSET_XCMPRR_S 7
#define AM_REG_IOSLAVE_INTSET_XCMPRR_M 0x00000080
#define AM_REG_IOSLAVE_INTSET_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080)
// Transfer complete interrupt, read from FIFO space.
#define AM_REG_IOSLAVE_INTSET_XCMPRF_S 6
#define AM_REG_IOSLAVE_INTSET_XCMPRF_M 0x00000040
#define AM_REG_IOSLAVE_INTSET_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040)
// I2C Interrupt Write interrupt.
#define AM_REG_IOSLAVE_INTSET_IOINTW_S 5
#define AM_REG_IOSLAVE_INTSET_IOINTW_M 0x00000020
#define AM_REG_IOSLAVE_INTSET_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020)
// I2C General Address interrupt.
#define AM_REG_IOSLAVE_INTSET_GENAD_S 4
#define AM_REG_IOSLAVE_INTSET_GENAD_M 0x00000010
#define AM_REG_IOSLAVE_INTSET_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010)
// FIFO Read Error interrupt.
#define AM_REG_IOSLAVE_INTSET_FRDERR_S 3
#define AM_REG_IOSLAVE_INTSET_FRDERR_M 0x00000008
#define AM_REG_IOSLAVE_INTSET_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008)
// FIFO Underflow interrupt.
#define AM_REG_IOSLAVE_INTSET_FUNDFL_S 2
#define AM_REG_IOSLAVE_INTSET_FUNDFL_M 0x00000004
#define AM_REG_IOSLAVE_INTSET_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// FIFO Overflow interrupt.
#define AM_REG_IOSLAVE_INTSET_FOVFL_S 1
#define AM_REG_IOSLAVE_INTSET_FOVFL_M 0x00000002
#define AM_REG_IOSLAVE_INTSET_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002)
// FIFO Size interrupt.
#define AM_REG_IOSLAVE_INTSET_FSIZE_S 0
#define AM_REG_IOSLAVE_INTSET_FSIZE_M 0x00000001
#define AM_REG_IOSLAVE_INTSET_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOSLAVE_REGACCINTEN - Register Access Interrupts: Enable
//
//*****************************************************************************
// Register access interrupts.
#define AM_REG_IOSLAVE_REGACCINTEN_REGACC_S 0
#define AM_REG_IOSLAVE_REGACCINTEN_REGACC_M 0xFFFFFFFF
#define AM_REG_IOSLAVE_REGACCINTEN_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// IOSLAVE_REGACCINTSTAT - Register Access Interrupts: Status
//
//*****************************************************************************
// Register access interrupts.
#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_S 0
#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_M 0xFFFFFFFF
#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// IOSLAVE_REGACCINTCLR - Register Access Interrupts: Clear
//
//*****************************************************************************
// Register access interrupts.
#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_S 0
#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_M 0xFFFFFFFF
#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// IOSLAVE_REGACCINTSET - Register Access Interrupts: Set
//
//*****************************************************************************
// Register access interrupts.
#define AM_REG_IOSLAVE_REGACCINTSET_REGACC_S 0
#define AM_REG_IOSLAVE_REGACCINTSET_REGACC_M 0xFFFFFFFF
#define AM_REG_IOSLAVE_REGACCINTSET_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// IOSLAVE_FIFOPTR - Current FIFO Pointer
//
//*****************************************************************************
// The number of bytes currently in the hardware FIFO.
#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S 8
#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M 0x0000FF00
#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Current FIFO pointer.
#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S 0
#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M 0x000000FF
#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// IOSLAVE_FIFOCFG - FIFO Configuration
//
//*****************************************************************************
// Defines the read-only area. The IO Slave read-only area is situated in LRAM
// at (ROBASE*8) to (FIFOOBASE*8-1)
#define AM_REG_IOSLAVE_FIFOCFG_ROBASE_S 24
#define AM_REG_IOSLAVE_FIFOCFG_ROBASE_M 0x3F000000
#define AM_REG_IOSLAVE_FIFOCFG_ROBASE(n) (((uint32_t)(n) << 24) & 0x3F000000)
// These bits hold the maximum FIFO address in 8 byte segments. It is also the
// beginning of the RAM area of the LRAM. Note that no RAM area is configured
// if FIFOMAX is set to 0x1F.
#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_S 8
#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_M 0x00003F00
#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX(n) (((uint32_t)(n) << 8) & 0x00003F00)
// These bits hold the base address of the I/O FIFO in 8 byte segments. The IO
// Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1).
#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_S 0
#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_M 0x0000001F
#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE(n) (((uint32_t)(n) << 0) & 0x0000001F)
//*****************************************************************************
//
// IOSLAVE_FIFOTHR - FIFO Threshold Configuration
//
//*****************************************************************************
// FIFO size interrupt threshold.
#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_S 0
#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_M 0x000000FF
#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// IOSLAVE_FUPD - FIFO Update Status
//
//*****************************************************************************
// This bitfield indicates an IO read is active.
#define AM_REG_IOSLAVE_FUPD_IOREAD_S 1
#define AM_REG_IOSLAVE_FUPD_IOREAD_M 0x00000002
#define AM_REG_IOSLAVE_FUPD_IOREAD(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit indicates that a FIFO update is underway.
#define AM_REG_IOSLAVE_FUPD_FIFOUPD_S 0
#define AM_REG_IOSLAVE_FUPD_FIFOUPD_M 0x00000001
#define AM_REG_IOSLAVE_FUPD_FIFOUPD(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// IOSLAVE_FIFOCTR - Overall FIFO Counter
//
//*****************************************************************************
// Virtual FIFO byte count
#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_S 0
#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_M 0x000003FF
#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR(n) (((uint32_t)(n) << 0) & 0x000003FF)
//*****************************************************************************
//
// IOSLAVE_FIFOINC - Overall FIFO Counter Increment
//
//*****************************************************************************
// Increment the Overall FIFO Counter by this value on a write
#define AM_REG_IOSLAVE_FIFOINC_FIFOINC_S 0
#define AM_REG_IOSLAVE_FIFOINC_FIFOINC_M 0x000003FF
#define AM_REG_IOSLAVE_FIFOINC_FIFOINC(n) (((uint32_t)(n) << 0) & 0x000003FF)
//*****************************************************************************
//
// IOSLAVE_CFG - I/O Slave Configuration
//
//*****************************************************************************
// IOSLAVE interface enable.
#define AM_REG_IOSLAVE_CFG_IFCEN_S 31
#define AM_REG_IOSLAVE_CFG_IFCEN_M 0x80000000
#define AM_REG_IOSLAVE_CFG_IFCEN(n) (((uint32_t)(n) << 31) & 0x80000000)
#define AM_REG_IOSLAVE_CFG_IFCEN_DIS 0x00000000
#define AM_REG_IOSLAVE_CFG_IFCEN_EN 0x80000000
// 7-bit or 10-bit I2C device address.
#define AM_REG_IOSLAVE_CFG_I2CADDR_S 8
#define AM_REG_IOSLAVE_CFG_I2CADDR_M 0x000FFF00
#define AM_REG_IOSLAVE_CFG_I2CADDR(n) (((uint32_t)(n) << 8) & 0x000FFF00)
// This bit holds the cycle to initiate an I/O RAM read.
#define AM_REG_IOSLAVE_CFG_STARTRD_S 4
#define AM_REG_IOSLAVE_CFG_STARTRD_M 0x00000010
#define AM_REG_IOSLAVE_CFG_STARTRD(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_IOSLAVE_CFG_STARTRD_LATE 0x00000000
#define AM_REG_IOSLAVE_CFG_STARTRD_EARLY 0x00000010
// This bit selects the transfer bit ordering.
#define AM_REG_IOSLAVE_CFG_LSB_S 2
#define AM_REG_IOSLAVE_CFG_LSB_M 0x00000004
#define AM_REG_IOSLAVE_CFG_LSB(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_IOSLAVE_CFG_LSB_MSB_FIRST 0x00000000
#define AM_REG_IOSLAVE_CFG_LSB_LSB_FIRST 0x00000004
// This bit selects SPI polarity.
#define AM_REG_IOSLAVE_CFG_SPOL_S 1
#define AM_REG_IOSLAVE_CFG_SPOL_M 0x00000002
#define AM_REG_IOSLAVE_CFG_SPOL(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3 0x00000000
#define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2 0x00000002
// This bit selects the I/O interface.
#define AM_REG_IOSLAVE_CFG_IFCSEL_S 0
#define AM_REG_IOSLAVE_CFG_IFCSEL_M 0x00000001
#define AM_REG_IOSLAVE_CFG_IFCSEL(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_IOSLAVE_CFG_IFCSEL_I2C 0x00000000
#define AM_REG_IOSLAVE_CFG_IFCSEL_SPI 0x00000001
//*****************************************************************************
//
// IOSLAVE_PRENC - I/O Slave Interrupt Priority Encode
//
//*****************************************************************************
// These bits hold the priority encode of the REGACC interrupts.
#define AM_REG_IOSLAVE_PRENC_PRENC_S 0
#define AM_REG_IOSLAVE_PRENC_PRENC_M 0x0000001F
#define AM_REG_IOSLAVE_PRENC_PRENC(n) (((uint32_t)(n) << 0) & 0x0000001F)
//*****************************************************************************
//
// IOSLAVE_IOINTCTL - I/O Interrupt Control
//
//*****************************************************************************
// These bits set the IOINT interrupts when written with a 1.
#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_S 24
#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_M 0xFF000000
#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET(n) (((uint32_t)(n) << 24) & 0xFF000000)
// This bit clears all of the IOINT interrupts when written with a 1.
#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_S 16
#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_M 0x00010000
#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR(n) (((uint32_t)(n) << 16) & 0x00010000)
// These bits read the IOINT interrupts.
#define AM_REG_IOSLAVE_IOINTCTL_IOINT_S 8
#define AM_REG_IOSLAVE_IOINTCTL_IOINT_M 0x0000FF00
#define AM_REG_IOSLAVE_IOINTCTL_IOINT(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// These read-only bits indicate whether the IOINT interrupts are enabled.
#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_S 0
#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_M 0x000000FF
#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// IOSLAVE_GENADD - General Address Data
//
//*****************************************************************************
// The data supplied on the last General Address reference.
#define AM_REG_IOSLAVE_GENADD_GADATA_S 0
#define AM_REG_IOSLAVE_GENADD_GADATA_M 0x000000FF
#define AM_REG_IOSLAVE_GENADD_GADATA(n) (((uint32_t)(n) << 0) & 0x000000FF)
#endif // AM_REG_IOSLAVE_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_itm.h
+662
View File
@@ -0,0 +1,662 @@
//*****************************************************************************
//
// am_reg_itm.h
//! @file
//!
//! @brief Register macros for the ITM module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_ITM_H
#define AM_REG_ITM_H
//*****************************************************************************
//
// ITM
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_ITM_NUM_MODULES 1
#define AM_REG_ITMn(n) \
(REG_ITM_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_ITM_STIM0_O 0xE0000000
#define AM_REG_ITM_STIM1_O 0xE0000004
#define AM_REG_ITM_STIM2_O 0xE0000008
#define AM_REG_ITM_STIM3_O 0xE000000C
#define AM_REG_ITM_STIM4_O 0xE0000010
#define AM_REG_ITM_STIM5_O 0xE0000014
#define AM_REG_ITM_STIM6_O 0xE0000018
#define AM_REG_ITM_STIM7_O 0xE000001C
#define AM_REG_ITM_STIM8_O 0xE0000020
#define AM_REG_ITM_STIM9_O 0xE0000024
#define AM_REG_ITM_STIM10_O 0xE0000028
#define AM_REG_ITM_STIM11_O 0xE000002C
#define AM_REG_ITM_STIM12_O 0xE0000030
#define AM_REG_ITM_STIM13_O 0xE0000034
#define AM_REG_ITM_STIM14_O 0xE0000038
#define AM_REG_ITM_STIM15_O 0xE000003C
#define AM_REG_ITM_STIM16_O 0xE0000040
#define AM_REG_ITM_STIM17_O 0xE0000044
#define AM_REG_ITM_STIM18_O 0xE0000048
#define AM_REG_ITM_STIM19_O 0xE000004C
#define AM_REG_ITM_STIM20_O 0xE0000050
#define AM_REG_ITM_STIM21_O 0xE0000054
#define AM_REG_ITM_STIM22_O 0xE0000058
#define AM_REG_ITM_STIM23_O 0xE000005C
#define AM_REG_ITM_STIM24_O 0xE0000060
#define AM_REG_ITM_STIM25_O 0xE0000064
#define AM_REG_ITM_STIM26_O 0xE0000068
#define AM_REG_ITM_STIM27_O 0xE000006C
#define AM_REG_ITM_STIM28_O 0xE0000070
#define AM_REG_ITM_STIM29_O 0xE0000074
#define AM_REG_ITM_STIM30_O 0xE0000078
#define AM_REG_ITM_STIM31_O 0xE000007C
#define AM_REG_ITM_TER_O 0xE0000E00
#define AM_REG_ITM_TPR_O 0xE0000E40
#define AM_REG_ITM_TCR_O 0xE0000E80
#define AM_REG_ITM_LOCKSREG_O 0xE0000FB4
#define AM_REG_ITM_PID4_O 0xE0000FD0
#define AM_REG_ITM_PID5_O 0xE0000FD4
#define AM_REG_ITM_PID6_O 0xE0000FD8
#define AM_REG_ITM_PID7_O 0xE0000FDC
#define AM_REG_ITM_PID0_O 0xE0000FE0
#define AM_REG_ITM_PID1_O 0xE0000FE4
#define AM_REG_ITM_PID2_O 0xE0000FE8
#define AM_REG_ITM_PID3_O 0xE0000FEC
#define AM_REG_ITM_CID0_O 0xE0000FF0
#define AM_REG_ITM_CID1_O 0xE0000FF4
#define AM_REG_ITM_CID2_O 0xE0000FF8
#define AM_REG_ITM_CID3_O 0xE0000FFC
#define AM_REG_ITM_LOCKAREG_O 0xE0000FB0
//*****************************************************************************
//
// Key values.
//
//*****************************************************************************
#define AM_REG_ITM_LOCKAREG_KEYVAL 0xC5ACCE55
//*****************************************************************************
//
// ITM_STIM0 - Stimulus Port Register 0
//
//*****************************************************************************
// Stimulus Port Register 0.
#define AM_REG_ITM_STIM0_STIM0_S 0
#define AM_REG_ITM_STIM0_STIM0_M 0xFFFFFFFF
#define AM_REG_ITM_STIM0_STIM0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM1 - Stimulus Port Register 1
//
//*****************************************************************************
// Stimulus Port Register 1.
#define AM_REG_ITM_STIM1_STIM1_S 0
#define AM_REG_ITM_STIM1_STIM1_M 0xFFFFFFFF
#define AM_REG_ITM_STIM1_STIM1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM2 - Stimulus Port Register 2
//
//*****************************************************************************
// Stimulus Port Register 2.
#define AM_REG_ITM_STIM2_STIM2_S 0
#define AM_REG_ITM_STIM2_STIM2_M 0xFFFFFFFF
#define AM_REG_ITM_STIM2_STIM2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM3 - Stimulus Port Register 3
//
//*****************************************************************************
// Stimulus Port Register 3.
#define AM_REG_ITM_STIM3_STIM3_S 0
#define AM_REG_ITM_STIM3_STIM3_M 0xFFFFFFFF
#define AM_REG_ITM_STIM3_STIM3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM4 - Stimulus Port Register 4
//
//*****************************************************************************
// Stimulus Port Register 4.
#define AM_REG_ITM_STIM4_STIM4_S 0
#define AM_REG_ITM_STIM4_STIM4_M 0xFFFFFFFF
#define AM_REG_ITM_STIM4_STIM4(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM5 - Stimulus Port Register 5
//
//*****************************************************************************
// Stimulus Port Register 5.
#define AM_REG_ITM_STIM5_STIM5_S 0
#define AM_REG_ITM_STIM5_STIM5_M 0xFFFFFFFF
#define AM_REG_ITM_STIM5_STIM5(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM6 - Stimulus Port Register 6
//
//*****************************************************************************
// Stimulus Port Register 6.
#define AM_REG_ITM_STIM6_STIM6_S 0
#define AM_REG_ITM_STIM6_STIM6_M 0xFFFFFFFF
#define AM_REG_ITM_STIM6_STIM6(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM7 - Stimulus Port Register 7
//
//*****************************************************************************
// Stimulus Port Register 7.
#define AM_REG_ITM_STIM7_STIM7_S 0
#define AM_REG_ITM_STIM7_STIM7_M 0xFFFFFFFF
#define AM_REG_ITM_STIM7_STIM7(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM8 - Stimulus Port Register 8
//
//*****************************************************************************
// Stimulus Port Register 8.
#define AM_REG_ITM_STIM8_STIM8_S 0
#define AM_REG_ITM_STIM8_STIM8_M 0xFFFFFFFF
#define AM_REG_ITM_STIM8_STIM8(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM9 - Stimulus Port Register 9
//
//*****************************************************************************
// Stimulus Port Register 9.
#define AM_REG_ITM_STIM9_STIM9_S 0
#define AM_REG_ITM_STIM9_STIM9_M 0xFFFFFFFF
#define AM_REG_ITM_STIM9_STIM9(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM10 - Stimulus Port Register 10
//
//*****************************************************************************
// Stimulus Port Register 10.
#define AM_REG_ITM_STIM10_STIM10_S 0
#define AM_REG_ITM_STIM10_STIM10_M 0xFFFFFFFF
#define AM_REG_ITM_STIM10_STIM10(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM11 - Stimulus Port Register 11
//
//*****************************************************************************
// Stimulus Port Register 11.
#define AM_REG_ITM_STIM11_STIM11_S 0
#define AM_REG_ITM_STIM11_STIM11_M 0xFFFFFFFF
#define AM_REG_ITM_STIM11_STIM11(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM12 - Stimulus Port Register 12
//
//*****************************************************************************
// Stimulus Port Register 12.
#define AM_REG_ITM_STIM12_STIM12_S 0
#define AM_REG_ITM_STIM12_STIM12_M 0xFFFFFFFF
#define AM_REG_ITM_STIM12_STIM12(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM13 - Stimulus Port Register 13
//
//*****************************************************************************
// Stimulus Port Register 13.
#define AM_REG_ITM_STIM13_STIM13_S 0
#define AM_REG_ITM_STIM13_STIM13_M 0xFFFFFFFF
#define AM_REG_ITM_STIM13_STIM13(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM14 - Stimulus Port Register 14
//
//*****************************************************************************
// Stimulus Port Register 14.
#define AM_REG_ITM_STIM14_STIM14_S 0
#define AM_REG_ITM_STIM14_STIM14_M 0xFFFFFFFF
#define AM_REG_ITM_STIM14_STIM14(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM15 - Stimulus Port Register 15
//
//*****************************************************************************
// Stimulus Port Register 15.
#define AM_REG_ITM_STIM15_STIM15_S 0
#define AM_REG_ITM_STIM15_STIM15_M 0xFFFFFFFF
#define AM_REG_ITM_STIM15_STIM15(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM16 - Stimulus Port Register 16
//
//*****************************************************************************
// Stimulus Port Register 16.
#define AM_REG_ITM_STIM16_STIM16_S 0
#define AM_REG_ITM_STIM16_STIM16_M 0xFFFFFFFF
#define AM_REG_ITM_STIM16_STIM16(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM17 - Stimulus Port Register 17
//
//*****************************************************************************
// Stimulus Port Register 17.
#define AM_REG_ITM_STIM17_STIM17_S 0
#define AM_REG_ITM_STIM17_STIM17_M 0xFFFFFFFF
#define AM_REG_ITM_STIM17_STIM17(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM18 - Stimulus Port Register 18
//
//*****************************************************************************
// Stimulus Port Register 18.
#define AM_REG_ITM_STIM18_STIM18_S 0
#define AM_REG_ITM_STIM18_STIM18_M 0xFFFFFFFF
#define AM_REG_ITM_STIM18_STIM18(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM19 - Stimulus Port Register 19
//
//*****************************************************************************
// Stimulus Port Register 19.
#define AM_REG_ITM_STIM19_STIM19_S 0
#define AM_REG_ITM_STIM19_STIM19_M 0xFFFFFFFF
#define AM_REG_ITM_STIM19_STIM19(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM20 - Stimulus Port Register 20
//
//*****************************************************************************
// Stimulus Port Register 20.
#define AM_REG_ITM_STIM20_STIM20_S 0
#define AM_REG_ITM_STIM20_STIM20_M 0xFFFFFFFF
#define AM_REG_ITM_STIM20_STIM20(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM21 - Stimulus Port Register 21
//
//*****************************************************************************
// Stimulus Port Register 21.
#define AM_REG_ITM_STIM21_STIM21_S 0
#define AM_REG_ITM_STIM21_STIM21_M 0xFFFFFFFF
#define AM_REG_ITM_STIM21_STIM21(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM22 - Stimulus Port Register 22
//
//*****************************************************************************
// Stimulus Port Register 22.
#define AM_REG_ITM_STIM22_STIM22_S 0
#define AM_REG_ITM_STIM22_STIM22_M 0xFFFFFFFF
#define AM_REG_ITM_STIM22_STIM22(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM23 - Stimulus Port Register 23
//
//*****************************************************************************
// Stimulus Port Register 23.
#define AM_REG_ITM_STIM23_STIM23_S 0
#define AM_REG_ITM_STIM23_STIM23_M 0xFFFFFFFF
#define AM_REG_ITM_STIM23_STIM23(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM24 - Stimulus Port Register 24
//
//*****************************************************************************
// Stimulus Port Register 24.
#define AM_REG_ITM_STIM24_STIM24_S 0
#define AM_REG_ITM_STIM24_STIM24_M 0xFFFFFFFF
#define AM_REG_ITM_STIM24_STIM24(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM25 - Stimulus Port Register 25
//
//*****************************************************************************
// Stimulus Port Register 25.
#define AM_REG_ITM_STIM25_STIM25_S 0
#define AM_REG_ITM_STIM25_STIM25_M 0xFFFFFFFF
#define AM_REG_ITM_STIM25_STIM25(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM26 - Stimulus Port Register 26
//
//*****************************************************************************
// Stimulus Port Register 26.
#define AM_REG_ITM_STIM26_STIM26_S 0
#define AM_REG_ITM_STIM26_STIM26_M 0xFFFFFFFF
#define AM_REG_ITM_STIM26_STIM26(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM27 - Stimulus Port Register 27
//
//*****************************************************************************
// Stimulus Port Register 27.
#define AM_REG_ITM_STIM27_STIM27_S 0
#define AM_REG_ITM_STIM27_STIM27_M 0xFFFFFFFF
#define AM_REG_ITM_STIM27_STIM27(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM28 - Stimulus Port Register 28
//
//*****************************************************************************
// Stimulus Port Register 28.
#define AM_REG_ITM_STIM28_STIM28_S 0
#define AM_REG_ITM_STIM28_STIM28_M 0xFFFFFFFF
#define AM_REG_ITM_STIM28_STIM28(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM29 - Stimulus Port Register 29
//
//*****************************************************************************
// Stimulus Port Register 29.
#define AM_REG_ITM_STIM29_STIM29_S 0
#define AM_REG_ITM_STIM29_STIM29_M 0xFFFFFFFF
#define AM_REG_ITM_STIM29_STIM29(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM30 - Stimulus Port Register 30
//
//*****************************************************************************
// Stimulus Port Register 30.
#define AM_REG_ITM_STIM30_STIM30_S 0
#define AM_REG_ITM_STIM30_STIM30_M 0xFFFFFFFF
#define AM_REG_ITM_STIM30_STIM30(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_STIM31 - Stimulus Port Register 31
//
//*****************************************************************************
// Stimulus Port Register 31.
#define AM_REG_ITM_STIM31_STIM31_S 0
#define AM_REG_ITM_STIM31_STIM31_M 0xFFFFFFFF
#define AM_REG_ITM_STIM31_STIM31(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_TER - Trace Enable Register.
//
//*****************************************************************************
// Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port..
#define AM_REG_ITM_TER_STIMENA_S 0
#define AM_REG_ITM_TER_STIMENA_M 0xFFFFFFFF
#define AM_REG_ITM_TER_STIMENA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_TPR - Trace Privilege Register.
//
//*****************************************************************************
// Bit mask to enable tracing on ITM stimulus ports. bit[0] = stimulus
// ports[7:0], bit[1] = stimulus ports[15:8], bit[2] = stimulus ports[23:16],
// bit[3] = stimulus ports[31:24].
#define AM_REG_ITM_TPR_PRIVMASK_S 0
#define AM_REG_ITM_TPR_PRIVMASK_M 0x0000000F
#define AM_REG_ITM_TPR_PRIVMASK(n) (((uint32_t)(n) << 0) & 0x0000000F)
//*****************************************************************************
//
// ITM_TCR - Trace Control Register.
//
//*****************************************************************************
// Set when ITM events present and being drained.
#define AM_REG_ITM_TCR_BUSY_S 23
#define AM_REG_ITM_TCR_BUSY_M 0x00800000
#define AM_REG_ITM_TCR_BUSY(n) (((uint32_t)(n) << 23) & 0x00800000)
// ATB ID for CoreSight system.
#define AM_REG_ITM_TCR_ATB_ID_S 16
#define AM_REG_ITM_TCR_ATB_ID_M 0x007F0000
#define AM_REG_ITM_TCR_ATB_ID(n) (((uint32_t)(n) << 16) & 0x007F0000)
// Global Timestamp Frequency.
#define AM_REG_ITM_TCR_TS_FREQ_S 10
#define AM_REG_ITM_TCR_TS_FREQ_M 0x00000C00
#define AM_REG_ITM_TCR_TS_FREQ(n) (((uint32_t)(n) << 10) & 0x00000C00)
// Timestamp prescaler: 0b00 = no prescaling 0b01 = divide by 4 0b10 = divide by
// 16 0b11 = divide by 64.
#define AM_REG_ITM_TCR_TS_PRESCALE_S 8
#define AM_REG_ITM_TCR_TS_PRESCALE_M 0x00000300
#define AM_REG_ITM_TCR_TS_PRESCALE(n) (((uint32_t)(n) << 8) & 0x00000300)
// Enable SWV (Serial Wire Viewer) behavior - count on TPIUEMIT and TPIUBAUD:
// Aka SWOENA Enables asynchronous clocking of the timestamp counter.
#define AM_REG_ITM_TCR_SWV_ENABLE_S 4
#define AM_REG_ITM_TCR_SWV_ENABLE_M 0x00000010
#define AM_REG_ITM_TCR_SWV_ENABLE(n) (((uint32_t)(n) << 4) & 0x00000010)
// Enables the DWT stimulus.
#define AM_REG_ITM_TCR_DWT_ENABLE_S 3
#define AM_REG_ITM_TCR_DWT_ENABLE_M 0x00000008
#define AM_REG_ITM_TCR_DWT_ENABLE(n) (((uint32_t)(n) << 3) & 0x00000008)
// Enables sync packets for TPIU.
#define AM_REG_ITM_TCR_SYNC_ENABLE_S 2
#define AM_REG_ITM_TCR_SYNC_ENABLE_M 0x00000004
#define AM_REG_ITM_TCR_SYNC_ENABLE(n) (((uint32_t)(n) << 2) & 0x00000004)
// Enables differential timestamps. Differential timestamps are emitted when a
// packet is written to the FIFO with a non-zero timestamp counter, and when the
// timestamp counter overflows. Timestamps are emitted during idle times after a
// fixed number of cycles. This provides a time reference for packets and inter-
// packet gaps.
#define AM_REG_ITM_TCR_TS_ENABLE_S 1
#define AM_REG_ITM_TCR_TS_ENABLE_M 0x00000002
#define AM_REG_ITM_TCR_TS_ENABLE(n) (((uint32_t)(n) << 1) & 0x00000002)
// Enable ITM. This is the master enable, and must be set before ITM Stimulus
// and Trace Enable registers can be written.
#define AM_REG_ITM_TCR_ITM_ENABLE_S 0
#define AM_REG_ITM_TCR_ITM_ENABLE_M 0x00000001
#define AM_REG_ITM_TCR_ITM_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// ITM_LOCKSREG - Lock Status Register
//
//*****************************************************************************
// You cannot implement 8-bit lock accesses.
#define AM_REG_ITM_LOCKSREG_BYTEACC_S 2
#define AM_REG_ITM_LOCKSREG_BYTEACC_M 0x00000004
#define AM_REG_ITM_LOCKSREG_BYTEACC(n) (((uint32_t)(n) << 2) & 0x00000004)
// Write access to component is blocked. All writes are ignored, reads are
// permitted.
#define AM_REG_ITM_LOCKSREG_ACCESS_S 1
#define AM_REG_ITM_LOCKSREG_ACCESS_M 0x00000002
#define AM_REG_ITM_LOCKSREG_ACCESS(n) (((uint32_t)(n) << 1) & 0x00000002)
// Indicates that a lock mechanism exists for this component.
#define AM_REG_ITM_LOCKSREG_PRESENT_S 0
#define AM_REG_ITM_LOCKSREG_PRESENT_M 0x00000001
#define AM_REG_ITM_LOCKSREG_PRESENT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// ITM_PID4 - Peripheral Identification Register 4
//
//*****************************************************************************
// Peripheral Identification 4.
#define AM_REG_ITM_PID4_PID4_S 0
#define AM_REG_ITM_PID4_PID4_M 0xFFFFFFFF
#define AM_REG_ITM_PID4_PID4(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_PID5 - Peripheral Identification Register 5
//
//*****************************************************************************
// Peripheral Identification 5.
#define AM_REG_ITM_PID5_PID5_S 0
#define AM_REG_ITM_PID5_PID5_M 0xFFFFFFFF
#define AM_REG_ITM_PID5_PID5(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_PID6 - Peripheral Identification Register 6
//
//*****************************************************************************
// Peripheral Identification 6.
#define AM_REG_ITM_PID6_PID6_S 0
#define AM_REG_ITM_PID6_PID6_M 0xFFFFFFFF
#define AM_REG_ITM_PID6_PID6(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_PID7 - Peripheral Identification Register 7
//
//*****************************************************************************
// Peripheral Identification 7.
#define AM_REG_ITM_PID7_PID7_S 0
#define AM_REG_ITM_PID7_PID7_M 0xFFFFFFFF
#define AM_REG_ITM_PID7_PID7(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_PID0 - Peripheral Identification Register 0
//
//*****************************************************************************
// Peripheral Identification 0.
#define AM_REG_ITM_PID0_PID0_S 0
#define AM_REG_ITM_PID0_PID0_M 0xFFFFFFFF
#define AM_REG_ITM_PID0_PID0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_PID1 - Peripheral Identification Register 1
//
//*****************************************************************************
// Peripheral Identification 1.
#define AM_REG_ITM_PID1_PID1_S 0
#define AM_REG_ITM_PID1_PID1_M 0xFFFFFFFF
#define AM_REG_ITM_PID1_PID1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_PID2 - Peripheral Identification Register 2
//
//*****************************************************************************
// Peripheral Identification 2.
#define AM_REG_ITM_PID2_PID2_S 0
#define AM_REG_ITM_PID2_PID2_M 0xFFFFFFFF
#define AM_REG_ITM_PID2_PID2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_PID3 - Peripheral Identification Register 3
//
//*****************************************************************************
// Peripheral Identification 3.
#define AM_REG_ITM_PID3_PID3_S 0
#define AM_REG_ITM_PID3_PID3_M 0xFFFFFFFF
#define AM_REG_ITM_PID3_PID3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_CID0 - Component Identification Register 1
//
//*****************************************************************************
// Component Identification 1.
#define AM_REG_ITM_CID0_CID0_S 0
#define AM_REG_ITM_CID0_CID0_M 0xFFFFFFFF
#define AM_REG_ITM_CID0_CID0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_CID1 - Component Identification Register 1
//
//*****************************************************************************
// Component Identification 1.
#define AM_REG_ITM_CID1_CID1_S 0
#define AM_REG_ITM_CID1_CID1_M 0xFFFFFFFF
#define AM_REG_ITM_CID1_CID1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_CID2 - Component Identification Register 2
//
//*****************************************************************************
// Component Identification 2.
#define AM_REG_ITM_CID2_CID2_S 0
#define AM_REG_ITM_CID2_CID2_M 0xFFFFFFFF
#define AM_REG_ITM_CID2_CID2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// ITM_CID3 - Component Identification Register 3
//
//*****************************************************************************
// Component Identification 3.
#define AM_REG_ITM_CID3_CID3_S 0
#define AM_REG_ITM_CID3_CID3_M 0xFFFFFFFF
#define AM_REG_ITM_CID3_CID3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#endif // AM_REG_ITM_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_jedec.h
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//*****************************************************************************
//
// am_reg_jedec.h
//! @file
//!
//! @brief Register macros for the JEDEC module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_JEDEC_H
#define AM_REG_JEDEC_H
//*****************************************************************************
//
// JEDEC
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_JEDEC_NUM_MODULES 1
#define AM_REG_JEDECn(n) \
(REG_JEDEC_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_JEDEC_PID4_O 0xF0000FD0
#define AM_REG_JEDEC_PID5_O 0xF0000FD4
#define AM_REG_JEDEC_PID6_O 0xF0000FD8
#define AM_REG_JEDEC_PID7_O 0xF0000FDC
#define AM_REG_JEDEC_PID0_O 0xF0000FE0
#define AM_REG_JEDEC_PID1_O 0xF0000FE4
#define AM_REG_JEDEC_PID2_O 0xF0000FE8
#define AM_REG_JEDEC_PID3_O 0xF0000FEC
#define AM_REG_JEDEC_CID0_O 0xF0000FF0
#define AM_REG_JEDEC_CID1_O 0xF0000FF4
#define AM_REG_JEDEC_CID2_O 0xF0000FF8
#define AM_REG_JEDEC_CID3_O 0xF0000FFC
//*****************************************************************************
//
// JEDEC_PID4 - JEP Continuation Register
//
//*****************************************************************************
// Contains the JEP Continuation bits.
#define AM_REG_JEDEC_PID4_JEPCONT_S 0
#define AM_REG_JEDEC_PID4_JEPCONT_M 0x0000000F
#define AM_REG_JEDEC_PID4_JEPCONT(n) (((uint32_t)(n) << 0) & 0x0000000F)
//*****************************************************************************
//
// JEDEC_PID5 - JEP reserved Register
//
//*****************************************************************************
// Contains the value of 0x00000000.
#define AM_REG_JEDEC_PID5_VALUE_S 0
#define AM_REG_JEDEC_PID5_VALUE_M 0xFFFFFFFF
#define AM_REG_JEDEC_PID5_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// JEDEC_PID6 - JEP reserved Register
//
//*****************************************************************************
// Contains the value of 0x00000000.
#define AM_REG_JEDEC_PID6_VALUE_S 0
#define AM_REG_JEDEC_PID6_VALUE_M 0xFFFFFFFF
#define AM_REG_JEDEC_PID6_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// JEDEC_PID7 - JEP reserved Register
//
//*****************************************************************************
// Contains the value of 0x00000000.
#define AM_REG_JEDEC_PID7_VALUE_S 0
#define AM_REG_JEDEC_PID7_VALUE_M 0xFFFFFFFF
#define AM_REG_JEDEC_PID7_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// JEDEC_PID0 - Ambiq Partnum low byte
//
//*****************************************************************************
// Contains the low 8 bits of the Ambiq Micro device part number.
#define AM_REG_JEDEC_PID0_PNL8_S 0
#define AM_REG_JEDEC_PID0_PNL8_M 0x000000FF
#define AM_REG_JEDEC_PID0_PNL8(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble.
//
//*****************************************************************************
// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID
// is therefore 0x9B.
#define AM_REG_JEDEC_PID1_JEPIDL_S 4
#define AM_REG_JEDEC_PID1_JEPIDL_M 0x000000F0
#define AM_REG_JEDEC_PID1_JEPIDL(n) (((uint32_t)(n) << 4) & 0x000000F0)
// Contains the high 4 bits of the Ambiq Micro device part number.
#define AM_REG_JEDEC_PID1_PNH4_S 0
#define AM_REG_JEDEC_PID1_PNH4_M 0x0000000F
#define AM_REG_JEDEC_PID1_PNH4(n) (((uint32_t)(n) << 0) & 0x0000000F)
//*****************************************************************************
//
// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble
//
//*****************************************************************************
// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also
// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
// chip.
#define AM_REG_JEDEC_PID2_CHIPREVH4_S 4
#define AM_REG_JEDEC_PID2_CHIPREVH4_M 0x000000F0
#define AM_REG_JEDEC_PID2_CHIPREVH4(n) (((uint32_t)(n) << 4) & 0x000000F0)
// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this
// field is hard-coded to 1. The full JEPID is therefore 0x9B.
#define AM_REG_JEDEC_PID2_JEPIDH_S 0
#define AM_REG_JEDEC_PID2_JEPIDH_M 0x0000000F
#define AM_REG_JEDEC_PID2_JEPIDH(n) (((uint32_t)(n) << 0) & 0x0000000F)
//*****************************************************************************
//
// JEDEC_PID3 - Ambiq chip revision high-nibble.
//
//*****************************************************************************
// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also
// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
// chip.
#define AM_REG_JEDEC_PID3_CHIPREVL4_S 4
#define AM_REG_JEDEC_PID3_CHIPREVL4_M 0x000000F0
#define AM_REG_JEDEC_PID3_CHIPREVL4(n) (((uint32_t)(n) << 4) & 0x000000F0)
// This field is hard-coded to 0x0.
#define AM_REG_JEDEC_PID3_ZERO_S 0
#define AM_REG_JEDEC_PID3_ZERO_M 0x0000000F
#define AM_REG_JEDEC_PID3_ZERO(n) (((uint32_t)(n) << 0) & 0x0000000F)
//*****************************************************************************
//
// JEDEC_CID0 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID0.
#define AM_REG_JEDEC_CID0_CID_S 0
#define AM_REG_JEDEC_CID0_CID_M 0x000000FF
#define AM_REG_JEDEC_CID0_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// JEDEC_CID1 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID1.
#define AM_REG_JEDEC_CID1_CID_S 0
#define AM_REG_JEDEC_CID1_CID_M 0x000000FF
#define AM_REG_JEDEC_CID1_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// JEDEC_CID2 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID2.
#define AM_REG_JEDEC_CID2_CID_S 0
#define AM_REG_JEDEC_CID2_CID_M 0x000000FF
#define AM_REG_JEDEC_CID2_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// JEDEC_CID3 - Coresight ROM Table.
//
//*****************************************************************************
// Coresight ROM Table, CID3.
#define AM_REG_JEDEC_CID3_CID_S 0
#define AM_REG_JEDEC_CID3_CID_M 0x000000FF
#define AM_REG_JEDEC_CID3_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
#endif // AM_REG_JEDEC_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_macros.h
+370
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//*****************************************************************************
//
// am_reg_macros.h
//! @file
//!
//! @brief Helper macros for using hardware registers.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_MACROS_H
#define AM_REG_MACROS_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Include the inline assembly macros.
//
//*****************************************************************************
#include "am_reg_macros_asm.h"
//*****************************************************************************
//
// High-level Helper Macros.
//
// Usage:
//
// For direct 32-bit access to a register, use AM_REGVAL:
// AM_REGVAL(REG_VCOMP_BASEADDR + AM_VCOMP_VCMPCFG_O) |= 0xDEADBEEF;
//
// The AM_REG macro can also be used as a shorthand version of AM_REGVAL:
// AM_REG(VCOMP, VCMPCFG) |= 0xDEADBEEF;
//
// The AM_REGn macro is used for accessing registers of peripherals with
// multiple instances, such as IOMSTR.
// AM_REGn(IOMSTR, 1, CLKCFG) |= 0xDEADBEEF;
//
// To write to a specific bitfield within a register, use AM_BFW or AM_BFWn:
// AM_BFW(CTIMER, 0, CTCTRL0, TMRB0FN, 0x3);
//
// To read a field, use AM_BFR or AM_BFRn:
// ui32Timer0Fn = AM_BFR((CTIMER, 0, CTCTRL0, TMRB0FN);
//
// Note:
//
// AM_REGn, AM_BFW and AM_BFR are concatenation-based, which means that
// standalone macro definitions should not be used for the 'module', 'reg', and
// 'field' arguments.All macro names in the various peripheral header files are
// written in one of the following forms:
// - AM_REG_##module_reg_O
// - AM_REG_##module_reg_field_S
// - AM_REG_##module_reg_field_M
//
// The "module", "reg" and "field" fragments may be used as valid arguments to
// the AM_REGn, AM_BFW, and AM_BFR macros, all of which are able to perform the
// necessary concatenation operations to reconstruct the full macros and look
// up the appropriate base address for the instance number given. For
// peripherals with only one instance, use instance number 0.
//
// The AM_REGVAL macro does not perform any concatenation operations, so the
// complete macro name (including any suffix) must be specified.
//
//*****************************************************************************
#define AM_REGVAL(x) (*((volatile uint32_t *)(x)))
#define AM_REGVAL_FLOAT(x) (*((volatile float *)(x)))
//*****************************************************************************
//
// Register access macros for single-instance modules
// AM_REG - Write a register of a module.
// AM_BFW - Write a value to a bitfield of a register.
// AM_BFWe - Use a defined enum value to write a value to a register bitfield.
// AM_BFR - Read a bitfield value from a register.
// AM_BFM - Read and mask a bitfield from a register, but leave the value in
// its bit position. Useful for comparing with enums.
//
// AM_BFV - Move a value to a bitfield. This macro is used for creating a
// value, it does not modify any register.
// AM_BFX - Extract the value of a bitfield from a 32-bit value, such as that
// read from a register. Does not read or modify any register.
//
//*****************************************************************************
#define AM_REG(module, reg) \
/*AM_REGn(m, 0, r) */ \
(*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O)))
#define AM_BFW(module, reg, field, value) \
/* AM_BFWn(m,0,r,f,v) */ \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \
AM_REG_##module##_##reg##_##field##_M) )
#define AM_BFWe(module, reg, field, enumval) \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(AM_REG_##module##_##reg##_##field##_##enumval))
#define AM_BFR(module, reg, field) \
/* AM_BFRn(m,0,r,f) */ \
( ( (uint32_t) \
(*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \
AM_REG_##module##_##reg##_##field##_M ) >> \
AM_REG_##module##_##reg##_##field##_S )
#define AM_BFM(module, reg, field) \
/* AM_BFMn(m,0,r,f) */ \
( (*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \
AM_REG_##module##_##reg##_##field##_M)
#define AM_BFV(module, reg, field, value) \
(((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \
AM_REG_##module##_##reg##_##field##_M)
#define AM_BFX(module, reg, field, value) \
(((uint32_t)(value) & AM_REG_##module##_##reg##_##field##_M) >> \
AM_REG_##module##_##reg##_##field##_S)
//*****************************************************************************
//
// Register access macros for multi-instance modules
// AM_REGADDRn - Calc the register address inside a multiple instance module.
// AM_REGn - Write a register of a multiple instance module.
// AM_BFWn - Write a value to a bitfield of a register in a multiple instance.
// AM_BFWen - Use a defined enum value to write a value to a bitfield of a
// register in a multiple instance.
// AM_BFRn - Read a bitfield value from a register in a multiple instance.
// AM_BFMn - Read and mask a bitfield, but leave the value in its bit position.
// (Useful for comparing with enums.)
//
//*****************************************************************************
#define AM_REGADDRn(module, instance, reg) \
(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O)
#define AM_REGn(module, instance, reg) \
(*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O)))
#define AM_BFWn(module, instance, reg, field, value) \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \
AM_REG_##module##_##reg##_##field##_M) )
#define AM_BFWen(module, instance, reg, field, enumval) \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(AM_REG_##module##_##reg##_##field##_##enumval))
#define AM_BFRn(module, instance, reg, field) \
( ( (uint32_t) \
(*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \
AM_REG_##module##_##reg##_##field##_M ) >> \
AM_REG_##module##_##reg##_##field##_S )
#define AM_BFMn(module, instance, reg, field) \
( (*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \
AM_REG_##module##_##reg##_##field##_M)
//*****************************************************************************
//
// "Atomic" register access macros - use when a read-modify-write is required.
//
// These macros will be slower than the normal macros, but they will also
// guarantee threadsafe hardware access.
//
// These macros require a nesting-friendly critical section implementation. If
// you are using the HAL, you can use the default definitions below. If not,
// you will need to supply your own.
//
// Atomic register access macros usage:
// AM_REGa - Write a register of a single instance module. Provide operator
// (&,|,etc) to perform that operation on the reg using value, or
// no operator to simply write the value atomically.
// AM_REGa_SET - Set bits in a single instance module according to the mask.
// AM_REGa_CLR - Clear bits in a single instance module according to the mask.
// AM_REGan - Multiple module version of AM_REGa.
// AM_REGan_SET - Multiple instance version of AM_REGa_SET.
// AM_REGan_CLR - Multiple instance version of AM_REGa_CLR.
// AM_BFWa - Write a value to a register bitfield.
// AM_BFWae - Use a defined enum value to write a value to a bitfield.
// AM_BFWan - Write a value to a bitfield of a register in a multiple instance.
// AM_BFWaen - Use a defined enum value to write a value to a bitfield of a
// register in a multiple instance.
//
//*****************************************************************************
#define AM_REGan(module, instance, reg, operator, value) \
AM_CRITICAL_BEGIN \
/* AM_REGn(m, i, r) <op>= (value) */ \
(*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) operator##= (value); \
AM_CRITICAL_END
#define AM_REGan_SET(module, instance, reg, mask) \
AM_CRITICAL_BEGIN \
(*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) |= (mask); \
AM_CRITICAL_END
#define AM_REGan_CLR(module, instance, reg, mask) \
AM_CRITICAL_BEGIN \
(*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) &= (~mask); \
AM_CRITICAL_END
#define AM_REGa(module, reg, operator, value) \
/* AM_REGan(m,0,r,op,v) */ \
AM_CRITICAL_BEGIN \
(*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) operator##= (value); \
AM_CRITICAL_END
#define AM_REGa_CLR(module, reg, mask) \
/* AM_REGan_CLR(m, 0, r, m) */ \
AM_CRITICAL_BEGIN \
(*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) &= (~mask); \
AM_CRITICAL_END
#define AM_REGa_SET(module, reg, mask) \
/* AM_REGan_SET(m, 0, r, m) */ \
AM_CRITICAL_BEGIN \
(*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) |= (mask); \
AM_CRITICAL_END
#define AM_BFWa(module, reg, field, value) \
AM_CRITICAL_BEGIN \
/* AM_BFW(module, reg, field, value); */ \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \
AM_REG_##module##_##reg##_##field##_M) ); \
AM_CRITICAL_END
#define AM_BFWae(module, reg, field, enumval) \
AM_CRITICAL_BEGIN \
/* AM_BFWe(module, reg, field, enumval); */ \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(AM_REG_##module##_##reg##_##field##_##enumval)); \
AM_CRITICAL_END
#define AM_BFWan(module, instance, reg, field, value) \
AM_CRITICAL_BEGIN \
/* AM_BFWn(module, instance, reg, field, enumval); */ \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \
AM_REG_##module##_##reg##_##field##_M) ); \
AM_CRITICAL_END
#define AM_BFWaen(module, instance, reg, field, enumval) \
AM_CRITICAL_BEGIN \
/* AM_BFWen(module, instance reg, field, enumval); */ \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \
((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \
(~AM_REG_##module##_##reg##_##field##_M)) | \
(AM_REG_##module##_##reg##_##field##_##enumval)); \
AM_CRITICAL_END
//*****************************************************************************
//
// Other helper Macros.
//
// Note: These macros make use of macro concatenation, so the '_S' or '_M'
// suffix on a register bitfield macro should not be supplied by the user.
// The macro will apply each suffix as needed.
//
//*****************************************************************************
//
// AM_ENUMX extracts a register bitfield enumeration to the bit 0 position,
// which makes it possible to use enums directly with existing macros such
// as AM_BFR() or AM_BFW().
// Brief overview: bitfield enumerations are pre-shifted such that the defined
// value lines up with the bitfield. This is convenient for many operations,
// but not so when using AM_BFR() to read the value of a register bitfield
// as AM_BFR() shifts the bitfield value to the bit 0 position.
// Note that this type of bitfield extraction is Cortex efficient via the
// UBFX (unsigned bit field extract) instruction.
//
// Alternately, AM_BFM() can also be used. AM_BFM() reads a register and masks
// the bitfield value (without shifting), thereby allowing direct comparison
// with a defined enum.
//
// Examples:
// if ( AM_BFR(CLKGEN, CCTRL, CORESEL) ==
// AM_ENUMX(CLKGEN, CCTRL, CORESEL, HFRC) )
//
// or alternatively:
// if ( AM_BFM(CLKGEN, CCTRL, CORESEL) == AM_REG_CLKGEN_CCTRL_CORESEL_HFRC )
//
#define AM_ENUMX(module, reg, field, enumname) \
((AM_REG_##module##_##reg##_##field##_##enumname) >> \
(AM_REG_##module##_##reg##_##field##_S))
//
// AM_WRITE_SM performs a shift/mask operation to prepare the value 'x' to be
// written to the register field 'field'.
//
// For example:
// AM_REGVAL(ui32Base + AM_VCOMP_VCMP_CFG_O) |=
// AM_WRITE_SM(AM_VCOMP_VCMP_CFG_LVLSEL, ui32Value);
//
#define AM_WRITE_SM(field, x) (((x) << field##_S) & field##_M)
//
// AM_READ_SM performs a shift/mask operation to make it easier to interpret
// the value of a given bitfield. This is essentially the reverse of the
// AM_WRITE_SM operation. In most cases, you will want to use the shorter
// AM_BFR macro instead of this one.
//
// For example:
// ui32Value = AM_READ_SM(AM_VCOMP_VCMP_CFG_NSEL,
// AM_REGVAL(ui32Base + AM_VCOMP_VCMP_CFG_O));
//
#define AM_READ_SM(field, x) (((x) & field##_M) >> field##_S)
#ifdef __cplusplus
}
#endif
#endif // AM_REG_MACROS_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_macros_asm.h
+198
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@@ -0,0 +1,198 @@
//*****************************************************************************
//
// am_reg_macros_asm.h
//! @file
//!
//! @brief Inline assembly macros. Initially for critical section handling in
//! protecting hardware registers.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_MACROS_ASM_H
#define AM_REG_MACROS_ASM_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Critical section assembly macros
//
// These macros implement critical section protection using inline assembly
// for various compilers. They are intended to be used in other register
// macros or directly in sections of code.
//
// Important usage note: These macros create a local scope and therefore MUST
// be used in pairs.
//
//*****************************************************************************
#define AM_CRITICAL_BEGIN \
if ( 1 ) \
{ \
volatile uint32_t ui32Primask_04172010; \
ui32Primask_04172010 = am_hal_interrupt_master_disable();
#define AM_CRITICAL_END \
am_hal_interrupt_master_set(ui32Primask_04172010); \
}
//*****************************************************************************
//
// A collection of some common inline assembly instructions / intrinsics.
//
//*****************************************************************************
//
// AM_ASM_BKPT(n)
//
#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
#define AM_ASM_BKPT(n) __breakpoint(n)
#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000)
#define AM_ASM_BKPT(n) __asm(" bkpt "#n);
#elif defined(__GNUC_STDC_INLINE__)
#define AM_ASM_BKPT(n) __asm(" bkpt "#n);
#elif defined(__IAR_SYSTEMS_ICC__)
#define AM_ASM_BKPT(n) asm(" bkpt "#n);
#else
#error Compiler is unknown, please contact Ambiq support team
#endif
//
// AM_ASM_WFI
//
#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
#define AM_ASM_WFI __wfi();
#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000)
#define AM_ASM_WFI __asm(" wfi");
#elif defined(__GNUC_STDC_INLINE__)
#define AM_ASM_WFI __asm(" wfi");
#elif defined(__IAR_SYSTEMS_ICC__)
#define AM_ASM_WFI asm(" wfi");
#else
#error Compiler is unknown, please contact Ambiq support team
#endif
//
// AM_ASM_WFE
//
#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
#define AM_ASM_WFE __wfe();
#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000)
#define AM_ASM_WFE __asm(" wfe");
#elif defined(__GNUC_STDC_INLINE__)
#define AM_ASM_WFE __asm(" wfe");
#elif defined(__IAR_SYSTEMS_ICC__)
#define AM_ASM_WFE asm(" wfe");
#else
#error Compiler is unknown, please contact Ambiq support team
#endif
//
// AM_ASM_SEV
//
#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
#define AM_ASM_SEV __sev();
#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000)
#define AM_ASM_SEV __asm(" sev");
#elif defined(__GNUC_STDC_INLINE__)
#define AM_ASM_SEV __asm(" sev");
#elif defined(__IAR_SYSTEMS_ICC__)
#define AM_ASM_SEV asm(" sev");
#else
#error Compiler is unknown, please contact Ambiq support team
#endif
//
// AM_ASM_NOP
//
#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
#define AM_ASM_NOP __nop();
#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000)
#define AM_ASM_NOP __asm(" nop");
#elif defined(__GNUC_STDC_INLINE__)
#define AM_ASM_NOP __asm(" nop");
#elif defined(__IAR_SYSTEMS_ICC__)
#define AM_ASM_NOP asm(" nop");
#else
#error Compiler is unknown, please contact Ambiq support team
#endif
//
// AM_ASM_DSB
// In cmsis_armcc.h, __DSB() is defined as __dsb(0xF).
//
#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
#define AM_ASM_DSB __dsb(15);
#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000)
#define AM_ASM_DSB __asm(" dsb #15");
#elif defined(__GNUC_STDC_INLINE__)
#define AM_ASM_DSB __asm(" dsb #15");
#elif defined(__IAR_SYSTEMS_ICC__)
#define AM_ASM_DSB asm(" dsb #15");
#else
#error Compiler is unknown, please contact Ambiq support team
#endif
//
// AM_ASM_ISB
// In cmsis_armcc.h, __ISB() is defined as __isb(0xF).
//
#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000)
#define AM_ASM_ISB __isb(15);
#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000)
#define AM_ASM_ISB __asm(" isb #15");
#elif defined(__GNUC_STDC_INLINE__)
#define AM_ASM_ISB __asm(" isb #15");
#elif defined(__IAR_SYSTEMS_ICC__)
#define AM_ASM_ISB asm(" isb #15");
#else
#error Compiler is unknown, please contact Ambiq support team
#endif
#ifdef __cplusplus
}
#endif
#endif // AM_REG_MACROS_ASM_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_mcuctrl.h
+639
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@@ -0,0 +1,639 @@
//*****************************************************************************
//
// am_reg_mcuctrl.h
//! @file
//!
//! @brief Register macros for the MCUCTRL module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_MCUCTRL_H
#define AM_REG_MCUCTRL_H
//*****************************************************************************
//
// MCUCTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_MCUCTRL_NUM_MODULES 1
#define AM_REG_MCUCTRLn(n) \
(REG_MCUCTRL_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_MCUCTRL_CHIP_INFO_O 0x00000000
#define AM_REG_MCUCTRL_CHIPID0_O 0x00000004
#define AM_REG_MCUCTRL_CHIPID1_O 0x00000008
#define AM_REG_MCUCTRL_CHIPREV_O 0x0000000C
#define AM_REG_MCUCTRL_VENDORID_O 0x00000010
#define AM_REG_MCUCTRL_DEBUGGER_O 0x00000014
#define AM_REG_MCUCTRL_BUCK_O 0x00000060
#define AM_REG_MCUCTRL_BUCK3_O 0x00000068
#define AM_REG_MCUCTRL_LDOREG1_O 0x00000080
#define AM_REG_MCUCTRL_LDOREG3_O 0x00000088
#define AM_REG_MCUCTRL_BODPORCTRL_O 0x00000100
#define AM_REG_MCUCTRL_ADCPWRDLY_O 0x00000104
#define AM_REG_MCUCTRL_ADCCAL_O 0x0000010C
#define AM_REG_MCUCTRL_ADCBATTLOAD_O 0x00000110
#define AM_REG_MCUCTRL_BUCKTRIM_O 0x00000114
#define AM_REG_MCUCTRL_XTALGENCTRL_O 0x00000124
#define AM_REG_MCUCTRL_BOOTLOADERLOW_O 0x000001A0
#define AM_REG_MCUCTRL_SHADOWVALID_O 0x000001A4
#define AM_REG_MCUCTRL_ICODEFAULTADDR_O 0x000001C0
#define AM_REG_MCUCTRL_DCODEFAULTADDR_O 0x000001C4
#define AM_REG_MCUCTRL_SYSFAULTADDR_O 0x000001C8
#define AM_REG_MCUCTRL_FAULTSTATUS_O 0x000001CC
#define AM_REG_MCUCTRL_FAULTCAPTUREEN_O 0x000001D0
#define AM_REG_MCUCTRL_DBGR1_O 0x00000200
#define AM_REG_MCUCTRL_DBGR2_O 0x00000204
#define AM_REG_MCUCTRL_PMUENABLE_O 0x00000220
#define AM_REG_MCUCTRL_TPIUCTRL_O 0x00000250
//*****************************************************************************
//
// Key values.
//
//*****************************************************************************
//*****************************************************************************
//
// MCUCTRL_CHIP_INFO - Chip Information Register
//
//*****************************************************************************
// BCD part number.
#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_S 0
#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2 0x03000000
#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO 0x01000000
#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_PN_M 0xFF000000
//*****************************************************************************
//
// MCUCTRL_CHIPID0 - Unique Chip ID 0
//
//*****************************************************************************
// Unique chip ID 0.
#define AM_REG_MCUCTRL_CHIPID0_VALUE_S 0
#define AM_REG_MCUCTRL_CHIPID0_VALUE_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_CHIPID0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_MCUCTRL_CHIPID0_VALUE_APOLLO2 0x00000000
//*****************************************************************************
//
// MCUCTRL_CHIPID1 - Unique Chip ID 1
//
//*****************************************************************************
// Unique chip ID 1.
#define AM_REG_MCUCTRL_CHIPID1_VALUE_S 0
#define AM_REG_MCUCTRL_CHIPID1_VALUE_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_CHIPID1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_MCUCTRL_CHIPID1_VALUE_APOLLO2 0x00000000
//*****************************************************************************
//
// MCUCTRL_CHIPREV - Chip Revision
//
//*****************************************************************************
// Major Revision ID.
#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_S 4
#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_M 0x000000F0
#define AM_REG_MCUCTRL_CHIPREV_REVMAJ(n) (((uint32_t)(n) << 4) & 0x000000F0)
#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_B 0x00000020
#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_A 0x00000010
// Minor Revision ID.
#define AM_REG_MCUCTRL_CHIPREV_REVMIN_S 0
#define AM_REG_MCUCTRL_CHIPREV_REVMIN_M 0x0000000F
#define AM_REG_MCUCTRL_CHIPREV_REVMIN(n) (((uint32_t)(n) << 0) & 0x0000000F)
#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 0x00000000
#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2 0x00000002
//*****************************************************************************
//
// MCUCTRL_VENDORID - Unique Vendor ID
//
//*****************************************************************************
// Unique Vendor ID
#define AM_REG_MCUCTRL_VENDORID_VALUE_S 0
#define AM_REG_MCUCTRL_VENDORID_VALUE_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_VENDORID_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_MCUCTRL_VENDORID_VALUE_AMBIQ 0x414D4251
//*****************************************************************************
//
// MCUCTRL_DEBUGGER - Debugger Access Control
//
//*****************************************************************************
// Lockout of debugger (SWD).
#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT_S 0
#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT_M 0x00000001
#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// MCUCTRL_BUCK - Analog Buck Control
//
//*****************************************************************************
// Reset control override for Mem Buck; 0=enabled, 1=reset; Value is propagated
// only when the BUCKSWE bit is active, otherwise contrl is from the power
// control module.
#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST_S 7
#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST_M 0x00000080
#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST(n) (((uint32_t)(n) << 7) & 0x00000080)
// Reset control override for Core Buck; 0=enabled, 1=reset; Value is propagated
// only when the BUCKSWE bit is active, otherwise control is from the power
// control module.
#define AM_REG_MCUCTRL_BUCK_COREBUCKRST_S 6
#define AM_REG_MCUCTRL_BUCK_COREBUCKRST_M 0x00000040
#define AM_REG_MCUCTRL_BUCK_COREBUCKRST(n) (((uint32_t)(n) << 6) & 0x00000040)
// Not used. Additional control of buck is available in the power control
// module
#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM_S 5
#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM_M 0x00000020
#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM(n) (((uint32_t)(n) << 5) & 0x00000020)
// Memory buck power down override. 1=Powered Down; 0=Enabled; Value is
// propagated only when the BUCKSWE bit is active, otherwise control is from the
// power control module.
#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_S 4
#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_M 0x00000010
#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_EN 0x00000000
// HFRC clkgen bit 0 override. When set, this will override to 0 bit 0 of the
// hfrc_freq_clkgen internal bus (see internal Shelby-1473)
#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA_S 3
#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA_M 0x00000008
#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA(n) (((uint32_t)(n) << 3) & 0x00000008)
// Core buck power down override. 1=Powered Down; 0=Enabled; Value is propagated
// only when the BUCKSWE bit is active, otherwise control is from the power
// control module.
#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_S 2
#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_M 0x00000004
#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_EN 0x00000000
// Not used. Additional control of buck is available in the power control
// module
#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE_S 1
#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE_M 0x00000002
#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE(n) (((uint32_t)(n) << 1) & 0x00000002)
// Buck Register Software Override Enable. This will enable the override values
// for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, MEMBUCKRST, all to be propagated to
// the control logic, instead of the normal power control module signal. Note -
// Must take care to have correct value for ALL the register bits when this SWE
// is enabled.
#define AM_REG_MCUCTRL_BUCK_BUCKSWE_S 0
#define AM_REG_MCUCTRL_BUCK_BUCKSWE_M 0x00000001
#define AM_REG_MCUCTRL_BUCK_BUCKSWE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_BUCK_BUCKSWE_OVERRIDE_DIS 0x00000000
#define AM_REG_MCUCTRL_BUCK_BUCKSWE_OVERRIDE_EN 0x00000001
//*****************************************************************************
//
// MCUCTRL_BUCK3 - Buck control reg 3
//
//*****************************************************************************
// MEM Buck low TON trim value
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON_S 18
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON_M 0x003C0000
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON(n) (((uint32_t)(n) << 18) & 0x003C0000)
// MEM Buck burst enable 0=disable, 0=disabled, 1=enable.
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN_S 17
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN_M 0x00020000
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN(n) (((uint32_t)(n) << 17) & 0x00020000)
// Memory buck zero crossing trim value
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM_S 13
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM_M 0x0001E000
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM(n) (((uint32_t)(n) << 13) & 0x0001E000)
// Hysterisis trim for mem buck
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_S 11
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_M 0x00001800
#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM(n) (((uint32_t)(n) << 11) & 0x00001800)
// Core Buck low TON trim value
#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON_S 7
#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON_M 0x00000780
#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON(n) (((uint32_t)(n) << 7) & 0x00000780)
// Core Buck burst enable. 0=disabled, 1=enabled
#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN_S 6
#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN_M 0x00000040
#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN(n) (((uint32_t)(n) << 6) & 0x00000040)
// Core buck zero crossing trim value
#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM_S 2
#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM_M 0x0000003C
#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM(n) (((uint32_t)(n) << 2) & 0x0000003C)
// Hysterisis trim for core buck
#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM_S 0
#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM_M 0x00000003
#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM(n) (((uint32_t)(n) << 0) & 0x00000003)
//*****************************************************************************
//
// MCUCTRL_LDOREG1 - Analog LDO Reg 1
//
//*****************************************************************************
// CORE LDO IBIAS Trim
#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM_S 20
#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM_M 0x00100000
#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM(n) (((uint32_t)(n) << 20) & 0x00100000)
// CORE LDO Low Power Trim
#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM_S 14
#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM_M 0x000FC000
#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM(n) (((uint32_t)(n) << 14) & 0x000FC000)
// CORE LDO tempco trim (R3).
#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3_S 10
#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3_M 0x00003C00
#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3(n) (((uint32_t)(n) << 10) & 0x00003C00)
// CORE LDO Active mode ouput trim (R1).
#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1_S 0
#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1_M 0x000003FF
#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1(n) (((uint32_t)(n) << 0) & 0x000003FF)
//*****************************************************************************
//
// MCUCTRL_LDOREG3 - LDO Control Register 3
//
//*****************************************************************************
// MEM LDO active mode trim (R1).
#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1_S 12
#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1_M 0x0003F000
#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1(n) (((uint32_t)(n) << 12) & 0x0003F000)
// MEM LDO TRIM for low power mode with ADC active
#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_S 6
#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_M 0x00000FC0
#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM(n) (((uint32_t)(n) << 6) & 0x00000FC0)
// MEM LDO TRIM for low power mode with ADC inactive
#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM_S 0
#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM_M 0x0000003F
#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM(n) (((uint32_t)(n) << 0) & 0x0000003F)
//*****************************************************************************
//
// MCUCTRL_BODPORCTRL - BOD and PDR control Register
//
//*****************************************************************************
// BOD External Reference Select.
#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_S 3
#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_M 0x00000008
#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_SELECT 0x00000008
// PDR External Reference Select.
#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_S 2
#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_M 0x00000004
#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_SELECT 0x00000004
// BOD Power Down.
#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_S 1
#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_M 0x00000002
#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_PWR_DN 0x00000002
// PDR Power Down.
#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_S 0
#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_M 0x00000001
#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_PWR_DN 0x00000001
//*****************************************************************************
//
// MCUCTRL_ADCPWRDLY - ADC Power Up Delay Control
//
//*****************************************************************************
// ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL =
// 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.
#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1_S 8
#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1_M 0x0000FF00
#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for
// ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.
#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0_S 0
#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0_M 0x000000FF
#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// MCUCTRL_ADCCAL - ADC Calibration Control
//
//*****************************************************************************
// Status for ADC Calibration
#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_S 1
#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_M 0x00000002
#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE 0x00000000
#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE 0x00000002
// Run ADC Calibration on initial power up sequence
#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_S 0
#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_M 0x00000001
#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_DIS 0x00000000
#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_EN 0x00000001
//*****************************************************************************
//
// MCUCTRL_ADCBATTLOAD - ADC Battery Load Enable
//
//*****************************************************************************
// Enable the ADC battery load resistor
#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_S 0
#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_M 0x00000001
#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS 0x00000000
#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_EN 0x00000001
//*****************************************************************************
//
// MCUCTRL_BUCKTRIM - Trim settings for Core and Mem buck modules
//
//*****************************************************************************
// RESERVED.
#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2_S 24
#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2_M 0x3F000000
#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2(n) (((uint32_t)(n) << 24) & 0x3F000000)
// Core Buck voltage output trim bits[9:6]. Concatenate with field COREBUCKR1_LO
// for the full trim value.
#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI_S 16
#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI_M 0x000F0000
#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI(n) (((uint32_t)(n) << 16) & 0x000F0000)
// Core Buck voltage output trim bits[5:0], Concatenate with field COREBUCKR1_HI
// for the full trim value.
#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO_S 8
#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO_M 0x00003F00
#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO(n) (((uint32_t)(n) << 8) & 0x00003F00)
// Trim values for BUCK regulator.
#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1_S 0
#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1_M 0x0000003F
#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1(n) (((uint32_t)(n) << 0) & 0x0000003F)
//*****************************************************************************
//
// MCUCTRL_XTALGENCTRL - XTAL Oscillator General Control
//
//*****************************************************************************
// XTAL IBIAS Kick start trim . This trim value is used during the startup
// process to enable a faster lock and is applied when the kickstart signal is
// active.
#define AM_REG_MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_S 8
#define AM_REG_MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_M 0x00003F00
#define AM_REG_MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM(n) (((uint32_t)(n) << 8) & 0x00003F00)
// XTAL IBIAS trim
#define AM_REG_MCUCTRL_XTALGENCTRL_XTALBIASTRIM_S 2
#define AM_REG_MCUCTRL_XTALGENCTRL_XTALBIASTRIM_M 0x000000FC
#define AM_REG_MCUCTRL_XTALGENCTRL_XTALBIASTRIM(n) (((uint32_t)(n) << 2) & 0x000000FC)
// Auto-calibration delay control
#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_S 0
#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_M 0x00000003
#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP(n) (((uint32_t)(n) << 0) & 0x00000003)
#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_1SEC 0x00000000
#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_2SEC 0x00000001
#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_4SEC 0x00000002
#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_8SEC 0x00000003
//*****************************************************************************
//
// MCUCTRL_BOOTLOADERLOW - Determines whether the bootloader code is visible at
// address 0x00000000
//
//*****************************************************************************
// Determines whether the bootloader code is visible at address 0x00000000 or
// not.
#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_S 0
#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_M 0x00000001
#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_ADDR0 0x00000001
//*****************************************************************************
//
// MCUCTRL_SHADOWVALID - Register to indicate whether the shadow registers have
// been successfully loaded from the Flash Information Space.
//
//*****************************************************************************
// Indicates whether the bootloader should sleep or deep sleep if no image
// loaded.
#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_S 1
#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_M 0x00000002
#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_DEEPSLEEP 0x00000002
// Indicates whether the shadow registers contain valid data from the Flash
// Information Space.
#define AM_REG_MCUCTRL_SHADOWVALID_VALID_S 0
#define AM_REG_MCUCTRL_SHADOWVALID_VALID_M 0x00000001
#define AM_REG_MCUCTRL_SHADOWVALID_VALID(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_SHADOWVALID_VALID_VALID 0x00000001
//*****************************************************************************
//
// MCUCTRL_ICODEFAULTADDR - ICODE bus address which was present when a bus fault
// occurred.
//
//*****************************************************************************
// The ICODE bus address observed when a Bus Fault occurred. Once an address is
// captured in this field, it is held until the corresponding Fault Observed bit
// is cleared in the FAULTSTATUS register.
#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR_S 0
#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// MCUCTRL_DCODEFAULTADDR - DCODE bus address which was present when a bus fault
// occurred.
//
//*****************************************************************************
// The DCODE bus address observed when a Bus Fault occurred. Once an address is
// captured in this field, it is held until the corresponding Fault Observed bit
// is cleared in the FAULTSTATUS register.
#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR_S 0
#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// MCUCTRL_SYSFAULTADDR - System bus address which was present when a bus fault
// occurred.
//
//*****************************************************************************
// SYS bus address observed when a Bus Fault occurred. Once an address is
// captured in this field, it is held until the corresponding Fault Observed bit
// is cleared in the FAULTSTATUS register.
#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR_S 0
#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// MCUCTRL_FAULTSTATUS - Reflects the status of the bus decoders' fault
// detection. Any write to this register will clear all of the status bits
// within the register.
//
//*****************************************************************************
// SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and
// the SYSFAULTADDR register will contain the bus address which generated the
// fault.
#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_S 2
#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_M 0x00000004
#define AM_REG_MCUCTRL_FAULTSTATUS_SYS(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_NOFAULT 0x00000000
#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_FAULT 0x00000004
// DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected,
// and the DCODEFAULTADDR register will contain the bus address which generated
// the fault.
#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_S 1
#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_M 0x00000002
#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_NOFAULT 0x00000000
#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_FAULT 0x00000002
// The ICODE Bus Decoder Fault Detected bit. When set, a fault has been
// detected, and the ICODEFAULTADDR register will contain the bus address which
// generated the fault.
#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_S 0
#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_M 0x00000001
#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_NOFAULT 0x00000000
#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_FAULT 0x00000001
//*****************************************************************************
//
// MCUCTRL_FAULTCAPTUREEN - Enable the fault capture registers
//
//*****************************************************************************
// Fault Capture Enable field. When set, the Fault Capture monitors are enabled
// and addresses which generate a hard fault are captured into the FAULTADDR
// registers.
#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_S 0
#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_M 0x00000001
#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_DIS 0x00000000
#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_EN 0x00000001
//*****************************************************************************
//
// MCUCTRL_DBGR1 - Read-only debug register 1
//
//*****************************************************************************
// Read-only register for communication validation
#define AM_REG_MCUCTRL_DBGR1_ONETO8_S 0
#define AM_REG_MCUCTRL_DBGR1_ONETO8_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_DBGR1_ONETO8(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// MCUCTRL_DBGR2 - Read-only debug register 2
//
//*****************************************************************************
// Read-only register for communication validation
#define AM_REG_MCUCTRL_DBGR2_COOLCODE_S 0
#define AM_REG_MCUCTRL_DBGR2_COOLCODE_M 0xFFFFFFFF
#define AM_REG_MCUCTRL_DBGR2_COOLCODE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// MCUCTRL_PMUENABLE - Control bit to enable/disable the PMU
//
//*****************************************************************************
// PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the
// lowest power consuming Deep Sleep mode upon execution of a WFI instruction
// (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When
// cleared, regardless of the requested sleep mode, the PMU will not enter the
// lowest power Deep Sleep mode, instead entering the Sleep mode.
#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_S 0
#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_M 0x00000001
#define AM_REG_MCUCTRL_PMUENABLE_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_DIS 0x00000000
#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_EN 0x00000001
//*****************************************************************************
//
// MCUCTRL_TPIUCTRL - TPIU Control Register. Determines the clock enable and
// frequency for the M4's TPIU interface.
//
//*****************************************************************************
// This field selects the frequency of the ARM M4 TPIU port.
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_S 8
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_M 0x00000700
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(n) (((uint32_t)(n) << 8) & 0x00000700)
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_LOW_PWR 0x00000000
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz 0x00000000
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_2 0x00000100
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_8 0x00000200
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_16 0x00000300
#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_32 0x00000400
// TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be
// streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.
#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_S 0
#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_M 0x00000001
#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS 0x00000000
#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_EN 0x00000001
#endif // AM_REG_MCUCTRL_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_nvic.h
+329
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@@ -0,0 +1,329 @@
//*****************************************************************************
//
// am_reg_nvic.h
//! @file
//!
//! @brief Register macros for the NVIC module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_NVIC_H
#define AM_REG_NVIC_H
//*****************************************************************************
//
// NVIC
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_NVIC_NUM_MODULES 1
#define AM_REG_NVICn(n) \
(REG_NVIC_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_NVIC_ISER0_O 0xE000E100
#define AM_REG_NVIC_ICER0_O 0xE000E180
#define AM_REG_NVIC_ISPR0_O 0xE000E200
#define AM_REG_NVIC_ICPR0_O 0xE000E280
#define AM_REG_NVIC_IABR0_O 0xE000E300
#define AM_REG_NVIC_IPR0_O 0xE000E400
#define AM_REG_NVIC_IPR1_O 0xE000E404
#define AM_REG_NVIC_IPR2_O 0xE000E408
#define AM_REG_NVIC_IPR3_O 0xE000E40C
#define AM_REG_NVIC_IPR4_O 0xE000E410
#define AM_REG_NVIC_IPR5_O 0xE000E414
#define AM_REG_NVIC_IPR6_O 0xE000E418
#define AM_REG_NVIC_IPR7_O 0xE000E41C
//*****************************************************************************
//
// NVIC_ISER0 - Interrupt Set-Enable Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.
#define AM_REG_NVIC_ISER0_BITS_S 0
#define AM_REG_NVIC_ISER0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ISER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_ICER0 - Interrupt Clear-Enable Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.
#define AM_REG_NVIC_ICER0_BITS_S 0
#define AM_REG_NVIC_ICER0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ICER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_ISPR0 - Interrupt Set-Pending Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.
#define AM_REG_NVIC_ISPR0_BITS_S 0
#define AM_REG_NVIC_ISPR0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ISPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_ICPR0 - Interrupt Clear-Pending Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.
#define AM_REG_NVIC_ICPR0_BITS_S 0
#define AM_REG_NVIC_ICPR0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_ICPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_IABR0 - Interrupt Active Bit Register 0
//
//*****************************************************************************
// NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.
#define AM_REG_NVIC_IABR0_BITS_S 0
#define AM_REG_NVIC_IABR0_BITS_M 0xFFFFFFFF
#define AM_REG_NVIC_IABR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// NVIC_IPR0 - Interrupt Priority Register 0
//
//*****************************************************************************
// Priority assignment for interrupt vector 3.
#define AM_REG_NVIC_IPR0_PRI_N3_S 24
#define AM_REG_NVIC_IPR0_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR0_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 2.
#define AM_REG_NVIC_IPR0_PRI_N2_S 16
#define AM_REG_NVIC_IPR0_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR0_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 1.
#define AM_REG_NVIC_IPR0_PRI_N1_S 8
#define AM_REG_NVIC_IPR0_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR0_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 0.
#define AM_REG_NVIC_IPR0_PRI_N0_S 0
#define AM_REG_NVIC_IPR0_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR0_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR1 - Interrupt Priority Register 1
//
//*****************************************************************************
// Priority assignment for interrupt vector 7.
#define AM_REG_NVIC_IPR1_PRI_N3_S 24
#define AM_REG_NVIC_IPR1_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR1_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 6.
#define AM_REG_NVIC_IPR1_PRI_N2_S 16
#define AM_REG_NVIC_IPR1_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR1_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 5.
#define AM_REG_NVIC_IPR1_PRI_N1_S 8
#define AM_REG_NVIC_IPR1_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR1_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 4.
#define AM_REG_NVIC_IPR1_PRI_N0_S 0
#define AM_REG_NVIC_IPR1_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR1_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR2 - Interrupt Priority Register 2
//
//*****************************************************************************
// Priority assignment for interrupt vector 11.
#define AM_REG_NVIC_IPR2_PRI_N3_S 24
#define AM_REG_NVIC_IPR2_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR2_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 10.
#define AM_REG_NVIC_IPR2_PRI_N2_S 16
#define AM_REG_NVIC_IPR2_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR2_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 9.
#define AM_REG_NVIC_IPR2_PRI_N1_S 8
#define AM_REG_NVIC_IPR2_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR2_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 8.
#define AM_REG_NVIC_IPR2_PRI_N0_S 0
#define AM_REG_NVIC_IPR2_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR2_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR3 - Interrupt Priority Register 3
//
//*****************************************************************************
// Priority assignment for interrupt vector 15.
#define AM_REG_NVIC_IPR3_PRI_N3_S 24
#define AM_REG_NVIC_IPR3_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR3_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 14.
#define AM_REG_NVIC_IPR3_PRI_N2_S 16
#define AM_REG_NVIC_IPR3_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR3_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 13.
#define AM_REG_NVIC_IPR3_PRI_N1_S 8
#define AM_REG_NVIC_IPR3_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR3_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 12.
#define AM_REG_NVIC_IPR3_PRI_N0_S 0
#define AM_REG_NVIC_IPR3_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR3_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR4 - Interrupt Priority Register 4
//
//*****************************************************************************
// Priority assignment for interrupt vector 19.
#define AM_REG_NVIC_IPR4_PRI_N3_S 24
#define AM_REG_NVIC_IPR4_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR4_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 18.
#define AM_REG_NVIC_IPR4_PRI_N2_S 16
#define AM_REG_NVIC_IPR4_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR4_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 17.
#define AM_REG_NVIC_IPR4_PRI_N1_S 8
#define AM_REG_NVIC_IPR4_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR4_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 16.
#define AM_REG_NVIC_IPR4_PRI_N0_S 0
#define AM_REG_NVIC_IPR4_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR4_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR5 - Interrupt Priority Register 5
//
//*****************************************************************************
// Priority assignment for interrupt vector 23.
#define AM_REG_NVIC_IPR5_PRI_N3_S 24
#define AM_REG_NVIC_IPR5_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR5_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 22.
#define AM_REG_NVIC_IPR5_PRI_N2_S 16
#define AM_REG_NVIC_IPR5_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR5_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 21.
#define AM_REG_NVIC_IPR5_PRI_N1_S 8
#define AM_REG_NVIC_IPR5_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR5_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 20.
#define AM_REG_NVIC_IPR5_PRI_N0_S 0
#define AM_REG_NVIC_IPR5_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR5_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR6 - Interrupt Priority Register 6
//
//*****************************************************************************
// Priority assignment for interrupt vector 27.
#define AM_REG_NVIC_IPR6_PRI_N3_S 24
#define AM_REG_NVIC_IPR6_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR6_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 26.
#define AM_REG_NVIC_IPR6_PRI_N2_S 16
#define AM_REG_NVIC_IPR6_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR6_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 25.
#define AM_REG_NVIC_IPR6_PRI_N1_S 8
#define AM_REG_NVIC_IPR6_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR6_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 24.
#define AM_REG_NVIC_IPR6_PRI_N0_S 0
#define AM_REG_NVIC_IPR6_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR6_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// NVIC_IPR7 - Interrupt Priority Register 7
//
//*****************************************************************************
// Priority assignment for interrupt vector 31.
#define AM_REG_NVIC_IPR7_PRI_N3_S 24
#define AM_REG_NVIC_IPR7_PRI_N3_M 0xFF000000
#define AM_REG_NVIC_IPR7_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority assignment for interrupt vector 30.
#define AM_REG_NVIC_IPR7_PRI_N2_S 16
#define AM_REG_NVIC_IPR7_PRI_N2_M 0x00FF0000
#define AM_REG_NVIC_IPR7_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority assignment for interrupt vector 29.
#define AM_REG_NVIC_IPR7_PRI_N1_S 8
#define AM_REG_NVIC_IPR7_PRI_N1_M 0x0000FF00
#define AM_REG_NVIC_IPR7_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority assignment for interrupt vector 28.
#define AM_REG_NVIC_IPR7_PRI_N0_S 0
#define AM_REG_NVIC_IPR7_PRI_N0_M 0x000000FF
#define AM_REG_NVIC_IPR7_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
#endif // AM_REG_NVIC_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_pdm.h
+378
View File
@@ -0,0 +1,378 @@
//*****************************************************************************
//
// am_reg_pdm.h
//! @file
//!
//! @brief Register macros for the PDM module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_PDM_H
#define AM_REG_PDM_H
//*****************************************************************************
//
// PDM
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_PDM_NUM_MODULES 1
#define AM_REG_PDMn(n) \
(REG_PDM_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_PDM_PCFG_O 0x00000000
#define AM_REG_PDM_VCFG_O 0x00000004
#define AM_REG_PDM_FR_O 0x00000008
#define AM_REG_PDM_FRD_O 0x0000000C
#define AM_REG_PDM_FLUSH_O 0x00000010
#define AM_REG_PDM_FTHR_O 0x00000014
#define AM_REG_PDM_INTEN_O 0x00000200
#define AM_REG_PDM_INTSTAT_O 0x00000204
#define AM_REG_PDM_INTCLR_O 0x00000208
#define AM_REG_PDM_INTSET_O 0x0000020C
//*****************************************************************************
//
// PDM_INTEN - IO Master Interrupts: Enable
//
//*****************************************************************************
// This is the FIFO underflow interrupt.
#define AM_REG_PDM_INTEN_UNDFL_S 2
#define AM_REG_PDM_INTEN_UNDFL_M 0x00000004
#define AM_REG_PDM_INTEN_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO overflow interrupt.
#define AM_REG_PDM_INTEN_OVF_S 1
#define AM_REG_PDM_INTEN_OVF_M 0x00000002
#define AM_REG_PDM_INTEN_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the FIFO threshold interrupt.
#define AM_REG_PDM_INTEN_THR_S 0
#define AM_REG_PDM_INTEN_THR_M 0x00000001
#define AM_REG_PDM_INTEN_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// PDM_INTSTAT - IO Master Interrupts: Status
//
//*****************************************************************************
// This is the FIFO underflow interrupt.
#define AM_REG_PDM_INTSTAT_UNDFL_S 2
#define AM_REG_PDM_INTSTAT_UNDFL_M 0x00000004
#define AM_REG_PDM_INTSTAT_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO overflow interrupt.
#define AM_REG_PDM_INTSTAT_OVF_S 1
#define AM_REG_PDM_INTSTAT_OVF_M 0x00000002
#define AM_REG_PDM_INTSTAT_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the FIFO threshold interrupt.
#define AM_REG_PDM_INTSTAT_THR_S 0
#define AM_REG_PDM_INTSTAT_THR_M 0x00000001
#define AM_REG_PDM_INTSTAT_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// PDM_INTCLR - IO Master Interrupts: Clear
//
//*****************************************************************************
// This is the FIFO underflow interrupt.
#define AM_REG_PDM_INTCLR_UNDFL_S 2
#define AM_REG_PDM_INTCLR_UNDFL_M 0x00000004
#define AM_REG_PDM_INTCLR_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO overflow interrupt.
#define AM_REG_PDM_INTCLR_OVF_S 1
#define AM_REG_PDM_INTCLR_OVF_M 0x00000002
#define AM_REG_PDM_INTCLR_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the FIFO threshold interrupt.
#define AM_REG_PDM_INTCLR_THR_S 0
#define AM_REG_PDM_INTCLR_THR_M 0x00000001
#define AM_REG_PDM_INTCLR_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// PDM_INTSET - IO Master Interrupts: Set
//
//*****************************************************************************
// This is the FIFO underflow interrupt.
#define AM_REG_PDM_INTSET_UNDFL_S 2
#define AM_REG_PDM_INTSET_UNDFL_M 0x00000004
#define AM_REG_PDM_INTSET_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
// This is the FIFO overflow interrupt.
#define AM_REG_PDM_INTSET_OVF_S 1
#define AM_REG_PDM_INTSET_OVF_M 0x00000002
#define AM_REG_PDM_INTSET_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
// This is the FIFO threshold interrupt.
#define AM_REG_PDM_INTSET_THR_S 0
#define AM_REG_PDM_INTSET_THR_M 0x00000001
#define AM_REG_PDM_INTSET_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// PDM_PCFG - PDM Configuration Register
//
//*****************************************************************************
// Left/right channel swap.
#define AM_REG_PDM_PCFG_LRSWAP_S 31
#define AM_REG_PDM_PCFG_LRSWAP_M 0x80000000
#define AM_REG_PDM_PCFG_LRSWAP(n) (((uint32_t)(n) << 31) & 0x80000000)
#define AM_REG_PDM_PCFG_LRSWAP_EN 0x80000000
#define AM_REG_PDM_PCFG_LRSWAP_NOSWAP 0x00000000
// Right channel PGA gain.
#define AM_REG_PDM_PCFG_PGARIGHT_S 27
#define AM_REG_PDM_PCFG_PGARIGHT_M 0x78000000
#define AM_REG_PDM_PCFG_PGARIGHT(n) (((uint32_t)(n) << 27) & 0x78000000)
#define AM_REG_PDM_PCFG_PGARIGHT_M15DB 0x78000000
#define AM_REG_PDM_PCFG_PGARIGHT_M300DB 0x70000000
#define AM_REG_PDM_PCFG_PGARIGHT_M45DB 0x68000000
#define AM_REG_PDM_PCFG_PGARIGHT_M60DB 0x60000000
#define AM_REG_PDM_PCFG_PGARIGHT_M75DB 0x58000000
#define AM_REG_PDM_PCFG_PGARIGHT_M90DB 0x50000000
#define AM_REG_PDM_PCFG_PGARIGHT_M105DB 0x48000000
#define AM_REG_PDM_PCFG_PGARIGHT_M120DB 0x40000000
#define AM_REG_PDM_PCFG_PGARIGHT_P105DB 0x38000000
#define AM_REG_PDM_PCFG_PGARIGHT_P90DB 0x30000000
#define AM_REG_PDM_PCFG_PGARIGHT_P75DB 0x28000000
#define AM_REG_PDM_PCFG_PGARIGHT_P60DB 0x20000000
#define AM_REG_PDM_PCFG_PGARIGHT_P45DB 0x18000000
#define AM_REG_PDM_PCFG_PGARIGHT_P30DB 0x10000000
#define AM_REG_PDM_PCFG_PGARIGHT_P15DB 0x08000000
#define AM_REG_PDM_PCFG_PGARIGHT_0DB 0x00000000
// Left channel PGA gain.
#define AM_REG_PDM_PCFG_PGALEFT_S 23
#define AM_REG_PDM_PCFG_PGALEFT_M 0x07800000
#define AM_REG_PDM_PCFG_PGALEFT(n) (((uint32_t)(n) << 23) & 0x07800000)
#define AM_REG_PDM_PCFG_PGALEFT_M15DB 0x07800000
#define AM_REG_PDM_PCFG_PGALEFT_M300DB 0x07000000
#define AM_REG_PDM_PCFG_PGALEFT_M45DB 0x06800000
#define AM_REG_PDM_PCFG_PGALEFT_M60DB 0x06000000
#define AM_REG_PDM_PCFG_PGALEFT_M75DB 0x05800000
#define AM_REG_PDM_PCFG_PGALEFT_M90DB 0x05000000
#define AM_REG_PDM_PCFG_PGALEFT_M105DB 0x04800000
#define AM_REG_PDM_PCFG_PGALEFT_M120DB 0x04000000
#define AM_REG_PDM_PCFG_PGALEFT_P105DB 0x03800000
#define AM_REG_PDM_PCFG_PGALEFT_P90DB 0x03000000
#define AM_REG_PDM_PCFG_PGALEFT_P75DB 0x02800000
#define AM_REG_PDM_PCFG_PGALEFT_P60DB 0x02000000
#define AM_REG_PDM_PCFG_PGALEFT_P45DB 0x01800000
#define AM_REG_PDM_PCFG_PGALEFT_P30DB 0x01000000
#define AM_REG_PDM_PCFG_PGALEFT_P15DB 0x00800000
#define AM_REG_PDM_PCFG_PGALEFT_0DB 0x00000000
// PDM_CLK frequency divisor.
#define AM_REG_PDM_PCFG_MCLKDIV_S 17
#define AM_REG_PDM_PCFG_MCLKDIV_M 0x00060000
#define AM_REG_PDM_PCFG_MCLKDIV(n) (((uint32_t)(n) << 17) & 0x00060000)
#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV4 0x00060000
#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV3 0x00040000
#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV2 0x00020000
#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV1 0x00000000
// SINC decimation rate.
#define AM_REG_PDM_PCFG_SINCRATE_S 10
#define AM_REG_PDM_PCFG_SINCRATE_M 0x0001FC00
#define AM_REG_PDM_PCFG_SINCRATE(n) (((uint32_t)(n) << 10) & 0x0001FC00)
// High pass filter disable.
#define AM_REG_PDM_PCFG_ADCHPD_S 9
#define AM_REG_PDM_PCFG_ADCHPD_M 0x00000200
#define AM_REG_PDM_PCFG_ADCHPD(n) (((uint32_t)(n) << 9) & 0x00000200)
#define AM_REG_PDM_PCFG_ADCHPD_EN 0x00000000
#define AM_REG_PDM_PCFG_ADCHPD_DIS 0x00000200
// High pass filter coefficients.
#define AM_REG_PDM_PCFG_HPCUTOFF_S 5
#define AM_REG_PDM_PCFG_HPCUTOFF_M 0x000001E0
#define AM_REG_PDM_PCFG_HPCUTOFF(n) (((uint32_t)(n) << 5) & 0x000001E0)
// Number of clocks during gain-setting changes.
#define AM_REG_PDM_PCFG_CYCLES_S 2
#define AM_REG_PDM_PCFG_CYCLES_M 0x0000001C
#define AM_REG_PDM_PCFG_CYCLES(n) (((uint32_t)(n) << 2) & 0x0000001C)
// Soft mute control.
#define AM_REG_PDM_PCFG_SOFTMUTE_S 1
#define AM_REG_PDM_PCFG_SOFTMUTE_M 0x00000002
#define AM_REG_PDM_PCFG_SOFTMUTE(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_PDM_PCFG_SOFTMUTE_EN 0x00000002
#define AM_REG_PDM_PCFG_SOFTMUTE_DIS 0x00000000
// Data Streaming Control.
#define AM_REG_PDM_PCFG_PDMCORE_S 0
#define AM_REG_PDM_PCFG_PDMCORE_M 0x00000001
#define AM_REG_PDM_PCFG_PDMCORE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_PDM_PCFG_PDMCORE_EN 0x00000001
#define AM_REG_PDM_PCFG_PDMCORE_DIS 0x00000000
//*****************************************************************************
//
// PDM_VCFG - Voice Configuration Register
//
//*****************************************************************************
// Enable the IO clock.
#define AM_REG_PDM_VCFG_IOCLKEN_S 31
#define AM_REG_PDM_VCFG_IOCLKEN_M 0x80000000
#define AM_REG_PDM_VCFG_IOCLKEN(n) (((uint32_t)(n) << 31) & 0x80000000)
#define AM_REG_PDM_VCFG_IOCLKEN_DIS 0x00000000
#define AM_REG_PDM_VCFG_IOCLKEN_EN 0x80000000
// Reset the IP core.
#define AM_REG_PDM_VCFG_RSTB_S 30
#define AM_REG_PDM_VCFG_RSTB_M 0x40000000
#define AM_REG_PDM_VCFG_RSTB(n) (((uint32_t)(n) << 30) & 0x40000000)
#define AM_REG_PDM_VCFG_RSTB_RESET 0x00000000
#define AM_REG_PDM_VCFG_RSTB_NORM 0x40000000
// Select the PDM input clock.
#define AM_REG_PDM_VCFG_PDMCLKSEL_S 27
#define AM_REG_PDM_VCFG_PDMCLKSEL_M 0x38000000
#define AM_REG_PDM_VCFG_PDMCLKSEL(n) (((uint32_t)(n) << 27) & 0x38000000)
#define AM_REG_PDM_VCFG_PDMCLKSEL_DISABLE 0x00000000
#define AM_REG_PDM_VCFG_PDMCLKSEL_12MHz 0x08000000
#define AM_REG_PDM_VCFG_PDMCLKSEL_6MHz 0x10000000
#define AM_REG_PDM_VCFG_PDMCLKSEL_3MHz 0x18000000
#define AM_REG_PDM_VCFG_PDMCLKSEL_1_5MHz 0x20000000
#define AM_REG_PDM_VCFG_PDMCLKSEL_750KHz 0x28000000
#define AM_REG_PDM_VCFG_PDMCLKSEL_375KHz 0x30000000
#define AM_REG_PDM_VCFG_PDMCLKSEL_187KHz 0x38000000
// Enable the serial clock.
#define AM_REG_PDM_VCFG_PDMCLK_S 26
#define AM_REG_PDM_VCFG_PDMCLK_M 0x04000000
#define AM_REG_PDM_VCFG_PDMCLK(n) (((uint32_t)(n) << 26) & 0x04000000)
#define AM_REG_PDM_VCFG_PDMCLK_DIS 0x00000000
#define AM_REG_PDM_VCFG_PDMCLK_EN 0x04000000
// I2S interface enable.
#define AM_REG_PDM_VCFG_I2SMODE_S 20
#define AM_REG_PDM_VCFG_I2SMODE_M 0x00100000
#define AM_REG_PDM_VCFG_I2SMODE(n) (((uint32_t)(n) << 20) & 0x00100000)
#define AM_REG_PDM_VCFG_I2SMODE_DIS 0x00000000
#define AM_REG_PDM_VCFG_I2SMODE_EN 0x00100000
// I2S BCLK input inversion.
#define AM_REG_PDM_VCFG_BCLKINV_S 19
#define AM_REG_PDM_VCFG_BCLKINV_M 0x00080000
#define AM_REG_PDM_VCFG_BCLKINV(n) (((uint32_t)(n) << 19) & 0x00080000)
#define AM_REG_PDM_VCFG_BCLKINV_INV 0x00000000
#define AM_REG_PDM_VCFG_BCLKINV_NORM 0x00080000
// PDM clock sampling delay.
#define AM_REG_PDM_VCFG_DMICKDEL_S 17
#define AM_REG_PDM_VCFG_DMICKDEL_M 0x00020000
#define AM_REG_PDM_VCFG_DMICKDEL(n) (((uint32_t)(n) << 17) & 0x00020000)
#define AM_REG_PDM_VCFG_DMICKDEL_0CYC 0x00000000
#define AM_REG_PDM_VCFG_DMICKDEL_1CYC 0x00020000
// Select PDM input clock source.
#define AM_REG_PDM_VCFG_SELAP_S 16
#define AM_REG_PDM_VCFG_SELAP_M 0x00010000
#define AM_REG_PDM_VCFG_SELAP(n) (((uint32_t)(n) << 16) & 0x00010000)
#define AM_REG_PDM_VCFG_SELAP_I2S 0x00010000
#define AM_REG_PDM_VCFG_SELAP_INTERNAL 0x00000000
// PCM data packing enable.
#define AM_REG_PDM_VCFG_PCMPACK_S 8
#define AM_REG_PDM_VCFG_PCMPACK_M 0x00000100
#define AM_REG_PDM_VCFG_PCMPACK(n) (((uint32_t)(n) << 8) & 0x00000100)
#define AM_REG_PDM_VCFG_PCMPACK_DIS 0x00000000
#define AM_REG_PDM_VCFG_PCMPACK_EN 0x00000100
// Set PCM channels.
#define AM_REG_PDM_VCFG_CHSET_S 3
#define AM_REG_PDM_VCFG_CHSET_M 0x00000018
#define AM_REG_PDM_VCFG_CHSET(n) (((uint32_t)(n) << 3) & 0x00000018)
#define AM_REG_PDM_VCFG_CHSET_DIS 0x00000000
#define AM_REG_PDM_VCFG_CHSET_LEFT 0x00000008
#define AM_REG_PDM_VCFG_CHSET_RIGHT 0x00000010
#define AM_REG_PDM_VCFG_CHSET_STEREO 0x00000018
//*****************************************************************************
//
// PDM_FR - Voice Status Register
//
//*****************************************************************************
// Valid 32-bit entries currently in the FIFO.
#define AM_REG_PDM_FR_FIFOCNT_S 0
#define AM_REG_PDM_FR_FIFOCNT_M 0x000001FF
#define AM_REG_PDM_FR_FIFOCNT(n) (((uint32_t)(n) << 0) & 0x000001FF)
//*****************************************************************************
//
// PDM_FRD - FIFO Read
//
//*****************************************************************************
// FIFO read data.
#define AM_REG_PDM_FRD_FIFOREAD_S 0
#define AM_REG_PDM_FRD_FIFOREAD_M 0xFFFFFFFF
#define AM_REG_PDM_FRD_FIFOREAD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// PDM_FLUSH - FIFO Flush
//
//*****************************************************************************
// FIFO FLUSH.
#define AM_REG_PDM_FLUSH_FIFOFLUSH_S 0
#define AM_REG_PDM_FLUSH_FIFOFLUSH_M 0x00000001
#define AM_REG_PDM_FLUSH_FIFOFLUSH(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// PDM_FTHR - FIFO Threshold
//
//*****************************************************************************
// FIFO interrupt threshold.
#define AM_REG_PDM_FTHR_FIFOTHR_S 0
#define AM_REG_PDM_FTHR_FIFOTHR_M 0x000000FF
#define AM_REG_PDM_FTHR_FIFOTHR(n) (((uint32_t)(n) << 0) & 0x000000FF)
#endif // AM_REG_PDM_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_pwrctrl.h
+489
View File
@@ -0,0 +1,489 @@
//*****************************************************************************
//
// am_reg_pwrctrl.h
//! @file
//!
//! @brief Register macros for the PWRCTRL module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_PWRCTRL_H
#define AM_REG_PWRCTRL_H
//*****************************************************************************
//
// PWRCTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_PWRCTRL_NUM_MODULES 1
#define AM_REG_PWRCTRLn(n) \
(REG_PWRCTRL_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_PWRCTRL_SUPPLYSRC_O 0x00000000
#define AM_REG_PWRCTRL_POWERSTATUS_O 0x00000004
#define AM_REG_PWRCTRL_DEVICEEN_O 0x00000008
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_O 0x0000000C
#define AM_REG_PWRCTRL_MEMEN_O 0x00000010
#define AM_REG_PWRCTRL_PWRONSTATUS_O 0x00000014
#define AM_REG_PWRCTRL_SRAMCTRL_O 0x00000018
#define AM_REG_PWRCTRL_ADCSTATUS_O 0x0000001C
#define AM_REG_PWRCTRL_MISCOPT_O 0x00000020
//*****************************************************************************
//
// PWRCTRL_SUPPLYSRC - Memory and Core Voltage Supply Source Select Register
//
//*****************************************************************************
// Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in
// DEEP SLEEP. If all the devices are off then this does not matter and LDO (low
// power mode) is used
#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_S 2
#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_M 0x00000004
#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN 0x00000004
// Enables and Selects the Core Buck as the supply for the low-voltage power
// domain.
#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_S 1
#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_M 0x00000002
#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_EN 0x00000002
// Enables and select the Memory Buck as the supply for the Flash and SRAM power
// domain.
#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_S 0
#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_M 0x00000001
#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN 0x00000001
//*****************************************************************************
//
// PWRCTRL_POWERSTATUS - Power Status Register for MCU supplies and peripherals
//
//*****************************************************************************
// Indicates whether the Core low-voltage domain is supplied from the LDO or the
// Buck.
#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_S 1
#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M 0x00000002
#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_LDO 0x00000000
#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_BUCK 0x00000002
// Indicate whether the Memory power domain is supplied from the LDO or the
// Buck.
#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_S 0
#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M 0x00000001
#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_LDO 0x00000000
#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_BUCK 0x00000001
//*****************************************************************************
//
// PWRCTRL_DEVICEEN - DEVICE ENABLES for SHELBY
//
//*****************************************************************************
// Enable PDM Digital Block
#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_S 10
#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_M 0x00000400
#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM(n) (((uint32_t)(n) << 10) & 0x00000400)
#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_EN 0x00000400
#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_DIS 0x00000000
// Enable ADC Digital Block
#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_S 9
#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_M 0x00000200
#define AM_REG_PWRCTRL_DEVICEEN_PWRADC(n) (((uint32_t)(n) << 9) & 0x00000200)
#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_EN 0x00000200
#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_DIS 0x00000000
// Enable UART 1
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_S 8
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_M 0x00000100
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1(n) (((uint32_t)(n) << 8) & 0x00000100)
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_EN 0x00000100
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_DIS 0x00000000
// Enable UART 0
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_S 7
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_M 0x00000080
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0(n) (((uint32_t)(n) << 7) & 0x00000080)
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_EN 0x00000080
#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_DIS 0x00000000
// Enable IO MASTER 5
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_S 6
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_M 0x00000040
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5(n) (((uint32_t)(n) << 6) & 0x00000040)
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN 0x00000040
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_DIS 0x00000000
// Enable IO MASTER 4
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_S 5
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_M 0x00000020
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN 0x00000020
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_DIS 0x00000000
// Enable IO MASTER 3
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_S 4
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_M 0x00000010
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN 0x00000010
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_DIS 0x00000000
// Enable IO MASTER 2
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_S 3
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_M 0x00000008
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN 0x00000008
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_DIS 0x00000000
// Enable IO MASTER 1
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_S 2
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_M 0x00000004
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN 0x00000004
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_DIS 0x00000000
// Enable IO MASTER 0
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_S 1
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_M 0x00000002
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN 0x00000002
#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_DIS 0x00000000
// Enable IO SLAVE
#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_S 0
#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_M 0x00000001
#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN 0x00000001
#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_DIS 0x00000000
//*****************************************************************************
//
// PWRCTRL_SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode
//
//*****************************************************************************
// Enable CACHE BANKS to power down in deep sleep
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_S 31
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_M 0x80000000
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP(n) (((uint32_t)(n) << 31) & 0x80000000)
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_EN 0x80000000
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_DIS 0x00000000
// Selects which SRAM banks are powered down in deep sleep mode, causing the
// contents of the bank to be lost.
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_S 0
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_M 0x000007FF
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN(n) (((uint32_t)(n) << 0) & 0x000007FF)
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_NONE 0x00000000
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM0 0x00000001
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM1 0x00000002
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM2 0x00000004
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM3 0x00000008
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP1 0x00000010
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP2 0x00000020
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP3 0x00000040
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP4 0x00000080
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP5 0x00000100
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP6 0x00000200
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP7 0x00000400
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM8K 0x00000001
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM16K 0x00000003
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM32K 0x0000000F
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM64K 0x0000001F
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM128K 0x0000007F
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER8K 0x000007FE
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER16K 0x000007FC
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER24K 0x000007F8
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER32K 0x000007F0
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER64K 0x000007E0
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER128K 0x00000780
#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALL 0x000007FF
//*****************************************************************************
//
// PWRCTRL_MEMEN - Disables individual banks of the MEMORY array
//
//*****************************************************************************
// Enable CACHE BANK 2
#define AM_REG_PWRCTRL_MEMEN_CACHEB2_S 31
#define AM_REG_PWRCTRL_MEMEN_CACHEB2_M 0x80000000
#define AM_REG_PWRCTRL_MEMEN_CACHEB2(n) (((uint32_t)(n) << 31) & 0x80000000)
#define AM_REG_PWRCTRL_MEMEN_CACHEB2_EN 0x80000000
#define AM_REG_PWRCTRL_MEMEN_CACHEB2_DIS 0x00000000
// Enable CACHE BANK 0
#define AM_REG_PWRCTRL_MEMEN_CACHEB0_S 29
#define AM_REG_PWRCTRL_MEMEN_CACHEB0_M 0x20000000
#define AM_REG_PWRCTRL_MEMEN_CACHEB0(n) (((uint32_t)(n) << 29) & 0x20000000)
#define AM_REG_PWRCTRL_MEMEN_CACHEB0_EN 0x20000000
#define AM_REG_PWRCTRL_MEMEN_CACHEB0_DIS 0x00000000
// Enable FLASH1
#define AM_REG_PWRCTRL_MEMEN_FLASH1_S 12
#define AM_REG_PWRCTRL_MEMEN_FLASH1_M 0x00001000
#define AM_REG_PWRCTRL_MEMEN_FLASH1(n) (((uint32_t)(n) << 12) & 0x00001000)
#define AM_REG_PWRCTRL_MEMEN_FLASH1_EN 0x00001000
#define AM_REG_PWRCTRL_MEMEN_FLASH1_DIS 0x00000000
// Enable FLASH 0
#define AM_REG_PWRCTRL_MEMEN_FLASH0_S 11
#define AM_REG_PWRCTRL_MEMEN_FLASH0_M 0x00000800
#define AM_REG_PWRCTRL_MEMEN_FLASH0(n) (((uint32_t)(n) << 11) & 0x00000800)
#define AM_REG_PWRCTRL_MEMEN_FLASH0_EN 0x00000800
#define AM_REG_PWRCTRL_MEMEN_FLASH0_DIS 0x00000000
// Enables power for selected SRAM banks (else an access to its address space to
// generate a Hard Fault).
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_S 0
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_M 0x000007FF
#define AM_REG_PWRCTRL_MEMEN_SRAMEN(n) (((uint32_t)(n) << 0) & 0x000007FF)
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_NONE 0x00000000
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 0x00000001
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 0x00000002
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2 0x00000004
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM3 0x00000008
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP1 0x00000010
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2 0x00000020
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP3 0x00000040
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 0x00000080
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5 0x00000100
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6 0x00000200
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP7 0x00000400
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K 0x00000001
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K 0x00000003
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K 0x0000000F
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K 0x0000001F
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K 0x0000007F
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K 0x000007FF
#define AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL 0x000007FF
//*****************************************************************************
//
// PWRCTRL_PWRONSTATUS - POWER ON Status
//
//*****************************************************************************
// This bit is 1 if power is supplied to CACHE BANK 2
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_S 21
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M 0x00200000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2(n) (((uint32_t)(n) << 21) & 0x00200000)
// This bit is 1 if power is supplied to CACHE BANK 0
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_S 19
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M 0x00080000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0(n) (((uint32_t)(n) << 19) & 0x00080000)
// This bit is 1 if power is supplied to SRAM domain PD_GRP7
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_S 18
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M 0x00040000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM(n) (((uint32_t)(n) << 18) & 0x00040000)
// This bit is 1 if power is supplied to SRAM domain PD_GRP6
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_S 17
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M 0x00020000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM(n) (((uint32_t)(n) << 17) & 0x00020000)
// This bit is 1 if power is supplied to SRAM domain PD_GRP5
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_S 16
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M 0x00010000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM(n) (((uint32_t)(n) << 16) & 0x00010000)
// This bit is 1 if power is supplied to SRAM domain PD_GRP4
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_S 15
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M 0x00008000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM(n) (((uint32_t)(n) << 15) & 0x00008000)
// This bit is 1 if power is supplied to SRAM domain PD_GRP3
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_S 14
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M 0x00004000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM(n) (((uint32_t)(n) << 14) & 0x00004000)
// This bit is 1 if power is supplied to SRAM domain PD_GRP2
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_S 13
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M 0x00002000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM(n) (((uint32_t)(n) << 13) & 0x00002000)
// This bit is 1 if power is supplied to SRAM domain PD_GRP1
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_S 12
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M 0x00001000
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM(n) (((uint32_t)(n) << 12) & 0x00001000)
// This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_S 11
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M 0x00000800
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3(n) (((uint32_t)(n) << 11) & 0x00000800)
// This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_S 10
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M 0x00000400
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2(n) (((uint32_t)(n) << 10) & 0x00000400)
// This bit is 1 if power is supplied to SRAM domain SRAM0_1
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_S 9
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M 0x00000200
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1(n) (((uint32_t)(n) << 9) & 0x00000200)
// This bit is 1 if power is supplied to SRAM domain SRAM0_0
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_S 8
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M 0x00000100
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0(n) (((uint32_t)(n) << 8) & 0x00000100)
// This bit is 1 if power is supplied to domain PD_ADC
#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_S 7
#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M 0x00000080
#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC(n) (((uint32_t)(n) << 7) & 0x00000080)
// This bit is 1 if power is supplied to domain PD_FLAM1
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_S 6
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M 0x00000040
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1(n) (((uint32_t)(n) << 6) & 0x00000040)
// This bit is 1 if power is supplied to domain PD_FLAM0
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_S 5
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M 0x00000020
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0(n) (((uint32_t)(n) << 5) & 0x00000020)
// This bit is 1 if power is supplied to domain PD_PDM
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_S 4
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M 0x00000010
#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM(n) (((uint32_t)(n) << 4) & 0x00000010)
// This bit is 1 if power is supplied to power domain C, which supplies IOM3-5.
#define AM_REG_PWRCTRL_PWRONSTATUS_PDC_S 3
#define AM_REG_PWRCTRL_PWRONSTATUS_PDC_M 0x00000008
#define AM_REG_PWRCTRL_PWRONSTATUS_PDC(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit is 1 if power is supplied to power domain B, which supplies IOM0-2.
#define AM_REG_PWRCTRL_PWRONSTATUS_PDB_S 2
#define AM_REG_PWRCTRL_PWRONSTATUS_PDB_M 0x00000004
#define AM_REG_PWRCTRL_PWRONSTATUS_PDB(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit is 1 if power is supplied to power domain A, which supplies IOS and
// UART0,1.
#define AM_REG_PWRCTRL_PWRONSTATUS_PDA_S 1
#define AM_REG_PWRCTRL_PWRONSTATUS_PDA_M 0x00000002
#define AM_REG_PWRCTRL_PWRONSTATUS_PDA(n) (((uint32_t)(n) << 1) & 0x00000002)
//*****************************************************************************
//
// PWRCTRL_SRAMCTRL - SRAM Control register
//
//*****************************************************************************
// Enables top-level clock gating in the SRAM block. This bit should be enabled
// for lowest power operation.
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_S 2
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_M 0x00000004
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN 0x00000004
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_DIS 0x00000000
// Enables individual per-RAM clock gating in the SRAM block. This bit should
// be enabled for lowest power operation.
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_S 1
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_M 0x00000002
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN 0x00000002
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_DIS 0x00000000
// Enable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will
// be put into light sleep mode while inactive. NOTE: if the SRAM is actively
// used, this may have an adverse affect on power since entering/exiting LS mode
// may consume more power than would be saved.
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_S 0
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_M 0x00000001
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_EN 0x00000001
#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS 0x00000000
//*****************************************************************************
//
// PWRCTRL_ADCSTATUS - Power Status Register for ADC Block
//
//*****************************************************************************
// This bit indicates that the ADC REFBUF is powered down
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_S 5
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_M 0x00000020
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD(n) (((uint32_t)(n) << 5) & 0x00000020)
// This bit indicates that the ADC REFKEEP is powered down
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_S 4
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_M 0x00000010
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD(n) (((uint32_t)(n) << 4) & 0x00000010)
// This bit indicates that the ADC VBAT resistor divider is powered down
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_S 3
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_M 0x00000008
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit indicates that the ADC temperature sensor input buffer is powered
// down
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_S 2
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_M 0x00000004
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit indicates that the ADC Band Gap is powered down
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_S 1
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_M 0x00000002
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit indicates that the ADC is powered down
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_S 0
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_M 0x00000001
#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// PWRCTRL_MISCOPT - Power Optimization Control Bits
//
//*****************************************************************************
// Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep
// even when the ctimers or stimers are running
#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_S 2
#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_M 0x00000004
#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS(n) (((uint32_t)(n) << 2) & 0x00000004)
#endif // AM_REG_PWRCTRL_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_rstgen.h
+215
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//*****************************************************************************
//
// am_reg_rstgen.h
//! @file
//!
//! @brief Register macros for the RSTGEN module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_RSTGEN_H
#define AM_REG_RSTGEN_H
//*****************************************************************************
//
// RSTGEN
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_RSTGEN_NUM_MODULES 1
#define AM_REG_RSTGENn(n) \
(REG_RSTGEN_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_RSTGEN_CFG_O 0x00000000
#define AM_REG_RSTGEN_SWPOI_O 0x00000004
#define AM_REG_RSTGEN_SWPOR_O 0x00000008
#define AM_REG_RSTGEN_STAT_O 0x0000000C
#define AM_REG_RSTGEN_CLRSTAT_O 0x00000010
#define AM_REG_RSTGEN_TPIU_RST_O 0x00000014
#define AM_REG_RSTGEN_INTEN_O 0x00000200
#define AM_REG_RSTGEN_INTSTAT_O 0x00000204
#define AM_REG_RSTGEN_INTCLR_O 0x00000208
#define AM_REG_RSTGEN_INTSET_O 0x0000020C
//*****************************************************************************
//
// RSTGEN_INTEN - Reset Interrupt register: Enable
//
//*****************************************************************************
// Enables an interrupt that triggers when VCC is below BODH level.
#define AM_REG_RSTGEN_INTEN_BODH_S 0
#define AM_REG_RSTGEN_INTEN_BODH_M 0x00000001
#define AM_REG_RSTGEN_INTEN_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RSTGEN_INTSTAT - Reset Interrupt register: Status
//
//*****************************************************************************
// Enables an interrupt that triggers when VCC is below BODH level.
#define AM_REG_RSTGEN_INTSTAT_BODH_S 0
#define AM_REG_RSTGEN_INTSTAT_BODH_M 0x00000001
#define AM_REG_RSTGEN_INTSTAT_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RSTGEN_INTCLR - Reset Interrupt register: Clear
//
//*****************************************************************************
// Enables an interrupt that triggers when VCC is below BODH level.
#define AM_REG_RSTGEN_INTCLR_BODH_S 0
#define AM_REG_RSTGEN_INTCLR_BODH_M 0x00000001
#define AM_REG_RSTGEN_INTCLR_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RSTGEN_INTSET - Reset Interrupt register: Set
//
//*****************************************************************************
// Enables an interrupt that triggers when VCC is below BODH level.
#define AM_REG_RSTGEN_INTSET_BODH_S 0
#define AM_REG_RSTGEN_INTSET_BODH_M 0x00000001
#define AM_REG_RSTGEN_INTSET_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RSTGEN_CFG - Configuration Register
//
//*****************************************************************************
// Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured
// for WDT reset.
#define AM_REG_RSTGEN_CFG_WDREN_S 1
#define AM_REG_RSTGEN_CFG_WDREN_M 0x00000002
#define AM_REG_RSTGEN_CFG_WDREN(n) (((uint32_t)(n) << 1) & 0x00000002)
// Brown out high (2.1v) reset enable.
#define AM_REG_RSTGEN_CFG_BODHREN_S 0
#define AM_REG_RSTGEN_CFG_BODHREN_M 0x00000001
#define AM_REG_RSTGEN_CFG_BODHREN(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RSTGEN_SWPOI - Software POI Reset
//
//*****************************************************************************
// 0x1B generates a software POI reset.
#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_S 0
#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_M 0x000000FF
#define AM_REG_RSTGEN_SWPOI_SWPOIKEY(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE 0x0000001B
//*****************************************************************************
//
// RSTGEN_SWPOR - Software POR Reset
//
//*****************************************************************************
// 0xD4 generates a software POR reset.
#define AM_REG_RSTGEN_SWPOR_SWPORKEY_S 0
#define AM_REG_RSTGEN_SWPOR_SWPORKEY_M 0x000000FF
#define AM_REG_RSTGEN_SWPOR_SWPORKEY(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE 0x000000D4
//*****************************************************************************
//
// RSTGEN_STAT - Status Register
//
//*****************************************************************************
// Reset was initiated by a Watchdog Timer Reset.
#define AM_REG_RSTGEN_STAT_WDRSTAT_S 6
#define AM_REG_RSTGEN_STAT_WDRSTAT_M 0x00000040
#define AM_REG_RSTGEN_STAT_WDRSTAT(n) (((uint32_t)(n) << 6) & 0x00000040)
// Reset was a initiated by Debugger Reset.
#define AM_REG_RSTGEN_STAT_DBGRSTAT_S 5
#define AM_REG_RSTGEN_STAT_DBGRSTAT_M 0x00000020
#define AM_REG_RSTGEN_STAT_DBGRSTAT(n) (((uint32_t)(n) << 5) & 0x00000020)
// Reset was a initiated by Software POI Reset.
#define AM_REG_RSTGEN_STAT_POIRSTAT_S 4
#define AM_REG_RSTGEN_STAT_POIRSTAT_M 0x00000010
#define AM_REG_RSTGEN_STAT_POIRSTAT(n) (((uint32_t)(n) << 4) & 0x00000010)
// Reset was a initiated by SW POR or AIRCR Reset.
#define AM_REG_RSTGEN_STAT_SWRSTAT_S 3
#define AM_REG_RSTGEN_STAT_SWRSTAT_M 0x00000008
#define AM_REG_RSTGEN_STAT_SWRSTAT(n) (((uint32_t)(n) << 3) & 0x00000008)
// Reset was initiated by a Brown-Out Reset.
#define AM_REG_RSTGEN_STAT_BORSTAT_S 2
#define AM_REG_RSTGEN_STAT_BORSTAT_M 0x00000004
#define AM_REG_RSTGEN_STAT_BORSTAT(n) (((uint32_t)(n) << 2) & 0x00000004)
// Reset was initiated by a Power-On Reset.
#define AM_REG_RSTGEN_STAT_PORSTAT_S 1
#define AM_REG_RSTGEN_STAT_PORSTAT_M 0x00000002
#define AM_REG_RSTGEN_STAT_PORSTAT(n) (((uint32_t)(n) << 1) & 0x00000002)
// Reset was initiated by an External Reset.
#define AM_REG_RSTGEN_STAT_EXRSTAT_S 0
#define AM_REG_RSTGEN_STAT_EXRSTAT_M 0x00000001
#define AM_REG_RSTGEN_STAT_EXRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RSTGEN_CLRSTAT - Clear the status register
//
//*****************************************************************************
// Writing a 1 to this bit clears all bits in the RST_STAT.
#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_S 0
#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_M 0x00000001
#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RSTGEN_TPIU_RST - TPIU reset
//
//*****************************************************************************
// Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0'
// to clear the reset.
#define AM_REG_RSTGEN_TPIU_RST_TPIURST_S 0
#define AM_REG_RSTGEN_TPIU_RST_TPIURST_M 0x00000001
#define AM_REG_RSTGEN_TPIU_RST_TPIURST(n) (((uint32_t)(n) << 0) & 0x00000001)
#endif // AM_REG_RSTGEN_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_rtc.h
+330
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//*****************************************************************************
//
// am_reg_rtc.h
//! @file
//!
//! @brief Register macros for the RTC module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_RTC_H
#define AM_REG_RTC_H
//*****************************************************************************
//
// RTC
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_RTC_NUM_MODULES 1
#define AM_REG_RTCn(n) \
(REG_RTC_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_RTC_CTRLOW_O 0x00000000
#define AM_REG_RTC_CTRUP_O 0x00000004
#define AM_REG_RTC_ALMLOW_O 0x00000008
#define AM_REG_RTC_ALMUP_O 0x0000000C
#define AM_REG_RTC_RTCCTL_O 0x00000010
#define AM_REG_RTC_INTEN_O 0x000000C0
#define AM_REG_RTC_INTSTAT_O 0x000000C4
#define AM_REG_RTC_INTCLR_O 0x000000C8
#define AM_REG_RTC_INTSET_O 0x000000CC
//*****************************************************************************
//
// RTC_INTEN - RTC Interrupt Register: Enable
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_RTC_INTEN_ALM_S 3
#define AM_REG_RTC_INTEN_ALM_M 0x00000008
#define AM_REG_RTC_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_RTC_INTEN_OF_S 2
#define AM_REG_RTC_INTEN_OF_M 0x00000004
#define AM_REG_RTC_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_RTC_INTEN_ACC_S 1
#define AM_REG_RTC_INTEN_ACC_M 0x00000002
#define AM_REG_RTC_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_RTC_INTEN_ACF_S 0
#define AM_REG_RTC_INTEN_ACF_M 0x00000001
#define AM_REG_RTC_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RTC_INTSTAT - RTC Interrupt Register: Status
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_RTC_INTSTAT_ALM_S 3
#define AM_REG_RTC_INTSTAT_ALM_M 0x00000008
#define AM_REG_RTC_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_RTC_INTSTAT_OF_S 2
#define AM_REG_RTC_INTSTAT_OF_M 0x00000004
#define AM_REG_RTC_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_RTC_INTSTAT_ACC_S 1
#define AM_REG_RTC_INTSTAT_ACC_M 0x00000002
#define AM_REG_RTC_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_RTC_INTSTAT_ACF_S 0
#define AM_REG_RTC_INTSTAT_ACF_M 0x00000001
#define AM_REG_RTC_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RTC_INTCLR - RTC Interrupt Register: Clear
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_RTC_INTCLR_ALM_S 3
#define AM_REG_RTC_INTCLR_ALM_M 0x00000008
#define AM_REG_RTC_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_RTC_INTCLR_OF_S 2
#define AM_REG_RTC_INTCLR_OF_M 0x00000004
#define AM_REG_RTC_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_RTC_INTCLR_ACC_S 1
#define AM_REG_RTC_INTCLR_ACC_M 0x00000002
#define AM_REG_RTC_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_RTC_INTCLR_ACF_S 0
#define AM_REG_RTC_INTCLR_ACF_M 0x00000001
#define AM_REG_RTC_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RTC_INTSET - RTC Interrupt Register: Set
//
//*****************************************************************************
// RTC Alarm interrupt
#define AM_REG_RTC_INTSET_ALM_S 3
#define AM_REG_RTC_INTSET_ALM_M 0x00000008
#define AM_REG_RTC_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
// XT Oscillator Fail interrupt
#define AM_REG_RTC_INTSET_OF_S 2
#define AM_REG_RTC_INTSET_OF_M 0x00000004
#define AM_REG_RTC_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
// Autocalibration Complete interrupt
#define AM_REG_RTC_INTSET_ACC_S 1
#define AM_REG_RTC_INTSET_ACC_M 0x00000002
#define AM_REG_RTC_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
// Autocalibration Fail interrupt
#define AM_REG_RTC_INTSET_ACF_S 0
#define AM_REG_RTC_INTSET_ACF_M 0x00000001
#define AM_REG_RTC_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// RTC_CTRLOW - RTC Counters Lower
//
//*****************************************************************************
// Hours Counter
#define AM_REG_RTC_CTRLOW_CTRHR_S 24
#define AM_REG_RTC_CTRLOW_CTRHR_M 0x3F000000
#define AM_REG_RTC_CTRLOW_CTRHR(n) (((uint32_t)(n) << 24) & 0x3F000000)
// Minutes Counter
#define AM_REG_RTC_CTRLOW_CTRMIN_S 16
#define AM_REG_RTC_CTRLOW_CTRMIN_M 0x007F0000
#define AM_REG_RTC_CTRLOW_CTRMIN(n) (((uint32_t)(n) << 16) & 0x007F0000)
// Seconds Counter
#define AM_REG_RTC_CTRLOW_CTRSEC_S 8
#define AM_REG_RTC_CTRLOW_CTRSEC_M 0x00007F00
#define AM_REG_RTC_CTRLOW_CTRSEC(n) (((uint32_t)(n) << 8) & 0x00007F00)
// 100ths of a second Counter
#define AM_REG_RTC_CTRLOW_CTR100_S 0
#define AM_REG_RTC_CTRLOW_CTR100_M 0x000000FF
#define AM_REG_RTC_CTRLOW_CTR100(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// RTC_CTRUP - RTC Counters Upper
//
//*****************************************************************************
// Counter read error status
#define AM_REG_RTC_CTRUP_CTERR_S 31
#define AM_REG_RTC_CTRUP_CTERR_M 0x80000000
#define AM_REG_RTC_CTRUP_CTERR(n) (((uint32_t)(n) << 31) & 0x80000000)
#define AM_REG_RTC_CTRUP_CTERR_NOERR 0x00000000
#define AM_REG_RTC_CTRUP_CTERR_RDERR 0x80000000
// Century enable
#define AM_REG_RTC_CTRUP_CEB_S 28
#define AM_REG_RTC_CTRUP_CEB_M 0x10000000
#define AM_REG_RTC_CTRUP_CEB(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_RTC_CTRUP_CEB_DIS 0x00000000
#define AM_REG_RTC_CTRUP_CEB_EN 0x10000000
// Century
#define AM_REG_RTC_CTRUP_CB_S 27
#define AM_REG_RTC_CTRUP_CB_M 0x08000000
#define AM_REG_RTC_CTRUP_CB(n) (((uint32_t)(n) << 27) & 0x08000000)
#define AM_REG_RTC_CTRUP_CB_2000 0x00000000
#define AM_REG_RTC_CTRUP_CB_1900_2100 0x08000000
// Weekdays Counter
#define AM_REG_RTC_CTRUP_CTRWKDY_S 24
#define AM_REG_RTC_CTRUP_CTRWKDY_M 0x07000000
#define AM_REG_RTC_CTRUP_CTRWKDY(n) (((uint32_t)(n) << 24) & 0x07000000)
// Years Counter
#define AM_REG_RTC_CTRUP_CTRYR_S 16
#define AM_REG_RTC_CTRUP_CTRYR_M 0x00FF0000
#define AM_REG_RTC_CTRUP_CTRYR(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Months Counter
#define AM_REG_RTC_CTRUP_CTRMO_S 8
#define AM_REG_RTC_CTRUP_CTRMO_M 0x00001F00
#define AM_REG_RTC_CTRUP_CTRMO(n) (((uint32_t)(n) << 8) & 0x00001F00)
// Date Counter
#define AM_REG_RTC_CTRUP_CTRDATE_S 0
#define AM_REG_RTC_CTRUP_CTRDATE_M 0x0000003F
#define AM_REG_RTC_CTRUP_CTRDATE(n) (((uint32_t)(n) << 0) & 0x0000003F)
//*****************************************************************************
//
// RTC_ALMLOW - RTC Alarms Lower
//
//*****************************************************************************
// Hours Alarm
#define AM_REG_RTC_ALMLOW_ALMHR_S 24
#define AM_REG_RTC_ALMLOW_ALMHR_M 0x3F000000
#define AM_REG_RTC_ALMLOW_ALMHR(n) (((uint32_t)(n) << 24) & 0x3F000000)
// Minutes Alarm
#define AM_REG_RTC_ALMLOW_ALMMIN_S 16
#define AM_REG_RTC_ALMLOW_ALMMIN_M 0x007F0000
#define AM_REG_RTC_ALMLOW_ALMMIN(n) (((uint32_t)(n) << 16) & 0x007F0000)
// Seconds Alarm
#define AM_REG_RTC_ALMLOW_ALMSEC_S 8
#define AM_REG_RTC_ALMLOW_ALMSEC_M 0x00007F00
#define AM_REG_RTC_ALMLOW_ALMSEC(n) (((uint32_t)(n) << 8) & 0x00007F00)
// 100ths of a second Alarm
#define AM_REG_RTC_ALMLOW_ALM100_S 0
#define AM_REG_RTC_ALMLOW_ALM100_M 0x000000FF
#define AM_REG_RTC_ALMLOW_ALM100(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// RTC_ALMUP - RTC Alarms Upper
//
//*****************************************************************************
// Weekdays Alarm
#define AM_REG_RTC_ALMUP_ALMWKDY_S 16
#define AM_REG_RTC_ALMUP_ALMWKDY_M 0x00070000
#define AM_REG_RTC_ALMUP_ALMWKDY(n) (((uint32_t)(n) << 16) & 0x00070000)
// Months Alarm
#define AM_REG_RTC_ALMUP_ALMMO_S 8
#define AM_REG_RTC_ALMUP_ALMMO_M 0x00001F00
#define AM_REG_RTC_ALMUP_ALMMO(n) (((uint32_t)(n) << 8) & 0x00001F00)
// Date Alarm
#define AM_REG_RTC_ALMUP_ALMDATE_S 0
#define AM_REG_RTC_ALMUP_ALMDATE_M 0x0000003F
#define AM_REG_RTC_ALMUP_ALMDATE(n) (((uint32_t)(n) << 0) & 0x0000003F)
//*****************************************************************************
//
// RTC_RTCCTL - RTC Control Register
//
//*****************************************************************************
// Hours Counter mode
#define AM_REG_RTC_RTCCTL_HR1224_S 5
#define AM_REG_RTC_RTCCTL_HR1224_M 0x00000020
#define AM_REG_RTC_RTCCTL_HR1224(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_RTC_RTCCTL_HR1224_24HR 0x00000000
#define AM_REG_RTC_RTCCTL_HR1224_12HR 0x00000020
// RTC input clock control
#define AM_REG_RTC_RTCCTL_RSTOP_S 4
#define AM_REG_RTC_RTCCTL_RSTOP_M 0x00000010
#define AM_REG_RTC_RTCCTL_RSTOP(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_RTC_RTCCTL_RSTOP_RUN 0x00000000
#define AM_REG_RTC_RTCCTL_RSTOP_STOP 0x00000010
// Alarm repeat interval
#define AM_REG_RTC_RTCCTL_RPT_S 1
#define AM_REG_RTC_RTCCTL_RPT_M 0x0000000E
#define AM_REG_RTC_RTCCTL_RPT(n) (((uint32_t)(n) << 1) & 0x0000000E)
#define AM_REG_RTC_RTCCTL_RPT_DIS 0x00000000
#define AM_REG_RTC_RTCCTL_RPT_YEAR 0x00000002
#define AM_REG_RTC_RTCCTL_RPT_MONTH 0x00000004
#define AM_REG_RTC_RTCCTL_RPT_WEEK 0x00000006
#define AM_REG_RTC_RTCCTL_RPT_DAY 0x00000008
#define AM_REG_RTC_RTCCTL_RPT_HR 0x0000000A
#define AM_REG_RTC_RTCCTL_RPT_MIN 0x0000000C
#define AM_REG_RTC_RTCCTL_RPT_SEC 0x0000000E
// Counter write control
#define AM_REG_RTC_RTCCTL_WRTC_S 0
#define AM_REG_RTC_RTCCTL_WRTC_M 0x00000001
#define AM_REG_RTC_RTCCTL_WRTC(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_RTC_RTCCTL_WRTC_DIS 0x00000000
#define AM_REG_RTC_RTCCTL_WRTC_EN 0x00000001
#endif // AM_REG_RTC_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_sysctrl.h
+700
View File
@@ -0,0 +1,700 @@
//*****************************************************************************
//
// am_reg_sysctrl.h
//! @file
//!
//! @brief Register macros for the SYSCTRL module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_SYSCTRL_H
#define AM_REG_SYSCTRL_H
//*****************************************************************************
//
// SYSCTRL
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_SYSCTRL_NUM_MODULES 1
#define AM_REG_SYSCTRLn(n) \
(REG_SYSCTRL_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_SYSCTRL_ICTR_O 0xE000E004
#define AM_REG_SYSCTRL_ACTLR_O 0xE000E008
#define AM_REG_SYSCTRL_ICSR_O 0xE000ED04
#define AM_REG_SYSCTRL_VTOR_O 0xE000ED08
#define AM_REG_SYSCTRL_AIRCR_O 0xE000ED0C
#define AM_REG_SYSCTRL_SCR_O 0xE000ED10
#define AM_REG_SYSCTRL_CCR_O 0xE000ED14
#define AM_REG_SYSCTRL_SHPR1_O 0xE000ED18
#define AM_REG_SYSCTRL_SHPR2_O 0xE000ED1C
#define AM_REG_SYSCTRL_SHPR3_O 0xE000ED20
#define AM_REG_SYSCTRL_SHCSR_O 0xE000ED24
#define AM_REG_SYSCTRL_CFSR_O 0xE000ED28
#define AM_REG_SYSCTRL_HFSR_O 0xE000ED2C
#define AM_REG_SYSCTRL_MMFAR_O 0xE000ED34
#define AM_REG_SYSCTRL_BFAR_O 0xE000ED38
#define AM_REG_SYSCTRL_CPACR_O 0xE000ED88
#define AM_REG_SYSCTRL_DEMCR_O 0xE000EDFC
#define AM_REG_SYSCTRL_STIR_O 0xE000EF00
#define AM_REG_SYSCTRL_FPCCR_O 0xE000EF34
#define AM_REG_SYSCTRL_FPCAR_O 0xE000EF38
#define AM_REG_SYSCTRL_FPDSCR_O 0xE000EF3C
//*****************************************************************************
//
// SYSCTRL_ICTR - Interrupt Controller Type Register (NVIC)
//
//*****************************************************************************
// Total number of interrupt lines in groups of 32.
#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_S 0
#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_M 0x0000000F
#define AM_REG_SYSCTRL_ICTR_INTLINESNUM(n) (((uint32_t)(n) << 0) & 0x0000000F)
//*****************************************************************************
//
// SYSCTRL_ACTLR - Auxilliary Control Register
//
//*****************************************************************************
// Disables lazy stacking of floating point context.
#define AM_REG_SYSCTRL_ACTLR_DISFPCA_S 9
#define AM_REG_SYSCTRL_ACTLR_DISFPCA_M 0x00000200
#define AM_REG_SYSCTRL_ACTLR_DISFPCA(n) (((uint32_t)(n) << 9) & 0x00000200)
// Disables floating point instructions completing out of order with respect to
// integer instructions.
#define AM_REG_SYSCTRL_ACTLR_DISOOFP_S 8
#define AM_REG_SYSCTRL_ACTLR_DISOOFP_M 0x00000100
#define AM_REG_SYSCTRL_ACTLR_DISOOFP(n) (((uint32_t)(n) << 8) & 0x00000100)
// Disables folding of IT instructions.
#define AM_REG_SYSCTRL_ACTLR_DISFOLD_S 2
#define AM_REG_SYSCTRL_ACTLR_DISFOLD_M 0x00000004
#define AM_REG_SYSCTRL_ACTLR_DISFOLD(n) (((uint32_t)(n) << 2) & 0x00000004)
// Disables write buffer use during default memory map accesses.
#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_S 1
#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_M 0x00000002
#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF(n) (((uint32_t)(n) << 1) & 0x00000002)
// Disables interruption of multi-cycle instructions.
#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_S 0
#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_M 0x00000001
#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSCTRL_ICSR - Interrupt Control and State Register
//
//*****************************************************************************
// Pend an NMI exception.
#define AM_REG_SYSCTRL_ICSR_NMIPENDSET_S 31
#define AM_REG_SYSCTRL_ICSR_NMIPENDSET_M 0x80000000
#define AM_REG_SYSCTRL_ICSR_NMIPENDSET(n) (((uint32_t)(n) << 31) & 0x80000000)
// Set the PendSV interrupt as pending.
#define AM_REG_SYSCTRL_ICSR_PENDSVSET_S 28
#define AM_REG_SYSCTRL_ICSR_PENDSVSET_M 0x10000000
#define AM_REG_SYSCTRL_ICSR_PENDSVSET(n) (((uint32_t)(n) << 28) & 0x10000000)
// Remove the pending status of the PendSV exception.
#define AM_REG_SYSCTRL_ICSR_PENDSVCLR_S 27
#define AM_REG_SYSCTRL_ICSR_PENDSVCLR_M 0x08000000
#define AM_REG_SYSCTRL_ICSR_PENDSVCLR(n) (((uint32_t)(n) << 27) & 0x08000000)
// Set the SysTick exception as pending.
#define AM_REG_SYSCTRL_ICSR_PENDSTSET_S 26
#define AM_REG_SYSCTRL_ICSR_PENDSTSET_M 0x04000000
#define AM_REG_SYSCTRL_ICSR_PENDSTSET(n) (((uint32_t)(n) << 26) & 0x04000000)
// Remove the pending status of the SysTick exception.
#define AM_REG_SYSCTRL_ICSR_PENDSTCLR_S 25
#define AM_REG_SYSCTRL_ICSR_PENDSTCLR_M 0x02000000
#define AM_REG_SYSCTRL_ICSR_PENDSTCLR(n) (((uint32_t)(n) << 25) & 0x02000000)
// Indicates whether a pending exception will be serviced on exit from debug
// halt state.
#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_S 23
#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_M 0x00800000
#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT(n) (((uint32_t)(n) << 23) & 0x00800000)
// Indicates whether an external interrupt, generated by the NVIC, is pending.
#define AM_REG_SYSCTRL_ICSR_ISRPENDING_S 22
#define AM_REG_SYSCTRL_ICSR_ISRPENDING_M 0x00400000
#define AM_REG_SYSCTRL_ICSR_ISRPENDING(n) (((uint32_t)(n) << 22) & 0x00400000)
// The exception number of the highest priority pending exception.
#define AM_REG_SYSCTRL_ICSR_VECTPENDING_S 12
#define AM_REG_SYSCTRL_ICSR_VECTPENDING_M 0x001FF000
#define AM_REG_SYSCTRL_ICSR_VECTPENDING(n) (((uint32_t)(n) << 12) & 0x001FF000)
// Indicates whether there is an active exception other than the exception shown
// by IPSR.
#define AM_REG_SYSCTRL_ICSR_RETTOBASE_S 11
#define AM_REG_SYSCTRL_ICSR_RETTOBASE_M 0x00000800
#define AM_REG_SYSCTRL_ICSR_RETTOBASE(n) (((uint32_t)(n) << 11) & 0x00000800)
// The exception number of the current executing exception.
#define AM_REG_SYSCTRL_ICSR_VECTACTIVE_S 0
#define AM_REG_SYSCTRL_ICSR_VECTACTIVE_M 0x000001FF
#define AM_REG_SYSCTRL_ICSR_VECTACTIVE(n) (((uint32_t)(n) << 0) & 0x000001FF)
//*****************************************************************************
//
// SYSCTRL_VTOR - Vector Table Offset Register.
//
//*****************************************************************************
// Vector table base address.
#define AM_REG_SYSCTRL_VTOR_VALUE_S 0
#define AM_REG_SYSCTRL_VTOR_VALUE_M 0xFFFFFFFF
#define AM_REG_SYSCTRL_VTOR_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// SYSCTRL_AIRCR - Application Interrupt and Reset Control Register.
//
//*****************************************************************************
// Register writes must write 0x5FA to this field, otherwise the write is
// ignored.
#define AM_REG_SYSCTRL_AIRCR_VECTKEY_S 16
#define AM_REG_SYSCTRL_AIRCR_VECTKEY_M 0xFFFF0000
#define AM_REG_SYSCTRL_AIRCR_VECTKEY(n) (((uint32_t)(n) << 16) & 0xFFFF0000)
// Indicates endianness of memory architecture. (Little = 0, Big = 1)
#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_S 15
#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_M 0x00008000
#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS(n) (((uint32_t)(n) << 15) & 0x00008000)
// Priority grouping, indicates the binary point position.
#define AM_REG_SYSCTRL_AIRCR_PRIGROUP_S 8
#define AM_REG_SYSCTRL_AIRCR_PRIGROUP_M 0x00000700
#define AM_REG_SYSCTRL_AIRCR_PRIGROUP(n) (((uint32_t)(n) << 8) & 0x00000700)
// Writing a 1 to this bit reqests a local reset.
#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_S 2
#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_M 0x00000004
#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(n) (((uint32_t)(n) << 2) & 0x00000004)
// Writing a 1 to this bit clears all active state information for fixed and
// configurable exceptions.
#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_S 1
#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_M 0x00000002
#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE(n) (((uint32_t)(n) << 1) & 0x00000002)
// Writing a 1 to this bit causes a local system reset.
#define AM_REG_SYSCTRL_AIRCR_VECTRESET_S 0
#define AM_REG_SYSCTRL_AIRCR_VECTRESET_M 0x00000001
#define AM_REG_SYSCTRL_AIRCR_VECTRESET(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSCTRL_SCR - System Control Register.
//
//*****************************************************************************
// Determines whether a pending interrupt is a wakeup event.
#define AM_REG_SYSCTRL_SCR_SEVONPEND_S 4
#define AM_REG_SYSCTRL_SCR_SEVONPEND_M 0x00000010
#define AM_REG_SYSCTRL_SCR_SEVONPEND(n) (((uint32_t)(n) << 4) & 0x00000010)
// Determines whether the sleep mode should be regular or deep sleep
#define AM_REG_SYSCTRL_SCR_SLEEPDEEP_S 2
#define AM_REG_SYSCTRL_SCR_SLEEPDEEP_M 0x00000004
#define AM_REG_SYSCTRL_SCR_SLEEPDEEP(n) (((uint32_t)(n) << 2) & 0x00000004)
// Determines whether the processor shoudl automatically sleep when an ISR
// returns to the base-level.
#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_S 1
#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_M 0x00000002
#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT(n) (((uint32_t)(n) << 1) & 0x00000002)
//*****************************************************************************
//
// SYSCTRL_CCR - Configuration and Control Register.
//
//*****************************************************************************
// Set to force 8-byte alignment for the stack pointer.
#define AM_REG_SYSCTRL_CCR_STKALIGN_S 9
#define AM_REG_SYSCTRL_CCR_STKALIGN_M 0x00000200
#define AM_REG_SYSCTRL_CCR_STKALIGN(n) (((uint32_t)(n) << 9) & 0x00000200)
// Set to ignore precise data access faults during hard fault handlers.
#define AM_REG_SYSCTRL_CCR_BFHFNMIGN_S 8
#define AM_REG_SYSCTRL_CCR_BFHFNMIGN_M 0x00000100
#define AM_REG_SYSCTRL_CCR_BFHFNMIGN(n) (((uint32_t)(n) << 8) & 0x00000100)
// Set to enable trapping on divide-by-zero.
#define AM_REG_SYSCTRL_CCR_DIV0TRP_S 4
#define AM_REG_SYSCTRL_CCR_DIV0TRP_M 0x00000010
#define AM_REG_SYSCTRL_CCR_DIV0TRP(n) (((uint32_t)(n) << 4) & 0x00000010)
// Set to enable trapping of unaligned word or halfword accesses.
#define AM_REG_SYSCTRL_CCR_UNALIGNTRP_S 3
#define AM_REG_SYSCTRL_CCR_UNALIGNTRP_M 0x00000008
#define AM_REG_SYSCTRL_CCR_UNALIGNTRP(n) (((uint32_t)(n) << 3) & 0x00000008)
// Set to allow unpriveleged software to access the STIR
#define AM_REG_SYSCTRL_CCR_USERSETMPEND_S 1
#define AM_REG_SYSCTRL_CCR_USERSETMPEND_M 0x00000002
#define AM_REG_SYSCTRL_CCR_USERSETMPEND(n) (((uint32_t)(n) << 1) & 0x00000002)
// Set to enable the processor to enter Thread mode at an execution priority
// other than base level.
#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_S 0
#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_M 0x00000001
#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSCTRL_SHPR1 - System Handler Priority Register 1.
//
//*****************************************************************************
// Reserved for priority of system handler 7.
#define AM_REG_SYSCTRL_SHPR1_PRI_7_S 24
#define AM_REG_SYSCTRL_SHPR1_PRI_7_M 0xFF000000
#define AM_REG_SYSCTRL_SHPR1_PRI_7(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority of system handler 6, UsageFault.
#define AM_REG_SYSCTRL_SHPR1_PRI_6_S 16
#define AM_REG_SYSCTRL_SHPR1_PRI_6_M 0x00FF0000
#define AM_REG_SYSCTRL_SHPR1_PRI_6(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Priority of system handler 5, BusFault.
#define AM_REG_SYSCTRL_SHPR1_PRI_5_S 8
#define AM_REG_SYSCTRL_SHPR1_PRI_5_M 0x0000FF00
#define AM_REG_SYSCTRL_SHPR1_PRI_5(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority of system handler 4, MemManage.
#define AM_REG_SYSCTRL_SHPR1_PRI_4_S 0
#define AM_REG_SYSCTRL_SHPR1_PRI_4_M 0x000000FF
#define AM_REG_SYSCTRL_SHPR1_PRI_4(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// SYSCTRL_SHPR2 - System Handler Priority Register 2.
//
//*****************************************************************************
// Priority of system handler 11, SVCall.
#define AM_REG_SYSCTRL_SHPR2_PRI_11_S 24
#define AM_REG_SYSCTRL_SHPR2_PRI_11_M 0xFF000000
#define AM_REG_SYSCTRL_SHPR2_PRI_11(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Reserved for priority of system handler 10.
#define AM_REG_SYSCTRL_SHPR2_PRI_10_S 16
#define AM_REG_SYSCTRL_SHPR2_PRI_10_M 0x00FF0000
#define AM_REG_SYSCTRL_SHPR2_PRI_10(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Reserved for priority of system handler 9.
#define AM_REG_SYSCTRL_SHPR2_PRI_9_S 8
#define AM_REG_SYSCTRL_SHPR2_PRI_9_M 0x0000FF00
#define AM_REG_SYSCTRL_SHPR2_PRI_9(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Reserved for priority of system handler 8.
#define AM_REG_SYSCTRL_SHPR2_PRI_8_S 0
#define AM_REG_SYSCTRL_SHPR2_PRI_8_M 0x000000FF
#define AM_REG_SYSCTRL_SHPR2_PRI_8(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// SYSCTRL_SHPR3 - System Handler Priority Register 3.
//
//*****************************************************************************
// Priority of system handler 15, SysTick.
#define AM_REG_SYSCTRL_SHPR3_PRI_15_S 24
#define AM_REG_SYSCTRL_SHPR3_PRI_15_M 0xFF000000
#define AM_REG_SYSCTRL_SHPR3_PRI_15(n) (((uint32_t)(n) << 24) & 0xFF000000)
// Priority of system handler 14, PendSV.
#define AM_REG_SYSCTRL_SHPR3_PRI_14_S 16
#define AM_REG_SYSCTRL_SHPR3_PRI_14_M 0x00FF0000
#define AM_REG_SYSCTRL_SHPR3_PRI_14(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// Reserved for priority of system handler 13.
#define AM_REG_SYSCTRL_SHPR3_PRI_13_S 8
#define AM_REG_SYSCTRL_SHPR3_PRI_13_M 0x0000FF00
#define AM_REG_SYSCTRL_SHPR3_PRI_13(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// Priority of system handler 12, DebugMonitor.
#define AM_REG_SYSCTRL_SHPR3_PRI_12_S 0
#define AM_REG_SYSCTRL_SHPR3_PRI_12_M 0x000000FF
#define AM_REG_SYSCTRL_SHPR3_PRI_12(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// SYSCTRL_SHCSR - System Handler Control and State Register.
//
//*****************************************************************************
// Set to enable UsageFault.
#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_S 18
#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_M 0x00040000
#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA(n) (((uint32_t)(n) << 18) & 0x00040000)
// Set to enable BusFault.
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_S 17
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_M 0x00020000
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA(n) (((uint32_t)(n) << 17) & 0x00020000)
// Set to enable MemManageFault.
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_S 16
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_M 0x00010000
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA(n) (((uint32_t)(n) << 16) & 0x00010000)
// Set to pend the SVCall exception.
#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_S 15
#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_M 0x00008000
#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED(n) (((uint32_t)(n) << 15) & 0x00008000)
// Set to pend the BusFault exception.
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_S 14
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_M 0x00004000
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED(n) (((uint32_t)(n) << 14) & 0x00004000)
// Set to pend the MemManageFault exception.
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_S 13
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_M 0x00002000
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED(n) (((uint32_t)(n) << 13) & 0x00002000)
// Set to pend the UsageFault exception.
#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_S 12
#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_M 0x00001000
#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED(n) (((uint32_t)(n) << 12) & 0x00001000)
// Set when SysTick is active.
#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_S 11
#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_M 0x00000800
#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT(n) (((uint32_t)(n) << 11) & 0x00000800)
// Set when PendSV is active.
#define AM_REG_SYSCTRL_SHCSR_PENDSVACT_S 10
#define AM_REG_SYSCTRL_SHCSR_PENDSVACT_M 0x00000400
#define AM_REG_SYSCTRL_SHCSR_PENDSVACT(n) (((uint32_t)(n) << 10) & 0x00000400)
// Set when Monitor is active.
#define AM_REG_SYSCTRL_SHCSR_MONITORACT_S 8
#define AM_REG_SYSCTRL_SHCSR_MONITORACT_M 0x00000100
#define AM_REG_SYSCTRL_SHCSR_MONITORACT(n) (((uint32_t)(n) << 8) & 0x00000100)
// Set when SVCall is active.
#define AM_REG_SYSCTRL_SHCSR_SVCALLACT_S 7
#define AM_REG_SYSCTRL_SHCSR_SVCALLACT_M 0x00000080
#define AM_REG_SYSCTRL_SHCSR_SVCALLACT(n) (((uint32_t)(n) << 7) & 0x00000080)
// Set when UsageFault is active.
#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_S 3
#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_M 0x00000008
#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT(n) (((uint32_t)(n) << 3) & 0x00000008)
// Set when BusFault is active.
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_S 1
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_M 0x00000002
#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT(n) (((uint32_t)(n) << 1) & 0x00000002)
// Set when MemManageFault is active.
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_S 0
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_M 0x00000001
#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSCTRL_CFSR - Configurable Fault Status Register.
//
//*****************************************************************************
// Divide by zero error has occurred.
#define AM_REG_SYSCTRL_CFSR_DIVBYZERO_S 25
#define AM_REG_SYSCTRL_CFSR_DIVBYZERO_M 0x02000000
#define AM_REG_SYSCTRL_CFSR_DIVBYZERO(n) (((uint32_t)(n) << 25) & 0x02000000)
// Unaligned access error has occurred.
#define AM_REG_SYSCTRL_CFSR_UNALIGNED_S 24
#define AM_REG_SYSCTRL_CFSR_UNALIGNED_M 0x01000000
#define AM_REG_SYSCTRL_CFSR_UNALIGNED(n) (((uint32_t)(n) << 24) & 0x01000000)
// A coprocessor access error has occurred.
#define AM_REG_SYSCTRL_CFSR_NOCP_S 19
#define AM_REG_SYSCTRL_CFSR_NOCP_M 0x00080000
#define AM_REG_SYSCTRL_CFSR_NOCP(n) (((uint32_t)(n) << 19) & 0x00080000)
// An integrity check error has occurred on EXC_RETURN.
#define AM_REG_SYSCTRL_CFSR_INVPC_S 18
#define AM_REG_SYSCTRL_CFSR_INVPC_M 0x00040000
#define AM_REG_SYSCTRL_CFSR_INVPC(n) (((uint32_t)(n) << 18) & 0x00040000)
// Instruction executed with invalid EPSR.T or EPSR.IT field.
#define AM_REG_SYSCTRL_CFSR_INVSTATE_S 17
#define AM_REG_SYSCTRL_CFSR_INVSTATE_M 0x00020000
#define AM_REG_SYSCTRL_CFSR_INVSTATE(n) (((uint32_t)(n) << 17) & 0x00020000)
// Processor attempted to execute an undefined instruction.
#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_S 16
#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_M 0x00010000
#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR(n) (((uint32_t)(n) << 16) & 0x00010000)
// BFAR has valid contents.
#define AM_REG_SYSCTRL_CFSR_BFARVALID_S 15
#define AM_REG_SYSCTRL_CFSR_BFARVALID_M 0x00008000
#define AM_REG_SYSCTRL_CFSR_BFARVALID(n) (((uint32_t)(n) << 15) & 0x00008000)
// A bus fault occurred during FP lazy state preservation.
#define AM_REG_SYSCTRL_CFSR_LSPERR_S 13
#define AM_REG_SYSCTRL_CFSR_LSPERR_M 0x00002000
#define AM_REG_SYSCTRL_CFSR_LSPERR(n) (((uint32_t)(n) << 13) & 0x00002000)
// A derived bus fault has occurred on exception entry.
#define AM_REG_SYSCTRL_CFSR_STKERR_S 12
#define AM_REG_SYSCTRL_CFSR_STKERR_M 0x00001000
#define AM_REG_SYSCTRL_CFSR_STKERR(n) (((uint32_t)(n) << 12) & 0x00001000)
// A derived bus fault has occurred on exception return.
#define AM_REG_SYSCTRL_CFSR_UNSTKERR_S 11
#define AM_REG_SYSCTRL_CFSR_UNSTKERR_M 0x00000800
#define AM_REG_SYSCTRL_CFSR_UNSTKERR(n) (((uint32_t)(n) << 11) & 0x00000800)
// Imprecise data access error has occurred.
#define AM_REG_SYSCTRL_CFSR_IMPRECISERR_S 10
#define AM_REG_SYSCTRL_CFSR_IMPRECISERR_M 0x00000400
#define AM_REG_SYSCTRL_CFSR_IMPRECISERR(n) (((uint32_t)(n) << 10) & 0x00000400)
// A precise data access has occurrred. The faulting address is in BFAR.
#define AM_REG_SYSCTRL_CFSR_PRECISERR_S 9
#define AM_REG_SYSCTRL_CFSR_PRECISERR_M 0x00000200
#define AM_REG_SYSCTRL_CFSR_PRECISERR(n) (((uint32_t)(n) << 9) & 0x00000200)
// A bus fault on an instruction prefetch has occurred.
#define AM_REG_SYSCTRL_CFSR_IBUSERR_S 8
#define AM_REG_SYSCTRL_CFSR_IBUSERR_M 0x00000100
#define AM_REG_SYSCTRL_CFSR_IBUSERR(n) (((uint32_t)(n) << 8) & 0x00000100)
// MMAR has valid contents.
#define AM_REG_SYSCTRL_CFSR_MMARVALID_S 7
#define AM_REG_SYSCTRL_CFSR_MMARVALID_M 0x00000080
#define AM_REG_SYSCTRL_CFSR_MMARVALID(n) (((uint32_t)(n) << 7) & 0x00000080)
// MemManage fault occurred during FP lazy state preservation.
#define AM_REG_SYSCTRL_CFSR_MLSPERR_S 5
#define AM_REG_SYSCTRL_CFSR_MLSPERR_M 0x00000020
#define AM_REG_SYSCTRL_CFSR_MLSPERR(n) (((uint32_t)(n) << 5) & 0x00000020)
// Derived MemManage fault occurred on exception entry.
#define AM_REG_SYSCTRL_CFSR_MSTKERR_S 4
#define AM_REG_SYSCTRL_CFSR_MSTKERR_M 0x00000010
#define AM_REG_SYSCTRL_CFSR_MSTKERR(n) (((uint32_t)(n) << 4) & 0x00000010)
// Derived MemManage fault occurred on exception return.
#define AM_REG_SYSCTRL_CFSR_MUNSTKER_S 3
#define AM_REG_SYSCTRL_CFSR_MUNSTKER_M 0x00000008
#define AM_REG_SYSCTRL_CFSR_MUNSTKER(n) (((uint32_t)(n) << 3) & 0x00000008)
// Data access violation. Address is in MMAR.
#define AM_REG_SYSCTRL_CFSR_DACCVIOL_S 1
#define AM_REG_SYSCTRL_CFSR_DACCVIOL_M 0x00000002
#define AM_REG_SYSCTRL_CFSR_DACCVIOL(n) (((uint32_t)(n) << 1) & 0x00000002)
// MPU or Execute Never default memory map access violation.
#define AM_REG_SYSCTRL_CFSR_IACCVIOL_S 0
#define AM_REG_SYSCTRL_CFSR_IACCVIOL_M 0x00000001
#define AM_REG_SYSCTRL_CFSR_IACCVIOL(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSCTRL_HFSR - Hard Fault Status Register.
//
//*****************************************************************************
// Debug event has occurred.
#define AM_REG_SYSCTRL_HFSR_DEBUGEVT_S 31
#define AM_REG_SYSCTRL_HFSR_DEBUGEVT_M 0x80000000
#define AM_REG_SYSCTRL_HFSR_DEBUGEVT(n) (((uint32_t)(n) << 31) & 0x80000000)
// Processor has elevated a configurable-priority fault to a HardFault.
#define AM_REG_SYSCTRL_HFSR_FORCED_S 30
#define AM_REG_SYSCTRL_HFSR_FORCED_M 0x40000000
#define AM_REG_SYSCTRL_HFSR_FORCED(n) (((uint32_t)(n) << 30) & 0x40000000)
// Vector table read fault has occurred.
#define AM_REG_SYSCTRL_HFSR_VECTTBL_S 1
#define AM_REG_SYSCTRL_HFSR_VECTTBL_M 0x00000002
#define AM_REG_SYSCTRL_HFSR_VECTTBL(n) (((uint32_t)(n) << 1) & 0x00000002)
//*****************************************************************************
//
// SYSCTRL_MMFAR - MemManage Fault Address Register.
//
//*****************************************************************************
// Address of the memory location that caused an MMU fault.
#define AM_REG_SYSCTRL_MMFAR_ADDRESS_S 0
#define AM_REG_SYSCTRL_MMFAR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_SYSCTRL_MMFAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// SYSCTRL_BFAR - Bus Fault Address Register.
//
//*****************************************************************************
// Address of the memory location that caused an Bus fault.
#define AM_REG_SYSCTRL_BFAR_ADDRESS_S 0
#define AM_REG_SYSCTRL_BFAR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_SYSCTRL_BFAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// SYSCTRL_CPACR - Coprocessor Access Control Register.
//
//*****************************************************************************
// Access priveleges for the Floating point unit. Must always match CP10.
#define AM_REG_SYSCTRL_CPACR_CP11_S 22
#define AM_REG_SYSCTRL_CPACR_CP11_M 0x00C00000
#define AM_REG_SYSCTRL_CPACR_CP11(n) (((uint32_t)(n) << 22) & 0x00C00000)
// Access priveleges for the Floating point unit. Must always match CP11.
#define AM_REG_SYSCTRL_CPACR_CP10_S 20
#define AM_REG_SYSCTRL_CPACR_CP10_M 0x00300000
#define AM_REG_SYSCTRL_CPACR_CP10(n) (((uint32_t)(n) << 20) & 0x00300000)
//*****************************************************************************
//
// SYSCTRL_DEMCR - Debug Exception and Monitor Control Register
//
//*****************************************************************************
// Global enable for all DWT and ITM features.
#define AM_REG_SYSCTRL_DEMCR_TRCENA_S 24
#define AM_REG_SYSCTRL_DEMCR_TRCENA_M 0x01000000
#define AM_REG_SYSCTRL_DEMCR_TRCENA(n) (((uint32_t)(n) << 24) & 0x01000000)
//*****************************************************************************
//
// SYSCTRL_STIR - Software Triggered Interrupt Register
//
//*****************************************************************************
// Vector number of the interrupt that should be triggered.
#define AM_REG_SYSCTRL_STIR_INTID_S 0
#define AM_REG_SYSCTRL_STIR_INTID_M 0xFFFFFFFF
#define AM_REG_SYSCTRL_STIR_INTID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// SYSCTRL_FPCCR - Floating-Point Context Control Register.
//
//*****************************************************************************
// Set to enable automatic saving of FP registers on exception entry.
#define AM_REG_SYSCTRL_FPCCR_ASPEN_S 31
#define AM_REG_SYSCTRL_FPCCR_ASPEN_M 0x80000000
#define AM_REG_SYSCTRL_FPCCR_ASPEN(n) (((uint32_t)(n) << 31) & 0x80000000)
// Set to enable lazy context saving of FP registers on exception entry.
#define AM_REG_SYSCTRL_FPCCR_LSPEN_S 30
#define AM_REG_SYSCTRL_FPCCR_LSPEN_M 0x40000000
#define AM_REG_SYSCTRL_FPCCR_LSPEN(n) (((uint32_t)(n) << 30) & 0x40000000)
// Able to set DebugMonitor exception to pending on last FP stack allocation.
#define AM_REG_SYSCTRL_FPCCR_MONRDY_S 8
#define AM_REG_SYSCTRL_FPCCR_MONRDY_M 0x00000100
#define AM_REG_SYSCTRL_FPCCR_MONRDY(n) (((uint32_t)(n) << 8) & 0x00000100)
// Able to set BusFault exception to pending on last FP stack allocation.
#define AM_REG_SYSCTRL_FPCCR_BFRDY_S 6
#define AM_REG_SYSCTRL_FPCCR_BFRDY_M 0x00000040
#define AM_REG_SYSCTRL_FPCCR_BFRDY(n) (((uint32_t)(n) << 6) & 0x00000040)
// Able to set MemManage exception to pending on last FP stack allocation.
#define AM_REG_SYSCTRL_FPCCR_MMRDY_S 5
#define AM_REG_SYSCTRL_FPCCR_MMRDY_M 0x00000020
#define AM_REG_SYSCTRL_FPCCR_MMRDY(n) (((uint32_t)(n) << 5) & 0x00000020)
// Able to set HardFault exception to pending on last FP stack allocation.
#define AM_REG_SYSCTRL_FPCCR_HFRDY_S 4
#define AM_REG_SYSCTRL_FPCCR_HFRDY_M 0x00000010
#define AM_REG_SYSCTRL_FPCCR_HFRDY(n) (((uint32_t)(n) << 4) & 0x00000010)
// Running from Thread mode on last FP stack allocation.
#define AM_REG_SYSCTRL_FPCCR_THREAD_S 3
#define AM_REG_SYSCTRL_FPCCR_THREAD_M 0x00000008
#define AM_REG_SYSCTRL_FPCCR_THREAD(n) (((uint32_t)(n) << 3) & 0x00000008)
// Running from unprivileged mode on last FP stack allocation.
#define AM_REG_SYSCTRL_FPCCR_USER_S 1
#define AM_REG_SYSCTRL_FPCCR_USER_M 0x00000002
#define AM_REG_SYSCTRL_FPCCR_USER(n) (((uint32_t)(n) << 1) & 0x00000002)
// Lazy state preservation is active.
#define AM_REG_SYSCTRL_FPCCR_LSPACT_S 0
#define AM_REG_SYSCTRL_FPCCR_LSPACT_M 0x00000001
#define AM_REG_SYSCTRL_FPCCR_LSPACT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSCTRL_FPCAR - Floating-Point Context Address Register.
//
//*****************************************************************************
// Address of the unpopulated floating-point register space allocated on the
// exception stack frame.
#define AM_REG_SYSCTRL_FPCAR_ADDRESS_S 0
#define AM_REG_SYSCTRL_FPCAR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_SYSCTRL_FPCAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
//*****************************************************************************
//
// SYSCTRL_FPDSCR - Floating-Point Default Status Control Register.
//
//*****************************************************************************
// Default value for FPSCR.AHP.
#define AM_REG_SYSCTRL_FPDSCR_AHP_S 26
#define AM_REG_SYSCTRL_FPDSCR_AHP_M 0x04000000
#define AM_REG_SYSCTRL_FPDSCR_AHP(n) (((uint32_t)(n) << 26) & 0x04000000)
// Default value for FPSCR.DN.
#define AM_REG_SYSCTRL_FPDSCR_DN_S 25
#define AM_REG_SYSCTRL_FPDSCR_DN_M 0x02000000
#define AM_REG_SYSCTRL_FPDSCR_DN(n) (((uint32_t)(n) << 25) & 0x02000000)
// Default value for FPSCR.FZ.
#define AM_REG_SYSCTRL_FPDSCR_FZ_S 24
#define AM_REG_SYSCTRL_FPDSCR_FZ_M 0x01000000
#define AM_REG_SYSCTRL_FPDSCR_FZ(n) (((uint32_t)(n) << 24) & 0x01000000)
// Default value for FPSCR.RMode.
#define AM_REG_SYSCTRL_FPDSCR_RMODE_S 22
#define AM_REG_SYSCTRL_FPDSCR_RMODE_M 0x00C00000
#define AM_REG_SYSCTRL_FPDSCR_RMODE(n) (((uint32_t)(n) << 22) & 0x00C00000)
#endif // AM_REG_SYSCTRL_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_systick.h
+141
View File
@@ -0,0 +1,141 @@
//*****************************************************************************
//
// am_reg_systick.h
//! @file
//!
//! @brief Register macros for the SYSTICK module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_SYSTICK_H
#define AM_REG_SYSTICK_H
//*****************************************************************************
//
// SYSTICK
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_SYSTICK_NUM_MODULES 1
#define AM_REG_SYSTICKn(n) \
(REG_SYSTICK_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_SYSTICK_SYSTCSR_O 0xE000E010
#define AM_REG_SYSTICK_SYSTRVR_O 0xE000E014
#define AM_REG_SYSTICK_SYSTCVR_O 0xE000E018
#define AM_REG_SYSTICK_SYSTCALIB_O 0xE000E01C
//*****************************************************************************
//
// SYSTICK_SYSTCSR - SysTick Control and Status Register.
//
//*****************************************************************************
// Returns 1 if timer counted to 0 since last time this was read.
#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_S 16
#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_M 0x00010000
#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG(n) (((uint32_t)(n) << 16) & 0x00010000)
// Enables SysTick exception request. Software can use COUNTFLAG to determine if
// SysTick has ever counted to zero. 0 = counting down to zero does not assert
// the SysTick exception request; 1 = counting down to zero asserts the SysTick
// exception request.
#define AM_REG_SYSTICK_SYSTCSR_TICKINT_S 1
#define AM_REG_SYSTICK_SYSTCSR_TICKINT_M 0x00000002
#define AM_REG_SYSTICK_SYSTCSR_TICKINT(n) (((uint32_t)(n) << 1) & 0x00000002)
// Enables the counter. 0 = counter disabled; 1 = counter enabled.
#define AM_REG_SYSTICK_SYSTCSR_ENABLE_S 0
#define AM_REG_SYSTICK_SYSTCSR_ENABLE_M 0x00000001
#define AM_REG_SYSTICK_SYSTCSR_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSTICK_SYSTRVR - SysTick Reload Value Register.
//
//*****************************************************************************
// Value to load into the SYSTCVR register when the counter is enabled and when
// it reaches 0.
#define AM_REG_SYSTICK_SYSTRVR_RELOAD_S 0
#define AM_REG_SYSTICK_SYSTRVR_RELOAD_M 0x00FFFFFF
#define AM_REG_SYSTICK_SYSTRVR_RELOAD(n) (((uint32_t)(n) << 0) & 0x00FFFFFF)
//*****************************************************************************
//
// SYSTICK_SYSTCVR - SysTick Current Value Register.
//
//*****************************************************************************
// Reads return the current value of the SysTick counter. A write of any value
// clears the field to 0, and also clears the SYSTCSR COUNTFLAG bit to 0.
#define AM_REG_SYSTICK_SYSTCVR_CURRENT_S 0
#define AM_REG_SYSTICK_SYSTCVR_CURRENT_M 0x00FFFFFF
#define AM_REG_SYSTICK_SYSTCVR_CURRENT(n) (((uint32_t)(n) << 0) & 0x00FFFFFF)
//*****************************************************************************
//
// SYSTICK_SYSTCALIB - SysTick Calibration Value Register.
//
//*****************************************************************************
// Indicates whether the device provides a reference clock to the processor. 0 =
// reference clock provided; 1 = no reference clock provided. If your device
// does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one
// and ignores writes.
#define AM_REG_SYSTICK_SYSTCALIB_NOREF_S 31
#define AM_REG_SYSTICK_SYSTCALIB_NOREF_M 0x80000000
#define AM_REG_SYSTICK_SYSTCALIB_NOREF(n) (((uint32_t)(n) << 31) & 0x80000000)
// Indicates whether the TENMS value is exact. 0 = TENMS value is exact; 1 =
// TENMS value is inexact, or not given. An inexact TENMS value can affect the
// suitability of SysTick as a software real time clock.
#define AM_REG_SYSTICK_SYSTCALIB_SKEW_S 30
#define AM_REG_SYSTICK_SYSTCALIB_SKEW_M 0x40000000
#define AM_REG_SYSTICK_SYSTCALIB_SKEW(n) (((uint32_t)(n) << 30) & 0x40000000)
// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If
// the value reads as zero, the calibration value is not known.
#define AM_REG_SYSTICK_SYSTCALIB_TENMS_S 0
#define AM_REG_SYSTICK_SYSTCALIB_TENMS_M 0x00FFFFFF
#define AM_REG_SYSTICK_SYSTCALIB_TENMS(n) (((uint32_t)(n) << 0) & 0x00FFFFFF)
#endif // AM_REG_SYSTICK_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_tpiu.h
+168
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@@ -0,0 +1,168 @@
//*****************************************************************************
//
// am_reg_tpiu.h
//! @file
//!
//! @brief Register macros for the TPIU module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_TPIU_H
#define AM_REG_TPIU_H
//*****************************************************************************
//
// TPIU
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_TPIU_NUM_MODULES 1
#define AM_REG_TPIUn(n) \
(REG_TPIU_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_TPIU_SSPSR_O 0xE0040000
#define AM_REG_TPIU_CSPSR_O 0xE0040004
#define AM_REG_TPIU_ACPR_O 0xE0040010
#define AM_REG_TPIU_SPPR_O 0xE00400F0
#define AM_REG_TPIU_FFCR_O 0xE0040304
#define AM_REG_TPIU_ITCTRL_O 0xE0040F00
#define AM_REG_TPIU_TYPE_O 0xE0040FC8
//*****************************************************************************
//
// TPIU_SSPSR - Supported Parallel Port Sizes.
//
//*****************************************************************************
// Parallel Port Width 1 supported
#define AM_REG_TPIU_SSPSR_SWIDTH0_S 0
#define AM_REG_TPIU_SSPSR_SWIDTH0_M 0x00000001
#define AM_REG_TPIU_SSPSR_SWIDTH0(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// TPIU_CSPSR - Current Parallel Port Size.
//
//*****************************************************************************
// One-hot representation of the current port width.
#define AM_REG_TPIU_CSPSR_CWIDTH_S 0
#define AM_REG_TPIU_CSPSR_CWIDTH_M 0xFFFFFFFF
#define AM_REG_TPIU_CSPSR_CWIDTH(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_TPIU_CSPSR_CWIDTH_1BIT 0x00000001
//*****************************************************************************
//
// TPIU_ACPR - Asynchronous Clock Prescaler.
//
//*****************************************************************************
// Prescaler value for the baudrate of SWO.
#define AM_REG_TPIU_ACPR_SWOSCALER_S 0
#define AM_REG_TPIU_ACPR_SWOSCALER_M 0x0000FFFF
#define AM_REG_TPIU_ACPR_SWOSCALER(n) (((uint32_t)(n) << 0) & 0x0000FFFF)
#define AM_REG_TPIU_ACPR_SWOSCALER_115200 0x00000033
//*****************************************************************************
//
// TPIU_SPPR - Selected Pin Protocol.
//
//*****************************************************************************
// Selects the protocol used for trace output.
#define AM_REG_TPIU_SPPR_TXMODE_S 0
#define AM_REG_TPIU_SPPR_TXMODE_M 0x00000003
#define AM_REG_TPIU_SPPR_TXMODE(n) (((uint32_t)(n) << 0) & 0x00000003)
#define AM_REG_TPIU_SPPR_TXMODE_PARALLEL 0x00000000
#define AM_REG_TPIU_SPPR_TXMODE_MANCHESTER 0x00000001
#define AM_REG_TPIU_SPPR_TXMODE_NRZ 0x00000002
#define AM_REG_TPIU_SPPR_TXMODE_UART 0x00000002
//*****************************************************************************
//
// TPIU_FFCR - Formatter and Flush Control Register.
//
//*****************************************************************************
// Enable continuous formatting.
#define AM_REG_TPIU_FFCR_ENFCONT_S 1
#define AM_REG_TPIU_FFCR_ENFCONT_M 0x00000002
#define AM_REG_TPIU_FFCR_ENFCONT(n) (((uint32_t)(n) << 1) & 0x00000002)
//*****************************************************************************
//
// TPIU_ITCTRL - Specifies normal or integration mode for the TPIU.
//
//*****************************************************************************
// Specifies the current mode for the TPIU.
#define AM_REG_TPIU_ITCTRL_MODE_S 0
#define AM_REG_TPIU_ITCTRL_MODE_M 0x00000003
#define AM_REG_TPIU_ITCTRL_MODE(n) (((uint32_t)(n) << 0) & 0x00000003)
#define AM_REG_TPIU_ITCTRL_MODE_NORMAL 0x00000000
#define AM_REG_TPIU_ITCTRL_MODE_TEST 0x00000001
#define AM_REG_TPIU_ITCTRL_MODE_DATA_TEST 0x00000002
//*****************************************************************************
//
// TPIU_TYPE - TPIU Type.
//
//*****************************************************************************
// 1 Indicates UART/NRZ support.
#define AM_REG_TPIU_TYPE_NRZVALID_S 11
#define AM_REG_TPIU_TYPE_NRZVALID_M 0x00000800
#define AM_REG_TPIU_TYPE_NRZVALID(n) (((uint32_t)(n) << 11) & 0x00000800)
// 1 Indicates Manchester support.
#define AM_REG_TPIU_TYPE_MANCVALID_S 10
#define AM_REG_TPIU_TYPE_MANCVALID_M 0x00000400
#define AM_REG_TPIU_TYPE_MANCVALID(n) (((uint32_t)(n) << 10) & 0x00000400)
// 0 Indicates Parallel Trace support.
#define AM_REG_TPIU_TYPE_PTINVALID_S 9
#define AM_REG_TPIU_TYPE_PTINVALID_M 0x00000200
#define AM_REG_TPIU_TYPE_PTINVALID(n) (((uint32_t)(n) << 9) & 0x00000200)
// FIFO Size reported as a power of two. For instance, 0x3 indicates a FIFO size
// of 8 bytes.
#define AM_REG_TPIU_TYPE_FIFOSZ_S 6
#define AM_REG_TPIU_TYPE_FIFOSZ_M 0x000001C0
#define AM_REG_TPIU_TYPE_FIFOSZ(n) (((uint32_t)(n) << 6) & 0x000001C0)
#endif // AM_REG_TPIU_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_uart.h
+616
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@@ -0,0 +1,616 @@
//*****************************************************************************
//
// am_reg_uart.h
//! @file
//!
//! @brief Register macros for the UART module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_UART_H
#define AM_REG_UART_H
//*****************************************************************************
//
// UART
// Instance finder. (2 instance(s) available)
//
//*****************************************************************************
#define AM_REG_UART_NUM_MODULES 2
#define AM_REG_UARTn(n) \
(REG_UART_BASEADDR + 0x00001000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_UART_DR_O 0x00000000
#define AM_REG_UART_RSR_O 0x00000004
#define AM_REG_UART_FR_O 0x00000018
#define AM_REG_UART_ILPR_O 0x00000020
#define AM_REG_UART_IBRD_O 0x00000024
#define AM_REG_UART_FBRD_O 0x00000028
#define AM_REG_UART_LCRH_O 0x0000002C
#define AM_REG_UART_CR_O 0x00000030
#define AM_REG_UART_IFLS_O 0x00000034
#define AM_REG_UART_IER_O 0x00000038
#define AM_REG_UART_IES_O 0x0000003C
#define AM_REG_UART_MIS_O 0x00000040
#define AM_REG_UART_IEC_O 0x00000044
//*****************************************************************************
//
// UART_DR - UART Data Register
//
//*****************************************************************************
// This is the overrun error indicator.
#define AM_REG_UART_DR_OEDATA_S 11
#define AM_REG_UART_DR_OEDATA_M 0x00000800
#define AM_REG_UART_DR_OEDATA(n) (((uint32_t)(n) << 11) & 0x00000800)
#define AM_REG_UART_DR_OEDATA_NOERR 0x00000000
#define AM_REG_UART_DR_OEDATA_ERR 0x00000800
// This is the break error indicator.
#define AM_REG_UART_DR_BEDATA_S 10
#define AM_REG_UART_DR_BEDATA_M 0x00000400
#define AM_REG_UART_DR_BEDATA(n) (((uint32_t)(n) << 10) & 0x00000400)
#define AM_REG_UART_DR_BEDATA_NOERR 0x00000000
#define AM_REG_UART_DR_BEDATA_ERR 0x00000400
// This is the parity error indicator.
#define AM_REG_UART_DR_PEDATA_S 9
#define AM_REG_UART_DR_PEDATA_M 0x00000200
#define AM_REG_UART_DR_PEDATA(n) (((uint32_t)(n) << 9) & 0x00000200)
#define AM_REG_UART_DR_PEDATA_NOERR 0x00000000
#define AM_REG_UART_DR_PEDATA_ERR 0x00000200
// This is the framing error indicator.
#define AM_REG_UART_DR_FEDATA_S 8
#define AM_REG_UART_DR_FEDATA_M 0x00000100
#define AM_REG_UART_DR_FEDATA(n) (((uint32_t)(n) << 8) & 0x00000100)
#define AM_REG_UART_DR_FEDATA_NOERR 0x00000000
#define AM_REG_UART_DR_FEDATA_ERR 0x00000100
// This is the UART data port.
#define AM_REG_UART_DR_DATA_S 0
#define AM_REG_UART_DR_DATA_M 0x000000FF
#define AM_REG_UART_DR_DATA(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// UART_RSR - UART Status Register
//
//*****************************************************************************
// This is the overrun error indicator.
#define AM_REG_UART_RSR_OESTAT_S 3
#define AM_REG_UART_RSR_OESTAT_M 0x00000008
#define AM_REG_UART_RSR_OESTAT(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_UART_RSR_OESTAT_NOERR 0x00000000
#define AM_REG_UART_RSR_OESTAT_ERR 0x00000008
// This is the break error indicator.
#define AM_REG_UART_RSR_BESTAT_S 2
#define AM_REG_UART_RSR_BESTAT_M 0x00000004
#define AM_REG_UART_RSR_BESTAT(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_UART_RSR_BESTAT_NOERR 0x00000000
#define AM_REG_UART_RSR_BESTAT_ERR 0x00000004
// This is the parity error indicator.
#define AM_REG_UART_RSR_PESTAT_S 1
#define AM_REG_UART_RSR_PESTAT_M 0x00000002
#define AM_REG_UART_RSR_PESTAT(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_UART_RSR_PESTAT_NOERR 0x00000000
#define AM_REG_UART_RSR_PESTAT_ERR 0x00000002
// This is the framing error indicator.
#define AM_REG_UART_RSR_FESTAT_S 0
#define AM_REG_UART_RSR_FESTAT_M 0x00000001
#define AM_REG_UART_RSR_FESTAT(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_UART_RSR_FESTAT_NOERR 0x00000000
#define AM_REG_UART_RSR_FESTAT_ERR 0x00000001
//*****************************************************************************
//
// UART_FR - Flag Register
//
//*****************************************************************************
// This bit holds the transmit BUSY indicator.
#define AM_REG_UART_FR_TXBUSY_S 8
#define AM_REG_UART_FR_TXBUSY_M 0x00000100
#define AM_REG_UART_FR_TXBUSY(n) (((uint32_t)(n) << 8) & 0x00000100)
// This bit holds the transmit FIFO empty indicator.
#define AM_REG_UART_FR_TXFE_S 7
#define AM_REG_UART_FR_TXFE_M 0x00000080
#define AM_REG_UART_FR_TXFE(n) (((uint32_t)(n) << 7) & 0x00000080)
#define AM_REG_UART_FR_TXFE_XMTFIFO_EMPTY 0x00000080
// This bit holds the receive FIFO full indicator.
#define AM_REG_UART_FR_RXFF_S 6
#define AM_REG_UART_FR_RXFF_M 0x00000040
#define AM_REG_UART_FR_RXFF(n) (((uint32_t)(n) << 6) & 0x00000040)
#define AM_REG_UART_FR_RXFF_RCVFIFO_FULL 0x00000040
// This bit holds the transmit FIFO full indicator.
#define AM_REG_UART_FR_TXFF_S 5
#define AM_REG_UART_FR_TXFF_M 0x00000020
#define AM_REG_UART_FR_TXFF(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_UART_FR_TXFF_XMTFIFO_FULL 0x00000020
// This bit holds the receive FIFO empty indicator.
#define AM_REG_UART_FR_RXFE_S 4
#define AM_REG_UART_FR_RXFE_M 0x00000010
#define AM_REG_UART_FR_RXFE(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_UART_FR_RXFE_RCVFIFO_EMPTY 0x00000010
// This bit holds the busy indicator.
#define AM_REG_UART_FR_BUSY_S 3
#define AM_REG_UART_FR_BUSY_M 0x00000008
#define AM_REG_UART_FR_BUSY(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_UART_FR_BUSY_BUSY 0x00000008
// This bit holds the data carrier detect indicator.
#define AM_REG_UART_FR_DCD_S 2
#define AM_REG_UART_FR_DCD_M 0x00000004
#define AM_REG_UART_FR_DCD(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_UART_FR_DCD_DETECTED 0x00000004
// This bit holds the data set ready indicator.
#define AM_REG_UART_FR_DSR_S 1
#define AM_REG_UART_FR_DSR_M 0x00000002
#define AM_REG_UART_FR_DSR(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_UART_FR_DSR_READY 0x00000002
// This bit holds the clear to send indicator.
#define AM_REG_UART_FR_CTS_S 0
#define AM_REG_UART_FR_CTS_M 0x00000001
#define AM_REG_UART_FR_CTS(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_UART_FR_CTS_CLEARTOSEND 0x00000001
//*****************************************************************************
//
// UART_ILPR - IrDA Counter
//
//*****************************************************************************
// These bits hold the IrDA counter divisor.
#define AM_REG_UART_ILPR_ILPDVSR_S 0
#define AM_REG_UART_ILPR_ILPDVSR_M 0x000000FF
#define AM_REG_UART_ILPR_ILPDVSR(n) (((uint32_t)(n) << 0) & 0x000000FF)
//*****************************************************************************
//
// UART_IBRD - Integer Baud Rate Divisor
//
//*****************************************************************************
// These bits hold the baud integer divisor.
#define AM_REG_UART_IBRD_DIVINT_S 0
#define AM_REG_UART_IBRD_DIVINT_M 0x0000FFFF
#define AM_REG_UART_IBRD_DIVINT(n) (((uint32_t)(n) << 0) & 0x0000FFFF)
//*****************************************************************************
//
// UART_FBRD - Fractional Baud Rate Divisor
//
//*****************************************************************************
// These bits hold the baud fractional divisor.
#define AM_REG_UART_FBRD_DIVFRAC_S 0
#define AM_REG_UART_FBRD_DIVFRAC_M 0x0000003F
#define AM_REG_UART_FBRD_DIVFRAC(n) (((uint32_t)(n) << 0) & 0x0000003F)
//*****************************************************************************
//
// UART_LCRH - Line Control High
//
//*****************************************************************************
// This bit holds the stick parity select.
#define AM_REG_UART_LCRH_SPS_S 7
#define AM_REG_UART_LCRH_SPS_M 0x00000080
#define AM_REG_UART_LCRH_SPS(n) (((uint32_t)(n) << 7) & 0x00000080)
// These bits hold the write length.
#define AM_REG_UART_LCRH_WLEN_S 5
#define AM_REG_UART_LCRH_WLEN_M 0x00000060
#define AM_REG_UART_LCRH_WLEN(n) (((uint32_t)(n) << 5) & 0x00000060)
// This bit holds the FIFO enable.
#define AM_REG_UART_LCRH_FEN_S 4
#define AM_REG_UART_LCRH_FEN_M 0x00000010
#define AM_REG_UART_LCRH_FEN(n) (((uint32_t)(n) << 4) & 0x00000010)
// This bit holds the two stop bits select.
#define AM_REG_UART_LCRH_STP2_S 3
#define AM_REG_UART_LCRH_STP2_M 0x00000008
#define AM_REG_UART_LCRH_STP2(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit holds the even parity select.
#define AM_REG_UART_LCRH_EPS_S 2
#define AM_REG_UART_LCRH_EPS_M 0x00000004
#define AM_REG_UART_LCRH_EPS(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit holds the parity enable.
#define AM_REG_UART_LCRH_PEN_S 1
#define AM_REG_UART_LCRH_PEN_M 0x00000002
#define AM_REG_UART_LCRH_PEN(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit holds the break set.
#define AM_REG_UART_LCRH_BRK_S 0
#define AM_REG_UART_LCRH_BRK_M 0x00000001
#define AM_REG_UART_LCRH_BRK(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// UART_CR - Control Register
//
//*****************************************************************************
// This bit enables CTS hardware flow control.
#define AM_REG_UART_CR_CTSEN_S 15
#define AM_REG_UART_CR_CTSEN_M 0x00008000
#define AM_REG_UART_CR_CTSEN(n) (((uint32_t)(n) << 15) & 0x00008000)
// This bit enables RTS hardware flow control.
#define AM_REG_UART_CR_RTSEN_S 14
#define AM_REG_UART_CR_RTSEN_M 0x00004000
#define AM_REG_UART_CR_RTSEN(n) (((uint32_t)(n) << 14) & 0x00004000)
// This bit holds modem Out2.
#define AM_REG_UART_CR_OUT2_S 13
#define AM_REG_UART_CR_OUT2_M 0x00002000
#define AM_REG_UART_CR_OUT2(n) (((uint32_t)(n) << 13) & 0x00002000)
// This bit holds modem Out1.
#define AM_REG_UART_CR_OUT1_S 12
#define AM_REG_UART_CR_OUT1_M 0x00001000
#define AM_REG_UART_CR_OUT1(n) (((uint32_t)(n) << 12) & 0x00001000)
// This bit enables request to send.
#define AM_REG_UART_CR_RTS_S 11
#define AM_REG_UART_CR_RTS_M 0x00000800
#define AM_REG_UART_CR_RTS(n) (((uint32_t)(n) << 11) & 0x00000800)
// This bit enables data transmit ready.
#define AM_REG_UART_CR_DTR_S 10
#define AM_REG_UART_CR_DTR_M 0x00000400
#define AM_REG_UART_CR_DTR(n) (((uint32_t)(n) << 10) & 0x00000400)
// This bit is the receive enable.
#define AM_REG_UART_CR_RXE_S 9
#define AM_REG_UART_CR_RXE_M 0x00000200
#define AM_REG_UART_CR_RXE(n) (((uint32_t)(n) << 9) & 0x00000200)
// This bit is the transmit enable.
#define AM_REG_UART_CR_TXE_S 8
#define AM_REG_UART_CR_TXE_M 0x00000100
#define AM_REG_UART_CR_TXE(n) (((uint32_t)(n) << 8) & 0x00000100)
// This bit is the loopback enable.
#define AM_REG_UART_CR_LBE_S 7
#define AM_REG_UART_CR_LBE_M 0x00000080
#define AM_REG_UART_CR_LBE(n) (((uint32_t)(n) << 7) & 0x00000080)
// This bitfield is the UART clock select.
#define AM_REG_UART_CR_CLKSEL_S 4
#define AM_REG_UART_CR_CLKSEL_M 0x00000070
#define AM_REG_UART_CR_CLKSEL(n) (((uint32_t)(n) << 4) & 0x00000070)
#define AM_REG_UART_CR_CLKSEL_NOCLK 0x00000000
#define AM_REG_UART_CR_CLKSEL_24MHZ 0x00000010
#define AM_REG_UART_CR_CLKSEL_12MHZ 0x00000020
#define AM_REG_UART_CR_CLKSEL_6MHZ 0x00000030
#define AM_REG_UART_CR_CLKSEL_3MHZ 0x00000040
#define AM_REG_UART_CR_CLKSEL_RSVD5 0x00000050
#define AM_REG_UART_CR_CLKSEL_RSVD6 0x00000060
#define AM_REG_UART_CR_CLKSEL_RSVD7 0x00000070
// This bit is the UART clock enable.
#define AM_REG_UART_CR_CLKEN_S 3
#define AM_REG_UART_CR_CLKEN_M 0x00000008
#define AM_REG_UART_CR_CLKEN(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit is the SIR low power select.
#define AM_REG_UART_CR_SIRLP_S 2
#define AM_REG_UART_CR_SIRLP_M 0x00000004
#define AM_REG_UART_CR_SIRLP(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit is the SIR ENDEC enable.
#define AM_REG_UART_CR_SIREN_S 1
#define AM_REG_UART_CR_SIREN_M 0x00000002
#define AM_REG_UART_CR_SIREN(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit is the UART enable.
#define AM_REG_UART_CR_UARTEN_S 0
#define AM_REG_UART_CR_UARTEN_M 0x00000001
#define AM_REG_UART_CR_UARTEN(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// UART_IFLS - FIFO Interrupt Level Select
//
//*****************************************************************************
// These bits hold the receive FIFO interrupt level.
#define AM_REG_UART_IFLS_RXIFLSEL_S 3
#define AM_REG_UART_IFLS_RXIFLSEL_M 0x00000038
#define AM_REG_UART_IFLS_RXIFLSEL(n) (((uint32_t)(n) << 3) & 0x00000038)
// These bits hold the transmit FIFO interrupt level.
#define AM_REG_UART_IFLS_TXIFLSEL_S 0
#define AM_REG_UART_IFLS_TXIFLSEL_M 0x00000007
#define AM_REG_UART_IFLS_TXIFLSEL(n) (((uint32_t)(n) << 0) & 0x00000007)
//*****************************************************************************
//
// UART_IER - Interrupt Enable
//
//*****************************************************************************
// This bit holds the overflow interrupt enable.
#define AM_REG_UART_IER_OEIM_S 10
#define AM_REG_UART_IER_OEIM_M 0x00000400
#define AM_REG_UART_IER_OEIM(n) (((uint32_t)(n) << 10) & 0x00000400)
// This bit holds the break error interrupt enable.
#define AM_REG_UART_IER_BEIM_S 9
#define AM_REG_UART_IER_BEIM_M 0x00000200
#define AM_REG_UART_IER_BEIM(n) (((uint32_t)(n) << 9) & 0x00000200)
// This bit holds the parity error interrupt enable.
#define AM_REG_UART_IER_PEIM_S 8
#define AM_REG_UART_IER_PEIM_M 0x00000100
#define AM_REG_UART_IER_PEIM(n) (((uint32_t)(n) << 8) & 0x00000100)
// This bit holds the framing error interrupt enable.
#define AM_REG_UART_IER_FEIM_S 7
#define AM_REG_UART_IER_FEIM_M 0x00000080
#define AM_REG_UART_IER_FEIM(n) (((uint32_t)(n) << 7) & 0x00000080)
// This bit holds the receive timeout interrupt enable.
#define AM_REG_UART_IER_RTIM_S 6
#define AM_REG_UART_IER_RTIM_M 0x00000040
#define AM_REG_UART_IER_RTIM(n) (((uint32_t)(n) << 6) & 0x00000040)
// This bit holds the transmit interrupt enable.
#define AM_REG_UART_IER_TXIM_S 5
#define AM_REG_UART_IER_TXIM_M 0x00000020
#define AM_REG_UART_IER_TXIM(n) (((uint32_t)(n) << 5) & 0x00000020)
// This bit holds the receive interrupt enable.
#define AM_REG_UART_IER_RXIM_S 4
#define AM_REG_UART_IER_RXIM_M 0x00000010
#define AM_REG_UART_IER_RXIM(n) (((uint32_t)(n) << 4) & 0x00000010)
// This bit holds the modem DSR interrupt enable.
#define AM_REG_UART_IER_DSRMIM_S 3
#define AM_REG_UART_IER_DSRMIM_M 0x00000008
#define AM_REG_UART_IER_DSRMIM(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit holds the modem DCD interrupt enable.
#define AM_REG_UART_IER_DCDMIM_S 2
#define AM_REG_UART_IER_DCDMIM_M 0x00000004
#define AM_REG_UART_IER_DCDMIM(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit holds the modem CTS interrupt enable.
#define AM_REG_UART_IER_CTSMIM_S 1
#define AM_REG_UART_IER_CTSMIM_M 0x00000002
#define AM_REG_UART_IER_CTSMIM(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit holds the modem TXCMP interrupt enable.
#define AM_REG_UART_IER_TXCMPMIM_S 0
#define AM_REG_UART_IER_TXCMPMIM_M 0x00000001
#define AM_REG_UART_IER_TXCMPMIM(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// UART_IES - Interrupt Status
//
//*****************************************************************************
// This bit holds the overflow interrupt status.
#define AM_REG_UART_IES_OERIS_S 10
#define AM_REG_UART_IES_OERIS_M 0x00000400
#define AM_REG_UART_IES_OERIS(n) (((uint32_t)(n) << 10) & 0x00000400)
// This bit holds the break error interrupt status.
#define AM_REG_UART_IES_BERIS_S 9
#define AM_REG_UART_IES_BERIS_M 0x00000200
#define AM_REG_UART_IES_BERIS(n) (((uint32_t)(n) << 9) & 0x00000200)
// This bit holds the parity error interrupt status.
#define AM_REG_UART_IES_PERIS_S 8
#define AM_REG_UART_IES_PERIS_M 0x00000100
#define AM_REG_UART_IES_PERIS(n) (((uint32_t)(n) << 8) & 0x00000100)
// This bit holds the framing error interrupt status.
#define AM_REG_UART_IES_FERIS_S 7
#define AM_REG_UART_IES_FERIS_M 0x00000080
#define AM_REG_UART_IES_FERIS(n) (((uint32_t)(n) << 7) & 0x00000080)
// This bit holds the receive timeout interrupt status.
#define AM_REG_UART_IES_RTRIS_S 6
#define AM_REG_UART_IES_RTRIS_M 0x00000040
#define AM_REG_UART_IES_RTRIS(n) (((uint32_t)(n) << 6) & 0x00000040)
// This bit holds the transmit interrupt status.
#define AM_REG_UART_IES_TXRIS_S 5
#define AM_REG_UART_IES_TXRIS_M 0x00000020
#define AM_REG_UART_IES_TXRIS(n) (((uint32_t)(n) << 5) & 0x00000020)
// This bit holds the receive interrupt status.
#define AM_REG_UART_IES_RXRIS_S 4
#define AM_REG_UART_IES_RXRIS_M 0x00000010
#define AM_REG_UART_IES_RXRIS(n) (((uint32_t)(n) << 4) & 0x00000010)
// This bit holds the modem DSR interrupt status.
#define AM_REG_UART_IES_DSRMRIS_S 3
#define AM_REG_UART_IES_DSRMRIS_M 0x00000008
#define AM_REG_UART_IES_DSRMRIS(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit holds the modem DCD interrupt status.
#define AM_REG_UART_IES_DCDMRIS_S 2
#define AM_REG_UART_IES_DCDMRIS_M 0x00000004
#define AM_REG_UART_IES_DCDMRIS(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit holds the modem CTS interrupt status.
#define AM_REG_UART_IES_CTSMRIS_S 1
#define AM_REG_UART_IES_CTSMRIS_M 0x00000002
#define AM_REG_UART_IES_CTSMRIS(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit holds the modem TXCMP interrupt status.
#define AM_REG_UART_IES_TXCMPMRIS_S 0
#define AM_REG_UART_IES_TXCMPMRIS_M 0x00000001
#define AM_REG_UART_IES_TXCMPMRIS(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// UART_MIS - Masked Interrupt Status
//
//*****************************************************************************
// This bit holds the overflow interrupt status masked.
#define AM_REG_UART_MIS_OEMIS_S 10
#define AM_REG_UART_MIS_OEMIS_M 0x00000400
#define AM_REG_UART_MIS_OEMIS(n) (((uint32_t)(n) << 10) & 0x00000400)
// This bit holds the break error interrupt status masked.
#define AM_REG_UART_MIS_BEMIS_S 9
#define AM_REG_UART_MIS_BEMIS_M 0x00000200
#define AM_REG_UART_MIS_BEMIS(n) (((uint32_t)(n) << 9) & 0x00000200)
// This bit holds the parity error interrupt status masked.
#define AM_REG_UART_MIS_PEMIS_S 8
#define AM_REG_UART_MIS_PEMIS_M 0x00000100
#define AM_REG_UART_MIS_PEMIS(n) (((uint32_t)(n) << 8) & 0x00000100)
// This bit holds the framing error interrupt status masked.
#define AM_REG_UART_MIS_FEMIS_S 7
#define AM_REG_UART_MIS_FEMIS_M 0x00000080
#define AM_REG_UART_MIS_FEMIS(n) (((uint32_t)(n) << 7) & 0x00000080)
// This bit holds the receive timeout interrupt status masked.
#define AM_REG_UART_MIS_RTMIS_S 6
#define AM_REG_UART_MIS_RTMIS_M 0x00000040
#define AM_REG_UART_MIS_RTMIS(n) (((uint32_t)(n) << 6) & 0x00000040)
// This bit holds the transmit interrupt status masked.
#define AM_REG_UART_MIS_TXMIS_S 5
#define AM_REG_UART_MIS_TXMIS_M 0x00000020
#define AM_REG_UART_MIS_TXMIS(n) (((uint32_t)(n) << 5) & 0x00000020)
// This bit holds the receive interrupt status masked.
#define AM_REG_UART_MIS_RXMIS_S 4
#define AM_REG_UART_MIS_RXMIS_M 0x00000010
#define AM_REG_UART_MIS_RXMIS(n) (((uint32_t)(n) << 4) & 0x00000010)
// This bit holds the modem DSR interrupt status masked.
#define AM_REG_UART_MIS_DSRMMIS_S 3
#define AM_REG_UART_MIS_DSRMMIS_M 0x00000008
#define AM_REG_UART_MIS_DSRMMIS(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit holds the modem DCD interrupt status masked.
#define AM_REG_UART_MIS_DCDMMIS_S 2
#define AM_REG_UART_MIS_DCDMMIS_M 0x00000004
#define AM_REG_UART_MIS_DCDMMIS(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit holds the modem CTS interrupt status masked.
#define AM_REG_UART_MIS_CTSMMIS_S 1
#define AM_REG_UART_MIS_CTSMMIS_M 0x00000002
#define AM_REG_UART_MIS_CTSMMIS(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit holds the modem TXCMP interrupt status masked.
#define AM_REG_UART_MIS_TXCMPMMIS_S 0
#define AM_REG_UART_MIS_TXCMPMMIS_M 0x00000001
#define AM_REG_UART_MIS_TXCMPMMIS(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// UART_IEC - Interrupt Clear
//
//*****************************************************************************
// This bit holds the overflow interrupt clear.
#define AM_REG_UART_IEC_OEIC_S 10
#define AM_REG_UART_IEC_OEIC_M 0x00000400
#define AM_REG_UART_IEC_OEIC(n) (((uint32_t)(n) << 10) & 0x00000400)
// This bit holds the break error interrupt clear.
#define AM_REG_UART_IEC_BEIC_S 9
#define AM_REG_UART_IEC_BEIC_M 0x00000200
#define AM_REG_UART_IEC_BEIC(n) (((uint32_t)(n) << 9) & 0x00000200)
// This bit holds the parity error interrupt clear.
#define AM_REG_UART_IEC_PEIC_S 8
#define AM_REG_UART_IEC_PEIC_M 0x00000100
#define AM_REG_UART_IEC_PEIC(n) (((uint32_t)(n) << 8) & 0x00000100)
// This bit holds the framing error interrupt clear.
#define AM_REG_UART_IEC_FEIC_S 7
#define AM_REG_UART_IEC_FEIC_M 0x00000080
#define AM_REG_UART_IEC_FEIC(n) (((uint32_t)(n) << 7) & 0x00000080)
// This bit holds the receive timeout interrupt clear.
#define AM_REG_UART_IEC_RTIC_S 6
#define AM_REG_UART_IEC_RTIC_M 0x00000040
#define AM_REG_UART_IEC_RTIC(n) (((uint32_t)(n) << 6) & 0x00000040)
// This bit holds the transmit interrupt clear.
#define AM_REG_UART_IEC_TXIC_S 5
#define AM_REG_UART_IEC_TXIC_M 0x00000020
#define AM_REG_UART_IEC_TXIC(n) (((uint32_t)(n) << 5) & 0x00000020)
// This bit holds the receive interrupt clear.
#define AM_REG_UART_IEC_RXIC_S 4
#define AM_REG_UART_IEC_RXIC_M 0x00000010
#define AM_REG_UART_IEC_RXIC(n) (((uint32_t)(n) << 4) & 0x00000010)
// This bit holds the modem DSR interrupt clear.
#define AM_REG_UART_IEC_DSRMIC_S 3
#define AM_REG_UART_IEC_DSRMIC_M 0x00000008
#define AM_REG_UART_IEC_DSRMIC(n) (((uint32_t)(n) << 3) & 0x00000008)
// This bit holds the modem DCD interrupt clear.
#define AM_REG_UART_IEC_DCDMIC_S 2
#define AM_REG_UART_IEC_DCDMIC_M 0x00000004
#define AM_REG_UART_IEC_DCDMIC(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bit holds the modem CTS interrupt clear.
#define AM_REG_UART_IEC_CTSMIC_S 1
#define AM_REG_UART_IEC_CTSMIC_M 0x00000002
#define AM_REG_UART_IEC_CTSMIC(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit holds the modem TXCMP interrupt clear.
#define AM_REG_UART_IEC_TXCMPMIC_S 0
#define AM_REG_UART_IEC_TXCMPMIC_M 0x00000001
#define AM_REG_UART_IEC_TXCMPMIC(n) (((uint32_t)(n) << 0) & 0x00000001)
#endif // AM_REG_UART_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_vcomp.h
+204
View File
@@ -0,0 +1,204 @@
//*****************************************************************************
//
// am_reg_vcomp.h
//! @file
//!
//! @brief Register macros for the VCOMP module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_VCOMP_H
#define AM_REG_VCOMP_H
//*****************************************************************************
//
// VCOMP
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_VCOMP_NUM_MODULES 1
#define AM_REG_VCOMPn(n) \
(REG_VCOMP_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_VCOMP_CFG_O 0x00000000
#define AM_REG_VCOMP_STAT_O 0x00000004
#define AM_REG_VCOMP_PWDKEY_O 0x00000008
#define AM_REG_VCOMP_INTEN_O 0x00000200
#define AM_REG_VCOMP_INTSTAT_O 0x00000204
#define AM_REG_VCOMP_INTCLR_O 0x00000208
#define AM_REG_VCOMP_INTSET_O 0x0000020C
//*****************************************************************************
//
// Key values.
//
//*****************************************************************************
#define AM_REG_VCOMP_PWDKEY_KEYVAL 0x00000037
//*****************************************************************************
//
// VCOMP_INTEN - Voltage Comparator Interrupt registers: Enable
//
//*****************************************************************************
// This bit is the vcompout high interrupt.
#define AM_REG_VCOMP_INTEN_OUTHI_S 1
#define AM_REG_VCOMP_INTEN_OUTHI_M 0x00000002
#define AM_REG_VCOMP_INTEN_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit is the vcompout low interrupt.
#define AM_REG_VCOMP_INTEN_OUTLOW_S 0
#define AM_REG_VCOMP_INTEN_OUTLOW_M 0x00000001
#define AM_REG_VCOMP_INTEN_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// VCOMP_INTSTAT - Voltage Comparator Interrupt registers: Status
//
//*****************************************************************************
// This bit is the vcompout high interrupt.
#define AM_REG_VCOMP_INTSTAT_OUTHI_S 1
#define AM_REG_VCOMP_INTSTAT_OUTHI_M 0x00000002
#define AM_REG_VCOMP_INTSTAT_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit is the vcompout low interrupt.
#define AM_REG_VCOMP_INTSTAT_OUTLOW_S 0
#define AM_REG_VCOMP_INTSTAT_OUTLOW_M 0x00000001
#define AM_REG_VCOMP_INTSTAT_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// VCOMP_INTCLR - Voltage Comparator Interrupt registers: Clear
//
//*****************************************************************************
// This bit is the vcompout high interrupt.
#define AM_REG_VCOMP_INTCLR_OUTHI_S 1
#define AM_REG_VCOMP_INTCLR_OUTHI_M 0x00000002
#define AM_REG_VCOMP_INTCLR_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit is the vcompout low interrupt.
#define AM_REG_VCOMP_INTCLR_OUTLOW_S 0
#define AM_REG_VCOMP_INTCLR_OUTLOW_M 0x00000001
#define AM_REG_VCOMP_INTCLR_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// VCOMP_INTSET - Voltage Comparator Interrupt registers: Set
//
//*****************************************************************************
// This bit is the vcompout high interrupt.
#define AM_REG_VCOMP_INTSET_OUTHI_S 1
#define AM_REG_VCOMP_INTSET_OUTHI_M 0x00000002
#define AM_REG_VCOMP_INTSET_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bit is the vcompout low interrupt.
#define AM_REG_VCOMP_INTSET_OUTLOW_S 0
#define AM_REG_VCOMP_INTSET_OUTLOW_M 0x00000001
#define AM_REG_VCOMP_INTSET_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// VCOMP_CFG - Configuration Register
//
//*****************************************************************************
// When the reference input NSEL is set to NSEL_DAC, this bitfield selects the
// voltage level for the negative input to the comparator.
#define AM_REG_VCOMP_CFG_LVLSEL_S 16
#define AM_REG_VCOMP_CFG_LVLSEL_M 0x000F0000
#define AM_REG_VCOMP_CFG_LVLSEL(n) (((uint32_t)(n) << 16) & 0x000F0000)
#define AM_REG_VCOMP_CFG_LVLSEL_0P58V 0x00000000
#define AM_REG_VCOMP_CFG_LVLSEL_0P77V 0x00010000
#define AM_REG_VCOMP_CFG_LVLSEL_0P97V 0x00020000
#define AM_REG_VCOMP_CFG_LVLSEL_1P16V 0x00030000
#define AM_REG_VCOMP_CFG_LVLSEL_1P35V 0x00040000
#define AM_REG_VCOMP_CFG_LVLSEL_1P55V 0x00050000
#define AM_REG_VCOMP_CFG_LVLSEL_1P74V 0x00060000
#define AM_REG_VCOMP_CFG_LVLSEL_1P93V 0x00070000
#define AM_REG_VCOMP_CFG_LVLSEL_2P13V 0x00080000
#define AM_REG_VCOMP_CFG_LVLSEL_2P32V 0x00090000
#define AM_REG_VCOMP_CFG_LVLSEL_2P51V 0x000A0000
#define AM_REG_VCOMP_CFG_LVLSEL_2P71V 0x000B0000
#define AM_REG_VCOMP_CFG_LVLSEL_2P90V 0x000C0000
#define AM_REG_VCOMP_CFG_LVLSEL_3P09V 0x000D0000
#define AM_REG_VCOMP_CFG_LVLSEL_3P29V 0x000E0000
#define AM_REG_VCOMP_CFG_LVLSEL_3P48V 0x000F0000
// This bitfield selects the negative input to the comparator.
#define AM_REG_VCOMP_CFG_NSEL_S 8
#define AM_REG_VCOMP_CFG_NSEL_M 0x00000300
#define AM_REG_VCOMP_CFG_NSEL(n) (((uint32_t)(n) << 8) & 0x00000300)
#define AM_REG_VCOMP_CFG_NSEL_VREFEXT1 0x00000000
#define AM_REG_VCOMP_CFG_NSEL_VREFEXT2 0x00000100
#define AM_REG_VCOMP_CFG_NSEL_VREFEXT3 0x00000200
#define AM_REG_VCOMP_CFG_NSEL_DAC 0x00000300
// This bitfield selects the positive input to the comparator.
#define AM_REG_VCOMP_CFG_PSEL_S 0
#define AM_REG_VCOMP_CFG_PSEL_M 0x00000003
#define AM_REG_VCOMP_CFG_PSEL(n) (((uint32_t)(n) << 0) & 0x00000003)
#define AM_REG_VCOMP_CFG_PSEL_VDDADJ 0x00000000
#define AM_REG_VCOMP_CFG_PSEL_VTEMP 0x00000001
#define AM_REG_VCOMP_CFG_PSEL_VEXT1 0x00000002
#define AM_REG_VCOMP_CFG_PSEL_VEXT2 0x00000003
//*****************************************************************************
//
// VCOMP_STAT - Status Register
//
//*****************************************************************************
// This bit indicates the power down state of the voltage comparator.
#define AM_REG_VCOMP_STAT_PWDSTAT_S 1
#define AM_REG_VCOMP_STAT_PWDSTAT_M 0x00000002
#define AM_REG_VCOMP_STAT_PWDSTAT(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_VCOMP_STAT_PWDSTAT_POWERED_DOWN 0x00000002
// This bit is 1 if the positive input of the comparator is greater than the
// negative input.
#define AM_REG_VCOMP_STAT_CMPOUT_S 0
#define AM_REG_VCOMP_STAT_CMPOUT_M 0x00000001
#define AM_REG_VCOMP_STAT_CMPOUT(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_VCOMP_STAT_CMPOUT_VOUT_LOW 0x00000000
#define AM_REG_VCOMP_STAT_CMPOUT_VOUT_HIGH 0x00000001
#endif // AM_REG_VCOMP_H
ambiq-hal-sys/ambiq-sparkfun-sdk/mcu/apollo2/regs/am_reg_wdt.h
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//*****************************************************************************
//
// am_reg_wdt.h
//! @file
//!
//! @brief Register macros for the WDT module
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_WDT_H
#define AM_REG_WDT_H
//*****************************************************************************
//
// WDT
// Instance finder. (1 instance(s) available)
//
//*****************************************************************************
#define AM_REG_WDT_NUM_MODULES 1
#define AM_REG_WDTn(n) \
(REG_WDT_BASEADDR + 0x00000000 * n)
//*****************************************************************************
//
// Register offsets.
//
//*****************************************************************************
#define AM_REG_WDT_CFG_O 0x00000000
#define AM_REG_WDT_RSTRT_O 0x00000004
#define AM_REG_WDT_LOCK_O 0x00000008
#define AM_REG_WDT_COUNT_O 0x0000000C
#define AM_REG_WDT_INTEN_O 0x00000200
#define AM_REG_WDT_INTSTAT_O 0x00000204
#define AM_REG_WDT_INTCLR_O 0x00000208
#define AM_REG_WDT_INTSET_O 0x0000020C
//*****************************************************************************
//
// WDT_INTEN - WDT Interrupt register: Enable
//
//*****************************************************************************
// Watchdog Timer Interrupt.
#define AM_REG_WDT_INTEN_WDTINT_S 0
#define AM_REG_WDT_INTEN_WDTINT_M 0x00000001
#define AM_REG_WDT_INTEN_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// WDT_INTSTAT - WDT Interrupt register: Status
//
//*****************************************************************************
// Watchdog Timer Interrupt.
#define AM_REG_WDT_INTSTAT_WDTINT_S 0
#define AM_REG_WDT_INTSTAT_WDTINT_M 0x00000001
#define AM_REG_WDT_INTSTAT_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// WDT_INTCLR - WDT Interrupt register: Clear
//
//*****************************************************************************
// Watchdog Timer Interrupt.
#define AM_REG_WDT_INTCLR_WDTINT_S 0
#define AM_REG_WDT_INTCLR_WDTINT_M 0x00000001
#define AM_REG_WDT_INTCLR_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// WDT_INTSET - WDT Interrupt register: Set
//
//*****************************************************************************
// Watchdog Timer Interrupt.
#define AM_REG_WDT_INTSET_WDTINT_S 0
#define AM_REG_WDT_INTSET_WDTINT_M 0x00000001
#define AM_REG_WDT_INTSET_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// WDT_CFG - Configuration Register
//
//*****************************************************************************
// Select the frequency for the WDT. All values not enumerated below are
// undefined.
#define AM_REG_WDT_CFG_CLKSEL_S 24
#define AM_REG_WDT_CFG_CLKSEL_M 0x07000000
#define AM_REG_WDT_CFG_CLKSEL(n) (((uint32_t)(n) << 24) & 0x07000000)
#define AM_REG_WDT_CFG_CLKSEL_OFF 0x00000000
#define AM_REG_WDT_CFG_CLKSEL_128HZ 0x01000000
#define AM_REG_WDT_CFG_CLKSEL_16HZ 0x02000000
#define AM_REG_WDT_CFG_CLKSEL_1HZ 0x03000000
#define AM_REG_WDT_CFG_CLKSEL_1_16HZ 0x04000000
// This bitfield is the compare value for counter bits 7:0 to generate a
// watchdog interrupt.
#define AM_REG_WDT_CFG_INTVAL_S 16
#define AM_REG_WDT_CFG_INTVAL_M 0x00FF0000
#define AM_REG_WDT_CFG_INTVAL(n) (((uint32_t)(n) << 16) & 0x00FF0000)
// This bitfield is the compare value for counter bits 7:0 to generate a
// watchdog reset.
#define AM_REG_WDT_CFG_RESVAL_S 8
#define AM_REG_WDT_CFG_RESVAL_M 0x0000FF00
#define AM_REG_WDT_CFG_RESVAL(n) (((uint32_t)(n) << 8) & 0x0000FF00)
// This bitfield enables the WDT reset.
#define AM_REG_WDT_CFG_RESEN_S 2
#define AM_REG_WDT_CFG_RESEN_M 0x00000004
#define AM_REG_WDT_CFG_RESEN(n) (((uint32_t)(n) << 2) & 0x00000004)
// This bitfield enables the WDT interrupt. Note : This bit must be set before
// the interrupt status bit will reflect a watchdog timer expiration. The IER
// interrupt register must also be enabled for a WDT interrupt to be sent to the
// NVIC.
#define AM_REG_WDT_CFG_INTEN_S 1
#define AM_REG_WDT_CFG_INTEN_M 0x00000002
#define AM_REG_WDT_CFG_INTEN(n) (((uint32_t)(n) << 1) & 0x00000002)
// This bitfield enables the WDT.
#define AM_REG_WDT_CFG_WDTEN_S 0
#define AM_REG_WDT_CFG_WDTEN_M 0x00000001
#define AM_REG_WDT_CFG_WDTEN(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// WDT_RSTRT - Restart the watchdog timer
//
//*****************************************************************************
// Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
#define AM_REG_WDT_RSTRT_RSTRT_S 0
#define AM_REG_WDT_RSTRT_RSTRT_M 0x000000FF
#define AM_REG_WDT_RSTRT_RSTRT(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_WDT_RSTRT_RSTRT_KEYVALUE 0x000000B2
//*****************************************************************************
//
// WDT_LOCK - Locks the WDT
//
//*****************************************************************************
// Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be
// written and WDTEN is set.
#define AM_REG_WDT_LOCK_LOCK_S 0
#define AM_REG_WDT_LOCK_LOCK_M 0x000000FF
#define AM_REG_WDT_LOCK_LOCK(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_WDT_LOCK_LOCK_KEYVALUE 0x0000003A
//*****************************************************************************
//
// WDT_COUNT - Current Counter Value for WDT
//
//*****************************************************************************
// Read-Only current value of the WDT counter
#define AM_REG_WDT_COUNT_COUNT_S 0
#define AM_REG_WDT_COUNT_COUNT_M 0x000000FF
#define AM_REG_WDT_COUNT_COUNT(n) (((uint32_t)(n) << 0) & 0x000000FF)
#endif // AM_REG_WDT_H