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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/Makefile
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#******************************************************************************
#
# Makefile - Rules for compiling
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
# Include rules specific to this board
-include ../../board-defs.mk
-include example-defs.mk
# All makefiles use this to find the top level directory.
SWROOT?=../../../..
# Include rules for building generic examples.
include $(SWROOT)/makedefs/example.mk
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/README.txt
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Name:
=====
uart_boot_host
Description:
============
Converts UART Wired transfer commands to SPI for use with SBL SPI testing.
Purpose:
========
This example running on an intermediate board, along with the standard
uart_wired_update script running on host PC, can be used as a way to
communicate to Apollo3 SBL using SPI mode.
Printing takes place over the ITM at 1M Baud.
Additional Information:
=======================
PIN fly lead connections assumed:
HOST (this board) SLAVE (Apollo3 SBL target)
-------- --------
Apollo3 SPI or I2C common connections:
GPIO[2] GPIO Interrupt (slave to host) GPIO[4] GPIO interrupt
GPIO[4] OVERRIDE pin (host to slave) GPIO[16] Override pin or n/c
GPIO[17] Slave reset (host to slave) Reset Pin or n/c
GND GND
Apollo3 SPI additional connections:
GPIO[5] IOM0 SPI CLK GPIO[0] IOS SPI SCK
GPIO[6] IOM0 SPI MISO GPIO[2] IOS SPI MISO
GPIO[7] IOM0 SPI MOSI GPIO[1] IOS SPI MOSI
GPIO[11] IOM0 SPI nCE GPIO[3] IOS SPI nCE
Apollo3 I2C additional connections:
GPIO[5] I2C SCL GPIO[0] I2C SCL
GPIO[6] I2C SDA GPIO[1] I2C SDA
Reset and Override pin connections from Host are optional, but using them
automates the entire process.
SPI or I2C mode can be handled in a couple of ways:
- SPI mode is the default (i.e. don't press buttons or tie pins low).
- For I2C, press button2 during reset and hold it until the program begins,
i.e. you see the "I2C clock = " msg.
Alternatively the button2 pin can be tied low.
- Note that on the Apollo3 EVB, button2 is labelled as 'BTN4', which is
the button located nearest the end of the board.
Also on the Apollo3 EVB, BTN4 uses pin 19. It happens that the header
pin for pin 19 on the EVB is adjacent to a ground pin, so a jumper can
be used to assert I2C mode.
******************************************************************************
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/gcc/Makefile
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#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := uart_boot_host
COMPILERNAME := gcc
PROJECT := uart_boot_host_gcc
CONFIG := bin
SHELL:=/bin/bash
#### Setup ####
TOOLCHAIN ?= arm-none-eabi
PART = apollo3
CPU = cortex-m4
FPU = fpv4-sp-d16
# Default to FPU hardware calling convention. However, some customers and/or
# applications may need the software calling convention.
#FABI = softfp
FABI = hard
LINKER_FILE := ./uart_boot_host.ld
STARTUP_FILE := ./startup_$(COMPILERNAME).c
#### Required Executables ####
CC = $(TOOLCHAIN)-gcc
GCC = $(TOOLCHAIN)-gcc
CPP = $(TOOLCHAIN)-cpp
LD = $(TOOLCHAIN)-ld
CP = $(TOOLCHAIN)-objcopy
OD = $(TOOLCHAIN)-objdump
RD = $(TOOLCHAIN)-readelf
AR = $(TOOLCHAIN)-ar
SIZE = $(TOOLCHAIN)-size
RM = $(shell which rm 2>/dev/null)
EXECUTABLES = CC LD CP OD AR RD SIZE GCC
K := $(foreach exec,$(EXECUTABLES),\
$(if $(shell which $($(exec)) 2>/dev/null),,\
$(info $(exec) not found on PATH ($($(exec))).)$(exec)))
$(if $(strip $(value K)),$(info Required Program(s) $(strip $(value K)) not found))
ifneq ($(strip $(value K)),)
all clean:
$(info Tools $(TOOLCHAIN)-$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
DEFINES = -DPART_$(PART)
DEFINES+= -DAM_PACKAGE_BGA
DEFINES+= -DAM_PART_APOLLO3
DEFINES+= -Dgcc
INCLUDES = -I../../../../../utils
INCLUDES+= -I../../../../../CMSIS/ARM/Include
INCLUDES+= -I../../../bsp
INCLUDES+= -I../src
INCLUDES+= -I../../../../../mcu/apollo3
INCLUDES+= -I../../../../..
INCLUDES+= -I../../../../../devices
INCLUDES+= -I../../../../../CMSIS/AmbiqMicro/Include
VPATH = ../src
VPATH+=:../../../../../utils
VPATH+=:../../../../../devices
SRC = uart_boot_host.c
SRC += am_util_delay.c
SRC += am_util_faultisr.c
SRC += am_util_stdio.c
SRC += startup_gcc.c
CSRC = $(filter %.c,$(SRC))
ASRC = $(filter %.s,$(SRC))
OBJS = $(CSRC:%.c=$(CONFIG)/%.o)
OBJS+= $(ASRC:%.s=$(CONFIG)/%.o)
DEPS = $(CSRC:%.c=$(CONFIG)/%.d)
DEPS+= $(ASRC:%.s=$(CONFIG)/%.d)
LIBS = ../../../../../mcu/apollo3/hal/gcc/bin/libam_hal.a
LIBS += ../../../bsp/gcc/bin/libam_bsp.a
CFLAGS = -mthumb -mcpu=$(CPU) -mfpu=$(FPU) -mfloat-abi=$(FABI)
CFLAGS+= -ffunction-sections -fdata-sections -fomit-frame-pointer
CFLAGS+= -MMD -MP -std=c99 -Wall -g
CFLAGS+= -O0
CFLAGS+= $(DEFINES)
CFLAGS+= $(INCLUDES)
CFLAGS+=
LFLAGS = -mthumb -mcpu=$(CPU) -mfpu=$(FPU) -mfloat-abi=$(FABI)
LFLAGS+= -nostartfiles -static
LFLAGS+= -Wl,--gc-sections,--entry,Reset_Handler,-Map,$(CONFIG)/$(TARGET).map
LFLAGS+= -Wl,--start-group -lm -lc -lgcc $(LIBS) -Wl,--end-group
LFLAGS+=
# Additional user specified CFLAGS
CFLAGS+=$(EXTRA_CFLAGS)
CPFLAGS = -Obinary
ODFLAGS = -S
#### Rules ####
all: directories $(CONFIG)/$(TARGET).bin
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
$(CONFIG)/%.o: %.c $(CONFIG)/%.d
@echo " Compiling $(COMPILERNAME) $<" ;\
$(CC) -c $(CFLAGS) $< -o $@
$(CONFIG)/%.o: %.s $(CONFIG)/%.d
@echo " Assembling $(COMPILERNAME) $<" ;\
$(CC) -c $(CFLAGS) $< -o $@
$(CONFIG)/$(TARGET).axf: $(OBJS) $(LIBS)
@echo " Linking $(COMPILERNAME) $@" ;\
$(CC) -Wl,-T,$(LINKER_FILE) -o $@ $(OBJS) $(LFLAGS)
$(CONFIG)/$(TARGET).bin: $(CONFIG)/$(TARGET).axf
@echo " Copying $(COMPILERNAME) $@..." ;\
$(CP) $(CPFLAGS) $< $@ ;\
$(OD) $(ODFLAGS) $< > $(CONFIG)/$(TARGET).lst
clean:
@echo "Cleaning..." ;\
$(RM) -f $(OBJS) $(DEPS) \
$(CONFIG)/$(TARGET).bin $(CONFIG)/$(TARGET).axf \
$(CONFIG)/$(TARGET).lst $(CONFIG)/$(TARGET).map
$(CONFIG)/%.d: ;
../../../../../mcu/apollo3/hal/gcc/bin/libam_hal.a:
$(MAKE) -C ../../../../../mcu/apollo3/hal
../../../bsp/gcc/bin/libam_bsp.a:
$(MAKE) -C ../../../bsp
# Automatically include any generated dependencies
-include $(DEPS)
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/gcc/startup_gcc.c
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//*****************************************************************************
//
//! @file startup_gcc.c
//!
//! @brief Definitions for interrupt handlers, the vector table, and the stack.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
//*****************************************************************************
//
// Forward declaration of interrupt handlers.
//
//*****************************************************************************
extern void Reset_Handler(void) __attribute ((naked));
extern void NMI_Handler(void) __attribute ((weak));
extern void HardFault_Handler(void) __attribute ((weak));
extern void MemManage_Handler(void) __attribute ((weak, alias ("HardFault_Handler")));
extern void BusFault_Handler(void) __attribute ((weak, alias ("HardFault_Handler")));
extern void UsageFault_Handler(void) __attribute ((weak, alias ("HardFault_Handler")));
extern void SecureFault_Handler(void) __attribute ((weak));
extern void SVC_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void DebugMon_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void PendSV_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void SysTick_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_brownout_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_watchdog_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_rtc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_vcomp_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ioslave_ios_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ioslave_acc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster1_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster2_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster3_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster4_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster5_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ble_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_gpio_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ctimer_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_uart_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_uart1_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_scard_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_adc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_pdm0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_mspi0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_software0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr1_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr2_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr3_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr4_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr5_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr6_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr7_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_clkgen_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_default_isr(void) __attribute ((weak));
//*****************************************************************************
//
// The entry point for the application.
//
//*****************************************************************************
extern int main(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
__attribute__ ((section(".stack")))
static uint32_t g_pui32Stack[1024];
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
// am_usagefault_isr does not work if am_fault_isr is defined externally.
// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
//
//*****************************************************************************
__attribute__ ((section(".isr_vector")))
void (* const g_am_pfnVectors[])(void) =
{
(void (*)(void))((uint32_t)g_pui32Stack + sizeof(g_pui32Stack)),
// The initial stack pointer
Reset_Handler, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MemManage_Handler
BusFault_Handler, // The BusFault_Handler
UsageFault_Handler, // The UsageFault_Handler
SecureFault_Handler, // The SecureFault_Handler
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
//
// Peripheral Interrupts
//
am_brownout_isr, // 0: Brownout (rstgen)
am_watchdog_isr, // 1: Watchdog
am_rtc_isr, // 2: RTC
am_vcomp_isr, // 3: Voltage Comparator
am_ioslave_ios_isr, // 4: I/O Slave general
am_ioslave_acc_isr, // 5: I/O Slave access
am_iomaster0_isr, // 6: I/O Master 0
am_iomaster1_isr, // 7: I/O Master 1
am_iomaster2_isr, // 8: I/O Master 2
am_iomaster3_isr, // 9: I/O Master 3
am_iomaster4_isr, // 10: I/O Master 4
am_iomaster5_isr, // 11: I/O Master 5
am_ble_isr, // 12: BLEIF
am_gpio_isr, // 13: GPIO
am_ctimer_isr, // 14: CTIMER
am_uart_isr, // 15: UART0
am_uart1_isr, // 16: UART1
am_scard_isr, // 17: SCARD
am_adc_isr, // 18: ADC
am_pdm0_isr, // 19: PDM
am_mspi0_isr, // 20: MSPI0
am_software0_isr, // 21: SOFTWARE0
am_stimer_isr, // 22: SYSTEM TIMER
am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0
am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1
am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2
am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3
am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4
am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5
am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6
am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7
am_clkgen_isr, // 31: CLKGEN
};
//******************************************************************************
//
// Place code immediately following vector table.
//
//******************************************************************************
//******************************************************************************
//
// The Patch table.
//
// The patch table should pad the vector table size to a total of 64 entries
// (16 core + 48 periph) such that code begins at offset 0x100.
//
//******************************************************************************
__attribute__ ((section(".patch")))
uint32_t const __Patchable[] =
{
0, // 32
0, // 33
0, // 34
0, // 35
0, // 36
0, // 37
0, // 38
0, // 39
0, // 40
0, // 41
0, // 42
0, // 43
0, // 44
0, // 45
0, // 46
0, // 47
};
//*****************************************************************************
//
// The following are constructs created by the linker, indicating where the
// the "data" and "bss" segments reside in memory. The initializers for the
// "data" segment resides immediately following the "text" segment.
//
//*****************************************************************************
extern uint32_t _etext;
extern uint32_t _sdata;
extern uint32_t _edata;
extern uint32_t _sbss;
extern uint32_t _ebss;
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.
//
//*****************************************************************************
#if defined(__GNUC_STDC_INLINE__)
void
Reset_Handler(void)
{
//
// Set the vector table pointer.
//
__asm(" ldr r0, =0xE000ED08\n"
" ldr r1, =g_am_pfnVectors\n"
" str r1, [r0]");
//
// Set the stack pointer.
//
__asm(" ldr sp, [r1]");
#ifndef NOFPU
//
// Enable the FPU.
//
__asm("ldr r0, =0xE000ED88\n"
"ldr r1,[r0]\n"
"orr r1,#(0xF << 20)\n"
"str r1,[r0]\n"
"dsb\n"
"isb\n");
#endif
//
// Copy the data segment initializers from flash to SRAM.
//
__asm(" ldr r0, =_init_data\n"
" ldr r1, =_sdata\n"
" ldr r2, =_edata\n"
"copy_loop:\n"
" ldr r3, [r0], #4\n"
" str r3, [r1], #4\n"
" cmp r1, r2\n"
" blt copy_loop\n");
//
// Zero fill the bss segment.
//
__asm(" ldr r0, =_sbss\n"
" ldr r1, =_ebss\n"
" mov r2, #0\n"
"zero_loop:\n"
" cmp r0, r1\n"
" it lt\n"
" strlt r2, [r0], #4\n"
" blt zero_loop");
//
// Call the application's entry point.
//
main();
//
// If main returns then execute a break point instruction
//
__asm(" bkpt ");
}
#else
#error GNU STDC inline not supported.
#endif
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
void
NMI_Handler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void
HardFault_Handler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void
am_default_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/gcc/uart_boot_host.ld
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/******************************************************************************
*
* uart_boot_host.ld - Linker script for applications using startup_gnu.c
*
*****************************************************************************/
ENTRY(Reset_Handler)
MEMORY
{
ROMEM (rx) : ORIGIN = 0x0000C000, LENGTH = 960K
RWMEM (rwx) : ORIGIN = 0x10000000, LENGTH = 384K
}
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.isr_vector))
KEEP(*(.patch))
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
. = ALIGN(4);
_etext = .;
} > ROMEM
/* User stack section initialized by startup code. */
.stack (NOLOAD):
{
. = ALIGN(8);
*(.stack)
*(.stack*)
. = ALIGN(8);
} > RWMEM
.data :
{
. = ALIGN(4);
_sdata = .;
*(.data)
*(.data*)
. = ALIGN(4);
_edata = .;
} > RWMEM AT>ROMEM
/* used by startup to initialize data */
_init_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_sbss = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} > RWMEM
.ARM.attributes 0 : { *(.ARM.attributes) }
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/Makefile
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#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := uart_boot_host
COMPILERNAME := iar
PROJECT := uart_boot_host_iar
CONFIG := bin
AM_SoftwareRoot ?= ../../../..
SHELL:=/bin/bash
#### Required Executables ####
K := $(shell type -p IarBuild.exe)
RM = $(shell which rm 2>/dev/null)
ifeq ($(K),)
all clean:
$(info Tools w/$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
all: directories binary
.PHONY: binary
binary:
IarBuild.exe uart_boot_host.ewp -make Debug -log info
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
clean:
@echo Cleaning... ;\
IarBuild.exe uart_boot_host.ewp -clean Debug -log all
../../../../../mcu/apollo3/hal/iar/bin/libam_hal.a:
$(MAKE) -C ../../../../../mcu/apollo3/hal
../../../bsp/iar/bin/libam_bsp.a:
$(MAKE) -C ../../../bsp
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/bin/uart_boot_host.log
+5006
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File diff suppressed because it is too large Load Diff
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/bin/uart_boot_host.out
BIN
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Binary file not shown.
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/settings/uart_boot_host.dni
+127
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@@ -0,0 +1,127 @@
[Stack]
FillEnabled=0
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnLogOnly=1
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[Breakpoints]
Count=0
[GDBSERVERDriver]
GDB_LeaveTargetRunning=0x00000000
[DebugChecksum]
Checksum=-2034475309
[Exceptions]
StopOnUncaught=_ 0
StopOnThrow=_ 0
[CodeCoverage]
Enabled=_ 0
[CallStack]
ShowArgs=0
[Disassembly]
MixedMode=1
[JLinkDriver]
CStepIntDis=_ 0
LeaveTargetRunning=_ 0
TraceBufferSize=0x00010000
TraceStallIfFIFOFull=0x00000000
TracePortSize=0x00000000
[SWOTraceHWSettings]
OverrideDefaultClocks=1
CpuClock=6000000
ClockAutoDetect=0
ClockWanted=1000000
JtagSpeed=1000000
Prescaler=6
TimeStampPrescIndex=0
TimeStampPrescData=0
PcSampCYCTAP=1
PcSampPOSTCNT=15
PcSampIndex=0
DataLogMode=0
ITMportsEnable=1
ITMportsTermIO=1
ITMportsLogFile=0
ITMlogFile=$PROJ_DIR$\ITM.log
[Trace1]
Enabled=0
ShowSource=1
[Trace2]
Enabled=0
ShowSource=0
[SWOTraceWindow]
PcSampling=0
InterruptLogs=0
ForcedTimeStamps=0
EventCPI=0
EventEXC=0
EventFOLD=0
EventLSU=0
EventSLEEP=0
[PowerLog]
Title_0=I0
Symbol_0=0 4 0
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
LiveEnabled=0
LiveFile=PowerLogLive.log
[DataLog]
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
SumEnabled=0
ShowTimeSum=1
[EventLog]
Title_0=Ch3
Symbol_0=0 4 1
Title_1=Ch2
Symbol_1=0 4 1
Title_2=Ch1
Symbol_2=0 4 1
Title_3=Ch0
Symbol_3=0 4 1
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
SumEnabled=0
ShowTimeSum=1
SumSortOrder=0
[InterruptLog]
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
SumEnabled=0
ShowTimeSum=1
SumSortOrder=0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[DriverProfiling]
Enabled=0
Mode=1
Graph=0
Symbiont=0
Exclusions=
[CallStackLog]
Enabled=0
[CallStackStripe]
ShowTiming=1
[PowerProbe]
Frequency=10000
Probe0=I0
ProbeSetup0=2 1 1 2 0 0
[Disassemble mode]
mode=0
[Breakpoints2]
Count=0
[Aliases]
Count=0
SuppressDialog=0
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/settings/uart_boot_host.dnx
+167
View File
@@ -0,0 +1,167 @@
<?xml version="1.0"?>
<settings>
<DebugChecksum>
<Checksum>1749499678</Checksum>
</DebugChecksum>
<Exceptions>
<StopOnUncaught>_ 0</StopOnUncaught>
<StopOnThrow>_ 0</StopOnThrow>
</Exceptions>
<CodeCoverage>
<Enabled>_ 0</Enabled>
</CodeCoverage>
<Stack>
<FillEnabled>0</FillEnabled>
<OverflowWarningsEnabled>1</OverflowWarningsEnabled>
<WarningThreshold>90</WarningThreshold>
<SpWarningsEnabled>1</SpWarningsEnabled>
<WarnLogOnly>1</WarnLogOnly>
<UseTrigger>1</UseTrigger>
<TriggerName>main</TriggerName>
<LimitSize>0</LimitSize>
<ByteLimit>50</ByteLimit>
</Stack>
<CallStack>
<ShowArgs>0</ShowArgs>
</CallStack>
<JLinkDriver>
<CStepIntDis>_ 0</CStepIntDis>
<LeaveTargetRunning>_ 0</LeaveTargetRunning>
</JLinkDriver>
<SWOTraceHWSettings>
<OverrideDefaultClocks>1</OverrideDefaultClocks>
<CpuClock>6000000</CpuClock>
<ClockAutoDetect>0</ClockAutoDetect>
<ClockWanted>1000000</ClockWanted>
<JtagSpeed>1000000</JtagSpeed>
<Prescaler>6</Prescaler>
<TimeStampPrescIndex>0</TimeStampPrescIndex>
<TimeStampPrescData>0</TimeStampPrescData>
<PcSampCYCTAP>1</PcSampCYCTAP>
<PcSampPOSTCNT>15</PcSampPOSTCNT>
<PcSampIndex>0</PcSampIndex>
<DataLogMode>0</DataLogMode>
<ITMportsEnable>1</ITMportsEnable>
<ITMportsTermIO>1</ITMportsTermIO>
<ITMportsLogFile>1</ITMportsLogFile>
<ITMlogFile>$PROJ_DIR$\ITM.log</ITMlogFile>
</SWOTraceHWSettings>
<SfrWindow>
<Show>1 1</Show>
<Sort>4 0</Sort>
</SfrWindow>
<Disassembly>
<InstrCount>0</InstrCount>
<MixedMode>1</MixedMode>
</Disassembly>
<Interrupts>
<Enabled>1</Enabled>
</Interrupts>
<MemConfig>
<Base>1</Base>
<Manual>0</Manual>
<Ddf>1</Ddf>
<TypeViol>0</TypeViol>
<Stop>1</Stop>
</MemConfig>
<Simulator>
<Freq>10000000</Freq>
<FreqHi>0</FreqHi>
<MultiCoreRunAll>1</MultiCoreRunAll>
</Simulator>
<Trace1>
<Enabled>0</Enabled>
<ShowSource>1</ShowSource>
</Trace1>
<Trace2>
<Enabled>0</Enabled>
<ShowSource>0</ShowSource>
</Trace2>
<SWOTraceWindow>
<PcSampling>0</PcSampling>
<InterruptLogs>0</InterruptLogs>
<ForcedTimeStamps>0</ForcedTimeStamps>
<EventCPI>0</EventCPI>
<EventEXC>0</EventEXC>
<EventFOLD>0</EventFOLD>
<EventLSU>0</EventLSU>
<EventSLEEP>0</EventSLEEP>
</SWOTraceWindow>
<PowerLog>
<Title_0>I0</Title_0>
<Symbol_0>0 4 0</Symbol_0>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<LiveEnabled>0</LiveEnabled>
<LiveFile>PowerLogLive.log</LiveFile>
</PowerLog>
<DataLog>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
</DataLog>
<InterruptLog>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
<SumSortOrder>0</SumSortOrder>
</InterruptLog>
<EventLog>
<Title_0>Ch3</Title_0>
<Symbol_0>0 0 1</Symbol_0>
<Title_1>Ch2</Title_1>
<Symbol_1>0 0 1</Symbol_1>
<Title_2>Ch1</Title_2>
<Symbol_2>0 0 1</Symbol_2>
<Title_3>Ch0</Title_3>
<Symbol_3>0 0 1</Symbol_3>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
<SumSortOrder>0</SumSortOrder>
</EventLog>
<LogFile>
<LoggingEnabled>_ 0</LoggingEnabled>
<LogFile>_ ""</LogFile>
<Category>_ 0</Category>
</LogFile>
<TermIOLog>
<LoggingEnabled>_ 0</LoggingEnabled>
<LogFile>_ ""</LogFile>
</TermIOLog>
<DriverProfiling>
<Enabled>0</Enabled>
<Mode>1</Mode>
<Graph>0</Graph>
<Symbiont>0</Symbiont>
<Exclusions />
</DriverProfiling>
<CallStackLog>
<Enabled>0</Enabled>
</CallStackLog>
<CallStackStripe>
<ShowTiming>1</ShowTiming>
</CallStackStripe>
<PowerProbe>
<Frequency>10000</Frequency>
<Probe0>I0</Probe0>
<ProbeSetup0>2 1 1 2 0 0</ProbeSetup0>
</PowerProbe>
<DisassembleMode>
<mode>0</mode>
</DisassembleMode>
<Breakpoints2>
<Count>0</Count>
</Breakpoints2>
<Aliases>
<Count>0</Count>
<SuppressDialog>0</SuppressDialog>
</Aliases>
</settings>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/settings/uart_boot_host_Debug.jlink
+39
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@@ -0,0 +1,39 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile="AMA3B1KK-KBR.JLinkScript"
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="AMA3B1KK-KBR"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/startup_iar.c
+398
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@@ -0,0 +1,398 @@
//*****************************************************************************
//
//! @file startup_iar.c
//!
//! @brief Definitions for interrupt handlers, the vector table, and the stack.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
//*****************************************************************************
//
// Enable the IAR extensions for this source file.
//
//*****************************************************************************
#pragma language = extended
//*****************************************************************************
//
// Weak function links.
//
//*****************************************************************************
#pragma weak MemManage_Handler = HardFault_Handler
#pragma weak BusFault_Handler = HardFault_Handler
#pragma weak UsageFault_Handler = HardFault_Handler
#pragma weak SecureFault_Handler = HardFault_Handler
#pragma weak SVC_Handler = am_default_isr
#pragma weak DebugMon_Handler = am_default_isr
#pragma weak PendSV_Handler = am_default_isr
#pragma weak SysTick_Handler = am_default_isr
#pragma weak am_brownout_isr = am_default_isr
#pragma weak am_watchdog_isr = am_default_isr
#pragma weak am_rtc_isr = am_default_isr
#pragma weak am_vcomp_isr = am_default_isr
#pragma weak am_ioslave_ios_isr = am_default_isr
#pragma weak am_ioslave_acc_isr = am_default_isr
#pragma weak am_iomaster0_isr = am_default_isr
#pragma weak am_iomaster1_isr = am_default_isr
#pragma weak am_iomaster2_isr = am_default_isr
#pragma weak am_iomaster3_isr = am_default_isr
#pragma weak am_iomaster4_isr = am_default_isr
#pragma weak am_iomaster5_isr = am_default_isr
#pragma weak am_ble_isr = am_default_isr
#pragma weak am_gpio_isr = am_default_isr
#pragma weak am_ctimer_isr = am_default_isr
#pragma weak am_uart_isr = am_default_isr
#pragma weak am_uart1_isr = am_default_isr
#pragma weak am_scard_isr = am_default_isr
#pragma weak am_adc_isr = am_default_isr
#pragma weak am_pdm0_isr = am_default_isr
#pragma weak am_mspi0_isr = am_default_isr
#pragma weak am_software0_isr = am_default_isr
#pragma weak am_stimer_isr = am_default_isr
#pragma weak am_stimer_cmpr0_isr = am_default_isr
#pragma weak am_stimer_cmpr1_isr = am_default_isr
#pragma weak am_stimer_cmpr2_isr = am_default_isr
#pragma weak am_stimer_cmpr3_isr = am_default_isr
#pragma weak am_stimer_cmpr4_isr = am_default_isr
#pragma weak am_stimer_cmpr5_isr = am_default_isr
#pragma weak am_stimer_cmpr6_isr = am_default_isr
#pragma weak am_stimer_cmpr7_isr = am_default_isr
#pragma weak am_flash_isr = am_default_isr
#pragma weak am_clkgen_isr = am_default_isr
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
extern __stackless void Reset_Handler(void);
extern __weak void NMI_Handler(void);
extern __weak void HardFault_Handler(void);
extern void MemManage_Handler(void);
extern void BusFault_Handler(void);
extern void UsageFault_Handler(void);
extern void SecureFault_Handler(void);
extern void SVC_Handler(void);
extern void DebugMon_Handler(void);
extern void PendSV_Handler(void);
extern void SysTick_Handler(void);
extern void am_brownout_isr(void);
extern void am_watchdog_isr(void);
extern void am_rtc_isr(void);
extern void am_vcomp_isr(void);
extern void am_ioslave_ios_isr(void);
extern void am_ioslave_acc_isr(void);
extern void am_iomaster0_isr(void);
extern void am_iomaster1_isr(void);
extern void am_iomaster2_isr(void);
extern void am_iomaster3_isr(void);
extern void am_iomaster4_isr(void);
extern void am_iomaster5_isr(void);
extern void am_ble_isr(void);
extern void am_gpio_isr(void);
extern void am_ctimer_isr(void);
extern void am_uart_isr(void);
extern void am_uart1_isr(void);
extern void am_scard_isr(void);
extern void am_adc_isr(void);
extern void am_pdm0_isr(void);
extern void am_mspi0_isr(void);
extern void am_software0_isr(void);
extern void am_stimer_isr(void);
extern void am_stimer_cmpr0_isr(void);
extern void am_stimer_cmpr1_isr(void);
extern void am_stimer_cmpr2_isr(void);
extern void am_stimer_cmpr3_isr(void);
extern void am_stimer_cmpr4_isr(void);
extern void am_stimer_cmpr5_isr(void);
extern void am_stimer_cmpr6_isr(void);
extern void am_stimer_cmpr7_isr(void);
extern void am_flash_isr(void);
extern void am_clkgen_isr(void);
extern void am_default_isr(void);
//*****************************************************************************
//
// The entry point for the application startup code.
//
//*****************************************************************************
extern void __iar_program_start(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
static uint32_t pui32Stack[1024] @ ".stack";
//*****************************************************************************
//
// A union that describes the entries of the vector table. The union is needed
// since the first entry is the stack pointer and the remainder are function
// pointers.
//
//*****************************************************************************
typedef union
{
void (*pfnHandler)(void);
uint32_t ui32Ptr;
}
uVectorEntry;
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
// am_usagefault_isr does not work if am_fault_isr is defined externally.
// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
//
//*****************************************************************************
__root const uVectorEntry __vector_table[] @ ".intvec" =
{
{ .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) },
// The initial stack pointer
Reset_Handler, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MemManage_Handler
BusFault_Handler, // The BusFault_Handler
UsageFault_Handler, // The UsageFault_Handler
SecureFault_Handler, // The SecureFault_Handler
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
//
// Peripheral Interrupts
//
am_brownout_isr, // 0: Brownout (rstgen)
am_watchdog_isr, // 1: Watchdog
am_rtc_isr, // 2: RTC
am_vcomp_isr, // 3: Voltage Comparator
am_ioslave_ios_isr, // 4: I/O Slave general
am_ioslave_acc_isr, // 5: I/O Slave access
am_iomaster0_isr, // 6: I/O Master 0
am_iomaster1_isr, // 7: I/O Master 1
am_iomaster2_isr, // 8: I/O Master 2
am_iomaster3_isr, // 9: I/O Master 3
am_iomaster4_isr, // 10: I/O Master 4
am_iomaster5_isr, // 11: I/O Master 5
am_ble_isr, // 12: BLEIF
am_gpio_isr, // 13: GPIO
am_ctimer_isr, // 14: CTIMER
am_uart_isr, // 15: UART0
am_uart1_isr, // 16: UART1
am_scard_isr, // 17: SCARD
am_adc_isr, // 18: ADC
am_pdm0_isr, // 19: PDM
am_mspi0_isr, // 20: MSPI0
am_software0_isr, // 21: SOFTWARE0
am_stimer_isr, // 22: SYSTEM TIMER
am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0
am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1
am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2
am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3
am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4
am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5
am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6
am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7
am_clkgen_isr, // 31: CLKGEN
};
//******************************************************************************
//
// Place code immediately following vector table.
//
//******************************************************************************
//******************************************************************************
//
// The Patch table.
//
// The patch table should pad the vector table size to a total of 64 entries
// (16 core + 48 periph) such that code begins at offset 0x100.
//
//******************************************************************************
__root const uint32_t __Patchable[] @ ".patch" =
{
0, // 32
0, // 33
0, // 34
0, // 35
0, // 36
0, // 37
0, // 38
0, // 39
0, // 40
0, // 41
0, // 42
0, // 43
0, // 44
0, // 45
0, // 46
0, // 47
};
//*****************************************************************************
//
// Note - The template for this function is originally found in IAR's module,
// low_level_init.c. As supplied by IAR, it is an empty function.
//
// This module contains the function `__low_level_init', a function
// that is called before the `main' function of the program. Normally
// low-level initializations - such as setting the prefered interrupt
// level or setting the watchdog - can be performed here.
//
// Note that this function is called before the data segments are
// initialized, this means that this function cannot rely on the
// values of global or static variables.
//
// When this function returns zero, the startup code will inhibit the
// initialization of the data segments. The result is faster startup,
// the drawback is that neither global nor static data will be
// initialized.
//
// Copyright 1999-2017 IAR Systems AB.
//
// $Revision: 112610 $
//
//
//
//
//*****************************************************************************
#define AM_REGVAL(x) (*((volatile uint32_t *)(x)))
#define VTOR_ADDR 0xE000ED08
__interwork int __low_level_init(void)
{
AM_REGVAL(VTOR_ADDR) = (uint32_t)&__vector_table;
/*==================================*/
/* Choose if segment initialization */
/* should be done or not. */
/* Return: 0 to omit seg_init */
/* 1 to run seg_init */
/*==================================*/
return 1;
}
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.
//
//*****************************************************************************
void
Reset_Handler(void)
{
//
// Call the application's entry point.
//
__iar_program_start();
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
__weak void
NMI_Handler(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
__weak void
HardFault_Handler(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
am_default_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/uart_boot_host.ewd
+2810
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/uart_boot_host.ewp
+2067
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/uart_boot_host.eww
+10
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@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\uart_boot_host.ewp</path>
</project>
<batchBuild/>
</workspace>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/iar/uart_boot_host.icf
+87
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@@ -0,0 +1,87 @@
//*****************************************************************************
//
// uart_boot_host.icf
//
// IAR linker Configuration File
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
//
// Define a memory section that covers the entire 4 GB addressable space of the
// processor. (32-bit can address up to 4GB)
//
define memory mem with size = 4G;
//
// Define regions for the various types of internal memory.
//
define region ROMEM = mem:[from 0x0000C000 to 0x000FC000];
define region RWMEM = mem:[from 0x10000000 to 0x10060000];
//
// Define blocks for logical groups of data.
//
define block HEAP with alignment = 0x8, size = 0x00000000 { };
define block CSTACK with alignment = 0x8, size = 4096
{
section .stack
};
define block FLASHBASE with fixed order
{
readonly section .intvec,
readonly section .patch
};
//
// Set section properties.
//
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section .stack };
//
// Place code sections in memory regions.
//
place at start of ROMEM { block FLASHBASE };
place in ROMEM { readonly };
place at start of RWMEM { block CSTACK};
place in RWMEM { block HEAP, readwrite, section .noinit };
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/Dbg_RAM.ini
+55
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@@ -0,0 +1,55 @@
/*----------------------------------------------------------------------------
* Name: Dbg_RAM.ini
* Purpose: RAM Debug Initialization File
* Note(s):
*----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* This software is supplied "AS IS" without warranties of any kind.
*
* Copyright (c) 2008-2013 Keil - An ARM Company. All rights reserved.
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
TraceSetup() Turn on ITM clocks, etc.
*----------------------------------------------------------------------------*/
FUNC void TraceSetup (void)
{
// turn on the ITM/TPIU clock
//_WDWORD(0x40020250, 0x00000201); // TPIU clock enabled at 3MHz
}
/*----------------------------------------------------------------------------
Setup() configure PC & SP for RAM Debug
*----------------------------------------------------------------------------*/
FUNC void Setup (void) {
SP = _RDWORD(0x0000C000+0x0); // Setup Stack Pointer
PC = _RDWORD(0x0000C000+0x4); // Setup Program Counter
_WDWORD(0xE000ED08, 0x0000C000+0x0); // Setup Vector Table Offset Register (done in system file)
}
/*----------------------------------------------------------------------------
OnResetExec() executed after reset via uVision's 'Reset'-button
*----------------------------------------------------------------------------*/
FUNC void OnResetExec (void)
{
}
LOAD %L INCREMENTAL // load the application
Setup(); // Setup for Running
BS main
g
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/JLinkSettings.ini
+40
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@@ -0,0 +1,40 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
; ScriptFile="AMAPH1KK-KBR.JLinkScript"
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="AMA3B1KK-KBR"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/Makefile
+80
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@@ -0,0 +1,80 @@
#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := uart_boot_host
COMPILERNAME := Keil
PROJECT := uart_boot_host_Keil
CONFIG := bin
SHELL:=/bin/bash
#### Required Executables ####
K := $(shell type -p UV4.exe)
RM := $(shell which rm 2>/dev/null)
ifeq ($(K),)
all clean:
$(info Tools w/$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
all: directories binary
.PHONY: binary
binary:
UV4.exe -b -t "uart_boot_host" uart_boot_host.uvprojx -j0 || [ $$? -eq 1 ]
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
clean:
@echo Cleaning... ;\
$(RM) -rf $(CONFIG)
../../../../../mcu/apollo3/hal/keil/bin/libam_hal.lib:
$(MAKE) -C ../../../../../mcu/apollo3/hal
../../../bsp/keil/bin/libam_bsp.lib:
$(MAKE) -C ../../../bsp
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/bin/uart_boot_host.txt
+8715
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/startup_keil.s
+408
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@@ -0,0 +1,408 @@
;******************************************************************************
;
;! @file startup_keil.s
;!
;! @brief Definitions for Apollo3 interrupt handlers, the vector table, and the stack.
;
;******************************************************************************
;******************************************************************************
;
; Copyright (c) 2020, Ambiq Micro
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; Third party software included in this distribution is subject to the
; additional license terms as defined in the /docs/licenses directory.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
;
;******************************************************************************
;******************************************************************************
;
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;************************************************************************
Stack EQU 0x00001000
;******************************************************************************
;
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;
;******************************************************************************
Heap EQU 0x00000000
;******************************************************************************
;
; Allocate space for the stack.
;
;******************************************************************************
AREA STACK, NOINIT, READWRITE, ALIGN=3
StackMem
SPACE Stack
__initial_sp
;******************************************************************************
;
; Allocate space for the heap.
;
;******************************************************************************
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
HeapMem
SPACE Heap
__heap_limit
;******************************************************************************
;
; Indicate that the code in this file preserves 8-byte alignment of the stack.
;
;******************************************************************************
PRESERVE8
;******************************************************************************
;
; Place code into the reset code section.
;
;******************************************************************************
AREA RESET, CODE, READONLY
THUMB
;******************************************************************************
;
; The vector table.
;
;******************************************************************************
;
; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
; am_usagefault_isr does not work if am_fault_isr is defined externally.
; Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
;
EXPORT __Vectors
__Vectors
DCD StackMem + Stack ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; The MPU fault handler
DCD BusFault_Handler ; The bus fault handler
DCD UsageFault_Handler ; The usage fault handler
DCD SecureFault_Handler ; Secure fault handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall handler
DCD DebugMon_Handler ; Debug monitor handler
DCD 0 ; Reserved
DCD PendSV_Handler ; The PendSV handler
DCD SysTick_Handler ; The SysTick handler
;
; Peripheral Interrupts
;
DCD am_brownout_isr ; 0: Reserved
DCD am_watchdog_isr ; 1: Reserved
DCD am_rtc_isr ; 2: RTC
DCD am_vcomp_isr ; 3: Voltage Comparator
DCD am_ioslave_ios_isr ; 4: I/O Slave general
DCD am_ioslave_acc_isr ; 5: I/O Slave access
DCD am_iomaster0_isr ; 6: I/O Master 0
DCD am_iomaster1_isr ; 7: I/O Master 1
DCD am_iomaster2_isr ; 8: I/O Master 2
DCD am_iomaster3_isr ; 9: I/O Master 3
DCD am_iomaster4_isr ; 10: I/O Master 4
DCD am_iomaster5_isr ; 11: I/O Master 5
DCD am_ble_isr ; 12: BLEIF
DCD am_gpio_isr ; 13: GPIO
DCD am_ctimer_isr ; 14: CTIMER
DCD am_uart_isr ; 15: UART0
DCD am_uart1_isr ; 16: UART1
DCD am_scard_isr ; 17: SCARD
DCD am_adc_isr ; 18: ADC
DCD am_pdm0_isr ; 19: PDM
DCD am_mspi0_isr ; 20: MSPI0
DCD am_software0_isr ; 21: SOFTWARE0
DCD am_stimer_isr ; 22: SYSTEM TIMER
DCD am_stimer_cmpr0_isr ; 23: SYSTEM TIMER COMPARE0
DCD am_stimer_cmpr1_isr ; 24: SYSTEM TIMER COMPARE1
DCD am_stimer_cmpr2_isr ; 25: SYSTEM TIMER COMPARE2
DCD am_stimer_cmpr3_isr ; 26: SYSTEM TIMER COMPARE3
DCD am_stimer_cmpr4_isr ; 27: SYSTEM TIMER COMPARE4
DCD am_stimer_cmpr5_isr ; 28: SYSTEM TIMER COMPARE5
DCD am_stimer_cmpr6_isr ; 29: SYSTEM TIMER COMPARE6
DCD am_stimer_cmpr7_isr ; 30: SYSTEM TIMER COMPARE7
DCD am_clkgen_isr ; 31: CLKGEN
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
;******************************************************************************
;
; Place code immediately following vector table.
;
;******************************************************************************
;******************************************************************************
;
; The Patch table.
;
; The patch table should pad the vector table size to a total of 64 entries
; (16 core + 48 periph) such that code begins at offset 0x100.
;
;******************************************************************************
EXPORT __Patchable
__Patchable
DCD 0 ; 32
DCD 0 ; 33
DCD 0 ; 34
DCD 0 ; 35
DCD 0 ; 36
DCD 0 ; 37
DCD 0 ; 38
DCD 0 ; 39
DCD 0 ; 40
DCD 0 ; 41
DCD 0 ; 42
DCD 0 ; 43
DCD 0 ; 44
DCD 0 ; 45
DCD 0 ; 46
DCD 0 ; 47
;******************************************************************************
;
; This is the code that gets called when the processor first starts execution
; following a reset event.
;
;******************************************************************************
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
;
; Enable the FPU.
;
MOVW R0, #0xED88
MOVT R0, #0xE000
LDR R1, [R0]
ORR R1, #0x00F00000
STR R1, [R0]
DSB
ISB
;
; Branch to main.
;
LDR R0, =__main
BX R0
ENDP
;******************************************************************************
;
; Weak Exception Handlers.
;
;******************************************************************************
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SecureFault_Handler\
PROC
EXPORT SecureFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
am_default_isr\
PROC
EXPORT am_brownout_isr [WEAK]
EXPORT am_watchdog_isr [WEAK]
EXPORT am_rtc_isr [WEAK]
EXPORT am_vcomp_isr [WEAK]
EXPORT am_ioslave_ios_isr [WEAK]
EXPORT am_ioslave_acc_isr [WEAK]
EXPORT am_iomaster0_isr [WEAK]
EXPORT am_iomaster1_isr [WEAK]
EXPORT am_iomaster2_isr [WEAK]
EXPORT am_iomaster3_isr [WEAK]
EXPORT am_iomaster4_isr [WEAK]
EXPORT am_iomaster5_isr [WEAK]
EXPORT am_ble_isr [WEAK]
EXPORT am_gpio_isr [WEAK]
EXPORT am_ctimer_isr [WEAK]
EXPORT am_uart_isr [WEAK]
EXPORT am_uart0_isr [WEAK]
EXPORT am_uart1_isr [WEAK]
EXPORT am_scard_isr [WEAK]
EXPORT am_adc_isr [WEAK]
EXPORT am_pdm0_isr [WEAK]
EXPORT am_mspi0_isr [WEAK]
EXPORT am_software0_isr [WEAK]
EXPORT am_stimer_isr [WEAK]
EXPORT am_stimer_cmpr0_isr [WEAK]
EXPORT am_stimer_cmpr1_isr [WEAK]
EXPORT am_stimer_cmpr2_isr [WEAK]
EXPORT am_stimer_cmpr3_isr [WEAK]
EXPORT am_stimer_cmpr4_isr [WEAK]
EXPORT am_stimer_cmpr5_isr [WEAK]
EXPORT am_stimer_cmpr6_isr [WEAK]
EXPORT am_stimer_cmpr7_isr [WEAK]
EXPORT am_clkgen_isr [WEAK]
am_brownout_isr
am_watchdog_isr
am_rtc_isr
am_vcomp_isr
am_ioslave_ios_isr
am_ioslave_acc_isr
am_iomaster0_isr
am_iomaster1_isr
am_iomaster2_isr
am_iomaster3_isr
am_iomaster4_isr
am_iomaster5_isr
am_ble_isr
am_gpio_isr
am_ctimer_isr
am_uart_isr
am_uart0_isr
am_uart1_isr
am_scard_isr
am_adc_isr
am_pdm0_isr
am_mspi0_isr
am_software0_isr
am_stimer_isr
am_stimer_cmpr0_isr
am_stimer_cmpr1_isr
am_stimer_cmpr2_isr
am_stimer_cmpr3_isr
am_stimer_cmpr4_isr
am_stimer_cmpr5_isr
am_stimer_cmpr6_isr
am_stimer_cmpr7_isr
am_clkgen_isr
; all device interrupts go here unless the weak label is over
; ridden in the linker hard spin so the debugger will know it
; was an unhandled interrupt request a come-from-buffer or
; instruction trace hardware would sure be nice if you get here
B .
ENDP
;******************************************************************************
;
; Align the end of the section.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; Initialization of the heap and stack.
;
;******************************************************************************
AREA |.text|, CODE, READONLY
;******************************************************************************
;
; User Initial Stack & Heap.
;
;******************************************************************************
IF :DEF: __MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, =HeapMem
LDR R1, =(StackMem + Stack)
LDR R2, =(HeapMem + Heap)
LDR R3, =StackMem
BX LR
ENDP
ENDIF
;******************************************************************************
;
; Align the end of the section.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; All Done
;
;******************************************************************************
END
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/uart_boot_host.sct
+60
View File
@@ -0,0 +1,60 @@
;******************************************************************************
;
; uart_boot_host.sct
;
; Scatter file for Keil linker configuration.
;
;******************************************************************************
;******************************************************************************
;
; Copyright (c) 2020, Ambiq Micro
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; Third party software included in this distribution is subject to the
; additional license terms as defined in the /docs/licenses directory.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
;
;******************************************************************************
LR_1 0x0000C000
{
FLASH 0x0000C000 0x000F0000
{
*.o (RESET, +First)
* (+RO)
}
SRAM 0x10000000 0x00060000
{
startup_keil.o (STACK, +First)
* (+RW, +ZI)
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/uart_boot_host.uvoptx
+300
View File
@@ -0,0 +1,300 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>uart_boot_host</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>48000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/keil/uart_boot_host.uvprojx
+445
View File
@@ -0,0 +1,445 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
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<Header>### uVision Project, (C) Keil Software</Header>
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<FileName>uart_boot_host.c</FileName>
<FileType>1</FileType>
<FilePath>../src/uart_boot_host.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>utils</GroupName>
<Files>
<File>
<FileName>am_util_delay.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../utils/am_util_delay.c</FilePath>
</File>
<File>
<FileName>am_util_faultisr.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../utils/am_util_faultisr.c</FilePath>
</File>
<File>
<FileName>am_util_stdio.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../utils/am_util_stdio.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>keil</GroupName>
<Files>
<File>
<FileName>startup_keil.s</FileName>
<FileType>1</FileType>
<FilePath>../keil/startup_keil.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>lib</GroupName>
<Files>
<File>
<FileName>libam_hal.lib</FileName>
<FileType>4</FileType>
<FilePath>../../../../../mcu/apollo3/hal/keil/bin/libam_hal.lib</FilePath>
</File>
<File>
<FileName>libam_bsp.lib</FileName>
<FileType>4</FileType>
<FilePath>../../../bsp/keil/bin/libam_bsp.lib</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/mem_map.yaml
+32
View File
@@ -0,0 +1,32 @@
#******************************************************************************
#
# Memory configuration
#
# This is a configuration file to help you set up consistent linker settings
# across multiple toolchains.
#
#******************************************************************************
MemorySections:
# Default memory region for vector table, code, and read-only data.
ROMEM:
start: 0x0000C000
size: 2000K
# Default memory region for fast-access data
TCM:
start: 0x10000000
size: 64K
# Default memory location for read-write, zero-init, and no-init data.
RWMEM:
start: 0x10010000
end: 0x100C0000
StackOptions:
# Number of bytes to use for the stack.
size: 4K
# Should the stack be placed in TCM? If false, the stack will be placed in RWMEM.
place_in_tcm: false
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/uart_boot_host/src/uart_boot_host.c
+896
View File
@@ -0,0 +1,896 @@
//*****************************************************************************
//
//! @file uart_boot_host.c
//!
//! @brief Converts UART Wired transfer commands to SPI for use with SBL SPI testing.
//!
//! Purpose: This example running on an intermediate board, along with the standard
//! uart_wired_update script running on host PC, can be used as a way to
//! communicate to Apollo3 SBL using SPI mode.
//!
//! Printing takes place over the ITM at 1M Baud.
//!
//! Additional Information:
//! @verbatim
//! PIN fly lead connections assumed:
//! HOST (this board) SLAVE (Apollo3 SBL target)
//! -------- --------
//! Apollo3 SPI or I2C common connections:
//! GPIO[2] GPIO Interrupt (slave to host) GPIO[4] GPIO interrupt
//! GPIO[4] OVERRIDE pin (host to slave) GPIO[16] Override pin or n/c
//! GPIO[17] Slave reset (host to slave) Reset Pin or n/c
//! GND GND
//!
//! Apollo3 SPI additional connections:
//! GPIO[5] IOM0 SPI CLK GPIO[0] IOS SPI SCK
//! GPIO[6] IOM0 SPI MISO GPIO[2] IOS SPI MISO
//! GPIO[7] IOM0 SPI MOSI GPIO[1] IOS SPI MOSI
//! GPIO[11] IOM0 SPI nCE GPIO[3] IOS SPI nCE
//!
//! Apollo3 I2C additional connections:
//! GPIO[5] I2C SCL GPIO[0] I2C SCL
//! GPIO[6] I2C SDA GPIO[1] I2C SDA
//!
//! Reset and Override pin connections from Host are optional, but using them
//! automates the entire process.
//!
//! SPI or I2C mode can be handled in a couple of ways:
//! - SPI mode is the default (i.e. don't press buttons or tie pins low).
//! - For I2C, press button2 during reset and hold it until the program begins,
//! i.e. you see the "I2C clock = " msg.
//! Alternatively the button2 pin can be tied low.
//! - Note that on the Apollo3 EVB, button2 is labelled as 'BTN4', which is
//! the button located nearest the end of the board.
//! Also on the Apollo3 EVB, BTN4 uses pin 19. It happens that the header
//! pin for pin 19 on the EVB is adjacent to a ground pin, so a jumper can
//! be used to assert I2C mode.
//!
//! @endverbatim
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "am_mcu_apollo.h"
#include "am_bsp.h"
#include "am_util.h"
//*****************************************************************************
//
// Configuration options
//
//*****************************************************************************
//
// USE_SPI: Define to force configuration to output as SPI or I2C.
// Leave undefined when using a button/pin to determine SPI or I2C mode.
//
//#define USE_SPI 1 // 0 = I2C, 1 = SPI
//
// Define the UART module (0 or 1) to be used.
// Also define the max packet size
//
#define UART_HOST 0
#define MAX_UART_PACKET_SIZE 2048
#define IOM_MODULE 0
#define SLAVE_ADDRESS 0x20
#define MAX_SPI_SIZE 1023
#define MAX_I2C_SIZE 255
#define MAX_IOS_LRAM_SIZE 120 // LRAM can only accept 120 bytes at a time.
//
// This definition assumes Host is running on same type of board as target.
// If that is not case, this definition needs to be adjusted to match the
// desired pin on target board
//
#if 1
#define TARGET_BOARD_OVERRIDE_PIN AM_BSP_GPIO_BUTTON0
#else
#define TARGET_BOARD_OVERRIDE_PIN 16
#endif
#ifdef AM_BSP_GPIO_BUTTON2
#define USE_SPI_PIN AM_BSP_GPIO_BUTTON2 // Labelled BTN4 on the Apollo3 EVB
#else
#define USE_SPI_PIN 19
#endif
//
// Slave interrupt pin is connected here
//
#define BOOTLOADER_HANDSHAKE_PIN 2
//
// This pin is connected to RESET pin of slave
//
#define DRIVE_SLAVE_RESET_PIN 17
//
// This pin is connected to the 'Override' pin of slave
//
#define DRIVE_SLAVE_OVERRIDE_PIN 4
#define IOSOFFSET_WRITE_CMD 0x80
#define IOSOFFSET_READ_FIFO 0x7F
#define IOSOFFSET_READ_FIFOCTR 0x7C
#define PRT_INFO am_util_stdio_printf
//#define PRT_INFO no_print
//
// Define PRT_DATA if additional pkt data and other information is desired.
// PRT_INFO must also be defined.
//
#if PRT_INFO == am_util_stdio_printf
#define PRT_DATA no_print
//#define PRT_DATA am_util_stdio_printf
#endif
//*****************************************************************************
//
// Custom data type.
// Note - am_uart_buffer was simply derived from the am_hal_iom_buffer macro.
//
//*****************************************************************************
#define am_uart_buffer(A) \
union \
{ \
uint32_t words[(A + 3) >> 2]; \
uint8_t bytes[A]; \
}
typedef struct
{
uint32_t crc32; // First word
uint16_t msgType; // am_secboot_wired_msgtype_e
uint16_t length;
} am_secboot_wired_msghdr_t;
typedef struct
{
uint32_t length : 16;
uint32_t resv : 14;
uint32_t bEnd : 1;
uint32_t bStart : 1;
} am_secboot_ios_pkthdr_t;
typedef enum
{
AM_SECBOOT_WIRED_MSGTYPE_HELLO,
AM_SECBOOT_WIRED_MSGTYPE_STATUS,
AM_SECBOOT_WIRED_MSGTYPE_OTADESC,
AM_SECBOOT_WIRED_MSGTYPE_UPDATE,
AM_SECBOOT_WIRED_MSGTYPE_ABORT,
AM_SECBOOT_WIRED_MSGTYPE_RECOVER,
AM_SECBOOT_WIRED_MSGTYPE_RESET,
AM_SECBOOT_WIRED_MSGTYPE_ACK,
AM_SECBOOT_WIRED_MSGTYPE_DATA,
} am_secboot_wired_msgtype_e;
//*****************************************************************************
//
// Global Variables
//
//*****************************************************************************
uint8_t g_pui8UARTTXBuffer[MAX_UART_PACKET_SIZE];
am_uart_buffer(12 * 1024) g_psWriteData;
am_uart_buffer(12 * 1024) g_psReadData;
struct
{
am_secboot_ios_pkthdr_t header;
uint8_t data[MAX_IOS_LRAM_SIZE - sizeof(am_secboot_ios_pkthdr_t)];
} g_IosPktData;
volatile uint32_t g_ui32UARTRxIndex = 0;
volatile bool g_bRxTimeoutFlag = false;
volatile bool bIosInt = false;
void *g_IOMHandle;
void *g_pvUART;
//*****************************************************************************
//
// Function prototypes
//
//*****************************************************************************
void iom_slave_write(bool bSpi, uint32_t offset, uint32_t *pBuf, uint32_t size);
//*****************************************************************************
//
// Configuration structure for the IO Master.
//
//*****************************************************************************
static am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BOOT_HANDSHAKE =
{
.uFuncSel = AM_HAL_PIN_2_GPIO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
};
static am_hal_iom_config_t g_sIOMI2cConfig =
{
.eInterfaceMode = AM_HAL_IOM_I2C_MODE,
.ui32ClockFreq = AM_HAL_IOM_1MHZ,
};
static am_hal_iom_config_t g_sIOMSpiConfig =
{
.eInterfaceMode = AM_HAL_IOM_SPI_MODE,
.ui32ClockFreq = AM_HAL_IOM_8MHZ,
.eSpiMode = AM_HAL_IOM_SPI_MODE_0, // Default
};
//*****************************************************************************
//
// no_print
//
//*****************************************************************************
int no_print(char*pFmtStr, ...)
{
return 0;
}
//*****************************************************************************
//
// Interrupt handler for the UART.
//
//*****************************************************************************
#if UART_HOST == 0
void am_uart_isr(void)
#else
void am_uart1_isr(void)
#endif
{
uint32_t ui32Status;
//
// Read the masked interrupt status from the UART.
//
am_hal_uart_interrupt_status_get(g_pvUART, &ui32Status, true);
am_hal_uart_interrupt_clear(g_pvUART, ui32Status);
am_hal_uart_interrupt_service(g_pvUART, ui32Status, 0);
//
// If there's an RX interrupt, handle it in a way that preserves the
// timeout interrupt on gaps between packets.
//
if (ui32Status & (AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX))
{
uint32_t ui32BytesRead;
am_hal_uart_transfer_t sRead =
{
.ui32Direction = AM_HAL_UART_READ,
.pui8Data = (uint8_t *) &(g_psWriteData.bytes[g_ui32UARTRxIndex]),
.ui32NumBytes = 23,
.ui32TimeoutMs = 0,
.pui32BytesTransferred = &ui32BytesRead,
};
am_hal_uart_transfer(g_pvUART, &sRead);
g_ui32UARTRxIndex += ui32BytesRead;
//
// If there is a TMOUT interrupt, assume we have a compete packet, and
// send it over SPI.
//
if (ui32Status & (AM_HAL_UART_INT_RX_TMOUT))
{
NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + UART_HOST));
g_bRxTimeoutFlag = true;
}
}
}
//*****************************************************************************
//
// Interrupt handler for the GPIO pins.
//
//*****************************************************************************
void am_gpio_isr(void)
{
//
// Read and clear the GPIO interrupt status.
//
#if defined(AM_PART_APOLLO3P)
AM_HAL_GPIO_MASKCREATE(GpioIntStatusMask);
am_hal_gpio_interrupt_status_get(false, pGpioIntStatusMask);
am_hal_gpio_interrupt_clear(pGpioIntStatusMask);
am_hal_gpio_interrupt_service(pGpioIntStatusMask);
#elif defined(AM_PART_APOLLO3)
uint64_t ui64Status;
am_hal_gpio_interrupt_status_get(false, &ui64Status);
am_hal_gpio_interrupt_clear(ui64Status);
am_hal_gpio_interrupt_service(ui64Status);
#else
#error Unknown device.
#endif
}
// ISR callback for the host IOINT
static void hostint_handler(void)
{
bIosInt = true;
}
//*****************************************************************************
//
// Initialize the IOM.
//
//*****************************************************************************
static void iom_set_up(uint32_t iomModule, bool bSpi)
{
//
// Initialize the IOM.
//
am_hal_iom_initialize(iomModule, &g_IOMHandle);
am_hal_iom_power_ctrl(g_IOMHandle, AM_HAL_SYSCTRL_WAKE, false);
if ( bSpi )
{
//
// Configure the IOM for SPI.
//
am_hal_iom_configure(g_IOMHandle, &g_sIOMSpiConfig);
//
// Configure the IOM pins.
//
am_bsp_iom_pins_enable(iomModule, AM_HAL_IOM_SPI_MODE);
}
else
{
//
// Configure the IOM for I2C.
//
am_hal_iom_configure(g_IOMHandle, &g_sIOMI2cConfig);
//
// Configure the IOM pins.
//
am_bsp_iom_pins_enable(iomModule, AM_HAL_IOM_I2C_MODE);
}
//
// Enable the IOM.
//
am_hal_iom_enable(g_IOMHandle);
//
// Set up the host IO interrupt
//
am_hal_gpio_pinconfig(BOOTLOADER_HANDSHAKE_PIN, g_AM_BSP_GPIO_BOOT_HANDSHAKE);
AM_HAL_GPIO_MASKCREATE(GpioIntMask);
am_hal_gpio_interrupt_clear(AM_HAL_GPIO_MASKBIT(pGpioIntMask, BOOTLOADER_HANDSHAKE_PIN));
//
// Register handler for IOS => IOM interrupt
//
am_hal_gpio_interrupt_register(BOOTLOADER_HANDSHAKE_PIN, hostint_handler);
am_hal_gpio_interrupt_enable(AM_HAL_GPIO_MASKBIT(pGpioIntMask, BOOTLOADER_HANDSHAKE_PIN));
NVIC_EnableIRQ(GPIO_IRQn);
}
//*****************************************************************************
//
// Initialize the UART.
//
//*****************************************************************************
static void uart_set_up(uint32_t UARTNum)
{
//
// Start the UART.
//
am_hal_uart_config_t sUartConfig =
{
//
// Standard UART settings: 115200-8-N-1
//
.ui32BaudRate = 115200,
.ui32DataBits = AM_HAL_UART_DATA_BITS_8,
.ui32Parity = AM_HAL_UART_PARITY_NONE,
.ui32StopBits = AM_HAL_UART_ONE_STOP_BIT,
.ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE,
//
// Set TX and RX FIFOs to interrupt at three-quarters full.
//
.ui32FifoLevels = (AM_HAL_UART_TX_FIFO_3_4 |
AM_HAL_UART_RX_FIFO_3_4),
//
// This code will use the standard interrupt handling for UART TX, but
// we will have a custom routine for UART RX.
//
.pui8TxBuffer = g_pui8UARTTXBuffer,
.ui32TxBufferSize = sizeof(g_pui8UARTTXBuffer),
.pui8RxBuffer = 0,
.ui32RxBufferSize = 0,
};
am_hal_uart_initialize(UARTNum, &g_pvUART);
am_hal_uart_power_control(g_pvUART, AM_HAL_SYSCTRL_WAKE, false);
am_hal_uart_configure(g_pvUART, &sUartConfig);
am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX);
am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX);
//
// Make sure to enable the interrupts for RX, since the HAL doesn't already
// know we intend to use them.
//
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + UARTNum));
am_hal_uart_interrupt_enable(g_pvUART, (AM_HAL_UART_INT_RX |
AM_HAL_UART_INT_RX_TMOUT));
am_hal_interrupt_master_enable();
}
//*****************************************************************************
//
// Initialize the UART.
//
//*****************************************************************************
static bool USE_SPI_get(void)
{
#ifndef USE_SPI
uint32_t ui32Pinval;
//
// Configure the pin as input with a pullup.
//
am_hal_gpio_pinconfig(USE_SPI_PIN, g_AM_HAL_GPIO_INPUT_PULLUP);
//
// Short delay for the pin configuration.
//
am_util_delay_us(5);
//
// If the pin is not pulled down, assume SPI.
//
am_hal_gpio_state_read(USE_SPI_PIN, AM_HAL_GPIO_INPUT_READ, &ui32Pinval);
//
// Done with the pin.
//
am_hal_gpio_pinconfig(USE_SPI_PIN, g_AM_HAL_GPIO_DISABLE);
return ui32Pinval ? true : false;
#else
return (USE_SPI == 1);
#endif
} // USE_SPI_get()
//*****************************************************************************
//
// Reset the slave device and force it into boot mode.
//
//*****************************************************************************
void start_boot_mode(bool bReset)
{
if ( !bReset )
{
//
// Drive RESET high and configure the pin.
//
am_hal_gpio_state_write(DRIVE_SLAVE_RESET_PIN, AM_HAL_GPIO_OUTPUT_SET);
am_hal_gpio_pinconfig(DRIVE_SLAVE_RESET_PIN, g_AM_HAL_GPIO_OUTPUT);
//
// Drive the override pin high and configure the pin.
//
am_hal_gpio_state_write(DRIVE_SLAVE_OVERRIDE_PIN, AM_HAL_GPIO_OUTPUT_SET);
am_hal_gpio_pinconfig(DRIVE_SLAVE_OVERRIDE_PIN, g_AM_HAL_GPIO_OUTPUT);
}
else
{
//
// Drive RESET low.
//
am_hal_gpio_state_write(DRIVE_SLAVE_RESET_PIN, AM_HAL_GPIO_OUTPUT_CLEAR);
//
// Drive the override pin low to force the slave into boot mode.
//
am_hal_gpio_state_write(DRIVE_SLAVE_OVERRIDE_PIN, AM_HAL_GPIO_OUTPUT_CLEAR);
//
// Short delay.
//
am_util_delay_us(5);
//
// Release RESET.
//
am_hal_gpio_state_write(DRIVE_SLAVE_RESET_PIN, AM_HAL_GPIO_OUTPUT_SET);
//
// Short delay.
//
am_util_delay_us(5);
}
}
//*****************************************************************************
//
// Read a packet from the SBL IOS.
//
//*****************************************************************************
void iom_slave_read(bool bSpi, uint32_t offset, uint32_t *pBuf, uint32_t size)
{
am_hal_iom_transfer_t Transaction;
Transaction.ui32InstrLen = 1;
Transaction.ui32Instr = offset;
Transaction.eDirection = AM_HAL_IOM_RX;
Transaction.ui32NumBytes = size;
Transaction.pui32RxBuffer = pBuf;
Transaction.bContinue = false;
Transaction.ui8RepeatCount = 0;
Transaction.ui32PauseCondition = 0;
Transaction.ui32StatusSetClr = 0;
if ( bSpi )
{
Transaction.uPeerInfo.ui32SpiChipSelect = AM_BSP_IOM0_CS_CHNL;
}
else
{
Transaction.uPeerInfo.ui32I2CDevAddr = (SLAVE_ADDRESS);
}
am_hal_iom_blocking_transfer(g_IOMHandle, &Transaction);
}
//*****************************************************************************
//
// Write a packet to the SBL IOS.
//
//*****************************************************************************
void iom_slave_write(bool bSpi, uint32_t offset, uint32_t *pBuf, uint32_t size)
{
am_hal_iom_transfer_t Transaction;
Transaction.ui32InstrLen = 1;
Transaction.ui32Instr = offset;
Transaction.eDirection = AM_HAL_IOM_TX;
Transaction.ui32NumBytes = size;
Transaction.pui32TxBuffer = pBuf;
Transaction.bContinue = false;
Transaction.ui8RepeatCount = 0;
Transaction.ui32PauseCondition = 0;
Transaction.ui32StatusSetClr = 0;
if ( bSpi )
{
Transaction.uPeerInfo.ui32SpiChipSelect = AM_BSP_IOM0_CS_CHNL;
}
else
{
Transaction.uPeerInfo.ui32I2CDevAddr = (SLAVE_ADDRESS);
}
am_hal_iom_blocking_transfer(g_IOMHandle, &Transaction);
}
//*****************************************************************************
//
// Send a "HELLO" packet.
//
//*****************************************************************************
void send_hello(bool bSpi)
{
struct
{
am_secboot_ios_pkthdr_t hdr;
am_secboot_wired_msghdr_t msg;
} pkt;
pkt.hdr.bStart = 1;
pkt.hdr.bEnd = 1;
pkt.hdr.length = 12;
pkt.msg.msgType = AM_SECBOOT_WIRED_MSGTYPE_HELLO;
pkt.msg.length = sizeof(am_secboot_wired_msghdr_t);
//
// Compute CRC
//
PRT_INFO("send_hello: sending bytes: %d.\n", pkt.msg.length );
am_hal_crc32((uint32_t)&pkt.msg.msgType, pkt.msg.length - sizeof(uint32_t), &pkt.msg.crc32);
iom_slave_write(bSpi, IOSOFFSET_WRITE_CMD, (uint32_t*)&pkt, sizeof(pkt));
}
//*****************************************************************************
//
// Main
//
//*****************************************************************************
int
main(void)
{
bool bSpi;
uint32_t maxSize;
uint32_t ui32ByteCnt;
bool bIOShdr;
uint32_t ui32DotCnt = 0;
//
// Default setup.
//
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
am_bsp_low_power_init();
//
// Check the SPI pin
//
bSpi = USE_SPI_get();
maxSize = bSpi ? MAX_SPI_SIZE: MAX_I2C_SIZE;
//
// Enable the ITM
//
am_bsp_itm_printf_enable();
am_util_stdio_printf("\nApollo3 UART to IOS Host Bridge\n");
if ( bSpi )
{
am_util_stdio_printf("SPI clock = %d.%d MHz\n",
g_sIOMSpiConfig.ui32ClockFreq / 1000000,
g_sIOMSpiConfig.ui32ClockFreq % 1000000);
}
else
{
am_util_stdio_printf("I2C clock = %d.%d MHz\n",
g_sIOMI2cConfig.ui32ClockFreq / 1000000,
g_sIOMI2cConfig.ui32ClockFreq % 1000000);
}
//
// Set and configure the reset/bootmode pins high, but don't reset slave.
//
start_boot_mode(false);
//
// Start the IOM interface.
//
iom_set_up(IOM_MODULE, bSpi);
//
// Start up the UART interface.
//
uart_set_up(UART_HOST);
//
// Force the slave into boot mode.
//
start_boot_mode(true);
#if 1
//
// Wait for initial handshake signal to know that IOS interface is alive
//
while( !bIosInt );
bIosInt = false;
//
// Short delay.
//
am_util_delay_ms(1);
//
// Send the "HELLO" message to connect to the interface.
//
send_hello(bSpi);
while( !bIosInt );
bIosInt = false;
//
// Read the "STATUS" response from the IOS.
//
iom_slave_read(bSpi, IOSOFFSET_READ_FIFO, (uint32_t*)&g_psReadData, 88);
#endif
//
// Loop forever.
//
while (1)
{
//
// Disable interrupt while we decide whether we're going to sleep.
//
//uint32_t ui32IntStatus = am_hal_interrupt_master_disable();
if ( bIosInt == true )
{
bIosInt = false;
uint32_t iosSize = 0;
//
// Read the Data Size from the IOS.
//
iom_slave_read(bSpi, IOSOFFSET_READ_FIFOCTR, &iosSize, 2);
iosSize = (iosSize > maxSize) ? maxSize : iosSize;
if ( iosSize > 0 )
{
//
// Read the Data from the IOS.
//
iom_slave_read(bSpi, IOSOFFSET_READ_FIFO, (uint32_t*)&g_psReadData, iosSize);
//
// Write the Data to the UART.
//
{
am_hal_uart_transfer_t sWrite =
{
.ui32Direction = AM_HAL_UART_WRITE,
.pui8Data = g_psReadData.bytes,
.ui32NumBytes = iosSize,
.ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER,
.pui32BytesTransferred = 0,
};
//PRT_INFO("\nUART%d: %3d bytes.\n", UART_HOST, iosSize);
// bIOShdr = false;
am_hal_uart_transfer(g_pvUART, &sWrite);
am_util_delay_ms(1);
}
}
}
else if (g_bRxTimeoutFlag)
{
//
// UART Buffer can contain more than one packet.
// This outer loop parses
//
PRT_DATA("UART Data Size : %d\n", g_ui32UARTRxIndex);
uint32_t ui32UARTBufOffset = 0;
while ((ui32UARTBufOffset < g_ui32UARTRxIndex) && (g_ui32UARTRxIndex > 0))
{
am_secboot_wired_msghdr_t *pHdr = (am_secboot_wired_msghdr_t *)&g_psWriteData.bytes[ui32UARTBufOffset];
uint32_t ui32PktLength = pHdr->length;
PRT_DATA("Packet Length : %d\n", ui32PktLength);
if ( 0 == ui32PktLength )
{
break;
}
for (uint32_t index = 0; index < ui32PktLength; index += sizeof(g_IosPktData.data))
{
PRT_DATA("index : %d\n", index);
g_IosPktData.header.bStart = 0;
g_IosPktData.header.bEnd = 0;
g_IosPktData.header.length = 0;
//
// If this is the first packet, then set the Start flag.
//
if ( 0 == index )
{
g_IosPktData.header.bStart = 1;
}
//
// If this this the last packet, then set the End flag.
//
if ((index + sizeof(g_IosPktData.data)) >= ui32PktLength)
{
g_IosPktData.header.bEnd = 1;
}
//
// Build and Send the next packet.
//
g_IosPktData.header.length = ((ui32PktLength - index) < sizeof(g_IosPktData.data)) ? (ui32PktLength - index) : sizeof(g_IosPktData.data);
memcpy(&g_IosPktData.data[0], &g_psWriteData.bytes[index + ui32UARTBufOffset], g_IosPktData.header.length);
g_IosPktData.header.length += sizeof(am_secboot_ios_pkthdr_t);
bIosInt = false;
PRT_DATA("IOS Length : %d\n", g_IosPktData.header.length);
PRT_DATA("IOS Start Bit : %d\n", g_IosPktData.header.bStart);
PRT_DATA("IOS End Bit : %d\n", g_IosPktData.header.bEnd);
ui32ByteCnt += g_IosPktData.header.length;
if ( bIOShdr )
{
PRT_DATA(", %d", g_IosPktData.header.length );
}
else
{
PRT_DATA("IOM : sent bytes: %d (count=%d)", g_IosPktData.header.length, ui32ByteCnt );
bIOShdr = true;
}
if ( ui32DotCnt >= 20 )
{
PRT_INFO("\n");
ui32DotCnt = 0;
}
PRT_INFO("*");
ui32DotCnt++;
iom_slave_write(bSpi, IOSOFFSET_WRITE_CMD, (uint32_t*)&g_IosPktData, g_IosPktData.header.length);
//
// Wait for the GPIO Interrupt before sending the next packet.
//
for (uint32_t timeout = 0; timeout < 10000; timeout++)
{
if ( bIosInt )
{
PRT_DATA("Received Handshake for next packet\n");
break;
}
else
{
am_util_delay_us(1);
}
}
if ( !bIosInt )
{
PRT_DATA("Timed out waiting for Handshake signal\n");
}
}
ui32UARTBufOffset += ui32PktLength;
}
g_ui32UARTRxIndex = 0;
g_bRxTimeoutFlag = false;
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + UART_HOST));
}
}
}