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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/Makefile
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#******************************************************************************
#
# Makefile - Rules for compiling
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
# Include rules specific to this board
-include ../../board-defs.mk
-include example-defs.mk
# All makefiles use this to find the top level directory.
SWROOT?=../../../..
# Include rules for building generic examples.
include $(SWROOT)/makedefs/example.mk
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/README.txt
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Name:
=====
cache_monitor
Description:
============
Example to show the performance of cache.
Purpose:
========
This example provides a demonstration of the cache monitor to check
the cache hit rate and cache miss number.
Additional Information:
=======================
If the fireball device card is used, this example can work on:
Apollo3_eb + Fireball2
Recommend to use 3.3V power supply voltage.
Define FIREBALL_CARD and APS6404L in the config-template.ini file to select.
******************************************************************************
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/gcc/Makefile
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#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := cache_monitor
COMPILERNAME := gcc
PROJECT := cache_monitor_gcc
CONFIG := bin
SHELL:=/bin/bash
#### Setup ####
TOOLCHAIN ?= arm-none-eabi
PART = apollo3
CPU = cortex-m4
FPU = fpv4-sp-d16
# Default to FPU hardware calling convention. However, some customers and/or
# applications may need the software calling convention.
#FABI = softfp
FABI = hard
LINKER_FILE := ./cache_monitor.ld
STARTUP_FILE := ./startup_$(COMPILERNAME).c
#### Required Executables ####
CC = $(TOOLCHAIN)-gcc
GCC = $(TOOLCHAIN)-gcc
CPP = $(TOOLCHAIN)-cpp
LD = $(TOOLCHAIN)-ld
CP = $(TOOLCHAIN)-objcopy
OD = $(TOOLCHAIN)-objdump
RD = $(TOOLCHAIN)-readelf
AR = $(TOOLCHAIN)-ar
SIZE = $(TOOLCHAIN)-size
RM = $(shell which rm 2>/dev/null)
EXECUTABLES = CC LD CP OD AR RD SIZE GCC
K := $(foreach exec,$(EXECUTABLES),\
$(if $(shell which $($(exec)) 2>/dev/null),,\
$(info $(exec) not found on PATH ($($(exec))).)$(exec)))
$(if $(strip $(value K)),$(info Required Program(s) $(strip $(value K)) not found))
ifneq ($(strip $(value K)),)
all clean:
$(info Tools $(TOOLCHAIN)-$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
DEFINES = -DPART_$(PART)
DEFINES+= -DAM_PART_APOLLO3
DEFINES+= -DAM_PACKAGE_BGA
DEFINES+= -DAPS6404L
DEFINES+= -DFIREBALL_CARD
DEFINES+= -Dgcc
INCLUDES = -I../../../../..
INCLUDES+= -I../../../../../CMSIS/ARM/Include
INCLUDES+= -I../src
INCLUDES+= -I../../../../../utils
INCLUDES+= -I../../../../../mcu/apollo3
INCLUDES+= -I../../../bsp
INCLUDES+= -I../../../../../devices
INCLUDES+= -I../../../../../CMSIS/AmbiqMicro/Include
VPATH = ../../../../../devices
VPATH+=:../../../../../utils
VPATH+=:../src
VPATH+=:../../../../../third_party/prime_mpi/src
SRC = cache_monitor.c
SRC += prime_mpi.c
SRC += am_devices_fireball.c
SRC += am_devices_mspi_psram_aps6404l.c
SRC += am_util_delay.c
SRC += am_util_faultisr.c
SRC += am_util_stdio.c
SRC += startup_gcc.c
CSRC = $(filter %.c,$(SRC))
ASRC = $(filter %.s,$(SRC))
OBJS = $(CSRC:%.c=$(CONFIG)/%.o)
OBJS+= $(ASRC:%.s=$(CONFIG)/%.o)
DEPS = $(CSRC:%.c=$(CONFIG)/%.d)
DEPS+= $(ASRC:%.s=$(CONFIG)/%.d)
LIBS = ../../../bsp/gcc/bin/libam_bsp.a
LIBS += ../../../../../mcu/apollo3/hal/gcc/bin/libam_hal.a
CFLAGS = -mthumb -mcpu=$(CPU) -mfpu=$(FPU) -mfloat-abi=$(FABI)
CFLAGS+= -ffunction-sections -fdata-sections -fomit-frame-pointer
CFLAGS+= -MMD -MP -std=c99 -Wall -g
CFLAGS+= -O3
CFLAGS+= $(DEFINES)
CFLAGS+= $(INCLUDES)
CFLAGS+=
LFLAGS = -mthumb -mcpu=$(CPU) -mfpu=$(FPU) -mfloat-abi=$(FABI)
LFLAGS+= -nostartfiles -static
LFLAGS+= -Wl,--gc-sections,--entry,Reset_Handler,-Map,$(CONFIG)/$(TARGET).map
LFLAGS+= -Wl,--start-group -lm -lc -lgcc $(LIBS) -Wl,--end-group
LFLAGS+=
# Additional user specified CFLAGS
CFLAGS+=$(EXTRA_CFLAGS)
CPFLAGS = -Obinary
ODFLAGS = -S
#### Rules ####
all: directories $(CONFIG)/$(TARGET).bin
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
$(CONFIG)/%.o: %.c $(CONFIG)/%.d
@echo " Compiling $(COMPILERNAME) $<" ;\
$(CC) -c $(CFLAGS) $< -o $@
$(CONFIG)/%.o: %.s $(CONFIG)/%.d
@echo " Assembling $(COMPILERNAME) $<" ;\
$(CC) -c $(CFLAGS) $< -o $@
$(CONFIG)/$(TARGET).axf: $(OBJS) $(LIBS)
@echo " Linking $(COMPILERNAME) $@" ;\
$(CC) -Wl,-T,$(LINKER_FILE) -o $@ $(OBJS) $(LFLAGS)
$(CONFIG)/$(TARGET).bin: $(CONFIG)/$(TARGET).axf
@echo " Copying $(COMPILERNAME) $@..." ;\
$(CP) $(CPFLAGS) $< $@ ;\
$(OD) $(ODFLAGS) $< > $(CONFIG)/$(TARGET).lst
clean:
@echo "Cleaning..." ;\
$(RM) -f $(OBJS) $(DEPS) \
$(CONFIG)/$(TARGET).bin $(CONFIG)/$(TARGET).axf \
$(CONFIG)/$(TARGET).lst $(CONFIG)/$(TARGET).map
$(CONFIG)/%.d: ;
../../../bsp/gcc/bin/libam_bsp.a:
$(MAKE) -C ../../../bsp
../../../../../mcu/apollo3/hal/gcc/bin/libam_hal.a:
$(MAKE) -C ../../../../../mcu/apollo3/hal
# Automatically include any generated dependencies
-include $(DEPS)
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/gcc/cache_monitor.ld
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/******************************************************************************
*
* cache_monitor.ld - Linker script for applications using startup_gnu.c
*
*****************************************************************************/
ENTRY(Reset_Handler)
MEMORY
{
ROMEM (rx) : ORIGIN = 0x0000C000, LENGTH = 960K
RWMEM (rwx) : ORIGIN = 0x10000000, LENGTH = 384K
}
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.isr_vector))
KEEP(*(.patch))
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
. = ALIGN(4);
_etext = .;
} > ROMEM
/* User stack section initialized by startup code. */
.stack (NOLOAD):
{
. = ALIGN(8);
*(.stack)
*(.stack*)
. = ALIGN(8);
} > RWMEM
.data :
{
. = ALIGN(4);
_sdata = .;
*(.data)
*(.data*)
. = ALIGN(4);
_edata = .;
} > RWMEM AT>ROMEM
/* used by startup to initialize data */
_init_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_sbss = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} > RWMEM
.ARM.attributes 0 : { *(.ARM.attributes) }
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/gcc/startup_gcc.c
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//*****************************************************************************
//
//! @file startup_gcc.c
//!
//! @brief Definitions for interrupt handlers, the vector table, and the stack.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
//*****************************************************************************
//
// Forward declaration of interrupt handlers.
//
//*****************************************************************************
extern void Reset_Handler(void) __attribute ((naked));
extern void NMI_Handler(void) __attribute ((weak));
extern void HardFault_Handler(void) __attribute ((weak));
extern void MemManage_Handler(void) __attribute ((weak, alias ("HardFault_Handler")));
extern void BusFault_Handler(void) __attribute ((weak, alias ("HardFault_Handler")));
extern void UsageFault_Handler(void) __attribute ((weak, alias ("HardFault_Handler")));
extern void SecureFault_Handler(void) __attribute ((weak));
extern void SVC_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void DebugMon_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void PendSV_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void SysTick_Handler(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_brownout_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_watchdog_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_rtc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_vcomp_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ioslave_ios_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ioslave_acc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster1_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster2_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster3_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster4_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster5_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ble_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_gpio_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ctimer_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_uart_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_uart1_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_scard_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_adc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_pdm0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_mspi0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_software0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr1_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr2_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr3_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr4_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr5_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr6_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_stimer_cmpr7_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_clkgen_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_default_isr(void) __attribute ((weak));
//*****************************************************************************
//
// The entry point for the application.
//
//*****************************************************************************
extern int main(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
__attribute__ ((section(".stack")))
static uint32_t g_pui32Stack[1024];
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
// am_usagefault_isr does not work if am_fault_isr is defined externally.
// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
//
//*****************************************************************************
__attribute__ ((section(".isr_vector")))
void (* const g_am_pfnVectors[])(void) =
{
(void (*)(void))((uint32_t)g_pui32Stack + sizeof(g_pui32Stack)),
// The initial stack pointer
Reset_Handler, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MemManage_Handler
BusFault_Handler, // The BusFault_Handler
UsageFault_Handler, // The UsageFault_Handler
SecureFault_Handler, // The SecureFault_Handler
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
//
// Peripheral Interrupts
//
am_brownout_isr, // 0: Brownout (rstgen)
am_watchdog_isr, // 1: Watchdog
am_rtc_isr, // 2: RTC
am_vcomp_isr, // 3: Voltage Comparator
am_ioslave_ios_isr, // 4: I/O Slave general
am_ioslave_acc_isr, // 5: I/O Slave access
am_iomaster0_isr, // 6: I/O Master 0
am_iomaster1_isr, // 7: I/O Master 1
am_iomaster2_isr, // 8: I/O Master 2
am_iomaster3_isr, // 9: I/O Master 3
am_iomaster4_isr, // 10: I/O Master 4
am_iomaster5_isr, // 11: I/O Master 5
am_ble_isr, // 12: BLEIF
am_gpio_isr, // 13: GPIO
am_ctimer_isr, // 14: CTIMER
am_uart_isr, // 15: UART0
am_uart1_isr, // 16: UART1
am_scard_isr, // 17: SCARD
am_adc_isr, // 18: ADC
am_pdm0_isr, // 19: PDM
am_mspi0_isr, // 20: MSPI0
am_software0_isr, // 21: SOFTWARE0
am_stimer_isr, // 22: SYSTEM TIMER
am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0
am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1
am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2
am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3
am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4
am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5
am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6
am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7
am_clkgen_isr, // 31: CLKGEN
};
//******************************************************************************
//
// Place code immediately following vector table.
//
//******************************************************************************
//******************************************************************************
//
// The Patch table.
//
// The patch table should pad the vector table size to a total of 64 entries
// (16 core + 48 periph) such that code begins at offset 0x100.
//
//******************************************************************************
__attribute__ ((section(".patch")))
uint32_t const __Patchable[] =
{
0, // 32
0, // 33
0, // 34
0, // 35
0, // 36
0, // 37
0, // 38
0, // 39
0, // 40
0, // 41
0, // 42
0, // 43
0, // 44
0, // 45
0, // 46
0, // 47
};
//*****************************************************************************
//
// The following are constructs created by the linker, indicating where the
// the "data" and "bss" segments reside in memory. The initializers for the
// "data" segment resides immediately following the "text" segment.
//
//*****************************************************************************
extern uint32_t _etext;
extern uint32_t _sdata;
extern uint32_t _edata;
extern uint32_t _sbss;
extern uint32_t _ebss;
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.
//
//*****************************************************************************
#if defined(__GNUC_STDC_INLINE__)
void
Reset_Handler(void)
{
//
// Set the vector table pointer.
//
__asm(" ldr r0, =0xE000ED08\n"
" ldr r1, =g_am_pfnVectors\n"
" str r1, [r0]");
//
// Set the stack pointer.
//
__asm(" ldr sp, [r1]");
#ifndef NOFPU
//
// Enable the FPU.
//
__asm("ldr r0, =0xE000ED88\n"
"ldr r1,[r0]\n"
"orr r1,#(0xF << 20)\n"
"str r1,[r0]\n"
"dsb\n"
"isb\n");
#endif
//
// Copy the data segment initializers from flash to SRAM.
//
__asm(" ldr r0, =_init_data\n"
" ldr r1, =_sdata\n"
" ldr r2, =_edata\n"
"copy_loop:\n"
" ldr r3, [r0], #4\n"
" str r3, [r1], #4\n"
" cmp r1, r2\n"
" blt copy_loop\n");
//
// Zero fill the bss segment.
//
__asm(" ldr r0, =_sbss\n"
" ldr r1, =_ebss\n"
" mov r2, #0\n"
"zero_loop:\n"
" cmp r0, r1\n"
" it lt\n"
" strlt r2, [r0], #4\n"
" blt zero_loop");
//
// Call the application's entry point.
//
main();
//
// If main returns then execute a break point instruction
//
__asm(" bkpt ");
}
#else
#error GNU STDC inline not supported.
#endif
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
void
NMI_Handler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void
HardFault_Handler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void
am_default_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/Makefile
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#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := cache_monitor
COMPILERNAME := iar
PROJECT := cache_monitor_iar
CONFIG := bin
AM_SoftwareRoot ?= ../../../..
SHELL:=/bin/bash
#### Required Executables ####
K := $(shell type -p IarBuild.exe)
RM = $(shell which rm 2>/dev/null)
ifeq ($(K),)
all clean:
$(info Tools w/$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
all: directories binary
.PHONY: binary
binary:
IarBuild.exe cache_monitor.ewp -make Debug -log info
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
clean:
@echo Cleaning... ;\
IarBuild.exe cache_monitor.ewp -clean Debug -log all
../../../bsp/iar/bin/libam_bsp.a:
$(MAKE) -C ../../../bsp
../../../../../mcu/apollo3/hal/iar/bin/libam_hal.a:
$(MAKE) -C ../../../../../mcu/apollo3/hal
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/bin/cache_monitor.log
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/bin/cache_monitor.out
BIN
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/cache_monitor.ewd
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/cache_monitor.ewp
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/cache_monitor.eww
+10
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\cache_monitor.ewp</path>
</project>
<batchBuild/>
</workspace>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/cache_monitor.icf
+87
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@@ -0,0 +1,87 @@
//*****************************************************************************
//
// cache_monitor.icf
//
// IAR linker Configuration File
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
//
// Define a memory section that covers the entire 4 GB addressable space of the
// processor. (32-bit can address up to 4GB)
//
define memory mem with size = 4G;
//
// Define regions for the various types of internal memory.
//
define region ROMEM = mem:[from 0x0000C000 to 0x000FC000];
define region RWMEM = mem:[from 0x10000000 to 0x10060000];
//
// Define blocks for logical groups of data.
//
define block HEAP with alignment = 0x8, size = 0x00000000 { };
define block CSTACK with alignment = 0x8, size = 4096
{
section .stack
};
define block FLASHBASE with fixed order
{
readonly section .intvec,
readonly section .patch
};
//
// Set section properties.
//
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section .stack };
//
// Place code sections in memory regions.
//
place at start of ROMEM { block FLASHBASE };
place in ROMEM { readonly };
place at start of RWMEM { block CSTACK};
place in RWMEM { block HEAP, readwrite, section .noinit };
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/settings/cache_monitor.dni
+127
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[Stack]
FillEnabled=0
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnLogOnly=1
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[Breakpoints]
Count=0
[GDBSERVERDriver]
GDB_LeaveTargetRunning=0x00000000
[DebugChecksum]
Checksum=-2034475309
[Exceptions]
StopOnUncaught=_ 0
StopOnThrow=_ 0
[CodeCoverage]
Enabled=_ 0
[CallStack]
ShowArgs=0
[Disassembly]
MixedMode=1
[JLinkDriver]
CStepIntDis=_ 0
LeaveTargetRunning=_ 0
TraceBufferSize=0x00010000
TraceStallIfFIFOFull=0x00000000
TracePortSize=0x00000000
[SWOTraceHWSettings]
OverrideDefaultClocks=1
CpuClock=6000000
ClockAutoDetect=0
ClockWanted=1000000
JtagSpeed=1000000
Prescaler=6
TimeStampPrescIndex=0
TimeStampPrescData=0
PcSampCYCTAP=1
PcSampPOSTCNT=15
PcSampIndex=0
DataLogMode=0
ITMportsEnable=1
ITMportsTermIO=1
ITMportsLogFile=0
ITMlogFile=$PROJ_DIR$\ITM.log
[Trace1]
Enabled=0
ShowSource=1
[Trace2]
Enabled=0
ShowSource=0
[SWOTraceWindow]
PcSampling=0
InterruptLogs=0
ForcedTimeStamps=0
EventCPI=0
EventEXC=0
EventFOLD=0
EventLSU=0
EventSLEEP=0
[PowerLog]
Title_0=I0
Symbol_0=0 4 0
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
LiveEnabled=0
LiveFile=PowerLogLive.log
[DataLog]
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
SumEnabled=0
ShowTimeSum=1
[EventLog]
Title_0=Ch3
Symbol_0=0 4 1
Title_1=Ch2
Symbol_1=0 4 1
Title_2=Ch1
Symbol_2=0 4 1
Title_3=Ch0
Symbol_3=0 4 1
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
SumEnabled=0
ShowTimeSum=1
SumSortOrder=0
[InterruptLog]
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
SumEnabled=0
ShowTimeSum=1
SumSortOrder=0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[DriverProfiling]
Enabled=0
Mode=1
Graph=0
Symbiont=0
Exclusions=
[CallStackLog]
Enabled=0
[CallStackStripe]
ShowTiming=1
[PowerProbe]
Frequency=10000
Probe0=I0
ProbeSetup0=2 1 1 2 0 0
[Disassemble mode]
mode=0
[Breakpoints2]
Count=0
[Aliases]
Count=0
SuppressDialog=0
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/settings/cache_monitor.dnx
+167
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<?xml version="1.0"?>
<settings>
<DebugChecksum>
<Checksum>1749499678</Checksum>
</DebugChecksum>
<Exceptions>
<StopOnUncaught>_ 0</StopOnUncaught>
<StopOnThrow>_ 0</StopOnThrow>
</Exceptions>
<CodeCoverage>
<Enabled>_ 0</Enabled>
</CodeCoverage>
<Stack>
<FillEnabled>0</FillEnabled>
<OverflowWarningsEnabled>1</OverflowWarningsEnabled>
<WarningThreshold>90</WarningThreshold>
<SpWarningsEnabled>1</SpWarningsEnabled>
<WarnLogOnly>1</WarnLogOnly>
<UseTrigger>1</UseTrigger>
<TriggerName>main</TriggerName>
<LimitSize>0</LimitSize>
<ByteLimit>50</ByteLimit>
</Stack>
<CallStack>
<ShowArgs>0</ShowArgs>
</CallStack>
<JLinkDriver>
<CStepIntDis>_ 0</CStepIntDis>
<LeaveTargetRunning>_ 0</LeaveTargetRunning>
</JLinkDriver>
<SWOTraceHWSettings>
<OverrideDefaultClocks>1</OverrideDefaultClocks>
<CpuClock>6000000</CpuClock>
<ClockAutoDetect>0</ClockAutoDetect>
<ClockWanted>1000000</ClockWanted>
<JtagSpeed>1000000</JtagSpeed>
<Prescaler>6</Prescaler>
<TimeStampPrescIndex>0</TimeStampPrescIndex>
<TimeStampPrescData>0</TimeStampPrescData>
<PcSampCYCTAP>1</PcSampCYCTAP>
<PcSampPOSTCNT>15</PcSampPOSTCNT>
<PcSampIndex>0</PcSampIndex>
<DataLogMode>0</DataLogMode>
<ITMportsEnable>1</ITMportsEnable>
<ITMportsTermIO>1</ITMportsTermIO>
<ITMportsLogFile>1</ITMportsLogFile>
<ITMlogFile>$PROJ_DIR$\ITM.log</ITMlogFile>
</SWOTraceHWSettings>
<SfrWindow>
<Show>1 1</Show>
<Sort>4 0</Sort>
</SfrWindow>
<Disassembly>
<InstrCount>0</InstrCount>
<MixedMode>1</MixedMode>
</Disassembly>
<Interrupts>
<Enabled>1</Enabled>
</Interrupts>
<MemConfig>
<Base>1</Base>
<Manual>0</Manual>
<Ddf>1</Ddf>
<TypeViol>0</TypeViol>
<Stop>1</Stop>
</MemConfig>
<Simulator>
<Freq>10000000</Freq>
<FreqHi>0</FreqHi>
<MultiCoreRunAll>1</MultiCoreRunAll>
</Simulator>
<Trace1>
<Enabled>0</Enabled>
<ShowSource>1</ShowSource>
</Trace1>
<Trace2>
<Enabled>0</Enabled>
<ShowSource>0</ShowSource>
</Trace2>
<SWOTraceWindow>
<PcSampling>0</PcSampling>
<InterruptLogs>0</InterruptLogs>
<ForcedTimeStamps>0</ForcedTimeStamps>
<EventCPI>0</EventCPI>
<EventEXC>0</EventEXC>
<EventFOLD>0</EventFOLD>
<EventLSU>0</EventLSU>
<EventSLEEP>0</EventSLEEP>
</SWOTraceWindow>
<PowerLog>
<Title_0>I0</Title_0>
<Symbol_0>0 4 0</Symbol_0>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<LiveEnabled>0</LiveEnabled>
<LiveFile>PowerLogLive.log</LiveFile>
</PowerLog>
<DataLog>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
</DataLog>
<InterruptLog>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
<SumSortOrder>0</SumSortOrder>
</InterruptLog>
<EventLog>
<Title_0>Ch3</Title_0>
<Symbol_0>0 0 1</Symbol_0>
<Title_1>Ch2</Title_1>
<Symbol_1>0 0 1</Symbol_1>
<Title_2>Ch1</Title_2>
<Symbol_2>0 0 1</Symbol_2>
<Title_3>Ch0</Title_3>
<Symbol_3>0 0 1</Symbol_3>
<LogEnabled>0</LogEnabled>
<GraphEnabled>0</GraphEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
<SumSortOrder>0</SumSortOrder>
</EventLog>
<LogFile>
<LoggingEnabled>_ 0</LoggingEnabled>
<LogFile>_ ""</LogFile>
<Category>_ 0</Category>
</LogFile>
<TermIOLog>
<LoggingEnabled>_ 0</LoggingEnabled>
<LogFile>_ ""</LogFile>
</TermIOLog>
<DriverProfiling>
<Enabled>0</Enabled>
<Mode>1</Mode>
<Graph>0</Graph>
<Symbiont>0</Symbiont>
<Exclusions />
</DriverProfiling>
<CallStackLog>
<Enabled>0</Enabled>
</CallStackLog>
<CallStackStripe>
<ShowTiming>1</ShowTiming>
</CallStackStripe>
<PowerProbe>
<Frequency>10000</Frequency>
<Probe0>I0</Probe0>
<ProbeSetup0>2 1 1 2 0 0</ProbeSetup0>
</PowerProbe>
<DisassembleMode>
<mode>0</mode>
</DisassembleMode>
<Breakpoints2>
<Count>0</Count>
</Breakpoints2>
<Aliases>
<Count>0</Count>
<SuppressDialog>0</SuppressDialog>
</Aliases>
</settings>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/settings/cache_monitor_Debug.jlink
+39
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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile="AMA3B1KK-KBR.JLinkScript"
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="AMA3B1KK-KBR"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/iar/startup_iar.c
+398
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@@ -0,0 +1,398 @@
//*****************************************************************************
//
//! @file startup_iar.c
//!
//! @brief Definitions for interrupt handlers, the vector table, and the stack.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
//*****************************************************************************
//
// Enable the IAR extensions for this source file.
//
//*****************************************************************************
#pragma language = extended
//*****************************************************************************
//
// Weak function links.
//
//*****************************************************************************
#pragma weak MemManage_Handler = HardFault_Handler
#pragma weak BusFault_Handler = HardFault_Handler
#pragma weak UsageFault_Handler = HardFault_Handler
#pragma weak SecureFault_Handler = HardFault_Handler
#pragma weak SVC_Handler = am_default_isr
#pragma weak DebugMon_Handler = am_default_isr
#pragma weak PendSV_Handler = am_default_isr
#pragma weak SysTick_Handler = am_default_isr
#pragma weak am_brownout_isr = am_default_isr
#pragma weak am_watchdog_isr = am_default_isr
#pragma weak am_rtc_isr = am_default_isr
#pragma weak am_vcomp_isr = am_default_isr
#pragma weak am_ioslave_ios_isr = am_default_isr
#pragma weak am_ioslave_acc_isr = am_default_isr
#pragma weak am_iomaster0_isr = am_default_isr
#pragma weak am_iomaster1_isr = am_default_isr
#pragma weak am_iomaster2_isr = am_default_isr
#pragma weak am_iomaster3_isr = am_default_isr
#pragma weak am_iomaster4_isr = am_default_isr
#pragma weak am_iomaster5_isr = am_default_isr
#pragma weak am_ble_isr = am_default_isr
#pragma weak am_gpio_isr = am_default_isr
#pragma weak am_ctimer_isr = am_default_isr
#pragma weak am_uart_isr = am_default_isr
#pragma weak am_uart1_isr = am_default_isr
#pragma weak am_scard_isr = am_default_isr
#pragma weak am_adc_isr = am_default_isr
#pragma weak am_pdm0_isr = am_default_isr
#pragma weak am_mspi0_isr = am_default_isr
#pragma weak am_software0_isr = am_default_isr
#pragma weak am_stimer_isr = am_default_isr
#pragma weak am_stimer_cmpr0_isr = am_default_isr
#pragma weak am_stimer_cmpr1_isr = am_default_isr
#pragma weak am_stimer_cmpr2_isr = am_default_isr
#pragma weak am_stimer_cmpr3_isr = am_default_isr
#pragma weak am_stimer_cmpr4_isr = am_default_isr
#pragma weak am_stimer_cmpr5_isr = am_default_isr
#pragma weak am_stimer_cmpr6_isr = am_default_isr
#pragma weak am_stimer_cmpr7_isr = am_default_isr
#pragma weak am_flash_isr = am_default_isr
#pragma weak am_clkgen_isr = am_default_isr
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
extern __stackless void Reset_Handler(void);
extern __weak void NMI_Handler(void);
extern __weak void HardFault_Handler(void);
extern void MemManage_Handler(void);
extern void BusFault_Handler(void);
extern void UsageFault_Handler(void);
extern void SecureFault_Handler(void);
extern void SVC_Handler(void);
extern void DebugMon_Handler(void);
extern void PendSV_Handler(void);
extern void SysTick_Handler(void);
extern void am_brownout_isr(void);
extern void am_watchdog_isr(void);
extern void am_rtc_isr(void);
extern void am_vcomp_isr(void);
extern void am_ioslave_ios_isr(void);
extern void am_ioslave_acc_isr(void);
extern void am_iomaster0_isr(void);
extern void am_iomaster1_isr(void);
extern void am_iomaster2_isr(void);
extern void am_iomaster3_isr(void);
extern void am_iomaster4_isr(void);
extern void am_iomaster5_isr(void);
extern void am_ble_isr(void);
extern void am_gpio_isr(void);
extern void am_ctimer_isr(void);
extern void am_uart_isr(void);
extern void am_uart1_isr(void);
extern void am_scard_isr(void);
extern void am_adc_isr(void);
extern void am_pdm0_isr(void);
extern void am_mspi0_isr(void);
extern void am_software0_isr(void);
extern void am_stimer_isr(void);
extern void am_stimer_cmpr0_isr(void);
extern void am_stimer_cmpr1_isr(void);
extern void am_stimer_cmpr2_isr(void);
extern void am_stimer_cmpr3_isr(void);
extern void am_stimer_cmpr4_isr(void);
extern void am_stimer_cmpr5_isr(void);
extern void am_stimer_cmpr6_isr(void);
extern void am_stimer_cmpr7_isr(void);
extern void am_flash_isr(void);
extern void am_clkgen_isr(void);
extern void am_default_isr(void);
//*****************************************************************************
//
// The entry point for the application startup code.
//
//*****************************************************************************
extern void __iar_program_start(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
static uint32_t pui32Stack[1024] @ ".stack";
//*****************************************************************************
//
// A union that describes the entries of the vector table. The union is needed
// since the first entry is the stack pointer and the remainder are function
// pointers.
//
//*****************************************************************************
typedef union
{
void (*pfnHandler)(void);
uint32_t ui32Ptr;
}
uVectorEntry;
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
// am_usagefault_isr does not work if am_fault_isr is defined externally.
// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
//
//*****************************************************************************
__root const uVectorEntry __vector_table[] @ ".intvec" =
{
{ .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) },
// The initial stack pointer
Reset_Handler, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MemManage_Handler
BusFault_Handler, // The BusFault_Handler
UsageFault_Handler, // The UsageFault_Handler
SecureFault_Handler, // The SecureFault_Handler
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
//
// Peripheral Interrupts
//
am_brownout_isr, // 0: Brownout (rstgen)
am_watchdog_isr, // 1: Watchdog
am_rtc_isr, // 2: RTC
am_vcomp_isr, // 3: Voltage Comparator
am_ioslave_ios_isr, // 4: I/O Slave general
am_ioslave_acc_isr, // 5: I/O Slave access
am_iomaster0_isr, // 6: I/O Master 0
am_iomaster1_isr, // 7: I/O Master 1
am_iomaster2_isr, // 8: I/O Master 2
am_iomaster3_isr, // 9: I/O Master 3
am_iomaster4_isr, // 10: I/O Master 4
am_iomaster5_isr, // 11: I/O Master 5
am_ble_isr, // 12: BLEIF
am_gpio_isr, // 13: GPIO
am_ctimer_isr, // 14: CTIMER
am_uart_isr, // 15: UART0
am_uart1_isr, // 16: UART1
am_scard_isr, // 17: SCARD
am_adc_isr, // 18: ADC
am_pdm0_isr, // 19: PDM
am_mspi0_isr, // 20: MSPI0
am_software0_isr, // 21: SOFTWARE0
am_stimer_isr, // 22: SYSTEM TIMER
am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0
am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1
am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2
am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3
am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4
am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5
am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6
am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7
am_clkgen_isr, // 31: CLKGEN
};
//******************************************************************************
//
// Place code immediately following vector table.
//
//******************************************************************************
//******************************************************************************
//
// The Patch table.
//
// The patch table should pad the vector table size to a total of 64 entries
// (16 core + 48 periph) such that code begins at offset 0x100.
//
//******************************************************************************
__root const uint32_t __Patchable[] @ ".patch" =
{
0, // 32
0, // 33
0, // 34
0, // 35
0, // 36
0, // 37
0, // 38
0, // 39
0, // 40
0, // 41
0, // 42
0, // 43
0, // 44
0, // 45
0, // 46
0, // 47
};
//*****************************************************************************
//
// Note - The template for this function is originally found in IAR's module,
// low_level_init.c. As supplied by IAR, it is an empty function.
//
// This module contains the function `__low_level_init', a function
// that is called before the `main' function of the program. Normally
// low-level initializations - such as setting the prefered interrupt
// level or setting the watchdog - can be performed here.
//
// Note that this function is called before the data segments are
// initialized, this means that this function cannot rely on the
// values of global or static variables.
//
// When this function returns zero, the startup code will inhibit the
// initialization of the data segments. The result is faster startup,
// the drawback is that neither global nor static data will be
// initialized.
//
// Copyright 1999-2017 IAR Systems AB.
//
// $Revision: 112610 $
//
//
//
//
//*****************************************************************************
#define AM_REGVAL(x) (*((volatile uint32_t *)(x)))
#define VTOR_ADDR 0xE000ED08
__interwork int __low_level_init(void)
{
AM_REGVAL(VTOR_ADDR) = (uint32_t)&__vector_table;
/*==================================*/
/* Choose if segment initialization */
/* should be done or not. */
/* Return: 0 to omit seg_init */
/* 1 to run seg_init */
/*==================================*/
return 1;
}
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.
//
//*****************************************************************************
void
Reset_Handler(void)
{
//
// Call the application's entry point.
//
__iar_program_start();
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
__weak void
NMI_Handler(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
__weak void
HardFault_Handler(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
am_default_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/Dbg_RAM.ini
+55
View File
@@ -0,0 +1,55 @@
/*----------------------------------------------------------------------------
* Name: Dbg_RAM.ini
* Purpose: RAM Debug Initialization File
* Note(s):
*----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* This software is supplied "AS IS" without warranties of any kind.
*
* Copyright (c) 2008-2013 Keil - An ARM Company. All rights reserved.
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
TraceSetup() Turn on ITM clocks, etc.
*----------------------------------------------------------------------------*/
FUNC void TraceSetup (void)
{
// turn on the ITM/TPIU clock
//_WDWORD(0x40020250, 0x00000201); // TPIU clock enabled at 3MHz
}
/*----------------------------------------------------------------------------
Setup() configure PC & SP for RAM Debug
*----------------------------------------------------------------------------*/
FUNC void Setup (void) {
SP = _RDWORD(0x0000C000+0x0); // Setup Stack Pointer
PC = _RDWORD(0x0000C000+0x4); // Setup Program Counter
_WDWORD(0xE000ED08, 0x0000C000+0x0); // Setup Vector Table Offset Register (done in system file)
}
/*----------------------------------------------------------------------------
OnResetExec() executed after reset via uVision's 'Reset'-button
*----------------------------------------------------------------------------*/
FUNC void OnResetExec (void)
{
}
LOAD %L INCREMENTAL // load the application
Setup(); // Setup for Running
BS main
g
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/JLinkSettings.ini
+40
View File
@@ -0,0 +1,40 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
; ScriptFile="AMAPH1KK-KBR.JLinkScript"
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="AMA3B1KK-KBR"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/Makefile
+80
View File
@@ -0,0 +1,80 @@
#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := cache_monitor
COMPILERNAME := Keil
PROJECT := cache_monitor_Keil
CONFIG := bin
SHELL:=/bin/bash
#### Required Executables ####
K := $(shell type -p UV4.exe)
RM := $(shell which rm 2>/dev/null)
ifeq ($(K),)
all clean:
$(info Tools w/$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
all: directories binary
.PHONY: binary
binary:
UV4.exe -b -t "cache_monitor" cache_monitor.uvprojx -j0 || [ $$? -eq 1 ]
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
clean:
@echo Cleaning... ;\
$(RM) -rf $(CONFIG)
../../../../../mcu/apollo3/hal/keil/bin/libam_hal.lib:
$(MAKE) -C ../../../../../mcu/apollo3/hal
../../../bsp/keil/bin/libam_bsp.lib:
$(MAKE) -C ../../../bsp
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/bin/cache_monitor.txt
+10642
View File
File diff suppressed because it is too large Load Diff
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/cache_monitor.sct
+60
View File
@@ -0,0 +1,60 @@
;******************************************************************************
;
; cache_monitor.sct
;
; Scatter file for Keil linker configuration.
;
;******************************************************************************
;******************************************************************************
;
; Copyright (c) 2020, Ambiq Micro
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; Third party software included in this distribution is subject to the
; additional license terms as defined in the /docs/licenses directory.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
;
;******************************************************************************
LR_1 0x0000C000
{
FLASH 0x0000C000 0x000F0000
{
*.o (RESET, +First)
* (+RO)
}
SRAM 0x10000000 0x00060000
{
startup_keil.o (STACK, +First)
* (+RW, +ZI)
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/cache_monitor.uvoptx
+364
View File
@@ -0,0 +1,364 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>cache_monitor</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>48000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>0</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\Dbg_RAM.ini</tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U483020000 -O2510 -S2 -ZTIFSpeedSel1000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO1 -TC3000000 -TP21 -TDS2 -TDT0 -TDC1F -TIE1 -TIP0 -TB1 -TFE0 -FO7 -FD10000000 -FC4000 -FN1 -FF0Apollo3.FLM -FS00 -FL0100000 -FP0($$Device:AMA3B1KK-KBR$Flash\Apollo3.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DbgCM</Key>
<Name>-U-O206 -O206 -S2 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO1 -TC3000000 -TP21 -TDS2 -TDT0 -TDC1F -TIE1 -TIP8 -FO7 -FD10000000 -FC4000 -FN1 -FF0Apollo3 -FS00 -FL080000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-UV0264NGE -O2510 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO1 -TC3000000 -TP21 -TDS8002 -TDT0 -TDC1F -TIE1 -TIP8 -FO7 -FD10000000 -FC4000 -FN1 -FF0Apollo3.FLM -FS00 -FL0100000 -FP0($$Device:AMA3B1KK-KBR$Flash\Apollo3.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>1</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<Lin2Executable></Lin2Executable>
<Lin2ConfigFile></Lin2ConfigFile>
<bLin2Auto>0</bLin2Auto>
<bAutoGenD>0</bAutoGenD>
<bAuto2GenD>0</bAuto2GenD>
</TargetOption>
</Target>
<Group>
<GroupName>src</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../src/cache_monitor.c</PathWithFileName>
<FilenameWithoutPath>cache_monitor.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>prime_mpi_src</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../../../../../third_party/prime_mpi/src/prime_mpi.c</PathWithFileName>
<FilenameWithoutPath>prime_mpi.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>devices</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../../../../../devices/am_devices_fireball.c</PathWithFileName>
<FilenameWithoutPath>am_devices_fireball.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../../../../../devices/am_devices_mspi_psram_aps6404l.c</PathWithFileName>
<FilenameWithoutPath>am_devices_mspi_psram_aps6404l.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>utils</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../../../../../utils/am_util_delay.c</PathWithFileName>
<FilenameWithoutPath>am_util_delay.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../../../../../utils/am_util_faultisr.c</PathWithFileName>
<FilenameWithoutPath>am_util_faultisr.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../../../../../utils/am_util_stdio.c</PathWithFileName>
<FilenameWithoutPath>am_util_stdio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>keil</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>../keil/startup_keil.s</PathWithFileName>
<FilenameWithoutPath>startup_keil.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/cache_monitor.uvprojx
+470
View File
@@ -0,0 +1,470 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>cache_monitor</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pArmCC></pArmCC>
<TargetOption>
<TargetCommonOption>
<Device>AMA3B1KK-KBR</Device>
<Vendor>Ambiq Micro</Vendor>
<PackID>AmbiqMicro.Apollo_DFP.1.1.0</PackID>
<PackURL>http://s3.asia.ambiqmicro.com/pack/</PackURL>
<Cpu>IRAM(0x10000000,0x00060000) IROM(0x0000C000,0x000F4000) CPUTYPE("Cortex-M4") FPU2 CLOCK(48000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC4000 -FN1 -FF0Apollo3 -FS0C000 -FL0F4000 -FP0($$Device:AMA3B1KK-KBR$Flash\Apollo3.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$Device:AMA3B1KK-KBR$Device\Include\apollo3.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:AMA3B1KK-KBR$SVD\apollo3.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>1024 BGA$Device\Include\apollo3.h\</RegisterFilePath>
<DBRegisterFilePath>1024 BGA$Device\Include\apollo3.h\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\bin\</OutputDirectory>
<OutputName>cache_monitor</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>1</RunUserProg2>
<UserProg1Name>fromelf --bin --output bin\cache_monitor.bin bin\cache_monitor.axf</UserProg1Name>
<UserProg2Name>fromelf -cedrst --output bin\cache_monitor.txt bin\cache_monitor.axf</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x60000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0xC000</StartAddress>
<Size>0xF4000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0xC000</StartAddress>
<Size>0xF4000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x60000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>1</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>AM_PART_APOLLO3 AM_PACKAGE_BGA APS6404L FIREBALL_CARD keil</Define>
<Undefine></Undefine>
<IncludePath>../../../../..;../../../../../CMSIS/ARM/Include;../src;../../../../../utils;../../../../../mcu/apollo3;../../../bsp;../../../../../devices;../../../../../CMSIS/AmbiqMicro/Include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange></TextAddressRange>
<DataAddressRange></DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\cache_monitor.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>../../../../../mcu/apollo3/hal/keil/bin/libam_hal.lib(am_hal_global.o) --keep=am_hal_global.o(.data) </Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>src</GroupName>
<Files>
<File>
<FileName>cache_monitor.c</FileName>
<FileType>1</FileType>
<FilePath>../src/cache_monitor.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>prime_mpi_src</GroupName>
<Files>
<File>
<FileName>prime_mpi.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../third_party/prime_mpi/src/prime_mpi.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>devices</GroupName>
<Files>
<File>
<FileName>am_devices_fireball.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../devices/am_devices_fireball.c</FilePath>
</File>
<File>
<FileName>am_devices_mspi_psram_aps6404l.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../devices/am_devices_mspi_psram_aps6404l.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>utils</GroupName>
<Files>
<File>
<FileName>am_util_delay.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../utils/am_util_delay.c</FilePath>
</File>
<File>
<FileName>am_util_faultisr.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../utils/am_util_faultisr.c</FilePath>
</File>
<File>
<FileName>am_util_stdio.c</FileName>
<FileType>1</FileType>
<FilePath>../../../../../utils/am_util_stdio.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>keil</GroupName>
<Files>
<File>
<FileName>startup_keil.s</FileName>
<FileType>1</FileType>
<FilePath>../keil/startup_keil.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>lib</GroupName>
<Files>
<File>
<FileName>libam_hal.lib</FileName>
<FileType>4</FileType>
<FilePath>../../../../../mcu/apollo3/hal/keil/bin/libam_hal.lib</FilePath>
</File>
<File>
<FileName>libam_bsp.lib</FileName>
<FileType>4</FileType>
<FilePath>../../../bsp/keil/bin/libam_bsp.lib</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/keil/startup_keil.s
+408
View File
@@ -0,0 +1,408 @@
;******************************************************************************
;
;! @file startup_keil.s
;!
;! @brief Definitions for Apollo3 interrupt handlers, the vector table, and the stack.
;
;******************************************************************************
;******************************************************************************
;
; Copyright (c) 2020, Ambiq Micro
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; Third party software included in this distribution is subject to the
; additional license terms as defined in the /docs/licenses directory.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
;
;******************************************************************************
;******************************************************************************
;
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;************************************************************************
Stack EQU 0x00001000
;******************************************************************************
;
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;
;******************************************************************************
Heap EQU 0x00000000
;******************************************************************************
;
; Allocate space for the stack.
;
;******************************************************************************
AREA STACK, NOINIT, READWRITE, ALIGN=3
StackMem
SPACE Stack
__initial_sp
;******************************************************************************
;
; Allocate space for the heap.
;
;******************************************************************************
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
HeapMem
SPACE Heap
__heap_limit
;******************************************************************************
;
; Indicate that the code in this file preserves 8-byte alignment of the stack.
;
;******************************************************************************
PRESERVE8
;******************************************************************************
;
; Place code into the reset code section.
;
;******************************************************************************
AREA RESET, CODE, READONLY
THUMB
;******************************************************************************
;
; The vector table.
;
;******************************************************************************
;
; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
; am_usagefault_isr does not work if am_fault_isr is defined externally.
; Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
;
EXPORT __Vectors
__Vectors
DCD StackMem + Stack ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; The MPU fault handler
DCD BusFault_Handler ; The bus fault handler
DCD UsageFault_Handler ; The usage fault handler
DCD SecureFault_Handler ; Secure fault handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall handler
DCD DebugMon_Handler ; Debug monitor handler
DCD 0 ; Reserved
DCD PendSV_Handler ; The PendSV handler
DCD SysTick_Handler ; The SysTick handler
;
; Peripheral Interrupts
;
DCD am_brownout_isr ; 0: Reserved
DCD am_watchdog_isr ; 1: Reserved
DCD am_rtc_isr ; 2: RTC
DCD am_vcomp_isr ; 3: Voltage Comparator
DCD am_ioslave_ios_isr ; 4: I/O Slave general
DCD am_ioslave_acc_isr ; 5: I/O Slave access
DCD am_iomaster0_isr ; 6: I/O Master 0
DCD am_iomaster1_isr ; 7: I/O Master 1
DCD am_iomaster2_isr ; 8: I/O Master 2
DCD am_iomaster3_isr ; 9: I/O Master 3
DCD am_iomaster4_isr ; 10: I/O Master 4
DCD am_iomaster5_isr ; 11: I/O Master 5
DCD am_ble_isr ; 12: BLEIF
DCD am_gpio_isr ; 13: GPIO
DCD am_ctimer_isr ; 14: CTIMER
DCD am_uart_isr ; 15: UART0
DCD am_uart1_isr ; 16: UART1
DCD am_scard_isr ; 17: SCARD
DCD am_adc_isr ; 18: ADC
DCD am_pdm0_isr ; 19: PDM
DCD am_mspi0_isr ; 20: MSPI0
DCD am_software0_isr ; 21: SOFTWARE0
DCD am_stimer_isr ; 22: SYSTEM TIMER
DCD am_stimer_cmpr0_isr ; 23: SYSTEM TIMER COMPARE0
DCD am_stimer_cmpr1_isr ; 24: SYSTEM TIMER COMPARE1
DCD am_stimer_cmpr2_isr ; 25: SYSTEM TIMER COMPARE2
DCD am_stimer_cmpr3_isr ; 26: SYSTEM TIMER COMPARE3
DCD am_stimer_cmpr4_isr ; 27: SYSTEM TIMER COMPARE4
DCD am_stimer_cmpr5_isr ; 28: SYSTEM TIMER COMPARE5
DCD am_stimer_cmpr6_isr ; 29: SYSTEM TIMER COMPARE6
DCD am_stimer_cmpr7_isr ; 30: SYSTEM TIMER COMPARE7
DCD am_clkgen_isr ; 31: CLKGEN
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
;******************************************************************************
;
; Place code immediately following vector table.
;
;******************************************************************************
;******************************************************************************
;
; The Patch table.
;
; The patch table should pad the vector table size to a total of 64 entries
; (16 core + 48 periph) such that code begins at offset 0x100.
;
;******************************************************************************
EXPORT __Patchable
__Patchable
DCD 0 ; 32
DCD 0 ; 33
DCD 0 ; 34
DCD 0 ; 35
DCD 0 ; 36
DCD 0 ; 37
DCD 0 ; 38
DCD 0 ; 39
DCD 0 ; 40
DCD 0 ; 41
DCD 0 ; 42
DCD 0 ; 43
DCD 0 ; 44
DCD 0 ; 45
DCD 0 ; 46
DCD 0 ; 47
;******************************************************************************
;
; This is the code that gets called when the processor first starts execution
; following a reset event.
;
;******************************************************************************
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
;
; Enable the FPU.
;
MOVW R0, #0xED88
MOVT R0, #0xE000
LDR R1, [R0]
ORR R1, #0x00F00000
STR R1, [R0]
DSB
ISB
;
; Branch to main.
;
LDR R0, =__main
BX R0
ENDP
;******************************************************************************
;
; Weak Exception Handlers.
;
;******************************************************************************
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SecureFault_Handler\
PROC
EXPORT SecureFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
am_default_isr\
PROC
EXPORT am_brownout_isr [WEAK]
EXPORT am_watchdog_isr [WEAK]
EXPORT am_rtc_isr [WEAK]
EXPORT am_vcomp_isr [WEAK]
EXPORT am_ioslave_ios_isr [WEAK]
EXPORT am_ioslave_acc_isr [WEAK]
EXPORT am_iomaster0_isr [WEAK]
EXPORT am_iomaster1_isr [WEAK]
EXPORT am_iomaster2_isr [WEAK]
EXPORT am_iomaster3_isr [WEAK]
EXPORT am_iomaster4_isr [WEAK]
EXPORT am_iomaster5_isr [WEAK]
EXPORT am_ble_isr [WEAK]
EXPORT am_gpio_isr [WEAK]
EXPORT am_ctimer_isr [WEAK]
EXPORT am_uart_isr [WEAK]
EXPORT am_uart0_isr [WEAK]
EXPORT am_uart1_isr [WEAK]
EXPORT am_scard_isr [WEAK]
EXPORT am_adc_isr [WEAK]
EXPORT am_pdm0_isr [WEAK]
EXPORT am_mspi0_isr [WEAK]
EXPORT am_software0_isr [WEAK]
EXPORT am_stimer_isr [WEAK]
EXPORT am_stimer_cmpr0_isr [WEAK]
EXPORT am_stimer_cmpr1_isr [WEAK]
EXPORT am_stimer_cmpr2_isr [WEAK]
EXPORT am_stimer_cmpr3_isr [WEAK]
EXPORT am_stimer_cmpr4_isr [WEAK]
EXPORT am_stimer_cmpr5_isr [WEAK]
EXPORT am_stimer_cmpr6_isr [WEAK]
EXPORT am_stimer_cmpr7_isr [WEAK]
EXPORT am_clkgen_isr [WEAK]
am_brownout_isr
am_watchdog_isr
am_rtc_isr
am_vcomp_isr
am_ioslave_ios_isr
am_ioslave_acc_isr
am_iomaster0_isr
am_iomaster1_isr
am_iomaster2_isr
am_iomaster3_isr
am_iomaster4_isr
am_iomaster5_isr
am_ble_isr
am_gpio_isr
am_ctimer_isr
am_uart_isr
am_uart0_isr
am_uart1_isr
am_scard_isr
am_adc_isr
am_pdm0_isr
am_mspi0_isr
am_software0_isr
am_stimer_isr
am_stimer_cmpr0_isr
am_stimer_cmpr1_isr
am_stimer_cmpr2_isr
am_stimer_cmpr3_isr
am_stimer_cmpr4_isr
am_stimer_cmpr5_isr
am_stimer_cmpr6_isr
am_stimer_cmpr7_isr
am_clkgen_isr
; all device interrupts go here unless the weak label is over
; ridden in the linker hard spin so the debugger will know it
; was an unhandled interrupt request a come-from-buffer or
; instruction trace hardware would sure be nice if you get here
B .
ENDP
;******************************************************************************
;
; Align the end of the section.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; Initialization of the heap and stack.
;
;******************************************************************************
AREA |.text|, CODE, READONLY
;******************************************************************************
;
; User Initial Stack & Heap.
;
;******************************************************************************
IF :DEF: __MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, =HeapMem
LDR R1, =(StackMem + Stack)
LDR R2, =(HeapMem + Heap)
LDR R3, =StackMem
BX LR
ENDP
ENDIF
;******************************************************************************
;
; Align the end of the section.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; All Done
;
;******************************************************************************
END
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo3_evb/examples/cache_monitor/src/cache_monitor.c
+655
View File
@@ -0,0 +1,655 @@
//*****************************************************************************
//
//! @file cache_monitor.c
//!
//! @brief Example to show the performance of cache.
//!
//! Purpose: This example provides a demonstration of the cache monitor to check
//! the cache hit rate and cache miss number.
//!
//! Additional Information:
//! If the fireball device card is used, this example can work on:
//! Apollo3_eb + Fireball2
//! Recommend to use 3.3V power supply voltage.
//! Define FIREBALL_CARD and APS6404L in the config-template.ini file to select.
//!
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include "am_mcu_apollo.h"
#include "am_bsp.h"
#include "am_util.h"
#define FIREBALL_CARD 0
#if FIREBALL_CARD
#include "am_devices_fireball.h"
#endif
#include "am_devices_mspi_psram_aps6404l.h"
#include <string.h>
//#define XIP_UNCACHED
#define TEMP_BUFFER_SIZE AM_DEVICES_MSPI_PSRAM_PAGE_SIZE // ((AM_HAL_IOM_MAX_TXNSIZE_SPI + 256) & 0xFFFFFF00)
uint32_t g_TempBuf[2][TEMP_BUFFER_SIZE / 4];
#define INITIAL_DATA 0x12
#define DATA_STEP 0x11
#define SIZE_STEP 2
uint32_t g_ui32CurData = INITIAL_DATA;
uint32_t g_iteration = 0;
#define ITERATION_NUM 10
// 4 pixel worth of data
#define DATA_4P(data) ((data) | ((data) << 8) | ((data) << 16) | ((data) << 24))
uint32_t g_data_size = 120 * 120;
uint32_t g_prime_num[ITERATION_NUM] = {10, 20, 50, 100, 200, 500, 1000, 2000, 5000, 10000};
uint32_t g_exp_prime[ITERATION_NUM] = {4, 8, 15, 25, 46, 95, 168, 303, 669, 1229};
uint32_t DMATCBBuffer[4096];
void *g_MSPIDevHdl;
void *g_MSPIHdl;
uint32_t g_DMON[4] = {0};
uint32_t g_IMON[4] = {0};
#define MSPI_XIP_BASE_ADDRESS 0x04000000
#define PSRAM_XIP_BASE MSPI_XIP_BASE_ADDRESS
#define PSRAM_XIP_OFFSET (PSRAM_XIP_BASE - MSPI_XIP_BASE_ADDRESS)
#define PSRAM_XIP_SIZE (1024*1024)
#define XIP_REFRESH_RATE 10
#define MSPI_TEST_MODULE 0
typedef uint32_t (*mspi_xip_test_function_t)(uint32_t, uint32_t, uint32_t);
/* File automatically generated with
"BIN2C prime_mpi.bin"
BIN2C (C) JRVV, ELECSAN S.A., 2016
This program is freeware
*/
#define SZ_PRIME_MPI 98
const unsigned char Kc_PRIME_MPI[SZ_PRIME_MPI] =
{
0x70, 0xB4, 0x04, 0x46, 0x00, 0x20, 0x89, 0x1C, 0x8C, 0x42, 0x28, 0xDB, 0x45, 0x1C, 0x02, 0x26,
0x8E, 0x42, 0x20, 0xDA, 0x91, 0xFB, 0xF6, 0xF3, 0x06, 0xFB, 0x13, 0x13, 0xD3, 0xB1, 0x76, 0x1C,
0x8E, 0x42, 0x18, 0xDA, 0x91, 0xFB, 0xF6, 0xF3, 0x06, 0xFB, 0x13, 0x13, 0x93, 0xB1, 0x76, 0x1C,
0x8E, 0x42, 0x10, 0xDA, 0x91, 0xFB, 0xF6, 0xF3, 0x06, 0xFB, 0x13, 0x13, 0x53, 0xB1, 0x76, 0x1C,
0x8E, 0x42, 0x08, 0xDA, 0x91, 0xFB, 0xF6, 0xF3, 0x06, 0xFB, 0x13, 0x13, 0x00, 0x2B, 0x18, 0xBF,
0x76, 0x1C, 0xDD, 0xD1, 0x05, 0x46, 0x51, 0x18, 0x8C, 0x42, 0x28, 0x46, 0xD6, 0xDA, 0x70, 0xBC,
0x70, 0x47,
};
am_devices_mspi_psram_config_t MSPI_PSRAM_QuadCE0MSPIConfig =
{
.eDeviceConfig = AM_HAL_MSPI_FLASH_QUAD_CE0,
.eClockFreq = AM_HAL_MSPI_CLK_8MHZ,
.eMixedMode = AM_HAL_MSPI_XIPMIXED_NORMAL,
.ui32NBTxnBufLength = sizeof(DMATCBBuffer) / sizeof(uint32_t),
.pNBTxnBuf = DMATCBBuffer,
.ui32ScramblingStartAddr = 0,
.ui32ScramblingEndAddr = 0,
};
const am_hal_cachectrl_config_t cache_monitor_cachectrl =
{
.bLRU = 0,
.eDescript = AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E,
.eMode = AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA,
};
float g_hit_rate = 0.0;
uint32_t g_cache_miss = 0;
//! MSPI interrupts.
static const IRQn_Type mspi_interrupts[] =
{
MSPI0_IRQn,
#if defined(AM_PART_APOLLO3P)
MSPI1_IRQn,
MSPI2_IRQn,
#endif
};
//
// Take over the interrupt handler for whichever MSPI we're using.
//
#define psram_mspi_isr \
am_mspi_isr1(MSPI_TEST_MODULE)
#define am_mspi_isr1(n) \
am_mspi_isr(n)
#define am_mspi_isr(n) \
am_mspi ## n ## _isr
//*****************************************************************************
//
// MSPI ISRs.
//
//*****************************************************************************
void psram_mspi_isr(void)
{
uint32_t ui32Status;
am_hal_mspi_interrupt_status_get(g_MSPIHdl, &ui32Status, false);
am_hal_mspi_interrupt_clear(g_MSPIHdl, ui32Status);
am_hal_mspi_interrupt_service(g_MSPIHdl, ui32Status);
}
//*****************************************************************************
//
// Prototype for third-party algorithm.
//
//*****************************************************************************
// n: number of primes, id=process number (), p=number of processes (1)
int prime_number ( int n, int id, int p );
int
mspi_psram_init(void)
{
uint32_t ui32Status;
//
// Configure the MSPI and PSRAM Device.
//
ui32Status = am_devices_mspi_psram_init(MSPI_TEST_MODULE, &MSPI_PSRAM_QuadCE0MSPIConfig, &g_MSPIDevHdl, &g_MSPIHdl);
if (AM_DEVICES_MSPI_PSRAM_STATUS_SUCCESS != ui32Status)
{
am_util_stdio_printf("Failed to configure the MSPI and PSRAM Device correctly!\n");
return -1;
}
return 0;
}
//*****************************************************************************
//
// Function prototypes
//
//*****************************************************************************
bool
run_mspi_xip(void)
{
uint32_t ret;
mspi_xip_test_function_t test_function = (mspi_xip_test_function_t)((PSRAM_XIP_BASE) | 0x00000001); // // Execute a call to the test function in the sector.
CACHECTRL->CACHECFG |= CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
CACHECTRL->CTRL = CACHECTRL_CTRL_RESET_STAT_Msk;
// Test the function
ret = test_function(g_prime_num[g_iteration], 0, 1);
CACHECTRL->CACHECFG &= ~CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
g_IMON[0] = CACHECTRL->IMON0;
g_IMON[1] = CACHECTRL->IMON1;
g_IMON[2] = CACHECTRL->IMON2;
g_IMON[3] = CACHECTRL->IMON3;
return (ret == g_exp_prime[g_iteration]);
}
//*****************************************************************************
//
// Timer handling to execute XIP codes
//
//*****************************************************************************
static am_hal_ctimer_config_t g_sTimer =
{
// Don't link timers.
0,
// Set up TimerA.
(AM_HAL_CTIMER_FN_REPEAT |
AM_HAL_CTIMER_INT_ENABLE |
AM_HAL_CTIMER_HFRC_12KHZ),
// No configuration for TimerB.
0,
};
// Timer Interrupt Service Routine (ISR)
void
am_ctimer_isr(void)
{
uint32_t ui32Status;
ui32Status = am_hal_ctimer_int_status_get(false);
am_hal_ctimer_int_clear(ui32Status);
am_hal_ctimer_int_service(ui32Status);
}
void
stop_xip_timer(void)
{
//
// Stop timer A0
//
am_hal_ctimer_stop(0, AM_HAL_CTIMER_TIMERA);
}
void
start_xip_timer(void)
{
stop_xip_timer(); // Just in case host died without sending STOP last time
//
// Start timer A0
//
am_hal_ctimer_start(0, AM_HAL_CTIMER_TIMERA);
}
void
deinit_xip_timer(void)
{
NVIC_DisableIRQ(CTIMER_IRQn);
am_hal_ctimer_int_clear(AM_HAL_CTIMER_INT_TIMERA0);
am_hal_ctimer_int_disable(AM_HAL_CTIMER_INT_TIMERA0);
}
static void
XIP_handler(void)
{
if (!run_mspi_xip())
{
am_util_stdio_printf("Unable to run XIP successfully\n");
while(1);
}
g_cache_miss = g_IMON[1] - g_IMON[2];
g_hit_rate = (float)g_IMON[2] * 100.0 / (float)g_IMON[1];
am_util_stdio_printf("*****Iteration%d complete*****\n", g_iteration);
am_util_stdio_printf("Total fetch number: %d\n", g_IMON[0]);
am_util_stdio_printf("Look up number: %d\n", g_DMON[1]);
am_util_stdio_printf("Cache miss number: %d\n", g_cache_miss);
am_util_stdio_printf("Cache hit rate: %6.2f%%\n", g_hit_rate);
if ( ++g_iteration >= ITERATION_NUM )
{
g_iteration = 0;
stop_xip_timer();
deinit_xip_timer();
am_util_stdio_printf("XIP Cache Performance Demonstration End!\n");
am_util_stdio_printf("Cache monitor example completes...\n");
}
}
void
init_xip_timer(void)
{
uint32_t ui32Period;
//
// Set up timer A0.
//
am_hal_ctimer_clear(0, AM_HAL_CTIMER_TIMERA);
am_hal_ctimer_config(0, &g_sTimer);
ui32Period = 12000 / XIP_REFRESH_RATE;
am_hal_ctimer_period_set(0, AM_HAL_CTIMER_TIMERA, ui32Period,
(ui32Period >> 1));
//
// Clear the timer Interrupt
//
am_hal_ctimer_int_clear(AM_HAL_CTIMER_INT_TIMERA0);
//
// Enable the timer Interrupt.
//
am_hal_ctimer_int_register(AM_HAL_CTIMER_INT_TIMERA0,
XIP_handler);
am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA0);
//
// Enable the timer interrupt in the NVIC.
//
NVIC_EnableIRQ(CTIMER_IRQn);
}
int
mspi_xip_init()
{
uint32_t ui32Status;
//
// Write the executable function into the target sector.
//
am_util_stdio_printf("Writing Executable function of %d Bytes to address %d\n", SZ_PRIME_MPI, PSRAM_XIP_BASE);
ui32Status = am_devices_mspi_psram_write(g_MSPIDevHdl, (uint8_t *)Kc_PRIME_MPI, PSRAM_XIP_OFFSET, SZ_PRIME_MPI, true);
if (AM_DEVICES_MSPI_PSRAM_STATUS_SUCCESS != ui32Status)
{
am_util_stdio_printf("Failed to write executable function to Flash Device!\n");
return -1;
}
//
// Set up for XIP operation.
//
am_util_stdio_printf("Putting the MSPI and External PSRAM into XIP mode\n");
ui32Status = am_devices_mspi_psram_enable_xip(g_MSPIDevHdl);
if (AM_DEVICES_MSPI_PSRAM_STATUS_SUCCESS != ui32Status)
{
am_util_stdio_printf("Failed to put the MSPI into XIP mode!\n");
return -1;
}
#ifndef XIP_UNCACHED
ui32Status = am_hal_cachectrl_control(AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE, 0);
if (AM_HAL_STATUS_SUCCESS != ui32Status)
{
am_util_stdio_printf("Failed to invalidate Cache!\n");
return -1;
}
#else
// Mark XIP as non-cached - to make sure we see its impact
am_hal_cachectrl_nc_cfg_t ncCfg;
ncCfg.bEnable = true;
ncCfg.eNCRegion = AM_HAL_CACHECTRL_NCR0;
ncCfg.ui32StartAddr = PSRAM_XIP_BASE;
ncCfg.ui32EndAddr = PSRAM_XIP_BASE + PSRAM_XIP_SIZE;
ui32Status = am_hal_cachectrl_control(AM_HAL_CACHECTRL_CONTROL_NC_CFG, &ncCfg);
if (AM_HAL_STATUS_SUCCESS != ui32Status)
{
am_util_stdio_printf("Failed to mark XIP region as non-cacheable\n");
return -1;
}
#endif
return 0;
}
#if FIREBALL_CARD
int
fireball_init(void)
{
uint32_t ui32Ret, ui32ID;
//
// Get Fireball ID and Rev info.
//
ui32Ret = am_devices_fireball_control(AM_DEVICES_FIREBALL_STATE_ID_GET, &ui32ID);
if ( ui32Ret != 0 )
{
am_util_stdio_printf("\nFAIL: am_devices_fireball_control(%d) returned 0x%X.\n",
AM_DEVICES_FIREBALL_STATE_ID_GET, ui32Ret);
return -1;
}
else if ( ui32ID == FIREBALL2_ID ) // only fireball2 has psram
{
am_util_stdio_printf("\nFireball found, ID is 0x%X.\n", ui32ID);
}
else
{
am_util_stdio_printf("\nUnknown device returned ID as 0x%X.\n", ui32ID);
}
ui32Ret = am_devices_fireball_control(AM_DEVICES_FIREBALL_STATE_VER_GET, &ui32ID);
if ( ui32Ret != 0 )
{
am_util_stdio_printf("\nFAIL: am_devices_fireball_control(%d) returned 0x%X.\n",
AM_DEVICES_FIREBALL_STATE_VER_GET, ui32Ret);
return -1;
}
else
{
am_util_stdio_printf("\nFireball Version is 0x%X.\n", ui32ID);
}
/* ui32Ret = am_devices_fireball_control(AM_DEVICES_FIREBALL2_STATE_SPI_PSRAM_FLASH_3P3, 0);
if ( ui32Ret != 0 )
{
DEBUG_PRINT("\nFAIL: am_devices_fireball_control(%d) returned 0x%X.\n",
AM_DEVICES_FIREBALL2_STATE_SPI_PSRAM_FLASH_3P3, ui32Ret);
return -1;
}*/
ui32Ret = am_devices_fireball_control(AM_DEVICES_FIREBALL2_STATE_MSPI_PSRAM_FLASH_3P3, 0);
if ( ui32Ret != 0 )
{
am_util_stdio_printf("\nFAIL: am_devices_fireball_control(%d) returned 0x%X.\n",
AM_DEVICES_FIREBALL2_STATE_MSPI_PSRAM_FLASH_3P3, ui32Ret);
return -1;
}
return 0;
}
#endif
int
flush_mspi_psram_data(void)
{
uint32_t ui32Status;
//DEBUG_PRINT("\nWriting a known pattern to psram!\n");
for (uint32_t address = 0; address < g_data_size; address += TEMP_BUFFER_SIZE)
{
uint32_t i;
//
// Generate raw color data into PSRAM frame buffer
//
for (i = 0; i < TEMP_BUFFER_SIZE / 4; i++)
{
g_TempBuf[0][i] = DATA_4P(g_ui32CurData);
}
AM_CRITICAL_BEGIN
CACHECTRL->CACHECFG |= CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
CACHECTRL->CTRL = CACHECTRL_CTRL_RESET_STAT_Msk;
AM_CRITICAL_END
//
// Write the buffer into the target address in PSRAM
//
ui32Status = am_devices_mspi_psram_write(g_MSPIDevHdl, (uint8_t *)g_TempBuf[0], address, TEMP_BUFFER_SIZE, true);
AM_CRITICAL_BEGIN
CACHECTRL->CACHECFG &= ~CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
g_DMON[0] += CACHECTRL->DMON0;
g_DMON[1] += CACHECTRL->DMON1;
g_DMON[2] += CACHECTRL->DMON2;
g_DMON[3] += CACHECTRL->DMON3;
AM_CRITICAL_END
if (AM_DEVICES_MSPI_PSRAM_STATUS_SUCCESS != ui32Status)
{
am_util_stdio_printf("\nFailed to write buffer to PSRAM Device!\n");
return -1;
}
//
// Read the data back into the RX buffer.
//
ui32Status = am_devices_mspi_psram_read(g_MSPIDevHdl, (uint8_t *)g_TempBuf[1], address, TEMP_BUFFER_SIZE, true);
if (AM_DEVICES_MSPI_PSRAM_STATUS_SUCCESS != ui32Status)
{
am_util_stdio_printf("\nFailed to read buffer to PSRAM Device!\n");
return -1;
}
//
// Compare the buffers
//
for (uint32_t i = 0; i < TEMP_BUFFER_SIZE / 4; i++)
{
if (g_TempBuf[1][i] != g_TempBuf[0][i])
{
am_util_stdio_printf("\nTX and RX buffers failed to compare!\n");
return -1;
}
}
}
return 0;
}
//*****************************************************************************
//
// Main Function.
//
//*****************************************************************************
int
main(void)
{
int iRet;
uint32_t ui32Result;
//
// Set the clock frequency.
//
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
//
// Set the default cache configuration
//
am_hal_cachectrl_config(&cache_monitor_cachectrl);
am_hal_cachectrl_enable();
//
// Configure the board for low power operation.
//
am_bsp_low_power_init();
//
// Enable the ITM print interface.
//
am_bsp_itm_printf_enable();
//
// Clear the terminal and print the banner.
//
am_util_stdio_terminal_clear();
am_util_stdio_printf("Ambiq Micro cache monitor example.\n\n");
//
// Print the compiler version.
//
am_util_stdio_printf("App Compiler: %s\n", COMPILER_VERSION);
am_util_stdio_printf("HAL Compiler: %s\n", g_ui8HALcompiler);
am_util_stdio_printf("HAL SDK version: %d.%d.%d\n",
g_ui32HALversion.s.Major,
g_ui32HALversion.s.Minor,
g_ui32HALversion.s.Revision);
am_util_stdio_printf("HAL compiled with %s-style registers\n",
g_ui32HALversion.s.bAMREGS ? "AM_REG" : "CMSIS");
#if FIREBALL_CARD
iRet = fireball_init();
if (iRet)
{
am_util_stdio_printf("Unable to initialize fireball\n");
while(1);
}
#endif
// Initialize the MSPI PSRAM
iRet = mspi_psram_init();
if (iRet)
{
am_util_stdio_printf("Unable to initialize MSPI psram\n");
while(1);
}
NVIC_EnableIRQ(mspi_interrupts[MSPI_TEST_MODULE]);
am_hal_interrupt_master_enable();
am_util_stdio_printf("DCACHE Performance Demonstration Start!\n");
while(1)
{
memset(g_DMON, 0, sizeof(uint32_t) * 4);
iRet = flush_mspi_psram_data();
if (iRet)
{
am_util_stdio_printf("Unable to flush MSPI psram\n");
while(1);
}
g_cache_miss = g_DMON[1] - g_DMON[2];
g_hit_rate = (float)g_DMON[2] / (float)g_DMON[1] * 100.0;
am_util_stdio_printf("*****Iteration%d complete*****\n", g_iteration);
am_util_stdio_printf("Total fetch number: %d\n", g_DMON[0]);
am_util_stdio_printf("Look up number: %d\n", g_DMON[1]);
am_util_stdio_printf("Cache miss number: %d\n", g_cache_miss);
am_util_stdio_printf("Cache hit rate: %6.2f%%\n", g_hit_rate);
if ( ++g_iteration >= ITERATION_NUM )
{
g_iteration = 0;
break;
}
g_ui32CurData += DATA_STEP;
g_data_size *= SIZE_STEP;
}
am_util_stdio_printf("DCACHE Performance Demonstration End!\n");
am_util_stdio_printf("ICACHE Performance Demonstration Start!\n");
while(1)
{
memset(g_IMON, 0, sizeof(uint32_t) * 4);
AM_CRITICAL_BEGIN
CACHECTRL->CACHECFG |= CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
CACHECTRL->CTRL = CACHECTRL_CTRL_RESET_STAT_Msk;
AM_CRITICAL_END
//
// Determine the number of primes for the given value.
//
ui32Result = prime_number(g_prime_num[g_iteration], 0, 1);
AM_CRITICAL_BEGIN
CACHECTRL->CACHECFG &= ~CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
g_IMON[0] = CACHECTRL->IMON0;
g_IMON[1] = CACHECTRL->IMON1;
g_IMON[2] = CACHECTRL->IMON2;
g_IMON[3] = CACHECTRL->IMON3;
AM_CRITICAL_END
if ( ui32Result != g_exp_prime[g_iteration] )
{
am_util_stdio_printf("ERROR: Invalid result. Expected %d, got %d.\n", g_prime_num[g_iteration], ui32Result);
while(1);
}
g_cache_miss = g_IMON[1] - g_IMON[2];
g_hit_rate = (float)g_IMON[2] * 100.0 / (float)g_IMON[1];
am_util_stdio_printf("*****Iteration%d complete*****\n", g_iteration);
am_util_stdio_printf("Total fetch number: %d\n", g_IMON[0]);
am_util_stdio_printf("Look up number: %d\n", g_DMON[1]);
am_util_stdio_printf("Cache miss number: %d\n", g_cache_miss);
am_util_stdio_printf("Cache hit rate: %6.2f%%\n", g_hit_rate);
if ( ++g_iteration >= ITERATION_NUM )
{
g_iteration = 0;
break;
}
}
am_util_stdio_printf("ICACHE Performance Demonstration End!\n");
iRet = mspi_xip_init();
if (iRet)
{
am_util_stdio_printf("Unable to init XIP\n");
while(1);
}
// Configure a Timer to trigger XIP
init_xip_timer();
start_xip_timer();
am_util_stdio_printf("XIP Cache Performance Demonstration Start!\n");
while(1);
}