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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/Makefile
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#******************************************************************************
#
# Makefile - Rules for compiling
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
# Include rules specific to this board
-include ../../board-defs.mk
-include example-defs.mk
# All makefiles use this to find the top level directory.
SWROOT?=../../../..
# Include rules for building generic examples.
include $(SWROOT)/makedefs/example.mk
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/README.txt
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Name:
=====
ios_fifo_host
Description:
============
Example host used for demonstrating the use of the IOS FIFO.
This host component runs on one EVB and is used in conjunction with
the companion slave example, ios_fifo, which runs on a second EVB.
The host example uses the ITM SWO to let the user know progress and
status of the demonstration. The SWO is configured at 1M baud.
The ios_fifo example has no print output.
This example implements the host part of a protocol for data exchange with
an Apollo IO Slave (IOS). The host sends one byte commands on SPI/I2C by
writing to offset 0x80.
The command is issued by the host to Start/Stop Data accumulation, and also
to acknowledge read-complete of a block of data.
On the IOS side, once it is asked to start accumulating data (using START
command), two CTimer based events emulate sensors sending data to IOS.
When IOS has some data for host, it implements a state machine,
synchronizing with the host.
The IOS interrupts the host to indicate data availability. The host then
reads the available data (as indicated by FIFOCTR) by READing using IOS FIFO
(at address 0x7F). The IOS keeps accumulating any new data coming in the
background.
Host sends an acknowledgement to IOS once it has finished reading a block
of data initiated by IOS (partitally or complete). IOS interrupts the host
again if and when it has more data for the host to read, and the cycle
repeats - till host indicates that it is no longer interested in receiving
data by sending STOP command.
In order to run this example, a slave device (e.g. a second EVB) must be set
up to run the companion example, ios_fifo. The two boards can be connected
using fly leads between the two boards as follows.
Pin connections for the I/O Master board to the I/O Slave board.
HOST (ios_fifo_host) SLAVE (ios_fifo)
-------------------- ----------------
GPIO[10] GPIO Interrupt (slave to host) GPIO[4] GPIO interrupt
GPIO[5] IOM0 SPI CLK/I2C SCL GPIO[0] IOS SPI SCK/I2C SCL
GPIO[6] IOM0 SPI MISO/I2C SDA GPIO[1] IOS SPI MISO/I2C SDA
GPIO[7] IOM0 SPI MOSI GPIO[2] IOS SPI MOSI
GPIO[11] IOM0 SPI nCE GPIO[3] IOS SPI nCE
GND GND
******************************************************************************
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/gcc/Makefile
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#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := ios_fifo_host
COMPILERNAME := gcc
PROJECT := ios_fifo_host_gcc
CONFIG := bin
SHELL:=/bin/bash
#### Setup ####
TOOLCHAIN ?= arm-none-eabi
PART = apollo
CPU = cortex-m4
FPU = fpv4-sp-d16
#FABI = softfp
FABI = hard
LINKER_FILE := ./ios_fifo_host.ld
STARTUP_FILE := ./startup_$(COMPILERNAME).c
#### Required Executables ####
CC = $(TOOLCHAIN)-gcc
GCC = $(TOOLCHAIN)-gcc
CPP = $(TOOLCHAIN)-cpp
LD = $(TOOLCHAIN)-ld
CP = $(TOOLCHAIN)-objcopy
OD = $(TOOLCHAIN)-objdump
RD = $(TOOLCHAIN)-readelf
AR = $(TOOLCHAIN)-ar
SIZE = $(TOOLCHAIN)-size
RM = $(shell which rm 2>/dev/null)
EXECUTABLES = CC LD CP OD AR RD SIZE GCC
K := $(foreach exec,$(EXECUTABLES),\
$(if $(shell which $($(exec)) 2>/dev/null),,\
$(info $(exec) not found on PATH ($($(exec))).)$(exec)))
$(if $(strip $(value K)),$(info Required Program(s) $(strip $(value K)) not found))
ifneq ($(strip $(value K)),)
all clean:
$(info Tools $(TOOLCHAIN)-$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
DEFINES = -DPART_$(PART)
DEFINES+= -DAM_PART_APOLLO
DEFINES+= -DAM_PACKAGE_BGA
DEFINES+= -Dgcc
INCLUDES = -I../../../../../utils
INCLUDES+= -I../src
INCLUDES+= -I../../../../../devices
INCLUDES+= -I../../../../..
INCLUDES+= -I../../../bsp
INCLUDES+= -I../../../../../mcu/apollo
VPATH = ../../../../../utils
VPATH+=:../src
SRC = ios_fifo_host.c
SRC += am_util_delay.c
SRC += am_util_stdio.c
SRC += startup_gcc.c
CSRC = $(filter %.c,$(SRC))
ASRC = $(filter %.s,$(SRC))
OBJS = $(CSRC:%.c=$(CONFIG)/%.o)
OBJS+= $(ASRC:%.s=$(CONFIG)/%.o)
DEPS = $(CSRC:%.c=$(CONFIG)/%.d)
DEPS+= $(ASRC:%.s=$(CONFIG)/%.d)
LIBS = ../../../bsp/gcc/bin/libam_bsp.a
LIBS += ../../../../../mcu/apollo/hal/gcc/bin/libam_hal.a
CFLAGS = -mthumb -mcpu=$(CPU) -mfpu=$(FPU) -mfloat-abi=$(FABI)
CFLAGS+= -ffunction-sections -fdata-sections
CFLAGS+= -MMD -MP -std=c99 -Wall -g
CFLAGS+= -O0
CFLAGS+= $(DEFINES)
CFLAGS+= $(INCLUDES)
CFLAGS+=
LFLAGS = -mthumb -mcpu=$(CPU) -mfpu=$(FPU) -mfloat-abi=$(FABI)
LFLAGS+= -nostartfiles -static
LFLAGS+= -Wl,--gc-sections,--entry,am_reset_isr,-Map,$(CONFIG)/$(TARGET).map
LFLAGS+= -Wl,--start-group -lm -lc -lgcc $(LIBS) -Wl,--end-group
LFLAGS+=
# Additional user specified CFLAGS
CFLAGS+=$(EXTRA_CFLAGS)
CPFLAGS = -Obinary
ODFLAGS = -S
#### Rules ####
all: directories $(CONFIG)/$(TARGET).bin
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
$(CONFIG)/%.o: %.c $(CONFIG)/%.d
@echo " Compiling $(COMPILERNAME) $<" ;\
$(CC) -c $(CFLAGS) $< -o $@
$(CONFIG)/%.o: %.s $(CONFIG)/%.d
@echo " Assembling $(COMPILERNAME) $<" ;\
$(CC) -c $(CFLAGS) $< -o $@
$(CONFIG)/$(TARGET).axf: $(OBJS) $(LIBS)
@echo " Linking $(COMPILERNAME) $@" ;\
$(CC) -Wl,-T,$(LINKER_FILE) -o $@ $(OBJS) $(LFLAGS)
$(CONFIG)/$(TARGET).bin: $(CONFIG)/$(TARGET).axf
@echo " Copying $(COMPILERNAME) $@..." ;\
$(CP) $(CPFLAGS) $< $@ ;\
$(OD) $(ODFLAGS) $< > $(CONFIG)/$(TARGET).lst
clean:
@echo "Cleaning..." ;\
$(RM) -f $(OBJS) $(DEPS) \
$(CONFIG)/$(TARGET).bin $(CONFIG)/$(TARGET).axf \
$(CONFIG)/$(TARGET).lst $(CONFIG)/$(TARGET).map
$(CONFIG)/%.d: ;
../../../bsp/gcc/bin/libam_bsp.a:
$(MAKE) -C ../../../bsp
../../../../../mcu/apollo/hal/gcc/bin/libam_hal.a:
$(MAKE) -C ../../../../../mcu/apollo/hal
# Automatically include any generated dependencies
-include $(DEPS)
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/gcc/ios_fifo_host.ld
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/******************************************************************************
*
* ios_fifo_host.ld - Linker script for applications using startup_gnu.c
*
*****************************************************************************/
ENTRY(am_reset_isr)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
}
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.isr_vector))
KEEP(*(.patch))
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
. = ALIGN(4);
_etext = .;
} > FLASH
/* User stack section initialized by startup code. */
.stack (NOLOAD):
{
. = ALIGN(8);
*(.stack)
*(.stack*)
. = ALIGN(8);
} > SRAM
.data :
{
. = ALIGN(4);
_sdata = .;
*(.data)
*(.data*)
. = ALIGN(4);
_edata = .;
} > SRAM AT>FLASH
/* used by startup to initialize data */
_init_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_sbss = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} > SRAM
.ARM.attributes 0 : { *(.ARM.attributes) }
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/gcc/startup_gcc.c
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//*****************************************************************************
//
//! @file startup_gcc.c
//!
//! @brief Definitions for interrupt handlers, the vector table, and the stack.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
//*****************************************************************************
//
// Forward declaration of interrupt handlers.
//
//*****************************************************************************
extern void am_reset_isr(void) __attribute ((naked));
extern void am_nmi_isr(void) __attribute ((weak));
extern void am_fault_isr(void) __attribute ((weak));
extern void am_mpufault_isr(void) __attribute ((weak, alias ("am_fault_isr")));
extern void am_busfault_isr(void) __attribute ((weak, alias ("am_fault_isr")));
extern void am_usagefault_isr(void) __attribute ((weak, alias ("am_fault_isr")));
extern void am_svcall_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_debugmon_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_pendsv_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_systick_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_brownout_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_adc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_watchdog_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_clkgen_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_vcomp_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ioslave_ios_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ioslave_acc_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster0_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_iomaster1_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_gpio_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_ctimer_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_uart_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_software12_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_software13_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_software14_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_software15_isr(void) __attribute ((weak, alias ("am_default_isr")));
extern void am_default_isr(void) __attribute ((weak));
//*****************************************************************************
//
// The entry point for the application.
//
//*****************************************************************************
extern int main(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
__attribute__ ((section(".stack")))
static uint32_t g_pui32Stack[1024];
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
// am_usagefault_isr does not work if am_fault_isr is defined externally.
// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
//
//*****************************************************************************
__attribute__ ((section(".isr_vector")))
void (* const g_am_pfnVectors[])(void) =
{
(void (*)(void))((uint32_t)g_pui32Stack + sizeof(g_pui32Stack)),
// The initial stack pointer
am_reset_isr, // The reset handler
am_nmi_isr, // The NMI handler
am_fault_isr, // The hard fault handler
am_fault_isr, // The MPU fault handler
am_fault_isr, // The bus fault handler
am_fault_isr, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
am_svcall_isr, // SVCall handle
am_debugmon_isr, // Debug monitor handler
0, // Reserved
am_pendsv_isr, // The PendSV handler
am_systick_isr, // The SysTick handler
//
// Peripheral Interrupts
//
am_brownout_isr, // 0: Brownout
am_watchdog_isr, // 1: Watchdog
am_clkgen_isr, // 2: CLKGEN
am_vcomp_isr, // 3: Voltage Comparator
am_ioslave_ios_isr, // 4: I/O Slave general
am_ioslave_acc_isr, // 5: I/O Slave access
am_iomaster0_isr, // 6: I/O Master 0
am_iomaster1_isr, // 7: I/O Master 1
am_adc_isr, // 8: ADC
am_gpio_isr, // 9: GPIO
am_ctimer_isr, // 10: CTIMER
am_uart_isr, // 11: UART
am_software12_isr, // 12: Software Interrupt
am_software13_isr, // 13: Software Interrupt
am_software14_isr, // 14: Software Interrupt
am_software15_isr // 15: Software Interrupt
};
//*****************************************************************************
//
// The following are constructs created by the linker, indicating where the
// the "data" and "bss" segments reside in memory. The initializers for the
// "data" segment resides immediately following the "text" segment.
//
//*****************************************************************************
extern uint32_t _etext;
extern uint32_t _sdata;
extern uint32_t _edata;
extern uint32_t _sbss;
extern uint32_t _ebss;
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.
//
//*****************************************************************************
#if defined(__GNUC_STDC_INLINE__)
void
am_reset_isr(void)
{
//
// Set the vector table pointer.
//
__asm(" ldr r0, =0xE000ED08\n"
" ldr r1, =g_am_pfnVectors\n"
" str r1, [r0]");
//
// Set the stack pointer.
//
__asm(" ldr sp, [r1]");
#ifndef NOFPU
//
// Enable the FPU.
//
__asm("ldr r0, =0xE000ED88\n"
"ldr r1,[r0]\n"
"orr r1,#(0xF << 20)\n"
"str r1,[r0]\n"
"dsb\n"
"isb\n");
#endif
//
// Copy the data segment initializers from flash to SRAM.
//
__asm(" ldr r0, =_init_data\n"
" ldr r1, =_sdata\n"
" ldr r2, =_edata\n"
"copy_loop:\n"
" ldr r3, [r0], #4\n"
" str r3, [r1], #4\n"
" cmp r1, r2\n"
" blt copy_loop\n");
//
// Zero fill the bss segment.
//
__asm(" ldr r0, =_sbss\n"
" ldr r1, =_ebss\n"
" mov r2, #0\n"
"zero_loop:\n"
" cmp r0, r1\n"
" it lt\n"
" strlt r2, [r0], #4\n"
" blt zero_loop");
//
// Call the application's entry point.
//
main();
//
// If main returns then execute a break point instruction
//
__asm(" bkpt ");
}
#else
#error GNU STDC inline not supported.
#endif
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
void
am_nmi_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void
am_fault_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void
am_default_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/iar/Makefile
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#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := ios_fifo_host
COMPILERNAME := iar
PROJECT := ios_fifo_host_iar
CONFIG := bin
AM_SoftwareRoot ?= ../../../..
SHELL:=/bin/bash
#### Required Executables ####
K := $(shell type -p IarBuild.exe)
RM = $(shell which rm 2>/dev/null)
ifeq ($(K),)
all clean:
$(info Tools w/$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
all: directories binary
.PHONY: binary
binary:
IarBuild.exe ios_fifo_host.ewp -make Debug -log info
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
clean:
@echo Cleaning... ;\
IarBuild.exe ios_fifo_host.ewp -clean Debug -log all
../../../bsp/iar/bin/libam_bsp.a:
$(MAKE) -C ../../../bsp
../../../../../mcu/apollo/hal/iar/bin/libam_hal.a:
$(MAKE) -C ../../../../../mcu/apollo/hal
endif
.PHONY: all clean directories
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\ios_fifo_host.ewp</path>
</project>
<batchBuild/>
</workspace>
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/iar/ios_fifo_host.icf
+101
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//*****************************************************************************
//
// ios_fifo_host.icf
//
// IAR linker Configuration File
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
//
// Define a memory section that covers the entire 4 GB addressable space of the
// processor. (32-bit can address up to 4GB)
//
define memory mem with size = 4G;
//
// Define a region for the flash.
//
define region FLASH = mem:[from 0x00000000 to 0x00080000];
//
// Define a region for the SRAM.
//
define region SRAM = mem:[from 0x10000000 to 0x10010000];
//
// Define a block for the heap.
//
define block HEAP with alignment = 0x8, size = 0x00000000 { };
//
// Define a block for the stack.
//
define block CSTACK with alignment = 0x8, size = 1024 { };
//
// Read/Write values should be initialized by copying from flash.
//
initialize by copy { readwrite };
//
// Indicate that the noinit values should be left alone.
//
do not initialize { section .noinit };
//
// Place the interrupt vectors at the start of flash.
//
place at start of FLASH { readonly section .intvec };
//
// Place the remainder of the read-only items into flash.
//
place in FLASH { readonly };
//
// Place the stack at the start of SRAM.
//
place at start of SRAM { block CSTACK, section .noinit };
//
// Place all read/write items into SRAM.
//
place in SRAM { block HEAP, readwrite };
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/iar/startup_iar.c
+298
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//*****************************************************************************
//
//! @file startup_iar.c
//!
//! @brief Definitions for interrupt handlers, the vector table, and the stack.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
//*****************************************************************************
//
// Enable the IAR extensions for this source file.
//
//*****************************************************************************
#pragma language = extended
//*****************************************************************************
//
// Weak function links.
//
//*****************************************************************************
#pragma weak am_mpufault_isr = am_fault_isr
#pragma weak am_busfault_isr = am_fault_isr
#pragma weak am_usagefault_isr = am_fault_isr
#pragma weak am_svcall_isr = am_default_isr
#pragma weak am_debugmon_isr = am_default_isr
#pragma weak am_pendsv_isr = am_default_isr
#pragma weak am_systick_isr = am_default_isr
#pragma weak am_brownout_isr = am_default_isr
#pragma weak am_adc_isr = am_default_isr
#pragma weak am_watchdog_isr = am_default_isr
#pragma weak am_clkgen_isr = am_default_isr
#pragma weak am_vcomp_isr = am_default_isr
#pragma weak am_ioslave_ios_isr = am_default_isr
#pragma weak am_ioslave_acc_isr = am_default_isr
#pragma weak am_iomaster0_isr = am_default_isr
#pragma weak am_iomaster1_isr = am_default_isr
#pragma weak am_gpio_isr = am_default_isr
#pragma weak am_ctimer_isr = am_default_isr
#pragma weak am_uart_isr = am_default_isr
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
extern __stackless void am_reset_isr(void);
extern __weak void am_nmi_isr(void);
extern __weak void am_fault_isr(void);
extern void am_mpufault_isr(void);
extern void am_busfault_isr(void);
extern void am_usagefault_isr(void);
extern void am_svcall_isr(void);
extern void am_debugmon_isr(void);
extern void am_pendsv_isr(void);
extern void am_systick_isr(void);
extern void am_brownout_isr(void);
extern void am_adc_isr(void);
extern void am_watchdog_isr(void);
extern void am_clkgen_isr(void);
extern void am_vcomp_isr(void);
extern void am_ioslave_ios_isr(void);
extern void am_ioslave_acc_isr(void);
extern void am_iomaster0_isr(void);
extern void am_iomaster1_isr(void);
extern void am_gpio_isr(void);
extern void am_ctimer_isr(void);
extern void am_uart_isr(void);
extern void am_default_isr(void);
//*****************************************************************************
//
// The entry point for the application startup code.
//
//*****************************************************************************
extern void __iar_program_start(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
static uint32_t pui32Stack[1024] @ ".noinit";
//*****************************************************************************
//
// A union that describes the entries of the vector table. The union is needed
// since the first entry is the stack pointer and the remainder are function
// pointers.
//
//*****************************************************************************
typedef union
{
void (*pfnHandler)(void);
uint32_t ui32Ptr;
}
uVectorEntry;
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
// am_usagefault_isr does not work if am_fault_isr is defined externally.
// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
//
//*****************************************************************************
__root const uVectorEntry __vector_table[] @ ".intvec" =
{
{ .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) },
// The initial stack pointer
am_reset_isr, // The reset handler
am_nmi_isr, // The NMI handler
am_fault_isr, // The hard fault handler
am_fault_isr, // The MPU fault handler
am_fault_isr, // The bus fault handler
am_fault_isr, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
am_svcall_isr, // SVCall handle
am_debugmon_isr, // Debug monitor handler
0, // Reserved
am_pendsv_isr, // The PendSV handler
am_systick_isr, // The SysTick handler
//
// Peripheral Interrupts
//
am_brownout_isr, // 0: Brownout
am_watchdog_isr, // 1: Watchdog
am_clkgen_isr, // 2: CLKGEN
am_vcomp_isr, // 3: Voltage Comparator
am_ioslave_ios_isr, // 4: I/O Slave general
am_ioslave_acc_isr, // 5: I/O Slave access
am_iomaster0_isr, // 6: I/O Master 0
am_iomaster1_isr, // 7: I/O Master 1
am_adc_isr, // 8: ADC
am_gpio_isr, // 9: GPIO
am_ctimer_isr, // 10: CTIMER
am_uart_isr // 11: UART
};
//*****************************************************************************
//
// Note - The template for this function is originally found in IAR's module,
// low_level_init.c. As supplied by IAR, it is an empty function.
//
// This module contains the function `__low_level_init', a function
// that is called before the `main' function of the program. Normally
// low-level initializations - such as setting the prefered interrupt
// level or setting the watchdog - can be performed here.
//
// Note that this function is called before the data segments are
// initialized, this means that this function cannot rely on the
// values of global or static variables.
//
// When this function returns zero, the startup code will inhibit the
// initialization of the data segments. The result is faster startup,
// the drawback is that neither global nor static data will be
// initialized.
//
// Copyright 1999-2017 IAR Systems AB.
//
// $Revision: 112610 $
//
//
//
//
//*****************************************************************************
#define AM_REGVAL(x) (*((volatile uint32_t *)(x)))
#define VTOR_ADDR 0xE000ED08
__interwork int __low_level_init(void)
{
AM_REGVAL(VTOR_ADDR) = (uint32_t)&__vector_table;
/*==================================*/
/* Choose if segment initialization */
/* should be done or not. */
/* Return: 0 to omit seg_init */
/* 1 to run seg_init */
/*==================================*/
return 1;
}
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.
//
//*****************************************************************************
void
am_reset_isr(void)
{
//
// Call the application's entry point.
//
__iar_program_start();
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
__weak void
am_nmi_isr(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
__weak void
am_fault_isr(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
am_default_isr(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/Dbg_RAM.ini
+59
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/*----------------------------------------------------------------------------
* Name: Dbg_RAM.ini
* Purpose: RAM Debug Initialization File
* Note(s):
*----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* This software is supplied "AS IS" without warranties of any kind.
*
* Copyright (c) 2008-2013 Keil - An ARM Company. All rights reserved.
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
TraceSetup() Turn on ITM clocks, etc.
*----------------------------------------------------------------------------*/
FUNC void TraceSetup (void) {
// turn on the ITM/TPIU clock
_WDWORD(0x40020250, 0x00000201); // TPIU clock enabled at 3MHz
}
/*----------------------------------------------------------------------------
Setup() configure PC & SP for RAM Debug
*----------------------------------------------------------------------------*/
FUNC void Setup (void) {
SP = _RDWORD(0x00000000+0x0); // Setup Stack Pointer
PC = _RDWORD(0x00000000+0x4); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000+0x0); // Setup Vector Table Offset Register (done in system file)
}
LOAD %L INCREMENTAL // load the application
// Executed after reset via uVision's 'Reset'-button
FUNC void OnResetExec (void) {
//Set_ui32HALflags();
//TraceSetup();
}
FUNC void Set_ui32HALflags (void) {
TraceSetup();
g_ui32HALflags = 0x00000001;
_break_ = 1;
}
Setup(); // Setup for Running
BS main, 1, "Set_ui32HALflags()";
g
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/JLinkSettings.ini
+40
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@@ -0,0 +1,40 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="APOLLO512-KBR"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/Makefile
+80
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@@ -0,0 +1,80 @@
#******************************************************************************
#
# Makefile - Rules for building the libraries, examples and docs.
#
# Copyright (c) 2020, Ambiq Micro
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# Third party software included in this distribution is subject to the
# additional license terms as defined in the /docs/licenses directory.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This is part of revision 2.4.2 of the AmbiqSuite Development Package.
#
#******************************************************************************
TARGET := ios_fifo_host
COMPILERNAME := Keil
PROJECT := ios_fifo_host_Keil
CONFIG := bin
SHELL:=/bin/bash
#### Required Executables ####
K := $(shell type -p UV4.exe)
RM := $(shell which rm 2>/dev/null)
ifeq ($(K),)
all clean:
$(info Tools w/$(COMPILERNAME) not installed.)
$(RM) -rf bin
else
all: directories binary
.PHONY: binary
binary:
UV4.exe -b -t "ios_fifo_host" ios_fifo_host.uvprojx -j0 || [ $$? -eq 1 ]
directories: $(CONFIG)
$(CONFIG):
@mkdir -p $@
clean:
@echo Cleaning... ;\
$(RM) -rf $(CONFIG)
../../../../../mcu/apollo/hal/keil/bin/libam_hal.lib:
$(MAKE) -C ../../../../../mcu/apollo/hal
../../../bsp/keil/bin/libam_bsp.lib:
$(MAKE) -C ../../../bsp
endif
.PHONY: all clean directories
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/bin/ios_fifo_host.txt
+6118
View File
File diff suppressed because it is too large Load Diff
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/ios_fifo_host.sct
+59
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@@ -0,0 +1,59 @@
;******************************************************************************
;
; ios_fifo_host.sct
;
; Scatter file for Keil linker configuration.
;
;******************************************************************************
;******************************************************************************
;
; Copyright (c) 2020, Ambiq Micro
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; Third party software included in this distribution is subject to the
; additional license terms as defined in the /docs/licenses directory.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
;
;******************************************************************************
LR_1 0x00000000
{
FLASH 0x00000000 0x00080000
{
*.o (RESET, +First)
* (+RO)
}
SRAM 0x10000000 0x00010000
{
* (+RW, +ZI)
}
}
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/ios_fifo_host.uvoptx
+284
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@@ -0,0 +1,284 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>ios_fifo_host</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>24000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>0</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\Dbg_RAM.ini</tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>/</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U483025288 -O462 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO1 -TC3000000 -TP21 -TDS2 -TDT0 -TDC1F -TIE1 -TIP8 -TB1 -TFE0 -FO7 -FD10000000 -FC4000 -FN1 -FF0Apollo -FS00 -FL080000 -FP0($$Device:APOLLO512-KBR$Flash\Apollo.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
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<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DbgCM</Key>
<Name>-U-O206 -O206 -S2 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO1 -TC3000000 -TP21 -TDS2 -TDT0 -TDC1F -TIE1 -TIP8 -FO7 -FD10000000 -FC4000 -FN1 -FF0Apollo -FS00 -FL080000</Name>
</SetRegEntry>
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<Key>UL2CM3</Key>
<Name>-UV0236LFE -O462 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO1 -TC3000000 -TP21 -TDS8002 -TDT0 -TDC1F -TIE1 -TIP8 -FO7 -FD10000000 -FC4000 -FN1 -FF0Apollo.FLM -FS00 -FL080000 -FP0($$Device:APOLLO512-KBR$Flash\Apollo.FLM)</Name>
</SetRegEntry>
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</DebugFlag>
<LintExecutable></LintExecutable>
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</TargetOption>
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/ios_fifo_host.uvprojx
+434
View File
@@ -0,0 +1,434 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>ios_fifo_host</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pArmCC></pArmCC>
<TargetOption>
<TargetCommonOption>
<Device>APOLLO512-KBR</Device>
<Vendor>Ambiq Micro</Vendor>
<PackID>AmbiqMicro.Apollo_DFP.1.0.0</PackID>
<PackURL>http://s3.asia.ambiqmicro.com/pack/</PackURL>
<Cpu>IRAM(0x10000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC2000 -FN1 -FF0Apollo -FS00 -FL010000 -FP0($Device:APOLLO512-KBR$Flash\Apollo.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:APOLLO512-KBR$Device\Include\Apollo.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:APOLLO512-KBR$SVD\apollo.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\bin\</OutputDirectory>
<OutputName>ios_fifo_host</OutputName>
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<DebugInformation>1</DebugInformation>
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<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
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<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
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<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
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<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>1</RunUserProg2>
<UserProg1Name>fromelf --bin --output bin\ios_fifo_host.bin bin\ios_fifo_host.axf</UserProg1Name>
<UserProg2Name>fromelf -cedrst --output bin\ios_fifo_host.txt bin\ios_fifo_host.axf</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
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</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
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<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
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<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
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<AdsLsym>1</AdsLsym>
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<AdsLsun>1</AdsLsun>
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<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
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<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
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<OptFeed>0</OptFeed>
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<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
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<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
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<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
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</Ocm4>
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</Ocm5>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
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<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
</IRAM>
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<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</IROM>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
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<Type>1</Type>
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</OCR_RVCT1>
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<Type>1</Type>
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</OCR_RVCT2>
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</OCR_RVCT3>
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<Type>1</Type>
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</OCR_RVCT4>
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</OCR_RVCT5>
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</OCR_RVCT8>
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<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT9>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>1</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
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<MiscControls></MiscControls>
<Define>AM_PART_APOLLO AM_PACKAGE_BGA keil</Define>
<Undefine></Undefine>
<IncludePath>../../../../../utils;../src;../../../../../devices;../../../../..;../../../bsp;../../../../../mcu/apollo</IncludePath>
</VariousControls>
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<IncludeLibsPath></IncludeLibsPath>
<Misc>../../../../../mcu/apollo/hal/keil/bin/libam_hal.lib(am_hal_global.o) --keep=am_hal_global.o(.data) </Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
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<File>
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<FilePath>../src/ios_fifo_host.c</FilePath>
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<FilePath>../../../../../utils/am_util_stdio.c</FilePath>
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<File>
<FileName>startup_keil.s</FileName>
<FileType>1</FileType>
<FilePath>../keil/startup_keil.s</FilePath>
</File>
</Files>
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<File>
<FileName>libam_hal.lib</FileName>
<FileType>4</FileType>
<FilePath>../../../../../mcu/apollo/hal/keil/bin/libam_hal.lib</FilePath>
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<File>
<FileName>libam_bsp.lib</FileName>
<FileType>4</FileType>
<FilePath>../../../bsp/keil/bin/libam_bsp.lib</FilePath>
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ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/keil/startup_keil.s
+289
View File
@@ -0,0 +1,289 @@
;******************************************************************************
;
;! @file startup_keil.s
;!
;! @brief Definitions for Apollo1 interrupt handlers, the vector table, and the stack.
;
;******************************************************************************
;******************************************************************************
;
; Copyright (c) 2020, Ambiq Micro
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; Third party software included in this distribution is subject to the
; additional license terms as defined in the /docs/licenses directory.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
;
;******************************************************************************
;******************************************************************************
;
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;************************************************************************
Stack EQU 0x00001000
;******************************************************************************
;
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;
;******************************************************************************
Heap EQU 0x00000000
;******************************************************************************
;
; Allocate space for the stack.
;
;******************************************************************************
AREA STACK, NOINIT, READWRITE, ALIGN=3
StackMem
SPACE Stack
__initial_sp
;******************************************************************************
;
; Allocate space for the heap.
;
;******************************************************************************
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
HeapMem
SPACE Heap
__heap_limit
;******************************************************************************
;
; Indicate that the code in this file preserves 8-byte alignment of the stack.
;
;******************************************************************************
PRESERVE8
;******************************************************************************
;
; Place code into the reset code section.
;
;******************************************************************************
AREA RESET, CODE, READONLY
THUMB
;******************************************************************************
;
; The vector table.
;
;******************************************************************************
;
; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
; am_usagefault_isr does not work if am_fault_isr is defined externally.
; Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
;
EXPORT __Vectors
__Vectors
DCD StackMem + Stack ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD am_nmi_isr ; NMI Handler
DCD am_fault_isr ; Hard Fault Handler
DCD am_fault_isr ; The MPU fault handler
DCD am_fault_isr ; The bus fault handler
DCD am_fault_isr ; The usage fault handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD am_svcall_isr ; SVCall handler
DCD am_debugmon_isr ; Debug monitor handler
DCD 0 ; Reserved
DCD am_pendsv_isr ; The PendSV handler
DCD am_systick_isr ; The SysTick handler
;
; Peripheral Interrupts
;
DCD am_brownout_isr ; 0: Reserved
DCD am_watchdog_isr ; 1: Reserved
DCD am_clkgen_isr ; 2: CLKGEN
DCD am_vcomp_isr ; 3: Voltage Comparator
DCD am_ioslave_ios_isr ; 4: I/O Slave general
DCD am_ioslave_acc_isr ; 5: I/O Slave access
DCD am_iomaster0_isr ; 6: I/O Master 0
DCD am_iomaster1_isr ; 7: I/O Master 1
DCD am_adc_isr ; 8: Reserved
DCD am_gpio_isr ; 9: GPIO
DCD am_ctimer_isr ; 10: CTIMER
DCD am_uart_isr ; 11: UART
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
;******************************************************************************
;
; This is the code that gets called when the processor first starts execution
; following a reset event.
;
;******************************************************************************
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
;
; Enable the FPU.
;
MOVW R0, #0xED88
MOVT R0, #0xE000
LDR R1, [R0]
ORR R1, #0x00F00000
STR R1, [R0]
DSB
ISB
;
; Branch to main.
;
LDR R0, =__main
BX R0
ENDP
;******************************************************************************
;
; Weak Exception Handlers.
;
;******************************************************************************
am_nmi_isr PROC
EXPORT am_nmi_isr [WEAK]
B .
ENDP
am_fault_isr\
PROC
EXPORT am_fault_isr [WEAK]
B .
ENDP
am_memmanage_isr\
PROC
EXPORT am_memmanage_isr [WEAK]
B .
ENDP
am_default_isr\
PROC
EXPORT am_svcall_isr [WEAK]
EXPORT am_debugmon_isr [WEAK]
EXPORT am_pendsv_isr [WEAK]
EXPORT am_systick_isr [WEAK]
EXPORT am_brownout_isr [WEAK]
EXPORT am_adc_isr [WEAK]
EXPORT am_watchdog_isr [WEAK]
EXPORT am_clkgen_isr [WEAK]
EXPORT am_vcomp_isr [WEAK]
EXPORT am_ioslave_ios_isr [WEAK]
EXPORT am_ioslave_acc_isr [WEAK]
EXPORT am_iomaster0_isr [WEAK]
EXPORT am_iomaster1_isr [WEAK]
EXPORT am_gpio_isr [WEAK]
EXPORT am_ctimer_isr [WEAK]
EXPORT am_uart_isr [WEAK]
am_svcall_isr
am_debugmon_isr
am_pendsv_isr
am_systick_isr
am_brownout_isr
am_adc_isr
am_watchdog_isr
am_clkgen_isr
am_vcomp_isr
am_ioslave_ios_isr
am_ioslave_acc_isr
am_iomaster0_isr
am_iomaster1_isr
am_gpio_isr
am_ctimer_isr
am_uart_isr
; all device interrupts go here unless the weak label is over
; ridden in the linker hard spin so the debugger will know it
; was an unhandled interrupt request a come-from-buffer or
; instruction trace hardware would sure be nice if you get here
B .
ENDP
;******************************************************************************
;
; Align the end of the section.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; Initialization of the heap and stack.
;
;******************************************************************************
AREA |.text|, CODE, READONLY
;******************************************************************************
;
; User Initial Stack & Heap.
;
;******************************************************************************
IF :DEF: __MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, =HeapMem
LDR R1, =(StackMem + Stack)
LDR R2, =(HeapMem + Heap)
LDR R3, =StackMem
BX LR
ENDP
ENDIF
;******************************************************************************
;
; Align the end of the section.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; All Done
;
;******************************************************************************
END
ambiq-hal-sys/ambiq-sparkfun-sdk/boards/apollo1_evb/examples/ios_fifo_host/src/ios_fifo_host.c
+602
View File
@@ -0,0 +1,602 @@
//*****************************************************************************
//
//! @file ios_fifo_host.c
//!
//! @brief Example host used for demonstrating the use of the IOS FIFO.
//!
//! This host component runs on one EVB and is used in conjunction with
//! the companion slave example, ios_fifo, which runs on a second EVB.
//!
//! The host example uses the ITM SWO to let the user know progress and
//! status of the demonstration. The SWO is configured at 1M baud.
//! The ios_fifo example has no print output.
//!
//! This example implements the host part of a protocol for data exchange with
//! an Apollo IO Slave (IOS). The host sends one byte commands on SPI/I2C by
//! writing to offset 0x80.
//!
//! The command is issued by the host to Start/Stop Data accumulation, and also
//! to acknowledge read-complete of a block of data.
//!
//! On the IOS side, once it is asked to start accumulating data (using START
//! command), two CTimer based events emulate sensors sending data to IOS.
//! When IOS has some data for host, it implements a state machine,
//! synchronizing with the host.
//!
//! The IOS interrupts the host to indicate data availability. The host then
//! reads the available data (as indicated by FIFOCTR) by READing using IOS FIFO
//! (at address 0x7F). The IOS keeps accumulating any new data coming in the
//! background.
//!
//! Host sends an acknowledgement to IOS once it has finished reading a block
//! of data initiated by IOS (partitally or complete). IOS interrupts the host
//! again if and when it has more data for the host to read, and the cycle
//! repeats - till host indicates that it is no longer interested in receiving
//! data by sending STOP command.
//!
//! In order to run this example, a slave device (e.g. a second EVB) must be set
//! up to run the companion example, ios_fifo. The two boards can be connected
//! using fly leads between the two boards as follows.
//!
//! @verbatim
//! Pin connections for the I/O Master board to the I/O Slave board.
//!
//! HOST (ios_fifo_host) SLAVE (ios_fifo)
//! -------------------- ----------------
//! GPIO[10] GPIO Interrupt (slave to host) GPIO[4] GPIO interrupt
//! GPIO[5] IOM0 SPI CLK/I2C SCL GPIO[0] IOS SPI SCK/I2C SCL
//! GPIO[6] IOM0 SPI MISO/I2C SDA GPIO[1] IOS SPI MISO/I2C SDA
//! GPIO[7] IOM0 SPI MOSI GPIO[2] IOS SPI MOSI
//! GPIO[11] IOM0 SPI nCE GPIO[3] IOS SPI nCE
//! GND GND
//! @endverbatim
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp.h"
#include "am_util.h"
#include "am_devices.h"
#define IOM_MODULE 0
#define USE_SPI 1 // 0 = I2C, 1 = SPI
#define I2C_ADDR 0x10
// How much data to read from Slave before ending the test
#define MAX_SIZE 10000
#define XOR_BYTE 0
#define EMPTY_BYTE 0xEE
typedef enum
{
AM_IOSTEST_CMD_START_DATA = 0,
AM_IOSTEST_CMD_STOP_DATA = 1,
AM_IOSTEST_CMD_ACK_DATA = 2,
} AM_IOSTEST_CMD_E;
#define IOSOFFSET_WRITE_INTEN 0xF8
#define IOSOFFSET_WRITE_INTCLR 0xFA
#define IOSOFFSET_WRITE_CMD 0x80
#define IOSOFFSET_READ_INTSTAT 0x79
#define IOSOFFSET_READ_FIFO 0x7F
#define IOSOFFSET_READ_FIFOCTR 0x7C
#define AM_IOSTEST_IOSTOHOST_DATAAVAIL_INTMASK 1
#define HANDSHAKE_PIN 10
//*****************************************************************************
//
// Configure GPIOs for communicating with a SPI fram
// TODO: This should ideally come from BSP to keep the code portable
//
//*****************************************************************************
static const uint32_t apollo2_iomce0[AM_REG_IOMSTR_NUM_MODULES][2] =
{
{11, AM_HAL_PIN_11_M0nCE0},
{12, AM_HAL_PIN_12_M1nCE0},
#ifdef AM_PART_APOLLO2
{ 3, AM_HAL_PIN_3_M2nCE0},
{26, AM_HAL_PIN_26_M3nCE0},
{29, AM_HAL_PIN_29_M4nCE0},
{24, AM_HAL_PIN_24_M5nCE0}
#endif
};
//*****************************************************************************
//
// Global message buffer for the IO master.
//
//*****************************************************************************
#define AM_TEST_RCV_BUF_SIZE 1024 // Max Size we can receive is 1023
uint8_t g_pui8RcvBuf[AM_TEST_RCV_BUF_SIZE];
volatile uint32_t g_startIdx = 0;
volatile bool bIosInt = false;
//*****************************************************************************
//
// Configuration structure for the IO Master.
//
//*****************************************************************************
static am_hal_iom_config_t g_sIOMSpiConfig =
{
.ui32InterfaceMode = AM_HAL_IOM_SPIMODE,
// .ui32ClockFrequency = AM_HAL_IOM_12MHZ,
// .ui32ClockFrequency = AM_HAL_IOM_8MHZ,
// .ui32ClockFrequency = AM_HAL_IOM_6MHZ,
.ui32ClockFrequency = AM_HAL_IOM_4MHZ,
// .ui32ClockFrequency = AM_HAL_IOM_3MHZ,
// .ui32ClockFrequency = AM_HAL_IOM_2MHZ,
// .ui32ClockFrequency = AM_HAL_IOM_1_5MHZ,
// .ui32ClockFrequency = AM_HAL_IOM_1MHZ,
// .ui32ClockFrequency = AM_HAL_IOM_750KHZ,
// .ui32ClockFrequency = AM_HAL_IOM_500KHZ,
// .ui32ClockFrequency = AM_HAL_IOM_400KHZ,
// .ui32ClockFrequency = AM_HAL_IOM_375KHZ,
// .ui32ClockFrequency = AM_HAL_IOM_250KHZ,
// .ui32ClockFrequency = AM_HAL_IOM_100KHZ,
// .ui32ClockFrequency = AM_HAL_IOM_50KHZ,
// .ui32ClockFrequency = AM_HAL_IOM_10KHZ,
.bSPHA = 0,
.bSPOL = 0,
.ui8WriteThreshold = 4,
.ui8ReadThreshold = 60,
};
#define MAX_SPI_SIZE 1023
static am_hal_iom_config_t g_sIOMI2cConfig =
{
.ui32InterfaceMode = AM_HAL_IOM_I2CMODE,
.ui32ClockFrequency = AM_HAL_IOM_1MHZ,
.ui8WriteThreshold = 12,
.ui8ReadThreshold = 120,
};
#define MAX_I2C_SIZE 255
//*****************************************************************************
//
// Clear Rx Buffer for comparison
//
//*****************************************************************************
void
clear_rx_buf(void)
{
uint32_t i;
for ( i = 0; i < AM_TEST_RCV_BUF_SIZE; i++ )
{
g_pui8RcvBuf[i] = EMPTY_BYTE;
}
}
//*****************************************************************************
//
// Validate Rx Buffer
// Returns 0 for success case
//
//*****************************************************************************
uint32_t
validate_rx_buf(uint32_t rxSize)
{
uint32_t i;
for ( i = 0; i < rxSize; i++ )
{
if ( g_pui8RcvBuf[i] != (((g_startIdx + i) & 0xFF) ^ XOR_BYTE) )
{
am_util_stdio_printf("Failed to compare buffers at index %d \n", i);
break;
}
}
// Set the reference for next chunk
g_startIdx += rxSize;
return (i == rxSize);
}
// ISR callback for the host IOINT
static void hostint_handler(void)
{
bIosInt = true;
}
//*****************************************************************************
//
// Interrupt handler for the GPIO pins.
//
//*****************************************************************************
void
am_gpio_isr(void)
{
uint64_t ui64Status;
//
// Read and clear the GPIO interrupt status.
//
ui64Status = am_hal_gpio_int_status_get(false);
am_hal_gpio_int_clear(ui64Status);
am_hal_gpio_int_service(ui64Status);
}
//*****************************************************************************
//
// Start up the ITM interface.
//
//*****************************************************************************
void
itm_start(void)
{
//
// Initialize the printf interface for ITM/SWO output.
//
am_util_stdio_printf_init((am_util_stdio_print_char_t) am_bsp_itm_string_print);
//
// Initialize the SWO GPIO pin
//
am_bsp_pin_enable(ITM_SWO);
//
// Enable the ITM.
//
am_hal_itm_enable();
//
// Enable debug printf messages using ITM on SWO pin
//
am_bsp_debug_printf_enable();
//
// Clear the terminal.
//
am_util_stdio_terminal_clear();
}
void
iom_slave_read(uint32_t iom, bool bSpi, uint32_t offset, uint32_t *pBuf, uint32_t size)
{
if ( bSpi )
{
am_hal_iom_spi_read(iom, 0,
pBuf, size, AM_HAL_IOM_OFFSET(offset));
}
else
{
am_hal_iom_i2c_read(iom, I2C_ADDR,
pBuf, size, AM_HAL_IOM_OFFSET(offset));
}
}
void
iom_slave_write(uint32_t iom, bool bSpi, uint32_t offset, uint32_t *pBuf, uint32_t size)
{
if ( bSpi )
{
am_hal_iom_spi_write(iom, 0,
pBuf, size, AM_HAL_IOM_OFFSET(offset));
}
else
{
am_hal_iom_i2c_write(iom, I2C_ADDR,
pBuf, size, AM_HAL_IOM_OFFSET(offset) );
}
}
//*****************************************************************************
//
// Internal Helper functions
//
//*****************************************************************************
void
i2c_pins_enable(uint32_t ui32Module)
{
switch(ui32Module)
{
case 0:
//
// Set pins high to prevent bus dips.
//
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM0_SCL);
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM0_SDA);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM0_SCL, AM_HAL_PIN_5_M0SCL | AM_HAL_GPIO_PULLUP);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM0_SDA, AM_HAL_PIN_6_M0SDA | AM_HAL_GPIO_PULLUP);
break;
case 1:
//
// Set pins high to prevent bus dips.
//
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM1_SCL);
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM1_SDA);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM1_SCL, AM_HAL_PIN_8_M1SCL | AM_HAL_GPIO_PULLUP);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM1_SDA, AM_HAL_PIN_9_M1SDA | AM_HAL_GPIO_PULLUP);
break;
#ifndef AM_PART_APOLLO
case 2:
//
// Set pins high to prevent bus dips.
//
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM2_SCL);
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM2_SDA);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM2_SCL, AM_HAL_PIN_27_M2SCL | AM_HAL_GPIO_PULLUP);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM2_SDA, AM_HAL_PIN_25_M2SDA | AM_HAL_GPIO_PULLUP);
break;
case 3:
//
// Set pins high to prevent bus dips.
//
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM3_SCL);
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM3_SDA);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM3_SCL, AM_HAL_PIN_42_M3SCL | AM_HAL_GPIO_PULLUP);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM3_SDA, AM_HAL_PIN_43_M3SDA | AM_HAL_GPIO_PULLUP);
break;
case 4:
//
// Set pins high to prevent bus dips.
//
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM4_SCL);
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM4_SDA);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM4_SCL, AM_HAL_PIN_39_M4SCL | AM_HAL_GPIO_PULLUP);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM4_SDA, AM_HAL_PIN_40_M4SDA | AM_HAL_GPIO_PULLUP);
break;
case 5:
//
// Set pins high to prevent bus dips.
//
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM5_SCL);
am_hal_gpio_out_bit_set(AM_BSP_GPIO_IOM5_SDA);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM5_SCL, AM_HAL_PIN_48_M5SCL | AM_HAL_GPIO_PULLUP);
am_hal_gpio_pin_config(AM_BSP_GPIO_IOM5_SDA, AM_HAL_PIN_49_M5SDA | AM_HAL_GPIO_PULLUP);
break;
#endif
//
// If we get here, the caller's selected IOM interface couldn't be
// found in the BSP GPIO definitions. Halt program execution for
// debugging.
//
default:
while (1);
}
}
static void
iom_set_up(uint32_t iomModule, bool bSpi)
{
uint32_t ioIntEnable = AM_IOSTEST_IOSTOHOST_DATAAVAIL_INTMASK;
//
// Enable power to IOM.
//
am_hal_iom_pwrctrl_enable(iomModule);
if ( bSpi )
{
//
// Set the required configuration settings for the IOM.
//
am_hal_iom_config(iomModule, &g_sIOMSpiConfig);
//
// Set up IOM SPI pins. Attributes are set in am_bsp_gpio.h.
//
am_bsp_iom_spi_pins_enable(iomModule);
//
// Enable the chip-select and data-ready pin.
//! @note You can enable pins in the HAL or BSP.
//
am_hal_gpio_pin_config(apollo2_iomce0[iomModule][0],
apollo2_iomce0[iomModule][1]);
}
else
{
//
// Set the required configuration settings for the IOM.
//
am_hal_iom_config(iomModule, &g_sIOMI2cConfig);
i2c_pins_enable(iomModule);
}
//
// Turn on the IOM for this operation.
//
am_bsp_iom_enable(iomModule);
// Set up the host IO interrupt
am_hal_gpio_pin_config(HANDSHAKE_PIN, AM_HAL_GPIO_INPUT);
am_hal_gpio_int_polarity_bit_set(HANDSHAKE_PIN, AM_HAL_GPIO_RISING);
am_hal_gpio_int_clear(AM_HAL_GPIO_BIT(HANDSHAKE_PIN));
// Register handler for IOS => IOM interrupt
am_hal_gpio_int_register(HANDSHAKE_PIN, hostint_handler);
am_hal_gpio_int_enable(AM_HAL_GPIO_BIT(HANDSHAKE_PIN));
am_hal_interrupt_enable(AM_HAL_INTERRUPT_GPIO);
// Set up IOCTL interrupts
// IOS ==> IOM
iom_slave_write(iomModule, bSpi, IOSOFFSET_WRITE_INTEN, &ioIntEnable, 1);
}
uint32_t g_ui32LastUpdate = 0;
//*****************************************************************************
//
// Print a progress message.
//
//*****************************************************************************
void
update_progress(uint32_t ui32NumPackets)
{
//
// Print a dot every 10000 packets.
//
if ( (ui32NumPackets - g_ui32LastUpdate) > 1000 )
{
am_util_stdio_printf(".");
g_ui32LastUpdate = ui32NumPackets;
}
}
//*****************************************************************************
//
// Main function.
//
//*****************************************************************************
int
main(void)
{
uint32_t iom = IOM_MODULE;
bool bSpi = USE_SPI;
bool bReadIosData = false;
bool bDone = false;
uint32_t data;
uint32_t maxSize = (bSpi) ? MAX_SPI_SIZE: MAX_I2C_SIZE;
//
// Set the clock frequency.
//
am_hal_clkgen_sysclk_select(AM_HAL_CLKGEN_SYSCLK_MAX);
//
// Set the default cache configuration
//
am_hal_cachectrl_enable(&am_hal_cachectrl_defaults);
//
// Configure the board for low power operation.
//
am_bsp_low_power_init();
//
//
// Initialize the printf interface for ITM/SWO output.
//
itm_start();
//
// IOS test start message.
//
am_util_stdio_printf("IOS Test Host: Waiting for at least %d bytes from the slave.", MAX_SIZE);
// Set up IOM & Enable interrupt for IOS
iom_set_up(iom, bSpi);
// Send the START
data = AM_IOSTEST_CMD_START_DATA;
iom_slave_write(iom, bSpi, IOSOFFSET_WRITE_CMD, &data, 1);
//
// Loop forever.
//
while ( !bDone )
{
//
// Disable interrupt while we decide whether we're going to sleep.
//
uint32_t ui32IntStatus = am_hal_interrupt_master_disable();
if ( bIosInt == true )
{
//
// Enable interrupts
//
am_hal_interrupt_master_set(ui32IntStatus);
bIosInt = false;
// Read & Clear the IOINT status
iom_slave_read(iom, bSpi, IOSOFFSET_READ_INTSTAT, &data, 1);
// We need to clear the bit by writing to IOS
if ( data & AM_IOSTEST_IOSTOHOST_DATAAVAIL_INTMASK )
{
data = AM_IOSTEST_IOSTOHOST_DATAAVAIL_INTMASK;
iom_slave_write(iom, bSpi, IOSOFFSET_WRITE_INTCLR, &data, 1);
// Set bReadIosData
bReadIosData = true;
}
if ( bReadIosData )
{
uint32_t iosSize = 0;
bReadIosData = false;
// Read the Data Size
iom_slave_read(iom, bSpi, IOSOFFSET_READ_FIFOCTR, &iosSize, 2);
iosSize = (iosSize > maxSize)? maxSize: iosSize;
// Initialize Rx Buffer for later comparison
clear_rx_buf();
// Read the data
iom_slave_read(iom, bSpi, IOSOFFSET_READ_FIFO,
(uint32_t *)g_pui8RcvBuf, iosSize);
// Validate Content
if ( !validate_rx_buf(iosSize) )
{
am_util_stdio_printf("\nData Verification failed Accum:%lu rx=%d\n",
g_startIdx, iosSize);
}
// Send the ACK/STOP
data = AM_IOSTEST_CMD_ACK_DATA;
update_progress(g_startIdx);
if ( g_startIdx >= MAX_SIZE )
{
bDone = true;
data = AM_IOSTEST_CMD_STOP_DATA;
}
iom_slave_write(iom, bSpi, IOSOFFSET_WRITE_CMD, &data, 1);
}
}
else
{
am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
//
// Enable interrupts
//
am_hal_interrupt_master_set(ui32IntStatus);
}
}
am_util_stdio_printf("\nTest Done - Total Received = =%d\n", g_startIdx);
while (1);
}