324 lines
10 KiB
C
324 lines
10 KiB
C
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//*****************************************************************************
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//
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// am_hal_sysctrl.c
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//! @file
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//!
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//! @brief Functions for interfacing with the M4F system control registers
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//!
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//! @addtogroup sysctrl3p System Control (SYSCTRL)
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//! @ingroup apollo3phal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Globals
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//
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//*****************************************************************************
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//
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// g_ui32BusWriteFlush is used by the macro, am_hal_sysctrl_bus_write_flush().
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// It is made global here to avoid compiler 'set but not used' warnings.
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//
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static volatile uint32_t g_ui32BusWriteFlush;
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//*****************************************************************************
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//
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//! @brief Place the core into sleep or deepsleep.
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//!
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//! @param bSleepDeep - False for Normal or True Deep sleep.
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//!
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//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep.
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//!
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//! Valid values for bSleepDeep are:
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//!
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//! AM_HAL_SYSCTRL_SLEEP_NORMAL
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//! AM_HAL_SYSCTRL_SLEEP_DEEP
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_sleep(bool bSleepDeep)
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{
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bool bBurstModeSleep;
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am_hal_burst_mode_e eBurstMode;
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//
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// Disable interrupts and save the previous interrupt state.
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//
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AM_CRITICAL_BEGIN
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//
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// If Apollo3 Blue Plus rev 0 and in burst mode, must exit burst mode
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// before going to sleep.
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//
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if ( am_hal_burst_mode_status() == AM_HAL_BURST_MODE )
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{
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bBurstModeSleep = true;
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if ( (am_hal_burst_mode_disable(&eBurstMode) != AM_HAL_STATUS_SUCCESS) ||
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(eBurstMode != AM_HAL_NORMAL_MODE) )
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{
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//
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// FIXME - Although a failure is highly unlikely, this error needs
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// to be handled more cleanly!
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//
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while(1);
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}
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}
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else
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{
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bBurstModeSleep = false;
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}
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//
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// If the user selected DEEPSLEEP and the TPIU is off, attempt to enter
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// DEEP SLEEP.
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//
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if ( (bSleepDeep == AM_HAL_SYSCTRL_SLEEP_DEEP) &&
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(MCUCTRL->TPIUCTRL_b.ENABLE == MCUCTRL_TPIUCTRL_ENABLE_DIS) )
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{
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//
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// Retrieve the reset generator status bits
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// This gets reset on Deep Sleep, so we take a snapshot here
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//
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if (!gAmHalResetStatus)
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{
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gAmHalResetStatus = RSTGEN->STAT;
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}
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//
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// Prepare the core for deepsleep (write 1 to the DEEPSLEEP bit).
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//
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SCB->SCR |= _VAL2FLD(SCB_SCR_SLEEPDEEP, 1);
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}
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else
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{
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//
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// Prepare the core for normal sleep (write 0 to the DEEPSLEEP bit).
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//
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SCB->SCR &= ~_VAL2FLD(SCB_SCR_SLEEPDEEP, 1);
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}
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//
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// Before executing WFI, flush any buffered core and peripheral writes.
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//
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__DSB();
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am_hal_sysctrl_bus_write_flush();
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//
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// Execute the sleep instruction.
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//
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__WFI();
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//
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// Upon wake, execute the Instruction Sync Barrier instruction.
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//
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__ISB();
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//
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// Restore burst mode?
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//
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if ( bBurstModeSleep )
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{
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bBurstModeSleep = false;
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if ( (am_hal_burst_mode_enable(&eBurstMode) != AM_HAL_STATUS_SUCCESS) ||
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(eBurstMode != AM_HAL_BURST_MODE) )
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{
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//
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// FIXME - Although a failure is highly unlikely, this error needs
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// to be handled more cleanly!
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//
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//while(1);
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}
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}
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//
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// Restore the interrupt state.
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//
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AM_CRITICAL_END
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}
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//*****************************************************************************
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//
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//! @brief Enable the floating point module.
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//!
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//! Call this function to enable the ARM hardware floating point module.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_enable(void)
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{
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//
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// Enable access to the FPU in both privileged and user modes.
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// NOTE: Write 0s to all reserved fields in this register.
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//
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SCB->CPACR = _VAL2FLD(SCB_CPACR_CP11, 0x3) |
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_VAL2FLD(SCB_CPACR_CP10, 0x3);
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}
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//*****************************************************************************
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//
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//! @brief Disable the floating point module.
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//!
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//! Call this function to disable the ARM hardware floating point module.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_disable(void)
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{
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//
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// Disable access to the FPU in both privileged and user modes.
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// NOTE: Write 0s to all reserved fields in this register.
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//
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SCB->CPACR = 0x00000000 &
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~(_VAL2FLD(SCB_CPACR_CP11, 0x3) |
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_VAL2FLD(SCB_CPACR_CP10, 0x3));
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}
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//*****************************************************************************
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//
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//! @brief Enable stacking of FPU registers on exception entry.
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//!
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//! @param bLazy - Set to "true" to enable "lazy stacking".
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//!
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//! This function allows the core to save floating-point information to the
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//! stack on exception entry. Setting the bLazy option enables "lazy stacking"
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//! for interrupt handlers. Normally, mixing floating-point code and interrupt
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//! driven routines causes increased interrupt latency, because the core must
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//! save extra information to the stack upon exception entry. With the lazy
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//! stacking option enabled, the core will skip the saving of floating-point
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//! registers when possible, reducing average interrupt latency.
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//!
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//! @note At reset of the Cortex M4, the ASPEN and LSPEN bits are set to 1,
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//! enabling Lazy mode by default. Therefore this function will generally
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//! only have an affect when setting for full-context save (or when switching
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//! from full-context to lazy mode).
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//!
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//! @note See also:
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//! infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/DAFGGBJD.html
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//!
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//! @note Three valid FPU context saving modes are possible.
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//! 1. Lazy ASPEN=1 LSPEN=1 am_hal_sysctrl_fpu_stacking_enable(true)
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//! and default.
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//! 2. Full-context ASPEN=1 LSPEN=0 am_hal_sysctrl_fpu_stacking_enable(false)
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//! 3. No FPU state ASPEN=0 LSPEN=0 am_hal_sysctrl_fpu_stacking_disable()
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//! 4. Invalid ASPEN=0 LSPEN=1
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_stacking_enable(bool bLazy)
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{
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uint32_t ui32fpccr;
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//
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// Set the requested FPU stacking mode in ISRs.
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//
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AM_CRITICAL_BEGIN
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#define SYSCTRL_FPCCR_LAZY (FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk)
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ui32fpccr = FPU->FPCCR;
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ui32fpccr &= ~SYSCTRL_FPCCR_LAZY;
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ui32fpccr |= (bLazy ? SYSCTRL_FPCCR_LAZY : FPU_FPCCR_ASPEN_Msk);
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FPU->FPCCR = ui32fpccr;
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AM_CRITICAL_END
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}
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//*****************************************************************************
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//
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//! @brief Disable FPU register stacking on exception entry.
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//!
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//! This function disables all stacking of floating point registers for
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//! interrupt handlers. This mode should only be used when it is absolutely
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//! known that no FPU instructions will be executed in an ISR.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_stacking_disable(void)
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{
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//
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// Completely disable FPU context save on entry to ISRs.
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//
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AM_CRITICAL_BEGIN
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FPU->FPCCR &= ~SYSCTRL_FPCCR_LAZY;
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AM_CRITICAL_END
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}
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//*****************************************************************************
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//
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//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl.
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//!
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//! This function issues a system wide reset (Apollo POR level reset).
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_aircr_reset(void)
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{
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//
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// Set the system reset bit in the AIRCR register
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//
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__NVIC_SystemReset();
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}
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//*****************************************************************************
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//
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// End Doxygen group.
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//! @}
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//
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//*****************************************************************************
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