378 lines
16 KiB
C
378 lines
16 KiB
C
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//*****************************************************************************
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//
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// am_hal_ios.h
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//! @file
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//!
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//! @brief Functions for interfacing with the IO Slave module
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//!
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//! @addtogroup ios3 IO Slave (SPI/I2C)
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//! @ingroup apollo3hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_HAL_IOS_H
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#define AM_HAL_IOS_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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// CMSIS-style macro for handling a variable IOS module number.
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//
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#define IOSLAVEn(n) ((IOSLAVE_Type*)(IOSLAVE_BASE + (n * (IOSLAVE_BASE - IOSLAVE_BASE))))
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//*****************************************************************************
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//*****************************************************************************
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//
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//! @name Interface Configuration
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//! @brief Macro definitions for configuring the physical interface of the IO
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//! Slave
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//!
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//! These macros may be used with the am_hal_ios_config_t structure to set the
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//! physical parameters of the SPI/I2C slave module.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOS_USE_SPI _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_SPI)
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#define AM_HAL_IOS_SPIMODE_0 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3)
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#define AM_HAL_IOS_SPIMODE_1 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2)
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#define AM_HAL_IOS_SPIMODE_2 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2)
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#define AM_HAL_IOS_SPIMODE_3 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3)
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#define AM_HAL_IOS_USE_I2C _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_I2C)
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#define AM_HAL_IOS_I2C_ADDRESS(n) _VAL2FLD(IOSLAVE_CFG_I2CADDR, n)
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#define AM_HAL_IOS_LSB_FIRST _VAL2FLD(IOSLAVE_CFG_LSB, 1)
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//! @}
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//*****************************************************************************
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//
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//! @name Register Access Interrupts
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//! @brief Macro definitions for register access interrupts.
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//!
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//! These macros may be used with any of the
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOS_ACCESS_INT_00 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 31)
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#define AM_HAL_IOS_ACCESS_INT_01 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 30)
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#define AM_HAL_IOS_ACCESS_INT_02 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 29)
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#define AM_HAL_IOS_ACCESS_INT_03 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 28)
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#define AM_HAL_IOS_ACCESS_INT_04 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 27)
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#define AM_HAL_IOS_ACCESS_INT_05 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 26)
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#define AM_HAL_IOS_ACCESS_INT_06 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 25)
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#define AM_HAL_IOS_ACCESS_INT_07 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 24)
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#define AM_HAL_IOS_ACCESS_INT_08 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 23)
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#define AM_HAL_IOS_ACCESS_INT_09 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 22)
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#define AM_HAL_IOS_ACCESS_INT_0A _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 21)
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#define AM_HAL_IOS_ACCESS_INT_0B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 20)
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#define AM_HAL_IOS_ACCESS_INT_0C _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 19)
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#define AM_HAL_IOS_ACCESS_INT_0D _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 18)
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#define AM_HAL_IOS_ACCESS_INT_0E _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 17)
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#define AM_HAL_IOS_ACCESS_INT_0F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 16)
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#define AM_HAL_IOS_ACCESS_INT_13 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 15)
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#define AM_HAL_IOS_ACCESS_INT_17 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 14)
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#define AM_HAL_IOS_ACCESS_INT_1B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 13)
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#define AM_HAL_IOS_ACCESS_INT_1F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 12)
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#define AM_HAL_IOS_ACCESS_INT_23 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 11)
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#define AM_HAL_IOS_ACCESS_INT_27 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 10)
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#define AM_HAL_IOS_ACCESS_INT_2B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 9)
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#define AM_HAL_IOS_ACCESS_INT_2F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 8)
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#define AM_HAL_IOS_ACCESS_INT_33 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 7)
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#define AM_HAL_IOS_ACCESS_INT_37 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 6)
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#define AM_HAL_IOS_ACCESS_INT_3B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 5)
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#define AM_HAL_IOS_ACCESS_INT_3F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 4)
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#define AM_HAL_IOS_ACCESS_INT_43 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 3)
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#define AM_HAL_IOS_ACCESS_INT_47 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 2)
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#define AM_HAL_IOS_ACCESS_INT_4B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 1)
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#define AM_HAL_IOS_ACCESS_INT_4F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 0)
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#define AM_HAL_IOS_ACCESS_INT_ALL 0xFFFFFFFF
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//! @}
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//*****************************************************************************
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//
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//! @name I/O Slave Interrupts
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//! @brief Macro definitions for I/O slave (IOS) interrupts.
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//!
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//! These macros may be used with any of the
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOS_INT_FSIZE IOSLAVE_INTEN_FSIZE_Msk
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#define AM_HAL_IOS_INT_FOVFL IOSLAVE_INTEN_FOVFL_Msk
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#define AM_HAL_IOS_INT_FUNDFL IOSLAVE_INTEN_FUNDFL_Msk
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#define AM_HAL_IOS_INT_FRDERR IOSLAVE_INTEN_FRDERR_Msk
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#define AM_HAL_IOS_INT_GENAD IOSLAVE_INTEN_GENAD_Msk
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#define AM_HAL_IOS_INT_IOINTW IOSLAVE_INTEN_IOINTW_Msk
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#define AM_HAL_IOS_INT_XCMPWR IOSLAVE_INTEN_XCMPWR_Msk
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#define AM_HAL_IOS_INT_XCMPWF IOSLAVE_INTEN_XCMPWF_Msk
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#define AM_HAL_IOS_INT_XCMPRR IOSLAVE_INTEN_XCMPRR_Msk
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#define AM_HAL_IOS_INT_XCMPRF IOSLAVE_INTEN_XCMPRF_Msk
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#define AM_HAL_IOS_INT_ALL 0xFFFFFFFF
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//! @}
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//*****************************************************************************
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//
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//! @name I/O Slave Interrupts triggers
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//! @brief Macro definitions for I/O slave (IOS) interrupts.
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//!
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//! These macros may be used with am_hal_ios_interrupt_set and am_hal_ios_interrupt_clear
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOS_IOINTCTL_INT0 (0x01)
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#define AM_HAL_IOS_IOINTCTL_INT1 (0x02)
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#define AM_HAL_IOS_IOINTCTL_INT2 (0x04)
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#define AM_HAL_IOS_IOINTCTL_INT3 (0x08)
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#define AM_HAL_IOS_IOINTCTL_INT4 (0x10)
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#define AM_HAL_IOS_IOINTCTL_INT5 (0x20)
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//! @}
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//*****************************************************************************
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//
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// External variable definitions
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! @brief LRAM pointer
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//!
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//! Pointer to the base of the IO Slave LRAM.
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//
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//*****************************************************************************
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extern volatile uint8_t * const am_hal_ios_pui8LRAM;
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//*****************************************************************************
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//
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//! @brief Configuration structure for the IO slave module.
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//!
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//! This structure may be used along with the am_hal_ios_config() function to
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//! select key parameters of the IO Slave module. See the descriptions of each
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//! parameter within this structure for more information on what they control.
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//
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//*****************************************************************************
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typedef struct
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{
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//
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//! Interface Selection
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//!
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//! This word selects the physical behavior of the IO Slave port. For SPI
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//! mode, this word should be the logical OR of one or more of the
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//! following:
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//!
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//! AM_HAL_IOS_USE_SPI
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//! AM_HAL_IOS_SPIMODE_0
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//! AM_HAL_IOS_SPIMODE_1
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//! AM_HAL_IOS_SPIMODE_2
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//! AM_HAL_IOS_SPIMODE_3
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//!
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//! For I2C mode, use the logical OR of one or more of these values instead
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//! (where n is the 7 or 10-bit I2C address to use):
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//!
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//! AM_HAL_IOS_USE_I2C
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//! AM_HAL_IOS_I2C_ADDRESS(n)
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//!
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//! Also, in any mode, you may OR in this value to reverse the order of
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//! incoming data bits.
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//!
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//! AM_HAL_IOS_LSB_FIRST
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//
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uint32_t ui32InterfaceSelect;
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//
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//! Read-Only section
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//!
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//! The IO Slave LRAM is split into three main sections. The first section
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//! is a "Direct Write" section, which may be accessed for reads or write
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//! either directly through the Apollo CPU, or over the SPI/I2C bus. The
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//! "Direct Write" section always begins at LRAM offset 0x0. At the end of
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//! the normal "Direct Write" space, there is a "Read Only" space, which is
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//! read/write accessible to the Apollo CPU, but read-only over the I2C/SPI
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//! Bus. This word selects the base address of this "Read Only" space.
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//!
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//! This value may be set to any multiple of 8 between 0x0 and 0x78,
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//! inclusive. For the configuration to be valid, \e ui32ROBase must also
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//! be less than or equal to \e ui32FIFOBase
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//!
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//! @note The address given here is in units of BYTES. Since the location
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//! of the "Read Only" space may only be set in 8-byte increments, this
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//! value must be a multiple of 8.
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//!
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//! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
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//! will shift right by 8 internally.
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//
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uint32_t ui32ROBase;
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//
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//! FIFO section
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//!
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//! After the "Direct Access" and "Read Only" sections is a section of LRAM
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//! allocated to a FIFO. This section is accessible by the Apollo CPU
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//! through the FIFO control registers, and accessible on the SPI/I2C bus
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//! through the 0x7F address. This word selects the base address of the
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//! FIFO space. The FIFO will extend from the address specified here to the
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//! address specified in \e ui32RAMBase.
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//!
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//! This value may be set to any multiple of 8 between 0x0 and 0x78,
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//! inclusive. For the configuration to be valid, \e ui32FIFOBase must also
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//! be greater than or equal to \e ui32ROBase.
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//!
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//! @note The address given here is in units of BYTES. Since the location
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//! of the "FIFO" space may only be set in 8-byte increments, this value
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//! must be a multiple of 8.
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//!
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//! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
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//! will shift right by 8 internally.
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//
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uint32_t ui32FIFOBase;
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//
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//! RAM section
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//!
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//! At the end of the IOS LRAM, the user may allocate a "RAM" space that
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//! can only be accessed by the Apollo CPU. This space will not interact
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//! with the SPI/I2C bus at all, and may be used as general-purpose memory.
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//! Unlike normal SRAM, this section of LRAM will retain its state through
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//! Deep Sleep, so it may be used as a data retention space for
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//! ultra-low-power applications.
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//!
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//! This value may be set to any multiple of 8 between 0x0 and 0x100,
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//! inclusive. For the configuration to be valid, \e ui32RAMBase must also
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//! be greater than or equal to \e ui32FIFOBase.
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//!
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//! @note The address given here is in units of BYTES. Since the location
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//! of the "FIFO" space may only be set in 8-byte increments, this value
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//! must be a multiple of 8.
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//!
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//! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
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//! will shift right by 8 internally.
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//
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uint32_t ui32RAMBase;
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//
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//! FIFO threshold
|
||
|
|
//!
|
||
|
|
//! The IO Slave module will trigger an interrupt when the number of
|
||
|
|
//! entries in the FIFO drops below this number of bytes.
|
||
|
|
//
|
||
|
|
uint32_t ui32FIFOThreshold;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Pointer to an SRAM
|
||
|
|
//
|
||
|
|
uint8_t *pui8SRAMBuffer;
|
||
|
|
uint32_t ui32SRAMBufferCap;
|
||
|
|
}
|
||
|
|
am_hal_ios_config_t;
|
||
|
|
|
||
|
|
typedef enum
|
||
|
|
{
|
||
|
|
// Request with arg
|
||
|
|
AM_HAL_IOS_REQ_HOST_INTSET = 0,
|
||
|
|
AM_HAL_IOS_REQ_HOST_INTCLR,
|
||
|
|
AM_HAL_IOS_REQ_HOST_INTGET,
|
||
|
|
AM_HAL_IOS_REQ_HOST_INTEN_GET,
|
||
|
|
AM_HAL_IOS_REQ_READ_GADATA,
|
||
|
|
AM_HAL_IOS_REQ_ARG_MAX,
|
||
|
|
|
||
|
|
// Request without arg
|
||
|
|
AM_HAL_IOS_REQ_READ_POLL = AM_HAL_IOS_REQ_ARG_MAX,
|
||
|
|
AM_HAL_IOS_REQ_FIFO_UPDATE_CTR,
|
||
|
|
AM_HAL_IOS_REQ_FIFO_BUF_CLR,
|
||
|
|
AM_HAL_IOS_REQ_MAX
|
||
|
|
} am_hal_ios_request_e;
|
||
|
|
|
||
|
|
typedef struct
|
||
|
|
{
|
||
|
|
uint8_t *pui8Data;
|
||
|
|
volatile uint32_t ui32WriteIndex;
|
||
|
|
volatile uint32_t ui32ReadIndex;
|
||
|
|
volatile uint32_t ui32Length;
|
||
|
|
uint32_t ui32Capacity;
|
||
|
|
}am_hal_ios_buffer_t;
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// External function definitions
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern uint32_t am_hal_ios_uninitialize(void *pHandle);
|
||
|
|
extern uint32_t am_hal_ios_initialize(uint32_t ui32Module, void **ppHandle);
|
||
|
|
extern uint32_t am_hal_ios_enable(void *pHandle);
|
||
|
|
extern uint32_t am_hal_ios_disable(void *pHandle);
|
||
|
|
|
||
|
|
// the following interrupts go back to the NVIC
|
||
|
|
extern uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig);
|
||
|
|
extern uint32_t am_hal_ios_interrupt_enable(void *pHandle, uint32_t ui32IntMask);
|
||
|
|
extern uint32_t am_hal_ios_interrupt_disable(void *pHandle, uint32_t ui32IntMask);
|
||
|
|
extern uint32_t am_hal_ios_interrupt_clear(void *pHandle, uint32_t ui32IntMask);
|
||
|
|
extern uint32_t am_hal_ios_interrupt_status_get(void *pHandle, bool bEnabledOnly, uint32_t *pui32IntStatus);
|
||
|
|
extern uint32_t am_hal_ios_interrupt_service(void *pHandle, uint32_t ui32IntMask);
|
||
|
|
// Returns the number of bytes actually written
|
||
|
|
extern uint32_t am_hal_ios_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32WrittenBytes);
|
||
|
|
extern uint32_t am_hal_ios_fifo_space_used(void *pHandle, uint32_t *pui32UsedSpace);
|
||
|
|
extern uint32_t am_hal_ios_fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace);
|
||
|
|
|
||
|
|
extern uint32_t am_hal_ios_power_ctrl(void *pHandle, am_hal_sysctrl_power_state_e ePowerState, bool bRetainState);
|
||
|
|
extern uint32_t am_hal_ios_control(void *pHandle, am_hal_ios_request_e eReq, void *pArgs);
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif // AM_HAL_IOS_H
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// End Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|