331 lines
15 KiB
C
331 lines
15 KiB
C
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//*****************************************************************************
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//
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// am_reg_rtc.h
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//! @file
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//!
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//! @brief Register macros for the RTC module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_RTC_H
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#define AM_REG_RTC_H
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//*****************************************************************************
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//
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// RTC
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_RTC_NUM_MODULES 1
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#define AM_REG_RTCn(n) \
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(REG_RTC_BASEADDR + 0x00000000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_RTC_CTRLOW_O 0x00000000
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#define AM_REG_RTC_CTRUP_O 0x00000004
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#define AM_REG_RTC_ALMLOW_O 0x00000008
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#define AM_REG_RTC_ALMUP_O 0x0000000C
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#define AM_REG_RTC_RTCCTL_O 0x00000010
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#define AM_REG_RTC_INTEN_O 0x000000C0
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#define AM_REG_RTC_INTSTAT_O 0x000000C4
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#define AM_REG_RTC_INTCLR_O 0x000000C8
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#define AM_REG_RTC_INTSET_O 0x000000CC
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//*****************************************************************************
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//
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// RTC_INTEN - CLK_GEN Interrupt Register: Enable
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_RTC_INTEN_ALM_S 3
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#define AM_REG_RTC_INTEN_ALM_M 0x00000008
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#define AM_REG_RTC_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_RTC_INTEN_OF_S 2
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#define AM_REG_RTC_INTEN_OF_M 0x00000004
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#define AM_REG_RTC_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_RTC_INTEN_ACC_S 1
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#define AM_REG_RTC_INTEN_ACC_M 0x00000002
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#define AM_REG_RTC_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_RTC_INTEN_ACF_S 0
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#define AM_REG_RTC_INTEN_ACF_M 0x00000001
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#define AM_REG_RTC_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RTC_INTSTAT - CLK_GEN Interrupt Register: Status
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_RTC_INTSTAT_ALM_S 3
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#define AM_REG_RTC_INTSTAT_ALM_M 0x00000008
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#define AM_REG_RTC_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_RTC_INTSTAT_OF_S 2
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#define AM_REG_RTC_INTSTAT_OF_M 0x00000004
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#define AM_REG_RTC_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_RTC_INTSTAT_ACC_S 1
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#define AM_REG_RTC_INTSTAT_ACC_M 0x00000002
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#define AM_REG_RTC_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_RTC_INTSTAT_ACF_S 0
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#define AM_REG_RTC_INTSTAT_ACF_M 0x00000001
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#define AM_REG_RTC_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RTC_INTCLR - CLK_GEN Interrupt Register: Clear
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_RTC_INTCLR_ALM_S 3
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#define AM_REG_RTC_INTCLR_ALM_M 0x00000008
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#define AM_REG_RTC_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_RTC_INTCLR_OF_S 2
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#define AM_REG_RTC_INTCLR_OF_M 0x00000004
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#define AM_REG_RTC_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_RTC_INTCLR_ACC_S 1
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#define AM_REG_RTC_INTCLR_ACC_M 0x00000002
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#define AM_REG_RTC_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_RTC_INTCLR_ACF_S 0
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#define AM_REG_RTC_INTCLR_ACF_M 0x00000001
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#define AM_REG_RTC_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RTC_INTSET - CLK_GEN Interrupt Register: Set
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_RTC_INTSET_ALM_S 3
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#define AM_REG_RTC_INTSET_ALM_M 0x00000008
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#define AM_REG_RTC_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_RTC_INTSET_OF_S 2
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#define AM_REG_RTC_INTSET_OF_M 0x00000004
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#define AM_REG_RTC_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_RTC_INTSET_ACC_S 1
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#define AM_REG_RTC_INTSET_ACC_M 0x00000002
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#define AM_REG_RTC_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_RTC_INTSET_ACF_S 0
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#define AM_REG_RTC_INTSET_ACF_M 0x00000001
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#define AM_REG_RTC_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RTC_CTRLOW - RTC Counters Lower
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//
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//*****************************************************************************
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// Hours Counter
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#define AM_REG_RTC_CTRLOW_CTRHR_S 24
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#define AM_REG_RTC_CTRLOW_CTRHR_M 0x3F000000
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#define AM_REG_RTC_CTRLOW_CTRHR(n) (((uint32_t)(n) << 24) & 0x3F000000)
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// Minutes Counter
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#define AM_REG_RTC_CTRLOW_CTRMIN_S 16
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#define AM_REG_RTC_CTRLOW_CTRMIN_M 0x007F0000
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#define AM_REG_RTC_CTRLOW_CTRMIN(n) (((uint32_t)(n) << 16) & 0x007F0000)
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// Seconds Counter
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#define AM_REG_RTC_CTRLOW_CTRSEC_S 8
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#define AM_REG_RTC_CTRLOW_CTRSEC_M 0x00007F00
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#define AM_REG_RTC_CTRLOW_CTRSEC(n) (((uint32_t)(n) << 8) & 0x00007F00)
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// 100ths of a second Counter
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#define AM_REG_RTC_CTRLOW_CTR100_S 0
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#define AM_REG_RTC_CTRLOW_CTR100_M 0x000000FF
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#define AM_REG_RTC_CTRLOW_CTR100(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// RTC_CTRUP - RTC Counters Upper
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//
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//*****************************************************************************
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// Counter read error status
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#define AM_REG_RTC_CTRUP_CTERR_S 31
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#define AM_REG_RTC_CTRUP_CTERR_M 0x80000000
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#define AM_REG_RTC_CTRUP_CTERR(n) (((uint32_t)(n) << 31) & 0x80000000)
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#define AM_REG_RTC_CTRUP_CTERR_NOERR 0x00000000
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#define AM_REG_RTC_CTRUP_CTERR_RDERR 0x80000000
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// Century enable
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#define AM_REG_RTC_CTRUP_CEB_S 28
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#define AM_REG_RTC_CTRUP_CEB_M 0x10000000
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#define AM_REG_RTC_CTRUP_CEB(n) (((uint32_t)(n) << 28) & 0x10000000)
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#define AM_REG_RTC_CTRUP_CEB_DIS 0x00000000
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#define AM_REG_RTC_CTRUP_CEB_EN 0x10000000
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// Century
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#define AM_REG_RTC_CTRUP_CB_S 27
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#define AM_REG_RTC_CTRUP_CB_M 0x08000000
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#define AM_REG_RTC_CTRUP_CB(n) (((uint32_t)(n) << 27) & 0x08000000)
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#define AM_REG_RTC_CTRUP_CB_2000 0x00000000
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#define AM_REG_RTC_CTRUP_CB_1900_2100 0x08000000
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// Weekdays Counter
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#define AM_REG_RTC_CTRUP_CTRWKDY_S 24
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#define AM_REG_RTC_CTRUP_CTRWKDY_M 0x07000000
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#define AM_REG_RTC_CTRUP_CTRWKDY(n) (((uint32_t)(n) << 24) & 0x07000000)
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// Years Counter
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#define AM_REG_RTC_CTRUP_CTRYR_S 16
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#define AM_REG_RTC_CTRUP_CTRYR_M 0x00FF0000
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#define AM_REG_RTC_CTRUP_CTRYR(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Months Counter
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#define AM_REG_RTC_CTRUP_CTRMO_S 8
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#define AM_REG_RTC_CTRUP_CTRMO_M 0x00001F00
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#define AM_REG_RTC_CTRUP_CTRMO(n) (((uint32_t)(n) << 8) & 0x00001F00)
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// Date Counter
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#define AM_REG_RTC_CTRUP_CTRDATE_S 0
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#define AM_REG_RTC_CTRUP_CTRDATE_M 0x0000003F
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#define AM_REG_RTC_CTRUP_CTRDATE(n) (((uint32_t)(n) << 0) & 0x0000003F)
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//*****************************************************************************
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//
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// RTC_ALMLOW - RTC Alarms Lower
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//
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//*****************************************************************************
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// Hours Alarm
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#define AM_REG_RTC_ALMLOW_ALMHR_S 24
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#define AM_REG_RTC_ALMLOW_ALMHR_M 0x3F000000
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#define AM_REG_RTC_ALMLOW_ALMHR(n) (((uint32_t)(n) << 24) & 0x3F000000)
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// Minutes Alarm
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#define AM_REG_RTC_ALMLOW_ALMMIN_S 16
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#define AM_REG_RTC_ALMLOW_ALMMIN_M 0x007F0000
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#define AM_REG_RTC_ALMLOW_ALMMIN(n) (((uint32_t)(n) << 16) & 0x007F0000)
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// Seconds Alarm
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#define AM_REG_RTC_ALMLOW_ALMSEC_S 8
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#define AM_REG_RTC_ALMLOW_ALMSEC_M 0x00007F00
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#define AM_REG_RTC_ALMLOW_ALMSEC(n) (((uint32_t)(n) << 8) & 0x00007F00)
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// 100ths of a second Alarm
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#define AM_REG_RTC_ALMLOW_ALM100_S 0
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#define AM_REG_RTC_ALMLOW_ALM100_M 0x000000FF
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#define AM_REG_RTC_ALMLOW_ALM100(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// RTC_ALMUP - RTC Alarms Upper
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//
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//*****************************************************************************
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// Weekdays Alarm
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#define AM_REG_RTC_ALMUP_ALMWKDY_S 16
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#define AM_REG_RTC_ALMUP_ALMWKDY_M 0x00070000
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#define AM_REG_RTC_ALMUP_ALMWKDY(n) (((uint32_t)(n) << 16) & 0x00070000)
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// Months Alarm
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#define AM_REG_RTC_ALMUP_ALMMO_S 8
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#define AM_REG_RTC_ALMUP_ALMMO_M 0x00001F00
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#define AM_REG_RTC_ALMUP_ALMMO(n) (((uint32_t)(n) << 8) & 0x00001F00)
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// Date Alarm
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#define AM_REG_RTC_ALMUP_ALMDATE_S 0
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#define AM_REG_RTC_ALMUP_ALMDATE_M 0x0000003F
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#define AM_REG_RTC_ALMUP_ALMDATE(n) (((uint32_t)(n) << 0) & 0x0000003F)
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//*****************************************************************************
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//
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// RTC_RTCCTL - RTC Control Register
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//
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//*****************************************************************************
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// Hours Counter mode
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#define AM_REG_RTC_RTCCTL_HR1224_S 5
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#define AM_REG_RTC_RTCCTL_HR1224_M 0x00000020
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#define AM_REG_RTC_RTCCTL_HR1224(n) (((uint32_t)(n) << 5) & 0x00000020)
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#define AM_REG_RTC_RTCCTL_HR1224_24HR 0x00000000
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#define AM_REG_RTC_RTCCTL_HR1224_12HR 0x00000020
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// RTC input clock control
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#define AM_REG_RTC_RTCCTL_RSTOP_S 4
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#define AM_REG_RTC_RTCCTL_RSTOP_M 0x00000010
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#define AM_REG_RTC_RTCCTL_RSTOP(n) (((uint32_t)(n) << 4) & 0x00000010)
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#define AM_REG_RTC_RTCCTL_RSTOP_RUN 0x00000000
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#define AM_REG_RTC_RTCCTL_RSTOP_STOP 0x00000010
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// Alarm repeat interval
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#define AM_REG_RTC_RTCCTL_RPT_S 1
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#define AM_REG_RTC_RTCCTL_RPT_M 0x0000000E
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#define AM_REG_RTC_RTCCTL_RPT(n) (((uint32_t)(n) << 1) & 0x0000000E)
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#define AM_REG_RTC_RTCCTL_RPT_DIS 0x00000000
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#define AM_REG_RTC_RTCCTL_RPT_YEAR 0x00000002
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#define AM_REG_RTC_RTCCTL_RPT_MONTH 0x00000004
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#define AM_REG_RTC_RTCCTL_RPT_WEEK 0x00000006
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#define AM_REG_RTC_RTCCTL_RPT_DAY 0x00000008
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#define AM_REG_RTC_RTCCTL_RPT_HR 0x0000000A
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#define AM_REG_RTC_RTCCTL_RPT_MIN 0x0000000C
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#define AM_REG_RTC_RTCCTL_RPT_SEC 0x0000000E
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// Counter write control
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#define AM_REG_RTC_RTCCTL_WRTC_S 0
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#define AM_REG_RTC_RTCCTL_WRTC_M 0x00000001
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#define AM_REG_RTC_RTCCTL_WRTC(n) (((uint32_t)(n) << 0) & 0x00000001)
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#define AM_REG_RTC_RTCCTL_WRTC_DIS 0x00000000
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#define AM_REG_RTC_RTCCTL_WRTC_EN 0x00000001
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#endif // AM_REG_RTC_H
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