1955 lines
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1955 lines
81 KiB
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<title>AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview</title>
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<td style="padding-left: 0.5em;">
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<div id="projectname">Apollo Register Documentation  <span id="projectnumber">v2.4.2</span></div>
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</div>
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</li>
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<!-- window showing the filter options -->
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<div class="header">
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<div class="headertitle">
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<div class="title">NVIC - Nested Vectored Interrupt Controller</div>
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</div>
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</div>
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<!--header-->
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<body>
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<br>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 class="panel-title"> NVIC Register Index</h3>
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</div>
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<div class="panel-body">
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<table>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E100:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ISER0" target="_self">ISER0 - Interrupt Set-Enable Register 0</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E180:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ICER0" target="_self">ICER0 - Interrupt Clear-Enable Register 0</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E200:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ISPR0" target="_self">ISPR0 - Interrupt Set-Pending Register 0</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E280:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#ICPR0" target="_self">ICPR0 - Interrupt Clear-Pending Register 0</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E300:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IABR0" target="_self">IABR0 - Interrupt Active Bit Register 0</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E400:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR0" target="_self">IPR0 - Interrupt Priority Register 0</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E404:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR1" target="_self">IPR1 - Interrupt Priority Register 1</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E408:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR2" target="_self">IPR2 - Interrupt Priority Register 2</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E40C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR3" target="_self">IPR3 - Interrupt Priority Register 3</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E410:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR4" target="_self">IPR4 - Interrupt Priority Register 4</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E414:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR5" target="_self">IPR5 - Interrupt Priority Register 5</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E418:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR6" target="_self">IPR6 - Interrupt Priority Register 6</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E41C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IPR7" target="_self">IPR7 - Interrupt Priority Register 7</a>
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</td>
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</tr>
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</table>
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</div>
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</div>
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||
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||
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<div class="panel panel-default">
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<div class="panel-heading">
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||
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<h3 id="ISER0" class="panel-title">ISER0 - Interrupt Set-Enable Register 0</h3>
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</div>
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<div class="panel-body">
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<h3>Address:</h3>
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<table style="margin:10px">
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">Instance 0 Address:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0xE000E100</span>
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</td>
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</tr>
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</table>
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<h3>Description:</h3>
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<p>Interrupt Set-Enable Register 0</p>
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<h3>Example Macro Usage:</h3>
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<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
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// All macro-based register writes follow the same basic format. For
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// single-instance modules, you may use the simpler AM_REG macro. For
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// multi-instance macros, you will need to specify the instance number using
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// the AM_REGn macro format.
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//
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// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
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// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
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//
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// For registers that do not have specific enumeration values, you may use this alternate format instead.
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//
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// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
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//
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// For example, the following three lines of code are equivalent methods of
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// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
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//</span>
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AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
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AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
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AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
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<h3>Register Fields:</h3>
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<table style="margin:10px" class="table table-bordered table-condensed">
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<thead>
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<tr>
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<th>31</th>
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<th>30</th>
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<th>29</th>
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<th>28</th>
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<th>27</th>
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<th>26</th>
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<th>25</th>
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<th>24</th>
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<th>23</th>
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<th>22</th>
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<th>21</th>
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<th>20</th>
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<th>19</th>
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<th>18</th>
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<th>17</th>
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<th>16</th>
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<th>15</th>
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<th>14</th>
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<th>13</th>
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<th>12</th>
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<th>11</th>
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<th>10</th>
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<th>9</th>
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<th>8</th>
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<th>7</th>
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<th>6</th>
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<th>5</th>
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<th>4</th>
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<th>3</th>
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<th>2</th>
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<th>1</th>
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<th>0</th>
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</tr>
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||
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</thead>
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<tbody>
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<tr>
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<td align="center" colspan="32">BITS
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<br>0x0</td>
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</tr>
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||
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</tbody>
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||
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</table>
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||
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<br>
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||
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||
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<table style="margin:10px" class="table table-bordered table-condensed">
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<thead>
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<tr>
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<th>Bits</th>
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<th>Name</th>
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<th>RW</th>
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<th>Description</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>31:0</td>
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<td>BITS</td>
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<td>RW</td>
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<td>NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.<br><br>
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</td>
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||
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</tr>
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||
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||
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</tbody>
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||
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</table>
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||
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<br>
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||
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</div>
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||
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</div>
|
||
|
|
|
||
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|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="ICER0" class="panel-title">ICER0 - Interrupt Clear-Enable Register 0</h3>
|
||
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</div>
|
||
|
|
<div class="panel-body">
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||
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<h3>Address:</h3>
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||
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|
<table style="margin:10px">
|
||
|
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<tr id="row_0_0_">
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||
|
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<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E180</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
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<p>Interrupt Clear-Enable Register 0</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">BITS
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>BITS</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="ISPR0" class="panel-title">ISPR0 - Interrupt Set-Pending Register 0</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E200</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Set-Pending Register 0</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">BITS
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>BITS</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="ICPR0" class="panel-title">ICPR0 - Interrupt Clear-Pending Register 0</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E280</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Clear-Pending Register 0</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">BITS
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>BITS</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IABR0" class="panel-title">IABR0 - Interrupt Active Bit Register 0</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E300</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Active Bit Register 0</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">BITS
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>BITS</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR0" class="panel-title">IPR0 - Interrupt Priority Register 0</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E400</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 0</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 3.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 2.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 1.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 0.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR1" class="panel-title">IPR1 - Interrupt Priority Register 1</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E404</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 1</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 7.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 6.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 5.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 4.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR2" class="panel-title">IPR2 - Interrupt Priority Register 2</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E408</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 2</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 11.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 10.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 9.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 8.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR3" class="panel-title">IPR3 - Interrupt Priority Register 3</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E40C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 3</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 15.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 14.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 13.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 12.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR4" class="panel-title">IPR4 - Interrupt Priority Register 4</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E410</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 4</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 19.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 18.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 17.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 16.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR5" class="panel-title">IPR5 - Interrupt Priority Register 5</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E414</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 5</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 23.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 22.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 21.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 20.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR6" class="panel-title">IPR6 - Interrupt Priority Register 6</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E418</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 6</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 27.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 26.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 25.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 24.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IPR7" class="panel-title">IPR7 - Interrupt Priority Register 7</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0xE000E41C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Interrupt Priority Register 7</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// All macro-based register writes follow the same basic format. For
|
||
|
|
// single-instance modules, you may use the simpler AM_REG macro. For
|
||
|
|
// multi-instance macros, you will need to specify the instance number using
|
||
|
|
// the AM_REGn macro format.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
|
||
|
|
//
|
||
|
|
// For registers that do not have specific enumeration values, you may use this alternate format instead.
|
||
|
|
//
|
||
|
|
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
|
||
|
|
//
|
||
|
|
// For example, the following three lines of code are equivalent methods of
|
||
|
|
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
|
||
|
|
//</span>
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
|
||
|
|
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);</pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">PRI_N3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">PRI_N0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>PRI_N3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 31.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>PRI_N2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 30.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>PRI_N1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 29.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>PRI_N0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Priority assignment for interrupt vector 28.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
</body>
|
||
|
|
|
||
|
|
<hr size="1">
|
||
|
|
<body>
|
||
|
|
<div id="footer" align="right">
|
||
|
|
<small>
|
||
|
|
AmbiqSuite Register Documentation
|
||
|
|
<a href="http://www.ambiqmicro.com">
|
||
|
|
<img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>   Copyright © 2014  <br />
|
||
|
|
This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.  <br/>
|
||
|
|
</small>
|
||
|
|
</div>
|
||
|
|
</body>
|
||
|
|
</html>
|
||
|
|
|