3035 lines
127 KiB
HTML
3035 lines
127 KiB
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<title>AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview</title>
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<img alt="Logo" src="../resources/am_logo.png" />
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</td>
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<td style="padding-left: 0.5em;">
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<div id="projectname">Apollo Register Documentation  <span id="projectnumber">v2.4.2</span></div>
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</td>
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</tr>
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<div class="header">
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<div class="headertitle">
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<div class="title">IOSLAVE - I2C/SPI Slave</div>
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</div>
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</div>
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<body>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 class="panel-title"> IOSLAVE Register Index</h3>
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</div>
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<div class="panel-body">
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<table>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000100:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOPTR" target="_self">FIFOPTR - Current FIFO Pointer</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000104:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOCFG" target="_self">FIFOCFG - FIFO Configuration</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000108:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOTHR" target="_self">FIFOTHR - FIFO Threshold Configuration</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000010C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FUPD" target="_self">FUPD - FIFO Update Status</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000110:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOCTR" target="_self">FIFOCTR - Overall FIFO Counter</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000114:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#FIFOINC" target="_self">FIFOINC - Overall FIFO Counter Increment</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000118:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CFG" target="_self">CFG - I/O Slave Configuration</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000011C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#PRENC" target="_self">PRENC - I/O Slave Interrupt Priority Encode</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000120:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#IOINTCTL" target="_self">IOINTCTL - I/O Interrupt Control</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000124:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#GENADD" target="_self">GENADD - General Address Data</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000200:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTEN" target="_self">INTEN - IO Slave Interrupts: Enable</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000204:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTSTAT" target="_self">INTSTAT - IO Slave Interrupts: Status</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000208:</span>
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</td>
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTCLR" target="_self">INTCLR - IO Slave Interrupts: Clear</a>
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||
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</td>
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||
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x0000020C:</span>
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||
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</td>
|
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#INTSET" target="_self">INTSET - IO Slave Interrupts: Set</a>
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||
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</td>
|
||
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</tr>
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||
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x00000210:</span>
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||
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</td>
|
||
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#REGACCINTEN" target="_self">REGACCINTEN - Register Access Interrupts: Enable</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x00000214:</span>
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||
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</td>
|
||
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#REGACCINTSTAT" target="_self">REGACCINTSTAT - Register Access Interrupts: Status</a>
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</td>
|
||
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x00000218:</span>
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||
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</td>
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||
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#REGACCINTCLR" target="_self">REGACCINTCLR - Register Access Interrupts: Clear</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x0000021C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#REGACCINTSET" target="_self">REGACCINTSET - Register Access Interrupts: Set</a>
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</td>
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</tr>
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</table>
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</div>
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</div>
|
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 id="FIFOPTR" class="panel-title">FIFOPTR - Current FIFO Pointer</h3>
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||
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</div>
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<div class="panel-body">
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<h3>Address:</h3>
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<table style="margin:10px">
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">Instance 0 Address:</span>
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</td>
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x50000100</span>
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||
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</td>
|
||
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</tr>
|
||
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</table>
|
||
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<h3>Description:</h3>
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||
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<p>Current FIFO Pointer</p>
|
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<h3>Example Macro Usage:</h3>
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||
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<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
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// Register access is all performed through the standard CMSIS structure-based
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// interface. This includes module-level structure definitions with members and
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// bitfields corresponding to the physical registers and bitfields within each
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// module. In addition, Ambiq has provided instance-level macros for modules
|
||
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// that have more than one physical instance and a generic AM_REGVAL() macro
|
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// for directly accessing memory by address.
|
||
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//
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||
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// The following examples show how to use these structures and macros:
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||
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// Setting the ADC configuration register...</span>
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||
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AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
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||
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ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
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||
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ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
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||
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||
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<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
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||
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ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
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ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
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<h3>Register Fields:</h3>
|
||
|
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<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
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<thead>
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||
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<tr>
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||
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<th>31</th>
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<th>30</th>
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<th>29</th>
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<th>28</th>
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<th>27</th>
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<th>26</th>
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<th>25</th>
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<th>24</th>
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<th>23</th>
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<th>22</th>
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<th>21</th>
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<th>20</th>
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<th>19</th>
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||
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<th>18</th>
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||
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<th>17</th>
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||
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<th>16</th>
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||
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<th>15</th>
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||
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<th>14</th>
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||
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<th>13</th>
|
||
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<th>12</th>
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||
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<th>11</th>
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||
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<th>10</th>
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<th>9</th>
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||
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<th>8</th>
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||
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<th>7</th>
|
||
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<th>6</th>
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||
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<th>5</th>
|
||
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<th>4</th>
|
||
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<th>3</th>
|
||
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<th>2</th>
|
||
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<th>1</th>
|
||
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<th>0</th>
|
||
|
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</tr>
|
||
|
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</thead>
|
||
|
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<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="16">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">FIFOSIZ
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">FIFOPTR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:16</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>FIFOSIZ</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>The number of bytes currently in the hardware FIFO.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>FIFOPTR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Current FIFO pointer.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="FIFOCFG" class="panel-title">FIFOCFG - FIFO Configuration</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000104</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>FIFO Configuration</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="2">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">ROBASE
|
||
|
|
<br>0x20</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">FIFOMAX
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="5">FIFOBASE
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:30</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>29:24</td>
|
||
|
|
<td>ROBASE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:16</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:14</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>13:8</td>
|
||
|
|
<td>FIFOMAX</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:5</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4:0</td>
|
||
|
|
<td>FIFOBASE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1).<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="FIFOTHR" class="panel-title">FIFOTHR - FIFO Threshold Configuration</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000108</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>FIFO Threshold Configuration</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="24">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">FIFOTHR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:8</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>FIFOTHR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO size interrupt threshold.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="FUPD" class="panel-title">FUPD - FIFO Update Status</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5000010C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>FIFO Update Status</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="30">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">IOREAD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOUPD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>IOREAD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>This bitfield indicates an IO read is active.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>FIFOUPD</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit indicates that a FIFO update is underway.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="FIFOCTR" class="panel-title">FIFOCTR - Overall FIFO Counter</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000110</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Overall FIFO Counter</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="22">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="10">FIFOCTR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9:0</td>
|
||
|
|
<td>FIFOCTR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Virtual FIFO byte count<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="FIFOINC" class="panel-title">FIFOINC - Overall FIFO Counter Increment</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000114</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Overall FIFO Counter Increment</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="22">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="10">FIFOINC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9:0</td>
|
||
|
|
<td>FIFOINC</td>
|
||
|
|
<td>WO</td>
|
||
|
|
<td>Increment the Overall FIFO Counter by this value on a write<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="CFG" class="panel-title">CFG - I/O Slave Configuration</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000118</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>I/O Slave Configuration</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="1">IFCEN
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="11">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="12">I2CADDR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">STARTRD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">LSB
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SPOL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">IFCSEL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31</td>
|
||
|
|
<td>IFCEN</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>IOSLAVE interface enable.<br><br>
|
||
|
|
DIS = 0x0 - Disable the IOSLAVE<br>
|
||
|
|
EN = 0x1 - Enable the IOSLAVE</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>30:20</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>19:8</td>
|
||
|
|
<td>I2CADDR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>7-bit or 10-bit I2C device address.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:5</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>STARTRD</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit holds the cycle to initiate an I/O RAM read.<br><br>
|
||
|
|
LATE = 0x0 - Initiate I/O RAM read late in each transferred byte.<br>
|
||
|
|
EARLY = 0x1 - Initiate I/O RAM read early in each transferred byte.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>LSB</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit selects the transfer bit ordering.<br><br>
|
||
|
|
MSB_FIRST = 0x0 - Data is assumed to be sent and received with MSB first.<br>
|
||
|
|
LSB_FIRST = 0x1 - Data is assumed to be sent and received with LSB first.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>SPOL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit selects SPI polarity.<br><br>
|
||
|
|
SPI_MODES_0_3 = 0x0 - Polarity 0, handles SPI modes 0 and 3.<br>
|
||
|
|
SPI_MODES_1_2 = 0x1 - Polarity 1, handles SPI modes 1 and 2.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>IFCSEL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit selects the I/O interface.<br><br>
|
||
|
|
I2C = 0x0 - Selects I2C interface for the IO Slave.<br>
|
||
|
|
SPI = 0x1 - Selects SPI interface for the IO Slave.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="PRENC" class="panel-title">PRENC - I/O Slave Interrupt Priority Encode</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5000011C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>I/O Slave Interrupt Priority Encode</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="27">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="5">PRENC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:5</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4:0</td>
|
||
|
|
<td>PRENC</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>These bits hold the priority encode of the REGACC interrupts.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="IOINTCTL" class="panel-title">IOINTCTL - I/O Interrupt Control</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000120</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>I/O Interrupt Control</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="8">IOINTSET
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="7">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">IOINTCLR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">IOINT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">IOINTEN
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:24</td>
|
||
|
|
<td>IOINTSET</td>
|
||
|
|
<td>WO</td>
|
||
|
|
<td>These bits set the IOINT interrupts when written with a 1.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:17</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>16</td>
|
||
|
|
<td>IOINTCLR</td>
|
||
|
|
<td>WO</td>
|
||
|
|
<td>This bit clears all of the IOINT interrupts when written with a 1.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:8</td>
|
||
|
|
<td>IOINT</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>These bits read the IOINT interrupts.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>IOINTEN</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>These read-only bits indicate whether the IOINT interrupts are enabled.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="GENADD" class="panel-title">GENADD - General Address Data</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000124</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>General Address Data</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="24">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">GADATA
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:8</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>GADATA</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>The data supplied on the last General Address reference.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTEN" class="panel-title">INTEN - IO Slave Interrupts: Enable</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000200</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Set bits in this register to allow this module to generate the corresponding interrupt.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="22">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">IOINTW
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">GENAD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FRDERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FUNDFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FOVFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FSIZE
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9</td>
|
||
|
|
<td>XCMPWR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>8</td>
|
||
|
|
<td>XCMPWF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>XCMPRR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>XCMPRF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>IOINTW</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>IO Write interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>GENAD</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>I2C General Address interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FRDERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Read Error interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FUNDFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Underflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>FOVFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Overflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>FSIZE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Size interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTSTAT" class="panel-title">INTSTAT - IO Slave Interrupts: Status</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000204</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Read bits from this register to discover the cause of a recent interrupt.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="22">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">IOINTW
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">GENAD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FRDERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FUNDFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FOVFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FSIZE
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9</td>
|
||
|
|
<td>XCMPWR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>8</td>
|
||
|
|
<td>XCMPWF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>XCMPRR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>XCMPRF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>IOINTW</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>IO Write interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>GENAD</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>I2C General Address interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FRDERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Read Error interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FUNDFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Underflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>FOVFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Overflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>FSIZE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Size interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTCLR" class="panel-title">INTCLR - IO Slave Interrupts: Clear</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000208</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Write a 1 to a bit in this register to clear the interrupt status associated with that bit.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="22">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">IOINTW
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">GENAD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FRDERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FUNDFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FOVFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FSIZE
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9</td>
|
||
|
|
<td>XCMPWR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>8</td>
|
||
|
|
<td>XCMPWF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>XCMPRR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>XCMPRF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>IOINTW</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>IO Write interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>GENAD</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>I2C General Address interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FRDERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Read Error interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FUNDFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Underflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>FOVFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Overflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>FSIZE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Size interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTSET" class="panel-title">INTSET - IO Slave Interrupts: Set</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5000020C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="22">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPWF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">XCMPRF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">IOINTW
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">GENAD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FRDERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FUNDFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FOVFL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FSIZE
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9</td>
|
||
|
|
<td>XCMPWR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>8</td>
|
||
|
|
<td>XCMPWF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, write to FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>XCMPRR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from register space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>XCMPRF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Transfer complete interrupt, read from FIFO space.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>IOINTW</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>IO Write interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>GENAD</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>I2C General Address interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FRDERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Read Error interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FUNDFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Underflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>FOVFL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Overflow interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>FSIZE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO Size interrupt.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="REGACCINTEN" class="panel-title">REGACCINTEN - Register Access Interrupts: Enable</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000210</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Set bits in this register to allow this module to generate the corresponding interrupt.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">REGACC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>REGACC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Register access interrupts.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="REGACCINTSTAT" class="panel-title">REGACCINTSTAT - Register Access Interrupts: Status</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000214</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Read bits from this register to discover the cause of a recent interrupt.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">REGACC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>REGACC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Register access interrupts.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="REGACCINTCLR" class="panel-title">REGACCINTCLR - Register Access Interrupts: Clear</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50000218</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Write a 1 to a bit in this register to clear the interrupt status associated with that bit.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">REGACC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>REGACC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Register access interrupts.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="REGACCINTSET" class="panel-title">REGACCINTSET - Register Access Interrupts: Set</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5000021C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="32">REGACC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:0</td>
|
||
|
|
<td>REGACC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Register access interrupts.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
</body>
|
||
|
|
|
||
|
|
<hr size="1">
|
||
|
|
<body>
|
||
|
|
<div id="footer" align="right">
|
||
|
|
<small>
|
||
|
|
AmbiqSuite Register Documentation
|
||
|
|
<a href="http://www.ambiqmicro.com">
|
||
|
|
<img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>   Copyright © 2019  <br />
|
||
|
|
This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.  <br/>
|
||
|
|
</small>
|
||
|
|
</div>
|
||
|
|
</body>
|
||
|
|
</html>
|
||
|
|
|