5043 lines
230 KiB
HTML
5043 lines
230 KiB
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<head>
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<meta name="generator" content="AmbiqMicro" />
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<title>AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview</title>
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<link href="../resources/tabs.css" rel="stylesheet" type="text/css" />
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<link href="../resources/customdoxygen.css" rel="stylesheet" type="text/css" />
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</head>
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<body>
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<div id="top">
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<!-- do not remove this div, it is closed by doxygen! -->
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<div id="titlearea">
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<table cellspacing="0" cellpadding="0">
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<tbody>
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<tr style="height: 56px;">
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<td id="projectlogo">
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<img alt="Logo" src="../resources/am_logo.png" />
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</td>
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<td style="padding-left: 0.5em;">
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<div id="projectname">Apollo Register Documentation  <span id="projectnumber">v2.4.2</span></div>
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</td>
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</tr>
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</tbody>
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</table>
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</div>
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<!-- end header part -->
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<div id="navrow1" class="tabs">
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<ul class="tablist">
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<li class="current"><a href="../index.html"><span>Main Page</span></a>
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</li>
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</div>
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</li>
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</ul>
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</div>
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</div>
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<!-- top -->
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<!-- window showing the filter options -->
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<div class="header">
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<div class="headertitle">
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<div class="title">ADC - Analog Digital Converter Control</div>
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</div>
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</div>
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<!--header-->
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<body>
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<br>
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<div class="panel panel-default">
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<div class="panel-heading">
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<h3 class="panel-title"> ADC Register Index</h3>
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</div>
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<div class="panel-body">
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<table>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000000:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#CFG" target="_self">CFG - Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000004:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#STAT" target="_self">STAT - ADC Power Status</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000008:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SWT" target="_self">SWT - Software trigger</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000000C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL0CFG" target="_self">SL0CFG - Slot 0 Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000010:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL1CFG" target="_self">SL1CFG - Slot 1 Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000014:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL2CFG" target="_self">SL2CFG - Slot 2 Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000018:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL3CFG" target="_self">SL3CFG - Slot 3 Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000001C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL4CFG" target="_self">SL4CFG - Slot 4 Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000020:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL5CFG" target="_self">SL5CFG - Slot 5 Configuration Register</a>
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</td>
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x00000024:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL6CFG" target="_self">SL6CFG - Slot 6 Configuration Register</a>
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||
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</td>
|
||
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x00000028:</span>
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||
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<a class="el" href="#SL7CFG" target="_self">SL7CFG - Slot 7 Configuration Register</a>
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||
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</td>
|
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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<span class="h5">0x0000002C:</span>
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<a class="el" href="#WULIM" target="_self">WULIM - Window Comparator Upper Limits Register</a>
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||
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</td>
|
||
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</tr>
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<tr id="row_0_0_">
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x00000030:</span>
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||
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</td>
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<td class="entry">
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<span style="width:32px;display:inline-block;"> </span>
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||
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<a class="el" href="#WLLIM" target="_self">WLLIM - Window Comparator Lower Limits Register</a>
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||
|
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</td>
|
||
|
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</tr>
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||
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||
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<tr id="row_0_0_">
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
|
||
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<span class="h5">0x00000034:</span>
|
||
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</td>
|
||
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
|
||
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<a class="el" href="#SCWLIM" target="_self">SCWLIM - Scale Window Comparator Limits</a>
|
||
|
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</td>
|
||
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</tr>
|
||
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||
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<tr id="row_0_0_">
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
|
||
|
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<span class="h5">0x00000038:</span>
|
||
|
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</td>
|
||
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
|
||
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<a class="el" href="#FIFO" target="_self">FIFO - FIFO Data and Valid Count Register</a>
|
||
|
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</td>
|
||
|
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</tr>
|
||
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||
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<tr id="row_0_0_">
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
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||
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<span class="h5">0x0000003C:</span>
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||
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</td>
|
||
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
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||
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<a class="el" href="#FIFOPR" target="_self">FIFOPR - FIFO Data and Valid Count Register</a>
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||
|
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</td>
|
||
|
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</tr>
|
||
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||
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<tr id="row_0_0_">
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||
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<td class="entry">
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||
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<span style="width:32px;display:inline-block;"> </span>
|
||
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<span class="h5">0x00000200:</span>
|
||
|
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</td>
|
||
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
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||
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<a class="el" href="#INTEN" target="_self">INTEN - ADC Interrupt registers: Enable</a>
|
||
|
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</td>
|
||
|
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</tr>
|
||
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||
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<tr id="row_0_0_">
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
|
||
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<span class="h5">0x00000204:</span>
|
||
|
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</td>
|
||
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
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||
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<a class="el" href="#INTSTAT" target="_self">INTSTAT - ADC Interrupt registers: Status</a>
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||
|
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</td>
|
||
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</tr>
|
||
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||
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<tr id="row_0_0_">
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x00000208:</span>
|
||
|
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</td>
|
||
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<td class="entry">
|
||
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<span style="width:32px;display:inline-block;"> </span>
|
||
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<a class="el" href="#INTCLR" target="_self">INTCLR - ADC Interrupt registers: Clear</a>
|
||
|
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</td>
|
||
|
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</tr>
|
||
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|
||
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<tr id="row_0_0_">
|
||
|
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<td class="entry">
|
||
|
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<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x0000020C:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
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<span style="width:32px;display:inline-block;"> </span>
|
||
|
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<a class="el" href="#INTSET" target="_self">INTSET - ADC Interrupt registers: Set</a>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
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<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x00000240:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<a class="el" href="#DMATRIGEN" target="_self">DMATRIGEN - DMA Trigger Enable Register</a>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x00000244:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<a class="el" href="#DMATRIGSTAT" target="_self">DMATRIGSTAT - DMA Trigger Status Register</a>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x00000280:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<a class="el" href="#DMACFG" target="_self">DMACFG - DMA Configuration Register</a>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x00000288:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<a class="el" href="#DMATOTCOUNT" target="_self">DMATOTCOUNT - DMA Total Transfer Count</a>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
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|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x0000028C:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<a class="el" href="#DMATARGADDR" target="_self">DMATARGADDR - DMA Target Address Register</a>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
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<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x00000290:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<a class="el" href="#DMASTAT" target="_self">DMASTAT - DMA Status Register</a>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="CFG" class="panel-title">CFG - Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010000</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>The ADC Configuration Register contains the software control for selecting the clock frequency used for the SAR conversions, the trigger polarity, the trigger select, the reference voltage select, the low power mode, the operating mode (single scan per trigger vs. repeating mode) and ADC enable.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">CLKSEL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">TRIGPOL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">TRIGSEL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DFIFORDEN
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">REFSEL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">CKMODE
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">LPMODE
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">RPTEN
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">ADCEN
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:26</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>25:24</td>
|
||
|
|
<td>CLKSEL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the source and frequency for the ADC clock. All values not enumerated below are undefined.<br><br>
|
||
|
|
OFF = 0x0 - Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing.<br>
|
||
|
|
HFRC = 0x1 - HFRC Core Clock divided by (CORESEL+1)<br>
|
||
|
|
HFRC_DIV2 = 0x2 - HFRC Core Clock / 2 further divided by (CORESEL+1)</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:20</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>19</td>
|
||
|
|
<td>TRIGPOL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit selects the ADC trigger polarity for external off chip triggers.<br><br>
|
||
|
|
RISING_EDGE = 0x0 - Trigger on rising edge.<br>
|
||
|
|
FALLING_EDGE = 0x1 - Trigger on falling edge.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>18:16</td>
|
||
|
|
<td>TRIGSEL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the ADC trigger source.<br><br>
|
||
|
|
EXT0 = 0x0 - Off chip External Trigger0 (ADC_ET0)<br>
|
||
|
|
EXT1 = 0x1 - Off chip External Trigger1 (ADC_ET1)<br>
|
||
|
|
EXT2 = 0x2 - Off chip External Trigger2 (ADC_ET2)<br>
|
||
|
|
EXT3 = 0x3 - Off chip External Trigger3 (ADC_ET3)<br>
|
||
|
|
VCOMP = 0x4 - Voltage Comparator Output<br>
|
||
|
|
SWT = 0x7 - Software Trigger</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:13</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>12</td>
|
||
|
|
<td>DFIFORDEN</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register.<br><br>
|
||
|
|
DIS = 0x0 - Destructive Reads are prevented. Reads to the FIFOPR register will not POP an entry off the FIFO.<br>
|
||
|
|
EN = 0x1 - Reads to the FIFOPR registger will automatically pop an entry off the FIFO.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9:8</td>
|
||
|
|
<td>REFSEL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the ADC reference voltage.<br><br>
|
||
|
|
INT2P0 = 0x0 - Internal 2.0V Bandgap Reference Voltage<br>
|
||
|
|
INT1P5 = 0x1 - Internal 1.5V Bandgap Reference Voltage<br>
|
||
|
|
EXT2P0 = 0x2 - Off Chip 2.0V Reference<br>
|
||
|
|
EXT1P5 = 0x3 - Off Chip 1.5V Reference</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:5</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>CKMODE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Clock mode register<br><br>
|
||
|
|
LPCKMODE = 0x0 - Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC.<br>
|
||
|
|
LLCKMODE = 0x1 - Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>LPMODE</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select power mode to enter between active scans.<br><br>
|
||
|
|
MODE0 = 0x0 - Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection.<br>
|
||
|
|
MODE1 = 0x1 - Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>RPTEN</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables Repeating Scan Mode.<br><br>
|
||
|
|
SINGLE_SCAN = 0x0 - In Single Scan Mode, the ADC will complete a single scan upon each trigger event.<br>
|
||
|
|
REPEATING_SCAN = 0x1 - In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>ADCEN</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'.<br><br>
|
||
|
|
DIS = 0x0 - Disable the ADC module.<br>
|
||
|
|
EN = 0x1 - Enable the ADC module.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="STAT" class="panel-title">STAT - ADC Power Status</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010004</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>This register indicates the basic power status for the ADC. For detailed power status, see the power control power status register. ADC power mode 0 indicates the ADC is in it's full power state and is ready to process scans. ADC Power mode 1 indicates the ADC enabled and in a low power state.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="31">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">PWDSTAT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:1</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>PWDSTAT</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Indicates the power-status of the ADC.<br><br>
|
||
|
|
ON = 0x0 - Powered on.<br>
|
||
|
|
POWERED_DOWN = 0x1 - ADC Low Power Mode 1.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SWT" class="panel-title">SWT - Software trigger</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010008</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>This register enables initiating an ADC scan through software.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="24">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">SWT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:8</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:0</td>
|
||
|
|
<td>SWT</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Writing 0x37 to this register generates a software trigger.<br><br>
|
||
|
|
GEN_SW_TRIGGER = 0x37 - Writing this value generates a software trigger.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL0CFG" class="panel-title">SL0CFG - Slot 0 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5001000C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 0 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN0
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 0.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 0.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN0</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 0 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 0 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL1CFG" class="panel-title">SL1CFG - Slot 1 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010010</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 1 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 1.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 1.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 1 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 1 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL2CFG" class="panel-title">SL2CFG - Slot 2 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010014</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 2 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 2.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 2.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 2 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 2 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL3CFG" class="panel-title">SL3CFG - Slot 3 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010018</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 3 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN3
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 3.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 3.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN3</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 3 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 3 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL4CFG" class="panel-title">SL4CFG - Slot 4 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5001001C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 4 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL4
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE4
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL4
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN4
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN4
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL4</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE4</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL4</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN4</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 4.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 4.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN4</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 4 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 4 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL5CFG" class="panel-title">SL5CFG - Slot 5 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010020</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 5 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL5
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE5
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL5
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN5
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN5
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL5</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE5</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL5</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN5</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 5.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 5.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN5</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 5 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 5 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL6CFG" class="panel-title">SL6CFG - Slot 6 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010024</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 6 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL6
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE6
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL6
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN6
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN6
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL6</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE6</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL6</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN6</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 6.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 6.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN6</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 6 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 6 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SL7CFG" class="panel-title">SL7CFG - Slot 7 Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010028</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Slot 7 Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">ADSEL7
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">PRMODE7
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="4">CHSEL7
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEN7
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SLEN7
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:27</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>26:24</td>
|
||
|
|
<td>ADSEL7</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select the number of measurements to average in the accumulate divide module for this slot.<br><br>
|
||
|
|
AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.<br>
|
||
|
|
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>23:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:16</td>
|
||
|
|
<td>PRMODE7</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Set the Precision Mode For Slot.<br><br>
|
||
|
|
P14B = 0x0 - 14-bit precision mode<br>
|
||
|
|
P12B = 0x1 - 12-bit precision mode<br>
|
||
|
|
P10B = 0x2 - 10-bit precision mode<br>
|
||
|
|
P8B = 0x3 - 8-bit precision mode</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:12</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>11:8</td>
|
||
|
|
<td>CHSEL7</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Select one of the 14 channel inputs for this slot.<br><br>
|
||
|
|
SE0 = 0x0 - single ended external GPIO connection to pad16.<br>
|
||
|
|
SE1 = 0x1 - single ended external GPIO connection to pad29.<br>
|
||
|
|
SE2 = 0x2 - single ended external GPIO connection to pad11.<br>
|
||
|
|
SE3 = 0x3 - single ended external GPIO connection to pad31.<br>
|
||
|
|
SE4 = 0x4 - single ended external GPIO connection to pad32.<br>
|
||
|
|
SE5 = 0x5 - single ended external GPIO connection to pad33.<br>
|
||
|
|
SE6 = 0x6 - single ended external GPIO connection to pad34.<br>
|
||
|
|
SE7 = 0x7 - single ended external GPIO connection to pad35.<br>
|
||
|
|
SE8 = 0x8 - single ended external GPIO connection to pad13.<br>
|
||
|
|
SE9 = 0x9 - single ended external GPIO connection to pad12.<br>
|
||
|
|
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).<br>
|
||
|
|
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).<br>
|
||
|
|
TEMP = 0xC - internal temperature sensor.<br>
|
||
|
|
BATT = 0xD - internal voltage divide-by-3 connection.<br>
|
||
|
|
VSS = 0xE - Input VSS</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>WCEN7</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables the window compare function for slot 7.<br><br>
|
||
|
|
WCEN = 0x1 - Enable the window compare for slot 7.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SLEN7</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>This bit enables slot 7 for ADC conversions.<br><br>
|
||
|
|
SLEN = 0x1 - Enable slot 7 for ADC conversions.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="WULIM" class="panel-title">WULIM - Window Comparator Upper Limits Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5001002C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Window Comparator Upper Limits Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="12">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="20">ULIM
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:20</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>19:0</td>
|
||
|
|
<td>ULIM</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Sets the upper limit for the window comparator.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="WLLIM" class="panel-title">WLLIM - Window Comparator Lower Limits Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010030</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Window Comparator Lower Limits Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="12">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="20">LLIM
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:20</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>19:0</td>
|
||
|
|
<td>LLIM</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Sets the lower limit for the window comparator.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="SCWLIM" class="panel-title">SCWLIM - Scale Window Comparator Limits</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010034</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Scale Window Comparator Limits</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="31">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SCWLIMEN
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:1</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>SCWLIMEN</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="FIFO" class="panel-title">FIFO - FIFO Data and Valid Count Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010038</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>The ADC FIFO Register contains the slot number and fifo data for the oldest conversion data in the FIFO. The COUNT field indicates the total number of valid entries in the FIFO. A write to this register will pop one of the FIFO entries off the FIFO and decrease the COUNT by 1 if the COUNT is greater than zero.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="1">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">SLOTNUM
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">COUNT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="20">DATA
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>30:28</td>
|
||
|
|
<td>SLOTNUM</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Slot number associated with this FIFO data.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>27:20</td>
|
||
|
|
<td>COUNT</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Number of valid entries in the ADC FIFO.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>19:0</td>
|
||
|
|
<td>DATA</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Oldest data in the FIFO.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="FIFOPR" class="panel-title">FIFOPR - FIFO Data and Valid Count Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5001003C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>This is a Pop Read mirrored copy of the ADCFIFO register with the only difference being that reading this register will result in a simultaneous FIFO POP which is also achieved by writing to the ADCFIFO Register. Note: The DFIFORDEN bit must be set in the CFG register for the the destructive read to be enabled.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="1">RSVDPR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="3">SLOTNUMPR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="8">COUNT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="20">DATA
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31</td>
|
||
|
|
<td>RSVDPR</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>30:28</td>
|
||
|
|
<td>SLOTNUMPR</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Slot number associated with this FIFO data.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>27:20</td>
|
||
|
|
<td>COUNT</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Number of valid entries in the ADC FIFO.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>19:0</td>
|
||
|
|
<td>DATA</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Oldest data in the FIFO.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTEN" class="panel-title">INTEN - ADC Interrupt registers: Enable</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010200</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Set bits in this register to allow this module to generate the corresponding interrupt.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="24">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCINC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEXC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SCNCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">CNVCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:8</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>DERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Error Condition<br><br>
|
||
|
|
DMAERROR = 0x1 - DMA Error Condition Occurred</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>DCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Transfer Complete<br><br>
|
||
|
|
DMACOMPLETE = 0x1 - DMA Completed a transfer</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>WCINC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage incursion interrupt.<br><br>
|
||
|
|
WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>WCEXC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage excursion interrupt.<br><br>
|
||
|
|
WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FIFOOVR2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 100 percent full interrupt.<br><br>
|
||
|
|
FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FIFOOVR1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 75 percent full interrupt.<br><br>
|
||
|
|
FIFO75INT = 0x1 - FIFO 75 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>SCNCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC scan complete interrupt.<br><br>
|
||
|
|
SCNCMPINT = 0x1 - ADC scan complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>CNVCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC conversion complete interrupt.<br><br>
|
||
|
|
CNVCMPINT = 0x1 - ADC conversion complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTSTAT" class="panel-title">INTSTAT - ADC Interrupt registers: Status</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010204</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Read bits from this register to discover the cause of a recent interrupt.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="24">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCINC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEXC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SCNCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">CNVCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:8</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>DERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Error Condition<br><br>
|
||
|
|
DMAERROR = 0x1 - DMA Error Condition Occurred</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>DCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Transfer Complete<br><br>
|
||
|
|
DMACOMPLETE = 0x1 - DMA Completed a transfer</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>WCINC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage incursion interrupt.<br><br>
|
||
|
|
WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>WCEXC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage excursion interrupt.<br><br>
|
||
|
|
WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FIFOOVR2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 100 percent full interrupt.<br><br>
|
||
|
|
FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FIFOOVR1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 75 percent full interrupt.<br><br>
|
||
|
|
FIFO75INT = 0x1 - FIFO 75 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>SCNCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC scan complete interrupt.<br><br>
|
||
|
|
SCNCMPINT = 0x1 - ADC scan complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>CNVCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC conversion complete interrupt.<br><br>
|
||
|
|
CNVCMPINT = 0x1 - ADC conversion complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTCLR" class="panel-title">INTCLR - ADC Interrupt registers: Clear</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010208</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Write a 1 to a bit in this register to clear the interrupt status associated with that bit.</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="24">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCINC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEXC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SCNCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">CNVCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:8</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>DERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Error Condition<br><br>
|
||
|
|
DMAERROR = 0x1 - DMA Error Condition Occurred</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>DCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Transfer Complete<br><br>
|
||
|
|
DMACOMPLETE = 0x1 - DMA Completed a transfer</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>WCINC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage incursion interrupt.<br><br>
|
||
|
|
WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>WCEXC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage excursion interrupt.<br><br>
|
||
|
|
WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FIFOOVR2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 100 percent full interrupt.<br><br>
|
||
|
|
FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FIFOOVR1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 75 percent full interrupt.<br><br>
|
||
|
|
FIFO75INT = 0x1 - FIFO 75 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>SCNCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC scan complete interrupt.<br><br>
|
||
|
|
SCNCMPINT = 0x1 - ADC scan complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>CNVCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC conversion complete interrupt.<br><br>
|
||
|
|
CNVCMPINT = 0x1 - ADC conversion complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="INTSET" class="panel-title">INTSET - ADC Interrupt registers: Set</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5001020C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="24">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCINC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">WCEXC
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR2
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">FIFOOVR1
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">SCNCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">CNVCMP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:8</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7</td>
|
||
|
|
<td>DERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Error Condition<br><br>
|
||
|
|
DMAERROR = 0x1 - DMA Error Condition Occurred</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>6</td>
|
||
|
|
<td>DCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Transfer Complete<br><br>
|
||
|
|
DMACOMPLETE = 0x1 - DMA Completed a transfer</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>5</td>
|
||
|
|
<td>WCINC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage incursion interrupt.<br><br>
|
||
|
|
WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>4</td>
|
||
|
|
<td>WCEXC</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Window comparator voltage excursion interrupt.<br><br>
|
||
|
|
WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>3</td>
|
||
|
|
<td>FIFOOVR2</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 100 percent full interrupt.<br><br>
|
||
|
|
FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>FIFOOVR1</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>FIFO 75 percent full interrupt.<br><br>
|
||
|
|
FIFO75INT = 0x1 - FIFO 75 percent full interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>SCNCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC scan complete interrupt.<br><br>
|
||
|
|
SCNCMPINT = 0x1 - ADC scan complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>CNVCMP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>ADC conversion complete interrupt.<br><br>
|
||
|
|
CNVCMPINT = 0x1 - ADC conversion complete interrupt.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="DMATRIGEN" class="panel-title">DMATRIGEN - DMA Trigger Enable Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010240</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>DMA Trigger Enable Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="30">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DFIFOFULL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DFIFO75
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>DFIFOFULL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Trigger DMA upon FIFO 100 percent Full<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>DFIFO75</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Trigger DMA upon FIFO 75 percent Full<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="DMATRIGSTAT" class="panel-title">DMATRIGSTAT - DMA Trigger Status Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010244</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>DMA Trigger Status Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="30">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DFULLSTAT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">D75STAT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:2</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>DFULLSTAT</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Triggered DMA from FIFO 100 percent Full<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>D75STAT</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Triggered DMA from FIFO 75 percent Full<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="DMACFG" class="panel-title">DMACFG - DMA Configuration Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010280</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>DMA Configuration Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="13">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DPWROFF
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMAMSK
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMAHONSTAT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="6">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMADYNPRI
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMAPRI
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="5">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMADIR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMAEN
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:19</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>18</td>
|
||
|
|
<td>DPWROFF</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Power Off the ADC System upon DMACPL.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17</td>
|
||
|
|
<td>DMAMSK</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory<br><br>
|
||
|
|
DIS = 0x0 - FIFO Contents are copied directly to memory without modification.<br>
|
||
|
|
EN = 0x1 - Only the FIFODATA contents are copied to memory on DMA transfers. The SLOTNUM and FIFOCNT contents are cleared to zero.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>16</td>
|
||
|
|
<td>DMAHONSTAT</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared.<br><br>
|
||
|
|
DIS = 0x0 - ADC conversions will continue regardless of DMA status register<br>
|
||
|
|
EN = 0x1 - ADC conversions will not progress if DMAERR or DMACPL bits in DMA status register are set.</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>15:10</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>9</td>
|
||
|
|
<td>DMADYNPRI</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used.<br><br>
|
||
|
|
DIS = 0x0 - Disable dynamic priority (use DMAPRI setting only)<br>
|
||
|
|
EN = 0x1 - Enable dynamic priority</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>8</td>
|
||
|
|
<td>DMAPRI</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Sets the Priority of the DMA request<br><br>
|
||
|
|
LOW = 0x0 - Low Priority (service as best effort)<br>
|
||
|
|
HIGH = 0x1 - High Priority (service immediately)</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>7:3</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>DMADIR</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>Direction<br><br>
|
||
|
|
P2M = 0x0 - Peripheral to Memory (SRAM) transaction<br>
|
||
|
|
M2P = 0x1 - Memory to Peripheral transaction</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>DMAEN</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Enable<br><br>
|
||
|
|
DIS = 0x0 - Disable DMA Function<br>
|
||
|
|
EN = 0x1 - Enable DMA Function</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="DMATOTCOUNT" class="panel-title">DMATOTCOUNT - DMA Total Transfer Count</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010288</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>DMA Total Transfer Count</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="14">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="16">TOTCOUNT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="2">BTOTCOUNT
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:18</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>17:2</td>
|
||
|
|
<td>TOTCOUNT</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>Total Transfer Count<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1:0</td>
|
||
|
|
<td>BTOTCOUNT</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="DMATARGADDR" class="panel-title">DMATARGADDR - DMA Target Address Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x5001028C</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>DMA Target Address Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="13">UTARGADDR
|
||
|
|
<br>0x400</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="19">LTARGADDR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:19</td>
|
||
|
|
<td>UTARGADDR</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>SRAM Target<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>18:0</td>
|
||
|
|
<td>LTARGADDR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Target Address<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
</div>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<div class="panel panel-default">
|
||
|
|
<div class="panel-heading">
|
||
|
|
<h3 id="DMASTAT" class="panel-title">DMASTAT - DMA Status Register</h3>
|
||
|
|
</div>
|
||
|
|
<div class="panel-body">
|
||
|
|
<h3>Address:</h3>
|
||
|
|
<table style="margin:10px">
|
||
|
|
<tr id="row_0_0_">
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">Instance 0 Address:</span>
|
||
|
|
</td>
|
||
|
|
<td class="entry">
|
||
|
|
<span style="width:32px;display:inline-block;"> </span>
|
||
|
|
<span class="h5">0x50010290</span>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
</table>
|
||
|
|
<h3>Description:</h3>
|
||
|
|
<p>DMA Status Register</p>
|
||
|
|
<h3>Example Macro Usage:</h3>
|
||
|
|
<pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
|
||
|
|
// Register access is all performed through the standard CMSIS structure-based
|
||
|
|
// interface. This includes module-level structure definitions with members and
|
||
|
|
// bitfields corresponding to the physical registers and bitfields within each
|
||
|
|
// module. In addition, Ambiq has provided instance-level macros for modules
|
||
|
|
// that have more than one physical instance and a generic AM_REGVAL() macro
|
||
|
|
// for directly accessing memory by address.
|
||
|
|
//
|
||
|
|
// The following examples show how to use these structures and macros:
|
||
|
|
|
||
|
|
// Setting the ADC configuration register...</span>
|
||
|
|
AM_REGVAL(0x50010000) = 0x1234; <span style='color:#3f7f59; '>// by address.</span>
|
||
|
|
ADC->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer.</span>
|
||
|
|
ADCn(0)->CFG = 0x1234; <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>
|
||
|
|
|
||
|
|
<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = 0x2; <span style='color:#3f7f59; '>// by raw value.</span>
|
||
|
|
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
|
||
|
|
<h3>Register Fields:</h3>
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>31</th>
|
||
|
|
<th>30</th>
|
||
|
|
<th>29</th>
|
||
|
|
<th>28</th>
|
||
|
|
<th>27</th>
|
||
|
|
<th>26</th>
|
||
|
|
<th>25</th>
|
||
|
|
<th>24</th>
|
||
|
|
<th>23</th>
|
||
|
|
<th>22</th>
|
||
|
|
<th>21</th>
|
||
|
|
<th>20</th>
|
||
|
|
<th>19</th>
|
||
|
|
<th>18</th>
|
||
|
|
<th>17</th>
|
||
|
|
<th>16</th>
|
||
|
|
<th>15</th>
|
||
|
|
<th>14</th>
|
||
|
|
<th>13</th>
|
||
|
|
<th>12</th>
|
||
|
|
<th>11</th>
|
||
|
|
<th>10</th>
|
||
|
|
<th>9</th>
|
||
|
|
<th>8</th>
|
||
|
|
<th>7</th>
|
||
|
|
<th>6</th>
|
||
|
|
<th>5</th>
|
||
|
|
<th>4</th>
|
||
|
|
<th>3</th>
|
||
|
|
<th>2</th>
|
||
|
|
<th>1</th>
|
||
|
|
<th>0</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td align="center" colspan="29">RSVD
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMAERR
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMACPL
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
<td align="center" colspan="1">DMATIP
|
||
|
|
<br>0x0</td>
|
||
|
|
|
||
|
|
</tr>
|
||
|
|
</tbody>
|
||
|
|
</table>
|
||
|
|
<br>
|
||
|
|
|
||
|
|
<table style="margin:10px" class="table table-bordered table-condensed">
|
||
|
|
<thead>
|
||
|
|
<tr>
|
||
|
|
<th>Bits</th>
|
||
|
|
<th>Name</th>
|
||
|
|
<th>RW</th>
|
||
|
|
<th>Description</th>
|
||
|
|
</tr>
|
||
|
|
</thead>
|
||
|
|
<tbody>
|
||
|
|
<tr>
|
||
|
|
<td>31:3</td>
|
||
|
|
<td>RSVD</td>
|
||
|
|
<td>RO</td>
|
||
|
|
<td>RESERVED.<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>2</td>
|
||
|
|
<td>DMAERR</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Error<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>1</td>
|
||
|
|
<td>DMACPL</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Transfer Complete<br><br>
|
||
|
|
</td>
|
||
|
|
</tr>
|
||
|
|
|
||
|
|
<tr>
|
||
|
|
<td>0</td>
|
||
|
|
<td>DMATIP</td>
|
||
|
|
<td>RW</td>
|
||
|
|
<td>DMA Transfer In Progress<br><br>
|
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</td>
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</tr>
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</tbody>
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</table>
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<br>
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</div>
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</div>
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</body>
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<hr size="1">
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||
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<body>
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||
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<div id="footer" align="right">
|
||
|
|
<small>
|
||
|
|
AmbiqSuite Register Documentation
|
||
|
|
<a href="http://www.ambiqmicro.com">
|
||
|
|
<img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>   Copyright © 2019  <br />
|
||
|
|
This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.  <br/>
|
||
|
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</small>
|
||
|
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</div>
|
||
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</body>
|
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</html>
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