206 lines
8.9 KiB
C
206 lines
8.9 KiB
C
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//*****************************************************************************
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//
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//! @file am_devices_mspi_psram_aps6404l.h
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//!
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//! @brief Micron Serial SPI PSRAM driver.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_DEVICES_MSPI_PSRAM_APS6404L_H
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#define AM_DEVICES_MSPI_PSRAM_APS6404L_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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// Global definitions for psram commands
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//
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//*****************************************************************************
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#define AM_DEVICES_MSPI_PSRAM_WRITE 0x02
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#define AM_DEVICES_MSPI_PSRAM_READ 0x03
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#define AM_DEVICES_MSPI_PSRAM_FAST_READ 0x0B
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#define AM_DEVICES_MSPI_PSRAM_QUAD_MODE_ENTER 0x35
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#define AM_DEVICES_MSPI_PSRAM_QUAD_WRITE 0x38
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#define AM_DEVICES_MSPI_PSRAM_RESET_ENABLE 0x66
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#define AM_DEVICES_MSPI_PSRAM_RESET_MEMORY 0x99
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#define AM_DEVICES_MSPI_PSRAM_READ_ID 0x9F
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#define AM_DEVICES_MSPI_PSRAM_APS6404L_HALF_SLEEP_ENTER 0xC0
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#define AM_DEVICES_MSPI_PSRAM_QUAD_READ 0xEB
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#define AM_DEVICES_MSPI_PSRAM_QUAD_MODE_EXIT 0xF5
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//
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// The following definitions are typically specific to a multibit spi psram device.
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// They should be tailored
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//
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//*****************************************************************************
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//
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// Device specific identification.
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//
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//*****************************************************************************
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#define AM_DEVICES_MSPI_PSRAM_KGD_PASS 0x5D0D
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#define AM_DEVICES_MSPI_PSRAM_KGD_FAIL 0x550D
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// Page size - limits the bust write/read
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#define AM_DEVICES_MSPI_PSRAM_PAGE_SIZE 1024
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//#define AM_DEVICES_MSPI_PSRAM_TEST_BLOCK_SIZE 64*1024
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#define AM_DEVICES_MSPI_PSRAM_TEST_BLOCK_SIZE 8*1024
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// According to APS6404L tCEM restriction, we define maximum bytes for each speed empirically
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#define AM_DEVICES_MSPI_PSRAM_48MHZ_MAX_BYTES 128
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#define AM_DEVICES_MSPI_PSRAM_24MHZ_MAX_BYTES 64
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#define AM_DEVICES_MSPI_PSRAM_16MHZ_MAX_BYTES 32
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#define AM_DEVICES_MSPI_PSRAM_12MHZ_MAX_BYTES 16
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#define AM_DEVICES_MSPI_PSRAM_8MHZ_MAX_BYTES 8
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//*****************************************************************************
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//
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// Global definitions for the MSPI instance to use.
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//
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//*****************************************************************************
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#define AM_DEVICES_MSPI_PSRAM_MAX_DEVICE_NUM 2
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//*****************************************************************************
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//
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// Global type definitions.
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//
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//*****************************************************************************
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typedef enum
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{
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AM_DEVICES_MSPI_PSRAM_STATUS_SUCCESS,
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AM_DEVICES_MSPI_PSRAM_STATUS_ERROR
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} am_devices_mspi_psram_status_t;
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typedef struct
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{
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am_hal_mspi_device_e eDeviceConfig;
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am_hal_mspi_clock_e eClockFreq;
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am_hal_mspi_xipmixed_mode_e eMixedMode;
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uint32_t *pNBTxnBuf;
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uint32_t ui32NBTxnBufLength;
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uint32_t ui32ScramblingStartAddr;
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uint32_t ui32ScramblingEndAddr;
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} am_devices_mspi_psram_config_t;
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//*****************************************************************************
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//
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// External function definitions.
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//
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//*****************************************************************************
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extern uint32_t am_devices_mspi_psram_init(uint32_t ui32Module,
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am_devices_mspi_psram_config_t *pDevCfg,
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void **ppHandle,
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void **pMspiHandle);
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extern uint32_t am_devices_mspi_psram_deinit(void *pHandle);
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extern uint32_t am_devices_mspi_psram_id(void *pHandle);
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extern uint32_t am_devices_mspi_psram_reset(void *pHandle);
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extern uint32_t am_devices_mspi_psram_read(void *pHandle,
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uint8_t *pui8RxBuffer,
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uint32_t ui32ReadAddress,
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uint32_t ui32NumBytes,
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bool bWaitForCompletion);
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extern uint32_t am_devices_mspi_psram_read_adv(void *pHandle,
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uint8_t *pui8RxBuffer,
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uint32_t ui32ReadAddress,
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uint32_t ui32NumBytes,
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uint32_t ui32PauseCondition,
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uint32_t ui32StatusSetClr,
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am_hal_mspi_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mspi_psram_write(void *pHandle,
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uint8_t *ui8TxBuffer,
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uint32_t ui32WriteAddress,
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uint32_t ui32NumBytes,
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bool bWaitForCompletion);
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extern uint32_t am_devices_mspi_psram_write_adv(void *pHandle,
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uint8_t *puiTxBuffer,
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uint32_t ui32WriteAddress,
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uint32_t ui32NumBytes,
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uint32_t ui32PauseCondition,
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uint32_t ui32StatusSetClr,
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am_hal_mspi_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mspi_psram_enable_xip(void *pHandle);
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extern uint32_t am_devices_mspi_psram_disable_xip(void *pHandle);
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extern uint32_t am_devices_mspi_psram_enable_scrambling(void *pHandle);
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extern uint32_t am_devices_mspi_psram_disable_scrambling(void *pHandle);
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extern uint32_t am_devices_mspi_psram_read_hiprio(void *pHandle, uint8_t *pui8RxBuffer,
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uint32_t ui32ReadAddress,
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uint32_t ui32NumBytes,
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am_hal_mspi_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mspi_psram_nonblocking_read(void *pHandle, uint8_t *pui8RxBuffer,
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uint32_t ui32ReadAddress,
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uint32_t ui32NumBytes,
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am_hal_mspi_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mspi_psram_write_hiprio(void *pHandle, uint8_t *pui8TxBuffer,
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uint32_t ui32WriteAddress,
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uint32_t ui32NumBytes,
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am_hal_mspi_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mspi_psram_nonblocking_write(void *pHandle, uint8_t *pui8TxBuffer,
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uint32_t ui32WriteAddress,
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uint32_t ui32NumBytes,
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am_hal_mspi_callback_t pfnCallback,
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void *pCallbackCtxt);
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#ifdef __cplusplus
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}
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#endif
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#endif // AM_DEVICES_MSPI_PSRAM_APS6404L_H
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