5761 lines
221 KiB
Plaintext
5761 lines
221 KiB
Plaintext
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../gcc/artemis_module/bin/svl.axf: file format elf32-littlearm
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Disassembly of section .text:
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0000c000 <g_am_pfnVectors>:
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c000: f8 ff 05 10 4d cd 00 00 d1 cd 00 00 d7 cd 00 00 ....M...........
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c010: d7 cd 00 00 d7 cd 00 00 d7 cd 00 00 00 00 00 00 ................
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...
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c02c: dd cd 00 00 dd cd 00 00 00 00 00 00 dd cd 00 00 ................
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c03c: dd cd 00 00 dd cd 00 00 dd cd 00 00 dd cd 00 00 ................
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c04c: dd cd 00 00 dd cd 00 00 dd cd 00 00 dd cd 00 00 ................
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c05c: dd cd 00 00 dd cd 00 00 dd cd 00 00 dd cd 00 00 ................
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c06c: dd cd 00 00 dd cd 00 00 6d cc 00 00 dd cd 00 00 ........m.......
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c07c: ed cb 00 00 5d cc 00 00 dd cd 00 00 dd cd 00 00 ....]...........
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c08c: dd cd 00 00 dd cd 00 00 dd cd 00 00 b5 cc 00 00 ................
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c09c: dd cd 00 00 dd cd 00 00 dd cd 00 00 dd cd 00 00 ................
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c0ac: dd cd 00 00 dd cd 00 00 dd cd 00 00 dd cd 00 00 ................
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c0bc: dd cd 00 00 ....
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0000c0c0 <__Patchable>:
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...
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0000c100 <__aeabi_uldivmod>:
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c100: b953 cbnz r3, c118 <__aeabi_uldivmod+0x18>
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c102: b94a cbnz r2, c118 <__aeabi_uldivmod+0x18>
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c104: 2900 cmp r1, #0
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c106: bf08 it eq
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c108: 2800 cmpeq r0, #0
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c10a: bf1c itt ne
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c10c: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
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c110: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
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c114: f000 b96e b.w c3f4 <__aeabi_idiv0>
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c118: f1ad 0c08 sub.w ip, sp, #8
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c11c: e96d ce04 strd ip, lr, [sp, #-16]!
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c120: f000 f806 bl c130 <__udivmoddi4>
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c124: f8dd e004 ldr.w lr, [sp, #4]
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c128: e9dd 2302 ldrd r2, r3, [sp, #8]
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c12c: b004 add sp, #16
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c12e: 4770 bx lr
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0000c130 <__udivmoddi4>:
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c130: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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c134: 9d08 ldr r5, [sp, #32]
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c136: 4604 mov r4, r0
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c138: 468c mov ip, r1
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c13a: 2b00 cmp r3, #0
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c13c: f040 8083 bne.w c246 <__udivmoddi4+0x116>
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c140: 428a cmp r2, r1
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c142: 4617 mov r7, r2
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c144: d947 bls.n c1d6 <__udivmoddi4+0xa6>
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c146: fab2 f282 clz r2, r2
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c14a: b142 cbz r2, c15e <__udivmoddi4+0x2e>
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c14c: f1c2 0020 rsb r0, r2, #32
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c150: fa24 f000 lsr.w r0, r4, r0
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c154: 4091 lsls r1, r2
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c156: 4097 lsls r7, r2
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c158: ea40 0c01 orr.w ip, r0, r1
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c15c: 4094 lsls r4, r2
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c15e: ea4f 4817 mov.w r8, r7, lsr #16
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c162: 0c23 lsrs r3, r4, #16
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c164: fbbc f6f8 udiv r6, ip, r8
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c168: fa1f fe87 uxth.w lr, r7
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c16c: fb08 c116 mls r1, r8, r6, ip
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c170: ea43 4301 orr.w r3, r3, r1, lsl #16
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c174: fb06 f10e mul.w r1, r6, lr
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c178: 4299 cmp r1, r3
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c17a: d909 bls.n c190 <__udivmoddi4+0x60>
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c17c: 18fb adds r3, r7, r3
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c17e: f106 30ff add.w r0, r6, #4294967295 ; 0xffffffff
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c182: f080 8119 bcs.w c3b8 <__udivmoddi4+0x288>
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c186: 4299 cmp r1, r3
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c188: f240 8116 bls.w c3b8 <__udivmoddi4+0x288>
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c18c: 3e02 subs r6, #2
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c18e: 443b add r3, r7
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c190: 1a5b subs r3, r3, r1
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c192: b2a4 uxth r4, r4
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c194: fbb3 f0f8 udiv r0, r3, r8
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c198: fb08 3310 mls r3, r8, r0, r3
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c19c: ea44 4403 orr.w r4, r4, r3, lsl #16
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c1a0: fb00 fe0e mul.w lr, r0, lr
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c1a4: 45a6 cmp lr, r4
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c1a6: d909 bls.n c1bc <__udivmoddi4+0x8c>
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c1a8: 193c adds r4, r7, r4
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c1aa: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
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c1ae: f080 8105 bcs.w c3bc <__udivmoddi4+0x28c>
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c1b2: 45a6 cmp lr, r4
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c1b4: f240 8102 bls.w c3bc <__udivmoddi4+0x28c>
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c1b8: 3802 subs r0, #2
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c1ba: 443c add r4, r7
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c1bc: ea40 4006 orr.w r0, r0, r6, lsl #16
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c1c0: eba4 040e sub.w r4, r4, lr
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c1c4: 2600 movs r6, #0
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c1c6: b11d cbz r5, c1d0 <__udivmoddi4+0xa0>
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c1c8: 40d4 lsrs r4, r2
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c1ca: 2300 movs r3, #0
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c1cc: e9c5 4300 strd r4, r3, [r5]
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c1d0: 4631 mov r1, r6
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c1d2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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c1d6: b902 cbnz r2, c1da <__udivmoddi4+0xaa>
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c1d8: deff udf #255 ; 0xff
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c1da: fab2 f282 clz r2, r2
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c1de: 2a00 cmp r2, #0
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c1e0: d150 bne.n c284 <__udivmoddi4+0x154>
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c1e2: 1bcb subs r3, r1, r7
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c1e4: ea4f 4e17 mov.w lr, r7, lsr #16
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c1e8: fa1f f887 uxth.w r8, r7
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c1ec: 2601 movs r6, #1
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c1ee: fbb3 fcfe udiv ip, r3, lr
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c1f2: 0c21 lsrs r1, r4, #16
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c1f4: fb0e 331c mls r3, lr, ip, r3
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c1f8: ea41 4103 orr.w r1, r1, r3, lsl #16
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c1fc: fb08 f30c mul.w r3, r8, ip
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c200: 428b cmp r3, r1
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c202: d907 bls.n c214 <__udivmoddi4+0xe4>
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c204: 1879 adds r1, r7, r1
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c206: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
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c20a: d202 bcs.n c212 <__udivmoddi4+0xe2>
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c20c: 428b cmp r3, r1
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c20e: f200 80e9 bhi.w c3e4 <__udivmoddi4+0x2b4>
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c212: 4684 mov ip, r0
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c214: 1ac9 subs r1, r1, r3
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c216: b2a3 uxth r3, r4
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c218: fbb1 f0fe udiv r0, r1, lr
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c21c: fb0e 1110 mls r1, lr, r0, r1
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c220: ea43 4401 orr.w r4, r3, r1, lsl #16
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c224: fb08 f800 mul.w r8, r8, r0
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c228: 45a0 cmp r8, r4
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c22a: d907 bls.n c23c <__udivmoddi4+0x10c>
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c22c: 193c adds r4, r7, r4
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c22e: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
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c232: d202 bcs.n c23a <__udivmoddi4+0x10a>
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c234: 45a0 cmp r8, r4
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c236: f200 80d9 bhi.w c3ec <__udivmoddi4+0x2bc>
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c23a: 4618 mov r0, r3
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c23c: eba4 0408 sub.w r4, r4, r8
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c240: ea40 400c orr.w r0, r0, ip, lsl #16
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c244: e7bf b.n c1c6 <__udivmoddi4+0x96>
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c246: 428b cmp r3, r1
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c248: d909 bls.n c25e <__udivmoddi4+0x12e>
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c24a: 2d00 cmp r5, #0
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c24c: f000 80b1 beq.w c3b2 <__udivmoddi4+0x282>
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c250: 2600 movs r6, #0
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c252: e9c5 0100 strd r0, r1, [r5]
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c256: 4630 mov r0, r6
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c258: 4631 mov r1, r6
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c25a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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c25e: fab3 f683 clz r6, r3
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c262: 2e00 cmp r6, #0
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c264: d14a bne.n c2fc <__udivmoddi4+0x1cc>
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c266: 428b cmp r3, r1
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c268: d302 bcc.n c270 <__udivmoddi4+0x140>
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c26a: 4282 cmp r2, r0
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c26c: f200 80b8 bhi.w c3e0 <__udivmoddi4+0x2b0>
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c270: 1a84 subs r4, r0, r2
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c272: eb61 0103 sbc.w r1, r1, r3
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c276: 2001 movs r0, #1
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c278: 468c mov ip, r1
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c27a: 2d00 cmp r5, #0
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c27c: d0a8 beq.n c1d0 <__udivmoddi4+0xa0>
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c27e: e9c5 4c00 strd r4, ip, [r5]
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c282: e7a5 b.n c1d0 <__udivmoddi4+0xa0>
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c284: f1c2 0320 rsb r3, r2, #32
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c288: fa20 f603 lsr.w r6, r0, r3
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c28c: 4097 lsls r7, r2
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c28e: fa01 f002 lsl.w r0, r1, r2
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c292: ea4f 4e17 mov.w lr, r7, lsr #16
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c296: 40d9 lsrs r1, r3
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c298: 4330 orrs r0, r6
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c29a: 0c03 lsrs r3, r0, #16
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c29c: fbb1 f6fe udiv r6, r1, lr
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c2a0: fa1f f887 uxth.w r8, r7
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c2a4: fb0e 1116 mls r1, lr, r6, r1
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c2a8: ea43 4301 orr.w r3, r3, r1, lsl #16
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c2ac: fb06 f108 mul.w r1, r6, r8
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c2b0: 4299 cmp r1, r3
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c2b2: fa04 f402 lsl.w r4, r4, r2
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c2b6: d909 bls.n c2cc <__udivmoddi4+0x19c>
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c2b8: 18fb adds r3, r7, r3
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c2ba: f106 3cff add.w ip, r6, #4294967295 ; 0xffffffff
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c2be: f080 808d bcs.w c3dc <__udivmoddi4+0x2ac>
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c2c2: 4299 cmp r1, r3
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c2c4: f240 808a bls.w c3dc <__udivmoddi4+0x2ac>
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c2c8: 3e02 subs r6, #2
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c2ca: 443b add r3, r7
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c2cc: 1a5b subs r3, r3, r1
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c2ce: b281 uxth r1, r0
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c2d0: fbb3 f0fe udiv r0, r3, lr
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c2d4: fb0e 3310 mls r3, lr, r0, r3
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c2d8: ea41 4103 orr.w r1, r1, r3, lsl #16
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c2dc: fb00 f308 mul.w r3, r0, r8
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c2e0: 428b cmp r3, r1
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c2e2: d907 bls.n c2f4 <__udivmoddi4+0x1c4>
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c2e4: 1879 adds r1, r7, r1
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c2e6: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
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c2ea: d273 bcs.n c3d4 <__udivmoddi4+0x2a4>
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c2ec: 428b cmp r3, r1
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c2ee: d971 bls.n c3d4 <__udivmoddi4+0x2a4>
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c2f0: 3802 subs r0, #2
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c2f2: 4439 add r1, r7
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c2f4: 1acb subs r3, r1, r3
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c2f6: ea40 4606 orr.w r6, r0, r6, lsl #16
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c2fa: e778 b.n c1ee <__udivmoddi4+0xbe>
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c2fc: f1c6 0c20 rsb ip, r6, #32
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c300: fa03 f406 lsl.w r4, r3, r6
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c304: fa22 f30c lsr.w r3, r2, ip
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c308: 431c orrs r4, r3
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c30a: fa20 f70c lsr.w r7, r0, ip
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c30e: fa01 f306 lsl.w r3, r1, r6
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c312: ea4f 4e14 mov.w lr, r4, lsr #16
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c316: fa21 f10c lsr.w r1, r1, ip
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c31a: 431f orrs r7, r3
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c31c: 0c3b lsrs r3, r7, #16
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c31e: fbb1 f9fe udiv r9, r1, lr
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c322: fa1f f884 uxth.w r8, r4
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c326: fb0e 1119 mls r1, lr, r9, r1
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c32a: ea43 4101 orr.w r1, r3, r1, lsl #16
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c32e: fb09 fa08 mul.w sl, r9, r8
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c332: 458a cmp sl, r1
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c334: fa02 f206 lsl.w r2, r2, r6
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c338: fa00 f306 lsl.w r3, r0, r6
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c33c: d908 bls.n c350 <__udivmoddi4+0x220>
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c33e: 1861 adds r1, r4, r1
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c340: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
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c344: d248 bcs.n c3d8 <__udivmoddi4+0x2a8>
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c346: 458a cmp sl, r1
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c348: d946 bls.n c3d8 <__udivmoddi4+0x2a8>
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c34a: f1a9 0902 sub.w r9, r9, #2
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c34e: 4421 add r1, r4
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c350: eba1 010a sub.w r1, r1, sl
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c354: b2bf uxth r7, r7
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c356: fbb1 f0fe udiv r0, r1, lr
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c35a: fb0e 1110 mls r1, lr, r0, r1
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c35e: ea47 4701 orr.w r7, r7, r1, lsl #16
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c362: fb00 f808 mul.w r8, r0, r8
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c366: 45b8 cmp r8, r7
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c368: d907 bls.n c37a <__udivmoddi4+0x24a>
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c36a: 19e7 adds r7, r4, r7
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c36c: f100 31ff add.w r1, r0, #4294967295 ; 0xffffffff
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c370: d22e bcs.n c3d0 <__udivmoddi4+0x2a0>
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c372: 45b8 cmp r8, r7
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c374: d92c bls.n c3d0 <__udivmoddi4+0x2a0>
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c376: 3802 subs r0, #2
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c378: 4427 add r7, r4
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c37a: ea40 4009 orr.w r0, r0, r9, lsl #16
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c37e: eba7 0708 sub.w r7, r7, r8
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c382: fba0 8902 umull r8, r9, r0, r2
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c386: 454f cmp r7, r9
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c388: 46c6 mov lr, r8
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c38a: 4649 mov r1, r9
|
||
|
|
c38c: d31a bcc.n c3c4 <__udivmoddi4+0x294>
|
||
|
|
c38e: d017 beq.n c3c0 <__udivmoddi4+0x290>
|
||
|
|
c390: b15d cbz r5, c3aa <__udivmoddi4+0x27a>
|
||
|
|
c392: ebb3 020e subs.w r2, r3, lr
|
||
|
|
c396: eb67 0701 sbc.w r7, r7, r1
|
||
|
|
c39a: fa07 fc0c lsl.w ip, r7, ip
|
||
|
|
c39e: 40f2 lsrs r2, r6
|
||
|
|
c3a0: ea4c 0202 orr.w r2, ip, r2
|
||
|
|
c3a4: 40f7 lsrs r7, r6
|
||
|
|
c3a6: e9c5 2700 strd r2, r7, [r5]
|
||
|
|
c3aa: 2600 movs r6, #0
|
||
|
|
c3ac: 4631 mov r1, r6
|
||
|
|
c3ae: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
||
|
|
c3b2: 462e mov r6, r5
|
||
|
|
c3b4: 4628 mov r0, r5
|
||
|
|
c3b6: e70b b.n c1d0 <__udivmoddi4+0xa0>
|
||
|
|
c3b8: 4606 mov r6, r0
|
||
|
|
c3ba: e6e9 b.n c190 <__udivmoddi4+0x60>
|
||
|
|
c3bc: 4618 mov r0, r3
|
||
|
|
c3be: e6fd b.n c1bc <__udivmoddi4+0x8c>
|
||
|
|
c3c0: 4543 cmp r3, r8
|
||
|
|
c3c2: d2e5 bcs.n c390 <__udivmoddi4+0x260>
|
||
|
|
c3c4: ebb8 0e02 subs.w lr, r8, r2
|
||
|
|
c3c8: eb69 0104 sbc.w r1, r9, r4
|
||
|
|
c3cc: 3801 subs r0, #1
|
||
|
|
c3ce: e7df b.n c390 <__udivmoddi4+0x260>
|
||
|
|
c3d0: 4608 mov r0, r1
|
||
|
|
c3d2: e7d2 b.n c37a <__udivmoddi4+0x24a>
|
||
|
|
c3d4: 4660 mov r0, ip
|
||
|
|
c3d6: e78d b.n c2f4 <__udivmoddi4+0x1c4>
|
||
|
|
c3d8: 4681 mov r9, r0
|
||
|
|
c3da: e7b9 b.n c350 <__udivmoddi4+0x220>
|
||
|
|
c3dc: 4666 mov r6, ip
|
||
|
|
c3de: e775 b.n c2cc <__udivmoddi4+0x19c>
|
||
|
|
c3e0: 4630 mov r0, r6
|
||
|
|
c3e2: e74a b.n c27a <__udivmoddi4+0x14a>
|
||
|
|
c3e4: f1ac 0c02 sub.w ip, ip, #2
|
||
|
|
c3e8: 4439 add r1, r7
|
||
|
|
c3ea: e713 b.n c214 <__udivmoddi4+0xe4>
|
||
|
|
c3ec: 3802 subs r0, #2
|
||
|
|
c3ee: 443c add r4, r7
|
||
|
|
c3f0: e724 b.n c23c <__udivmoddi4+0x10c>
|
||
|
|
c3f2: bf00 nop
|
||
|
|
|
||
|
|
0000c3f4 <__aeabi_idiv0>:
|
||
|
|
c3f4: 4770 bx lr
|
||
|
|
c3f6: bf00 nop
|
||
|
|
|
||
|
|
0000c3f8 <__NVIC_EnableIRQ>:
|
||
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||
|
|
\param [in] IRQn Device specific interrupt number.
|
||
|
|
\note IRQn must not be negative.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||
|
|
{
|
||
|
|
c3f8: b480 push {r7}
|
||
|
|
c3fa: b083 sub sp, #12
|
||
|
|
c3fc: af00 add r7, sp, #0
|
||
|
|
c3fe: 4603 mov r3, r0
|
||
|
|
c400: 71fb strb r3, [r7, #7]
|
||
|
|
if ((int32_t)(IRQn) >= 0)
|
||
|
|
c402: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
c406: 2b00 cmp r3, #0
|
||
|
|
c408: db0b blt.n c422 <__NVIC_EnableIRQ+0x2a>
|
||
|
|
{
|
||
|
|
__COMPILER_BARRIER();
|
||
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||
|
|
c40a: 79fb ldrb r3, [r7, #7]
|
||
|
|
c40c: f003 021f and.w r2, r3, #31
|
||
|
|
c410: 4907 ldr r1, [pc, #28] ; (c430 <__NVIC_EnableIRQ+0x38>)
|
||
|
|
c412: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
c416: 095b lsrs r3, r3, #5
|
||
|
|
c418: 2001 movs r0, #1
|
||
|
|
c41a: fa00 f202 lsl.w r2, r0, r2
|
||
|
|
c41e: f841 2023 str.w r2, [r1, r3, lsl #2]
|
||
|
|
__COMPILER_BARRIER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
c422: bf00 nop
|
||
|
|
c424: 370c adds r7, #12
|
||
|
|
c426: 46bd mov sp, r7
|
||
|
|
c428: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
c42c: 4770 bx lr
|
||
|
|
c42e: bf00 nop
|
||
|
|
c430: e000e100 .word 0xe000e100
|
||
|
|
|
||
|
|
0000c434 <__NVIC_DisableIRQ>:
|
||
|
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||
|
|
\param [in] IRQn Device specific interrupt number.
|
||
|
|
\note IRQn must not be negative.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||
|
|
{
|
||
|
|
c434: b480 push {r7}
|
||
|
|
c436: b083 sub sp, #12
|
||
|
|
c438: af00 add r7, sp, #0
|
||
|
|
c43a: 4603 mov r3, r0
|
||
|
|
c43c: 71fb strb r3, [r7, #7]
|
||
|
|
if ((int32_t)(IRQn) >= 0)
|
||
|
|
c43e: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
c442: 2b00 cmp r3, #0
|
||
|
|
c444: db12 blt.n c46c <__NVIC_DisableIRQ+0x38>
|
||
|
|
{
|
||
|
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||
|
|
c446: 79fb ldrb r3, [r7, #7]
|
||
|
|
c448: f003 021f and.w r2, r3, #31
|
||
|
|
c44c: 490a ldr r1, [pc, #40] ; (c478 <__NVIC_DisableIRQ+0x44>)
|
||
|
|
c44e: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
c452: 095b lsrs r3, r3, #5
|
||
|
|
c454: 2001 movs r0, #1
|
||
|
|
c456: fa00 f202 lsl.w r2, r0, r2
|
||
|
|
c45a: 3320 adds r3, #32
|
||
|
|
c45c: f841 2023 str.w r2, [r1, r3, lsl #2]
|
||
|
|
\details Acts as a special kind of Data Memory Barrier.
|
||
|
|
It completes when all explicit memory accesses before this instruction complete.
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __DSB(void)
|
||
|
|
{
|
||
|
|
__ASM volatile ("dsb 0xF":::"memory");
|
||
|
|
c460: f3bf 8f4f dsb sy
|
||
|
|
}
|
||
|
|
c464: bf00 nop
|
||
|
|
__ASM volatile ("isb 0xF":::"memory");
|
||
|
|
c466: f3bf 8f6f isb sy
|
||
|
|
}
|
||
|
|
c46a: bf00 nop
|
||
|
|
__DSB();
|
||
|
|
__ISB();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
c46c: bf00 nop
|
||
|
|
c46e: 370c adds r7, #12
|
||
|
|
c470: 46bd mov sp, r7
|
||
|
|
c472: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
c476: 4770 bx lr
|
||
|
|
c478: e000e100 .word 0xe000e100
|
||
|
|
|
||
|
|
0000c47c <main>:
|
||
|
|
//
|
||
|
|
// Main
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
int main(void)
|
||
|
|
{
|
||
|
|
c47c: b580 push {r7, lr}
|
||
|
|
c47e: f6ad 2d28 subw sp, sp, #2600 ; 0xa28
|
||
|
|
c482: af00 add r7, sp, #0
|
||
|
|
|
||
|
|
bool baud_valid = false;
|
||
|
|
c484: 2300 movs r3, #0
|
||
|
|
c486: f887 3a27 strb.w r3, [r7, #2599] ; 0xa27
|
||
|
|
uint32_t bl_baud = 0x00;
|
||
|
|
c48a: 2300 movs r3, #0
|
||
|
|
c48c: f8c7 3a20 str.w r3, [r7, #2592] ; 0xa20
|
||
|
|
uint8_t bl_buffer[BL_UART_BUF_LEN] = {0};
|
||
|
|
c490: f107 0320 add.w r3, r7, #32
|
||
|
|
c494: 2200 movs r2, #0
|
||
|
|
c496: 601a str r2, [r3, #0]
|
||
|
|
c498: 3304 adds r3, #4
|
||
|
|
c49a: f640 12fc movw r2, #2556 ; 0x9fc
|
||
|
|
c49e: 2100 movs r1, #0
|
||
|
|
c4a0: 4618 mov r0, r3
|
||
|
|
c4a2: f001 f939 bl d718 <memset>
|
||
|
|
|
||
|
|
#define PLLEN_VER 1
|
||
|
|
uint8_t packet_ver_buf[PLLEN_VER] = {SVL_VERSION_NUMBER};
|
||
|
|
c4a6: f107 031c add.w r3, r7, #28
|
||
|
|
c4aa: 2205 movs r2, #5
|
||
|
|
c4ac: 701a strb r2, [r3, #0]
|
||
|
|
svl_packet_t svl_packet_version = {CMD_VERSION, packet_ver_buf, PLLEN_VER, PLLEN_VER};
|
||
|
|
c4ae: f107 0310 add.w r3, r7, #16
|
||
|
|
c4b2: 2201 movs r2, #1
|
||
|
|
c4b4: 701a strb r2, [r3, #0]
|
||
|
|
c4b6: f107 0310 add.w r3, r7, #16
|
||
|
|
c4ba: f107 021c add.w r2, r7, #28
|
||
|
|
c4be: 605a str r2, [r3, #4]
|
||
|
|
c4c0: f107 0310 add.w r3, r7, #16
|
||
|
|
c4c4: 2201 movs r2, #1
|
||
|
|
c4c6: 811a strh r2, [r3, #8]
|
||
|
|
c4c8: f107 0310 add.w r3, r7, #16
|
||
|
|
c4cc: 2201 movs r2, #1
|
||
|
|
c4ce: 815a strh r2, [r3, #10]
|
||
|
|
svl_packet_t svl_packet_blmode = {CMD_BLMODE, NULL, 0, 0};
|
||
|
|
c4d0: 1d3b adds r3, r7, #4
|
||
|
|
c4d2: 2202 movs r2, #2
|
||
|
|
c4d4: 701a strb r2, [r3, #0]
|
||
|
|
c4d6: 1d3b adds r3, r7, #4
|
||
|
|
c4d8: 2200 movs r2, #0
|
||
|
|
c4da: 605a str r2, [r3, #4]
|
||
|
|
c4dc: 1d3b adds r3, r7, #4
|
||
|
|
c4de: 2200 movs r2, #0
|
||
|
|
c4e0: 811a strh r2, [r3, #8]
|
||
|
|
c4e2: 1d3b adds r3, r7, #4
|
||
|
|
c4e4: 2200 movs r2, #0
|
||
|
|
c4e6: 815a strh r2, [r3, #10]
|
||
|
|
|
||
|
|
art_svl_ringbuf_init(&bl_rx_ringbuf, bl_buffer, BL_UART_BUF_LEN);
|
||
|
|
c4e8: f107 0320 add.w r3, r7, #32
|
||
|
|
c4ec: f44f 6220 mov.w r2, #2560 ; 0xa00
|
||
|
|
c4f0: 4619 mov r1, r3
|
||
|
|
c4f2: 4827 ldr r0, [pc, #156] ; (c590 <main+0x114>)
|
||
|
|
c4f4: f000 ff18 bl d328 <art_svl_ringbuf_init>
|
||
|
|
setup();
|
||
|
|
c4f8: f000 f85a bl c5b0 <setup>
|
||
|
|
|
||
|
|
debug_printf("\n\nArtemis SVL Bootloader - DEBUG\n\n");
|
||
|
|
c4fc: 4825 ldr r0, [pc, #148] ; (c594 <main+0x118>)
|
||
|
|
c4fe: f000 fb6b bl cbd8 <debug_printf>
|
||
|
|
|
||
|
|
baud_valid = detect_baud_rate(&bl_baud); // Detects the baud rate. Returns true if a valid baud rate was found
|
||
|
|
c502: f507 6322 add.w r3, r7, #2592 ; 0xa20
|
||
|
|
c506: 4618 mov r0, r3
|
||
|
|
c508: f000 f888 bl c61c <detect_baud_rate>
|
||
|
|
c50c: 4603 mov r3, r0
|
||
|
|
c50e: f887 3a27 strb.w r3, [r7, #2599] ; 0xa27
|
||
|
|
if (baud_valid == false)
|
||
|
|
c512: f897 3a27 ldrb.w r3, [r7, #2599] ; 0xa27
|
||
|
|
c516: f083 0301 eor.w r3, r3, #1
|
||
|
|
c51a: b2db uxtb r3, r3
|
||
|
|
c51c: 2b00 cmp r3, #0
|
||
|
|
c51e: d001 beq.n c524 <main+0xa8>
|
||
|
|
{
|
||
|
|
app_start(); // w/o valid baud rate jump t the app
|
||
|
|
c520: f000 fb42 bl cba8 <app_start>
|
||
|
|
}
|
||
|
|
|
||
|
|
start_uart_bl(bl_baud); // This will create a 23 us wide low 'blip' on the TX line (until possibly fixed)
|
||
|
|
c524: f8d7 3a20 ldr.w r3, [r7, #2592] ; 0xa20
|
||
|
|
c528: 4618 mov r0, r3
|
||
|
|
c52a: f000 f9b7 bl c89c <start_uart_bl>
|
||
|
|
am_util_delay_us(200); // At the minimum baud rate of 115200 one byte (10 bits with start/stop) takes 10/115200 or 87 us. 87+23 = 100, double to be safe
|
||
|
|
c52e: 20c8 movs r0, #200 ; 0xc8
|
||
|
|
c530: f000 fbee bl cd10 <am_util_delay_us>
|
||
|
|
|
||
|
|
debug_printf("phase:\tconfirm bootloading entry\n");
|
||
|
|
c534: 4818 ldr r0, [pc, #96] ; (c598 <main+0x11c>)
|
||
|
|
c536: f000 fb4f bl cbd8 <debug_printf>
|
||
|
|
debug_printf("\tsending Artemis SVL version packet\n");
|
||
|
|
c53a: 4818 ldr r0, [pc, #96] ; (c59c <main+0x120>)
|
||
|
|
c53c: f000 fb4c bl cbd8 <debug_printf>
|
||
|
|
svl_packet_send(&svl_packet_version); // when baud rate is determined send the version packet
|
||
|
|
c540: f107 0310 add.w r3, r7, #16
|
||
|
|
c544: 4618 mov r0, r3
|
||
|
|
c546: f000 fc9f bl ce88 <svl_packet_send>
|
||
|
|
|
||
|
|
debug_printf("\twaiting for bootloader confirmation\n");
|
||
|
|
c54a: 4815 ldr r0, [pc, #84] ; (c5a0 <main+0x124>)
|
||
|
|
c54c: f000 fb44 bl cbd8 <debug_printf>
|
||
|
|
if (svl_packet_wait(&svl_packet_blmode) != 0)
|
||
|
|
c550: 1d3b adds r3, r7, #4
|
||
|
|
c552: 4618 mov r0, r3
|
||
|
|
c554: f000 fd90 bl d078 <svl_packet_wait>
|
||
|
|
c558: 4603 mov r3, r0
|
||
|
|
c55a: 2b00 cmp r3, #0
|
||
|
|
c55c: d004 beq.n c568 <main+0xec>
|
||
|
|
{ // wait for the bootloader to confirm bootloader mode entry
|
||
|
|
debug_printf("\tno confirmation received\n");
|
||
|
|
c55e: 4811 ldr r0, [pc, #68] ; (c5a4 <main+0x128>)
|
||
|
|
c560: f000 fb3a bl cbd8 <debug_printf>
|
||
|
|
app_start(); // break to app
|
||
|
|
c564: f000 fb20 bl cba8 <app_start>
|
||
|
|
}
|
||
|
|
debug_printf("\tentering bootloader\n\n");
|
||
|
|
c568: 480f ldr r0, [pc, #60] ; (c5a8 <main+0x12c>)
|
||
|
|
c56a: f000 fb35 bl cbd8 <debug_printf>
|
||
|
|
|
||
|
|
enter_bootload(); // Now we are locked in
|
||
|
|
c56e: f000 f9ff bl c970 <enter_bootload>
|
||
|
|
am_util_delay_ms(10);
|
||
|
|
c572: 200a movs r0, #10
|
||
|
|
c574: f000 fbae bl ccd4 <am_util_delay_ms>
|
||
|
|
|
||
|
|
am_hal_reset_control(AM_HAL_RESET_CONTROL_SWPOI, 0); //Cause a system Power On Init to release as much of the stack as possible
|
||
|
|
c578: 2100 movs r1, #0
|
||
|
|
c57a: 2001 movs r0, #1
|
||
|
|
c57c: f001 fd56 bl e02c <am_hal_reset_control>
|
||
|
|
|
||
|
|
debug_printf("ERROR - runoff");
|
||
|
|
c580: 480a ldr r0, [pc, #40] ; (c5ac <main+0x130>)
|
||
|
|
c582: f000 fb29 bl cbd8 <debug_printf>
|
||
|
|
while (1)
|
||
|
|
{ // Loop forever while sleeping.
|
||
|
|
am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP); // Go to Deep Sleep.
|
||
|
|
c586: 2001 movs r0, #1
|
||
|
|
c588: f001 fd9a bl e0c0 <am_hal_sysctrl_sleep>
|
||
|
|
c58c: e7fb b.n c586 <main+0x10a>
|
||
|
|
c58e: bf00 nop
|
||
|
|
c590: 10000210 .word 0x10000210
|
||
|
|
c594: 0000eb40 .word 0x0000eb40
|
||
|
|
c598: 0000eb64 .word 0x0000eb64
|
||
|
|
c59c: 0000eb88 .word 0x0000eb88
|
||
|
|
c5a0: 0000ebb0 .word 0x0000ebb0
|
||
|
|
c5a4: 0000ebd8 .word 0x0000ebd8
|
||
|
|
c5a8: 0000ebf4 .word 0x0000ebf4
|
||
|
|
c5ac: 0000ec0c .word 0x0000ec0c
|
||
|
|
|
||
|
|
0000c5b0 <setup>:
|
||
|
|
//
|
||
|
|
// Setup
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void setup(void)
|
||
|
|
{
|
||
|
|
c5b0: b580 push {r7, lr}
|
||
|
|
c5b2: af00 add r7, sp, #0
|
||
|
|
// Set the clock frequency.
|
||
|
|
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
|
||
|
|
c5b4: 2100 movs r1, #0
|
||
|
|
c5b6: 2000 movs r0, #0
|
||
|
|
c5b8: f001 f9ca bl d950 <am_hal_clkgen_control>
|
||
|
|
|
||
|
|
// Set the default cache configuration
|
||
|
|
am_hal_cachectrl_config(&am_hal_cachectrl_defaults);
|
||
|
|
c5bc: 480b ldr r0, [pc, #44] ; (c5ec <setup+0x3c>)
|
||
|
|
c5be: f001 f999 bl d8f4 <am_hal_cachectrl_config>
|
||
|
|
am_hal_cachectrl_enable();
|
||
|
|
c5c2: f001 f9bb bl d93c <am_hal_cachectrl_enable>
|
||
|
|
|
||
|
|
// Configure the stimer
|
||
|
|
am_hal_stimer_int_enable(AM_HAL_STIMER_INT_OVERFLOW);
|
||
|
|
c5c6: f44f 7080 mov.w r0, #256 ; 0x100
|
||
|
|
c5ca: f001 fd5f bl e08c <am_hal_stimer_int_enable>
|
||
|
|
NVIC_EnableIRQ(STIMER_IRQn);
|
||
|
|
c5ce: 2016 movs r0, #22
|
||
|
|
c5d0: f7ff ff12 bl c3f8 <__NVIC_EnableIRQ>
|
||
|
|
am_hal_stimer_config(AM_HAL_STIMER_CFG_CLEAR | AM_HAL_STIMER_CFG_FREEZE);
|
||
|
|
c5d4: f04f 4040 mov.w r0, #3221225472 ; 0xc0000000
|
||
|
|
c5d8: f001 fd48 bl e06c <am_hal_stimer_config>
|
||
|
|
am_hal_stimer_config(AM_HAL_STIMER_HFRC_3MHZ);
|
||
|
|
c5dc: 2001 movs r0, #1
|
||
|
|
c5de: f001 fd45 bl e06c <am_hal_stimer_config>
|
||
|
|
#ifdef DEBUG
|
||
|
|
start_uart_debug();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// Enable interrupts.
|
||
|
|
am_hal_interrupt_master_enable();
|
||
|
|
c5e2: f001 fc99 bl df18 <am_hal_interrupt_master_enable>
|
||
|
|
}
|
||
|
|
c5e6: bf00 nop
|
||
|
|
c5e8: bd80 pop {r7, pc}
|
||
|
|
c5ea: bf00 nop
|
||
|
|
c5ec: 0000ee44 .word 0x0000ee44
|
||
|
|
|
||
|
|
0000c5f0 <unsetup>:
|
||
|
|
//
|
||
|
|
// Un-set-up
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void unsetup(void)
|
||
|
|
{
|
||
|
|
c5f0: b580 push {r7, lr}
|
||
|
|
c5f2: af00 add r7, sp, #0
|
||
|
|
disable_burst_mode();
|
||
|
|
c5f4: f001 f816 bl d624 <disable_burst_mode>
|
||
|
|
|
||
|
|
// Deconfigure the stimer
|
||
|
|
am_hal_stimer_int_disable(AM_HAL_STIMER_INT_OVERFLOW);
|
||
|
|
c5f8: f44f 7080 mov.w r0, #256 ; 0x100
|
||
|
|
c5fc: f001 fd50 bl e0a0 <am_hal_stimer_int_disable>
|
||
|
|
NVIC_DisableIRQ(STIMER_IRQn);
|
||
|
|
c600: 2016 movs r0, #22
|
||
|
|
c602: f7ff ff17 bl c434 <__NVIC_DisableIRQ>
|
||
|
|
am_hal_stimer_config(AM_HAL_STIMER_CFG_CLEAR | AM_HAL_STIMER_CFG_FREEZE);
|
||
|
|
c606: f04f 4040 mov.w r0, #3221225472 ; 0xc0000000
|
||
|
|
c60a: f001 fd2f bl e06c <am_hal_stimer_config>
|
||
|
|
am_hal_stimer_config(AM_HAL_STIMER_NO_CLK);
|
||
|
|
c60e: 2000 movs r0, #0
|
||
|
|
c610: f001 fd2c bl e06c <am_hal_stimer_config>
|
||
|
|
#ifdef DEBUG
|
||
|
|
stop_uart_debug();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// Disable interrupts.
|
||
|
|
am_hal_interrupt_master_disable();
|
||
|
|
c614: f001 fc84 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
}
|
||
|
|
c618: bf00 nop
|
||
|
|
c61a: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0000c61c <detect_baud_rate>:
|
||
|
|
//
|
||
|
|
// Baud Rate Detect Phase
|
||
|
|
//
|
||
|
|
// ****************************************
|
||
|
|
bool detect_baud_rate(uint32_t *baud)
|
||
|
|
{
|
||
|
|
c61c: b580 push {r7, lr}
|
||
|
|
c61e: b088 sub sp, #32
|
||
|
|
c620: af00 add r7, sp, #0
|
||
|
|
c622: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t bl_entry_timeout_ms = 200;
|
||
|
|
c624: 23c8 movs r3, #200 ; 0xc8
|
||
|
|
c626: 613b str r3, [r7, #16]
|
||
|
|
uint32_t bl_entry_timeout_start = millis();
|
||
|
|
c628: f000 ffce bl d5c8 <millis>
|
||
|
|
c62c: 60f8 str r0, [r7, #12]
|
||
|
|
bool baud_is_valid = false;
|
||
|
|
c62e: 2300 movs r3, #0
|
||
|
|
c630: 77fb strb r3, [r7, #31]
|
||
|
|
bool timed_out = true;
|
||
|
|
c632: 2301 movs r3, #1
|
||
|
|
c634: 77bb strb r3, [r7, #30]
|
||
|
|
|
||
|
|
debug_printf("phase:\tdetect baud rate\n");
|
||
|
|
c636: 488f ldr r0, [pc, #572] ; (c874 <detect_baud_rate+0x258>)
|
||
|
|
c638: f000 face bl cbd8 <debug_printf>
|
||
|
|
|
||
|
|
enable_burst_mode();
|
||
|
|
c63c: f000 ffd8 bl d5f0 <enable_burst_mode>
|
||
|
|
|
||
|
|
am_hal_gpio_pinconfig(BL_RX_PAD, g_AM_HAL_GPIO_INPUT_PULLUP);
|
||
|
|
c640: 4b8d ldr r3, [pc, #564] ; (c878 <detect_baud_rate+0x25c>)
|
||
|
|
c642: 6819 ldr r1, [r3, #0]
|
||
|
|
c644: 2031 movs r0, #49 ; 0x31
|
||
|
|
c646: f001 fabf bl dbc8 <am_hal_gpio_pinconfig>
|
||
|
|
|
||
|
|
ap3_gpio_enable_interrupts(BL_RX_PAD, AM_HAL_GPIO_PIN_INTDIR_LO2HI);
|
||
|
|
c64a: 2100 movs r1, #0
|
||
|
|
c64c: 2031 movs r0, #49 ; 0x31
|
||
|
|
c64e: f000 ffff bl d650 <ap3_gpio_enable_interrupts>
|
||
|
|
am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(BL_RX_PAD));
|
||
|
|
c652: f04f 0000 mov.w r0, #0
|
||
|
|
c656: f44f 3100 mov.w r1, #131072 ; 0x20000
|
||
|
|
c65a: f001 fc3f bl dedc <am_hal_gpio_interrupt_clear>
|
||
|
|
am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(BL_RX_PAD));
|
||
|
|
c65e: f04f 0000 mov.w r0, #0
|
||
|
|
c662: f44f 3100 mov.w r1, #131072 ; 0x20000
|
||
|
|
c666: f001 fbef bl de48 <am_hal_gpio_interrupt_enable>
|
||
|
|
NVIC_EnableIRQ(GPIO_IRQn);
|
||
|
|
c66a: 200d movs r0, #13
|
||
|
|
c66c: f7ff fec4 bl c3f8 <__NVIC_EnableIRQ>
|
||
|
|
|
||
|
|
while ((millis() - bl_entry_timeout_start) < bl_entry_timeout_ms)
|
||
|
|
c670: e0c9 b.n c806 <detect_baud_rate+0x1ea>
|
||
|
|
{
|
||
|
|
// try to detect baud rate
|
||
|
|
|
||
|
|
// debug_printf("\ttime (ms):\t%d\n", millis());
|
||
|
|
|
||
|
|
if (bl_baud_ticks_index == BL_BAUD_SAMPLES)
|
||
|
|
c672: 4b82 ldr r3, [pc, #520] ; (c87c <detect_baud_rate+0x260>)
|
||
|
|
c674: 781b ldrb r3, [r3, #0]
|
||
|
|
c676: b2db uxtb r3, r3
|
||
|
|
c678: 2b05 cmp r3, #5
|
||
|
|
c67a: f040 80c4 bne.w c806 <detect_baud_rate+0x1ea>
|
||
|
|
{
|
||
|
|
|
||
|
|
// compute differences between samples
|
||
|
|
for (uint8_t indi = 0; indi < (BL_BAUD_SAMPLES - 1); indi++)
|
||
|
|
c67e: 2300 movs r3, #0
|
||
|
|
c680: 777b strb r3, [r7, #29]
|
||
|
|
c682: e010 b.n c6a6 <detect_baud_rate+0x8a>
|
||
|
|
{
|
||
|
|
bl_baud_ticks[indi] = bl_baud_ticks[indi + 1] - bl_baud_ticks[indi];
|
||
|
|
c684: 7f7b ldrb r3, [r7, #29]
|
||
|
|
c686: 3301 adds r3, #1
|
||
|
|
c688: 4a7d ldr r2, [pc, #500] ; (c880 <detect_baud_rate+0x264>)
|
||
|
|
c68a: f852 1023 ldr.w r1, [r2, r3, lsl #2]
|
||
|
|
c68e: 7f7b ldrb r3, [r7, #29]
|
||
|
|
c690: 4a7b ldr r2, [pc, #492] ; (c880 <detect_baud_rate+0x264>)
|
||
|
|
c692: f852 2023 ldr.w r2, [r2, r3, lsl #2]
|
||
|
|
c696: 7f7b ldrb r3, [r7, #29]
|
||
|
|
c698: 1a8a subs r2, r1, r2
|
||
|
|
c69a: 4979 ldr r1, [pc, #484] ; (c880 <detect_baud_rate+0x264>)
|
||
|
|
c69c: f841 2023 str.w r2, [r1, r3, lsl #2]
|
||
|
|
for (uint8_t indi = 0; indi < (BL_BAUD_SAMPLES - 1); indi++)
|
||
|
|
c6a0: 7f7b ldrb r3, [r7, #29]
|
||
|
|
c6a2: 3301 adds r3, #1
|
||
|
|
c6a4: 777b strb r3, [r7, #29]
|
||
|
|
c6a6: 7f7b ldrb r3, [r7, #29]
|
||
|
|
c6a8: 2b03 cmp r3, #3
|
||
|
|
c6aa: d9eb bls.n c684 <detect_baud_rate+0x68>
|
||
|
|
}
|
||
|
|
|
||
|
|
float mean = 0.0;
|
||
|
|
c6ac: f04f 0300 mov.w r3, #0
|
||
|
|
c6b0: 61bb str r3, [r7, #24]
|
||
|
|
for (uint8_t indi = 0; indi < (BL_BAUD_SAMPLES - 1); indi++)
|
||
|
|
c6b2: 2300 movs r3, #0
|
||
|
|
c6b4: 75fb strb r3, [r7, #23]
|
||
|
|
c6b6: e010 b.n c6da <detect_baud_rate+0xbe>
|
||
|
|
{
|
||
|
|
mean += bl_baud_ticks[indi];
|
||
|
|
c6b8: 7dfb ldrb r3, [r7, #23]
|
||
|
|
c6ba: 4a71 ldr r2, [pc, #452] ; (c880 <detect_baud_rate+0x264>)
|
||
|
|
c6bc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
||
|
|
c6c0: ee07 3a90 vmov s15, r3
|
||
|
|
c6c4: eef8 7a67 vcvt.f32.u32 s15, s15
|
||
|
|
c6c8: ed97 7a06 vldr s14, [r7, #24]
|
||
|
|
c6cc: ee77 7a27 vadd.f32 s15, s14, s15
|
||
|
|
c6d0: edc7 7a06 vstr s15, [r7, #24]
|
||
|
|
for (uint8_t indi = 0; indi < (BL_BAUD_SAMPLES - 1); indi++)
|
||
|
|
c6d4: 7dfb ldrb r3, [r7, #23]
|
||
|
|
c6d6: 3301 adds r3, #1
|
||
|
|
c6d8: 75fb strb r3, [r7, #23]
|
||
|
|
c6da: 7dfb ldrb r3, [r7, #23]
|
||
|
|
c6dc: 2b03 cmp r3, #3
|
||
|
|
c6de: d9eb bls.n c6b8 <detect_baud_rate+0x9c>
|
||
|
|
}
|
||
|
|
mean /= (BL_BAUD_SAMPLES - 1);
|
||
|
|
c6e0: ed97 7a06 vldr s14, [r7, #24]
|
||
|
|
c6e4: eef1 6a00 vmov.f32 s13, #16 ; 0x40800000 4.0
|
||
|
|
c6e8: eec7 7a26 vdiv.f32 s15, s14, s13
|
||
|
|
c6ec: edc7 7a06 vstr s15, [r7, #24]
|
||
|
|
|
||
|
|
if (mean < 3)
|
||
|
|
c6f0: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c6f4: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0
|
||
|
|
c6f8: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c6fc: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c700: d47b bmi.n c7fa <detect_baud_rate+0x1de>
|
||
|
|
{
|
||
|
|
// invalid
|
||
|
|
}
|
||
|
|
else if ((mean >= 4) && (mean <= 8))
|
||
|
|
c702: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c706: eeb1 7a00 vmov.f32 s14, #16 ; 0x40800000 4.0
|
||
|
|
c70a: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c70e: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c712: db0f blt.n c734 <detect_baud_rate+0x118>
|
||
|
|
c714: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c718: eeb2 7a00 vmov.f32 s14, #32 ; 0x41000000 8.0
|
||
|
|
c71c: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c720: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c724: d806 bhi.n c734 <detect_baud_rate+0x118>
|
||
|
|
{
|
||
|
|
*baud = 921600;
|
||
|
|
c726: 687b ldr r3, [r7, #4]
|
||
|
|
c728: f44f 2261 mov.w r2, #921600 ; 0xe1000
|
||
|
|
c72c: 601a str r2, [r3, #0]
|
||
|
|
baud_is_valid = true;
|
||
|
|
c72e: 2301 movs r3, #1
|
||
|
|
c730: 77fb strb r3, [r7, #31]
|
||
|
|
c732: e062 b.n c7fa <detect_baud_rate+0x1de>
|
||
|
|
}
|
||
|
|
else if ((mean >= 10) && (mean <= 14))
|
||
|
|
c734: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c738: eeb2 7a04 vmov.f32 s14, #36 ; 0x41200000 10.0
|
||
|
|
c73c: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c740: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c744: db0f blt.n c766 <detect_baud_rate+0x14a>
|
||
|
|
c746: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c74a: eeb2 7a0c vmov.f32 s14, #44 ; 0x41600000 14.0
|
||
|
|
c74e: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c752: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c756: d806 bhi.n c766 <detect_baud_rate+0x14a>
|
||
|
|
{
|
||
|
|
*baud = 460800;
|
||
|
|
c758: 687b ldr r3, [r7, #4]
|
||
|
|
c75a: f44f 22e1 mov.w r2, #460800 ; 0x70800
|
||
|
|
c75e: 601a str r2, [r3, #0]
|
||
|
|
baud_is_valid = true;
|
||
|
|
c760: 2301 movs r3, #1
|
||
|
|
c762: 77fb strb r3, [r7, #31]
|
||
|
|
c764: e049 b.n c7fa <detect_baud_rate+0x1de>
|
||
|
|
}
|
||
|
|
else if ((mean >= 25) && (mean <= 30))
|
||
|
|
c766: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c76a: eeb3 7a09 vmov.f32 s14, #57 ; 0x41c80000 25.0
|
||
|
|
c76e: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c772: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c776: db0f blt.n c798 <detect_baud_rate+0x17c>
|
||
|
|
c778: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c77c: eeb3 7a0e vmov.f32 s14, #62 ; 0x41f00000 30.0
|
||
|
|
c780: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c784: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c788: d806 bhi.n c798 <detect_baud_rate+0x17c>
|
||
|
|
{
|
||
|
|
*baud = 230400;
|
||
|
|
c78a: 687b ldr r3, [r7, #4]
|
||
|
|
c78c: f44f 3261 mov.w r2, #230400 ; 0x38400
|
||
|
|
c790: 601a str r2, [r3, #0]
|
||
|
|
baud_is_valid = true;
|
||
|
|
c792: 2301 movs r3, #1
|
||
|
|
c794: 77fb strb r3, [r7, #31]
|
||
|
|
c796: e030 b.n c7fa <detect_baud_rate+0x1de>
|
||
|
|
}
|
||
|
|
else if ((mean >= 45) && (mean <= 55))
|
||
|
|
c798: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c79c: ed9f 7a39 vldr s14, [pc, #228] ; c884 <detect_baud_rate+0x268>
|
||
|
|
c7a0: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c7a4: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c7a8: db0f blt.n c7ca <detect_baud_rate+0x1ae>
|
||
|
|
c7aa: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c7ae: ed9f 7a36 vldr s14, [pc, #216] ; c888 <detect_baud_rate+0x26c>
|
||
|
|
c7b2: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c7b6: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c7ba: d806 bhi.n c7ca <detect_baud_rate+0x1ae>
|
||
|
|
{
|
||
|
|
*baud = 115200;
|
||
|
|
c7bc: 687b ldr r3, [r7, #4]
|
||
|
|
c7be: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
||
|
|
c7c2: 601a str r2, [r3, #0]
|
||
|
|
baud_is_valid = true;
|
||
|
|
c7c4: 2301 movs r3, #1
|
||
|
|
c7c6: 77fb strb r3, [r7, #31]
|
||
|
|
c7c8: e017 b.n c7fa <detect_baud_rate+0x1de>
|
||
|
|
}
|
||
|
|
else if ((mean >= 91) && (mean <= 111))
|
||
|
|
c7ca: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c7ce: ed9f 7a2f vldr s14, [pc, #188] ; c88c <detect_baud_rate+0x270>
|
||
|
|
c7d2: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c7d6: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c7da: db0e blt.n c7fa <detect_baud_rate+0x1de>
|
||
|
|
c7dc: edd7 7a06 vldr s15, [r7, #24]
|
||
|
|
c7e0: ed9f 7a2b vldr s14, [pc, #172] ; c890 <detect_baud_rate+0x274>
|
||
|
|
c7e4: eef4 7ac7 vcmpe.f32 s15, s14
|
||
|
|
c7e8: eef1 fa10 vmrs APSR_nzcv, fpscr
|
||
|
|
c7ec: d805 bhi.n c7fa <detect_baud_rate+0x1de>
|
||
|
|
{
|
||
|
|
*baud = 57600;
|
||
|
|
c7ee: 687b ldr r3, [r7, #4]
|
||
|
|
c7f0: f44f 4261 mov.w r2, #57600 ; 0xe100
|
||
|
|
c7f4: 601a str r2, [r3, #0]
|
||
|
|
baud_is_valid = true;
|
||
|
|
c7f6: 2301 movs r3, #1
|
||
|
|
c7f8: 77fb strb r3, [r7, #31]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
// invalid
|
||
|
|
}
|
||
|
|
|
||
|
|
if (baud_is_valid)
|
||
|
|
c7fa: 7ffb ldrb r3, [r7, #31]
|
||
|
|
c7fc: 2b00 cmp r3, #0
|
||
|
|
c7fe: d00c beq.n c81a <detect_baud_rate+0x1fe>
|
||
|
|
{
|
||
|
|
timed_out = false;
|
||
|
|
c800: 2300 movs r3, #0
|
||
|
|
c802: 77bb strb r3, [r7, #30]
|
||
|
|
}
|
||
|
|
|
||
|
|
break; // exit the timeout loop
|
||
|
|
c804: e009 b.n c81a <detect_baud_rate+0x1fe>
|
||
|
|
while ((millis() - bl_entry_timeout_start) < bl_entry_timeout_ms)
|
||
|
|
c806: f000 fedf bl d5c8 <millis>
|
||
|
|
c80a: 4602 mov r2, r0
|
||
|
|
c80c: 68fb ldr r3, [r7, #12]
|
||
|
|
c80e: 1ad3 subs r3, r2, r3
|
||
|
|
c810: 693a ldr r2, [r7, #16]
|
||
|
|
c812: 429a cmp r2, r3
|
||
|
|
c814: f63f af2d bhi.w c672 <detect_baud_rate+0x56>
|
||
|
|
c818: e000 b.n c81c <detect_baud_rate+0x200>
|
||
|
|
break; // exit the timeout loop
|
||
|
|
c81a: bf00 nop
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
am_hal_gpio_interrupt_disable(AM_HAL_GPIO_BIT(BL_RX_PAD));
|
||
|
|
c81c: f04f 0000 mov.w r0, #0
|
||
|
|
c820: f44f 3100 mov.w r1, #131072 ; 0x20000
|
||
|
|
c824: f001 fb34 bl de90 <am_hal_gpio_interrupt_disable>
|
||
|
|
am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(BL_RX_PAD));
|
||
|
|
c828: f04f 0000 mov.w r0, #0
|
||
|
|
c82c: f44f 3100 mov.w r1, #131072 ; 0x20000
|
||
|
|
c830: f001 fb54 bl dedc <am_hal_gpio_interrupt_clear>
|
||
|
|
NVIC_DisableIRQ(GPIO_IRQn);
|
||
|
|
c834: 200d movs r0, #13
|
||
|
|
c836: f7ff fdfd bl c434 <__NVIC_DisableIRQ>
|
||
|
|
|
||
|
|
disable_burst_mode();
|
||
|
|
c83a: f000 fef3 bl d624 <disable_burst_mode>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
debug_printf("}\n");
|
||
|
|
#endif // DEBUG
|
||
|
|
|
||
|
|
if (!baud_is_valid)
|
||
|
|
c83e: 7ffb ldrb r3, [r7, #31]
|
||
|
|
c840: f083 0301 eor.w r3, r3, #1
|
||
|
|
c844: b2db uxtb r3, r3
|
||
|
|
c846: 2b00 cmp r3, #0
|
||
|
|
c848: d009 beq.n c85e <detect_baud_rate+0x242>
|
||
|
|
{
|
||
|
|
debug_printf("\tbaud rate not detected.\n\t\trising edges:\t%d\n\t\ttimed out:\t%d\n\n", bl_baud_ticks_index, timed_out);
|
||
|
|
c84a: 4b0c ldr r3, [pc, #48] ; (c87c <detect_baud_rate+0x260>)
|
||
|
|
c84c: 781b ldrb r3, [r3, #0]
|
||
|
|
c84e: b2db uxtb r3, r3
|
||
|
|
c850: 4619 mov r1, r3
|
||
|
|
c852: 7fbb ldrb r3, [r7, #30]
|
||
|
|
c854: 461a mov r2, r3
|
||
|
|
c856: 480f ldr r0, [pc, #60] ; (c894 <detect_baud_rate+0x278>)
|
||
|
|
c858: f000 f9be bl cbd8 <debug_printf>
|
||
|
|
c85c: e005 b.n c86a <detect_baud_rate+0x24e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
debug_printf("\tdetected valid baud rate:\t%d\n\n", *baud);
|
||
|
|
c85e: 687b ldr r3, [r7, #4]
|
||
|
|
c860: 681b ldr r3, [r3, #0]
|
||
|
|
c862: 4619 mov r1, r3
|
||
|
|
c864: 480c ldr r0, [pc, #48] ; (c898 <detect_baud_rate+0x27c>)
|
||
|
|
c866: f000 f9b7 bl cbd8 <debug_printf>
|
||
|
|
}
|
||
|
|
|
||
|
|
return baud_is_valid;
|
||
|
|
c86a: 7ffb ldrb r3, [r7, #31]
|
||
|
|
}
|
||
|
|
c86c: 4618 mov r0, r3
|
||
|
|
c86e: 3720 adds r7, #32
|
||
|
|
c870: 46bd mov sp, r7
|
||
|
|
c872: bd80 pop {r7, pc}
|
||
|
|
c874: 0000ec1c .word 0x0000ec1c
|
||
|
|
c878: 0000ee4c .word 0x0000ee4c
|
||
|
|
c87c: 10000224 .word 0x10000224
|
||
|
|
c880: 10000228 .word 0x10000228
|
||
|
|
c884: 42340000 .word 0x42340000
|
||
|
|
c888: 425c0000 .word 0x425c0000
|
||
|
|
c88c: 42b60000 .word 0x42b60000
|
||
|
|
c890: 42de0000 .word 0x42de0000
|
||
|
|
c894: 0000ec38 .word 0x0000ec38
|
||
|
|
c898: 0000ec78 .word 0x0000ec78
|
||
|
|
|
||
|
|
0000c89c <start_uart_bl>:
|
||
|
|
//
|
||
|
|
// Start BL UART at desired baud
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void start_uart_bl(uint32_t baud)
|
||
|
|
{
|
||
|
|
c89c: b580 push {r7, lr}
|
||
|
|
c89e: b08e sub sp, #56 ; 0x38
|
||
|
|
c8a0: af00 add r7, sp, #0
|
||
|
|
c8a2: 6078 str r0, [r7, #4]
|
||
|
|
const am_hal_gpio_pincfg_t bl_uart_tx_pinconfig = UART_GPIO_PINCONFIG(BL_UART_INST, TX, BL_TX_PAD);
|
||
|
|
c8a4: 2300 movs r3, #0
|
||
|
|
c8a6: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
const am_hal_gpio_pincfg_t bl_uart_rx_pinconfig = UART_GPIO_PINCONFIG(BL_UART_INST, RX, BL_RX_PAD);
|
||
|
|
c8a8: 2300 movs r3, #0
|
||
|
|
c8aa: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
am_hal_uart_config_t bl_uart_config =
|
||
|
|
c8ac: 687b ldr r3, [r7, #4]
|
||
|
|
c8ae: 60bb str r3, [r7, #8]
|
||
|
|
c8b0: 2360 movs r3, #96 ; 0x60
|
||
|
|
c8b2: 60fb str r3, [r7, #12]
|
||
|
|
c8b4: 2300 movs r3, #0
|
||
|
|
c8b6: 613b str r3, [r7, #16]
|
||
|
|
c8b8: 2300 movs r3, #0
|
||
|
|
c8ba: 617b str r3, [r7, #20]
|
||
|
|
c8bc: 2300 movs r3, #0
|
||
|
|
c8be: 61bb str r3, [r7, #24]
|
||
|
|
c8c0: 2312 movs r3, #18
|
||
|
|
c8c2: 61fb str r3, [r7, #28]
|
||
|
|
c8c4: 2300 movs r3, #0
|
||
|
|
c8c6: 623b str r3, [r7, #32]
|
||
|
|
c8c8: 2300 movs r3, #0
|
||
|
|
c8ca: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
c8cc: 2300 movs r3, #0
|
||
|
|
c8ce: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
c8d0: 2300 movs r3, #0
|
||
|
|
c8d2: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
.pui8RxBuffer = NULL,
|
||
|
|
.ui32RxBufferSize = 0,
|
||
|
|
};
|
||
|
|
|
||
|
|
// Initialize the printf interface for UART output.
|
||
|
|
am_hal_uart_initialize(BL_UART_INST, &hUART_bl);
|
||
|
|
c8d4: 491f ldr r1, [pc, #124] ; (c954 <start_uart_bl+0xb8>)
|
||
|
|
c8d6: 2000 movs r0, #0
|
||
|
|
c8d8: f001 fc2a bl e130 <am_hal_uart_initialize>
|
||
|
|
am_hal_uart_power_control(hUART_bl, AM_HAL_SYSCTRL_WAKE, false);
|
||
|
|
c8dc: 4b1d ldr r3, [pc, #116] ; (c954 <start_uart_bl+0xb8>)
|
||
|
|
c8de: 681b ldr r3, [r3, #0]
|
||
|
|
c8e0: 2200 movs r2, #0
|
||
|
|
c8e2: 2100 movs r1, #0
|
||
|
|
c8e4: 4618 mov r0, r3
|
||
|
|
c8e6: f001 fc4b bl e180 <am_hal_uart_power_control>
|
||
|
|
am_hal_uart_configure(hUART_bl, &bl_uart_config);
|
||
|
|
c8ea: 4b1a ldr r3, [pc, #104] ; (c954 <start_uart_bl+0xb8>)
|
||
|
|
c8ec: 681b ldr r3, [r3, #0]
|
||
|
|
c8ee: f107 0208 add.w r2, r7, #8
|
||
|
|
c8f2: 4611 mov r1, r2
|
||
|
|
c8f4: 4618 mov r0, r3
|
||
|
|
c8f6: f001 fcbb bl e270 <am_hal_uart_configure>
|
||
|
|
|
||
|
|
// Disable that pesky FIFO
|
||
|
|
UARTn(BL_UART_INST)->LCRH_b.FEN = 0;
|
||
|
|
c8fa: 4a17 ldr r2, [pc, #92] ; (c958 <start_uart_bl+0xbc>)
|
||
|
|
c8fc: f892 302c ldrb.w r3, [r2, #44] ; 0x2c
|
||
|
|
c900: f36f 1304 bfc r3, #4, #1
|
||
|
|
c904: f882 302c strb.w r3, [r2, #44] ; 0x2c
|
||
|
|
|
||
|
|
// Enable the UART pins.
|
||
|
|
am_hal_gpio_pinconfig(BL_TX_PAD, bl_uart_tx_pinconfig);
|
||
|
|
c908: 6b79 ldr r1, [r7, #52] ; 0x34
|
||
|
|
c90a: 2030 movs r0, #48 ; 0x30
|
||
|
|
c90c: f001 f95c bl dbc8 <am_hal_gpio_pinconfig>
|
||
|
|
am_hal_gpio_pinconfig(BL_RX_PAD, bl_uart_rx_pinconfig);
|
||
|
|
c910: 6b39 ldr r1, [r7, #48] ; 0x30
|
||
|
|
c912: 2031 movs r0, #49 ; 0x31
|
||
|
|
c914: f001 f958 bl dbc8 <am_hal_gpio_pinconfig>
|
||
|
|
|
||
|
|
// Enable interrupts.
|
||
|
|
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + BL_UART_INST));
|
||
|
|
c918: 200f movs r0, #15
|
||
|
|
c91a: f7ff fd6d bl c3f8 <__NVIC_EnableIRQ>
|
||
|
|
am_hal_uart_interrupt_enable(hUART_bl, (AM_HAL_UART_INT_RX));
|
||
|
|
c91e: 4b0d ldr r3, [pc, #52] ; (c954 <start_uart_bl+0xb8>)
|
||
|
|
c920: 681b ldr r3, [r3, #0]
|
||
|
|
c922: 2110 movs r1, #16
|
||
|
|
c924: 4618 mov r0, r3
|
||
|
|
c926: f002 f841 bl e9ac <am_hal_uart_interrupt_enable>
|
||
|
|
|
||
|
|
// Provide SVL Packet interfaces
|
||
|
|
svl_packet_link_read_fn(art_svl_ringbuf_read, &bl_rx_ringbuf);
|
||
|
|
c92a: 490c ldr r1, [pc, #48] ; (c95c <start_uart_bl+0xc0>)
|
||
|
|
c92c: 480c ldr r0, [pc, #48] ; (c960 <start_uart_bl+0xc4>)
|
||
|
|
c92e: f000 fa59 bl cde4 <svl_packet_link_read_fn>
|
||
|
|
svl_packet_link_avail_fn(art_svl_ringbuf_available, &bl_rx_ringbuf);
|
||
|
|
c932: 490a ldr r1, [pc, #40] ; (c95c <start_uart_bl+0xc0>)
|
||
|
|
c934: 480b ldr r0, [pc, #44] ; (c964 <start_uart_bl+0xc8>)
|
||
|
|
c936: f000 fa81 bl ce3c <svl_packet_link_avail_fn>
|
||
|
|
svl_packet_link_millis_fn(millis);
|
||
|
|
c93a: 480b ldr r0, [pc, #44] ; (c968 <start_uart_bl+0xcc>)
|
||
|
|
c93c: f000 fa94 bl ce68 <svl_packet_link_millis_fn>
|
||
|
|
svl_packet_link_write_fn(svl_uart_write_byte, hUART_bl);
|
||
|
|
c940: 4b04 ldr r3, [pc, #16] ; (c954 <start_uart_bl+0xb8>)
|
||
|
|
c942: 681b ldr r3, [r3, #0]
|
||
|
|
c944: 4619 mov r1, r3
|
||
|
|
c946: 4809 ldr r0, [pc, #36] ; (c96c <start_uart_bl+0xd0>)
|
||
|
|
c948: f000 fa62 bl ce10 <svl_packet_link_write_fn>
|
||
|
|
}
|
||
|
|
c94c: bf00 nop
|
||
|
|
c94e: 3738 adds r7, #56 ; 0x38
|
||
|
|
c950: 46bd mov sp, r7
|
||
|
|
c952: bd80 pop {r7, pc}
|
||
|
|
c954: 10000220 .word 0x10000220
|
||
|
|
c958: 4001c000 .word 0x4001c000
|
||
|
|
c95c: 10000210 .word 0x10000210
|
||
|
|
c960: 0000d475 .word 0x0000d475
|
||
|
|
c964: 0000d36b .word 0x0000d36b
|
||
|
|
c968: 0000d5c9 .word 0x0000d5c9
|
||
|
|
c96c: 0000d54d .word 0x0000d54d
|
||
|
|
|
||
|
|
0000c970 <enter_bootload>:
|
||
|
|
//
|
||
|
|
// Bootload phase
|
||
|
|
//
|
||
|
|
// ****************************************
|
||
|
|
void enter_bootload(void)
|
||
|
|
{
|
||
|
|
c970: b580 push {r7, lr}
|
||
|
|
c972: b08c sub sp, #48 ; 0x30
|
||
|
|
c974: af00 add r7, sp, #0
|
||
|
|
enable_burst_mode();
|
||
|
|
c976: f000 fe3b bl d5f0 <enable_burst_mode>
|
||
|
|
bool done = false;
|
||
|
|
c97a: 2300 movs r3, #0
|
||
|
|
c97c: f887 302f strb.w r3, [r7, #47] ; 0x2f
|
||
|
|
uint32_t frame_address = 0;
|
||
|
|
c980: 2300 movs r3, #0
|
||
|
|
c982: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
uint16_t last_page_erased = 0;
|
||
|
|
c984: 2300 movs r3, #0
|
||
|
|
c986: 84fb strh r3, [r7, #38] ; 0x26
|
||
|
|
uint8_t retransmit = 0;
|
||
|
|
c988: 2300 movs r3, #0
|
||
|
|
c98a: f887 302e strb.w r3, [r7, #46] ; 0x2e
|
||
|
|
static uint32_t frame_buffer[FRAME_BUFFER_SIZE];
|
||
|
|
|
||
|
|
svl_packet_t svl_packet_incoming_frame = {CMD_FRAME, (uint8_t *)frame_buffer, sizeof(frame_buffer) / sizeof(uint8_t), sizeof(frame_buffer) / sizeof(uint8_t)};
|
||
|
|
c98e: 4a41 ldr r2, [pc, #260] ; (ca94 <enter_bootload+0x124>)
|
||
|
|
c990: f107 0318 add.w r3, r7, #24
|
||
|
|
c994: ca07 ldmia r2, {r0, r1, r2}
|
||
|
|
c996: e883 0007 stmia.w r3, {r0, r1, r2}
|
||
|
|
svl_packet_t svl_packet_retry = {CMD_RETRY, NULL, 0, 0};
|
||
|
|
c99a: 2305 movs r3, #5
|
||
|
|
c99c: 733b strb r3, [r7, #12]
|
||
|
|
c99e: 2300 movs r3, #0
|
||
|
|
c9a0: 613b str r3, [r7, #16]
|
||
|
|
c9a2: 2300 movs r3, #0
|
||
|
|
c9a4: 82bb strh r3, [r7, #20]
|
||
|
|
c9a6: 2300 movs r3, #0
|
||
|
|
c9a8: 82fb strh r3, [r7, #22]
|
||
|
|
svl_packet_t svl_packet_next = {CMD_NEXT, NULL, 0, 0};
|
||
|
|
c9aa: 2303 movs r3, #3
|
||
|
|
c9ac: 703b strb r3, [r7, #0]
|
||
|
|
c9ae: 2300 movs r3, #0
|
||
|
|
c9b0: 607b str r3, [r7, #4]
|
||
|
|
c9b2: 2300 movs r3, #0
|
||
|
|
c9b4: 813b strh r3, [r7, #8]
|
||
|
|
c9b6: 2300 movs r3, #0
|
||
|
|
c9b8: 817b strh r3, [r7, #10]
|
||
|
|
|
||
|
|
debug_printf("phase:\tbootload\n");
|
||
|
|
c9ba: 4837 ldr r0, [pc, #220] ; (ca98 <enter_bootload+0x128>)
|
||
|
|
c9bc: f000 f90c bl cbd8 <debug_printf>
|
||
|
|
|
||
|
|
while (!done)
|
||
|
|
c9c0: e05c b.n ca7c <enter_bootload+0x10c>
|
||
|
|
{
|
||
|
|
|
||
|
|
if (retransmit != 0)
|
||
|
|
c9c2: f897 302e ldrb.w r3, [r7, #46] ; 0x2e
|
||
|
|
c9c6: 2b00 cmp r3, #0
|
||
|
|
c9c8: d008 beq.n c9dc <enter_bootload+0x6c>
|
||
|
|
{
|
||
|
|
debug_printf("\trequesting retransmission\n");
|
||
|
|
c9ca: 4834 ldr r0, [pc, #208] ; (ca9c <enter_bootload+0x12c>)
|
||
|
|
c9cc: f000 f904 bl cbd8 <debug_printf>
|
||
|
|
svl_packet_send((svl_packet_t *)&svl_packet_retry); // Ask to retransmit
|
||
|
|
c9d0: f107 030c add.w r3, r7, #12
|
||
|
|
c9d4: 4618 mov r0, r3
|
||
|
|
c9d6: f000 fa57 bl ce88 <svl_packet_send>
|
||
|
|
c9da: e006 b.n c9ea <enter_bootload+0x7a>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
debug_printf("\trequesting next app frame\n");
|
||
|
|
c9dc: 4830 ldr r0, [pc, #192] ; (caa0 <enter_bootload+0x130>)
|
||
|
|
c9de: f000 f8fb bl cbd8 <debug_printf>
|
||
|
|
svl_packet_send((svl_packet_t *)&svl_packet_next); // Ask for the next frame packet
|
||
|
|
c9e2: 463b mov r3, r7
|
||
|
|
c9e4: 4618 mov r0, r3
|
||
|
|
c9e6: f000 fa4f bl ce88 <svl_packet_send>
|
||
|
|
}
|
||
|
|
retransmit = 0;
|
||
|
|
c9ea: 2300 movs r3, #0
|
||
|
|
c9ec: f887 302e strb.w r3, [r7, #46] ; 0x2e
|
||
|
|
|
||
|
|
uint8_t stat = svl_packet_wait(&svl_packet_incoming_frame);
|
||
|
|
c9f0: f107 0318 add.w r3, r7, #24
|
||
|
|
c9f4: 4618 mov r0, r3
|
||
|
|
c9f6: f000 fb3f bl d078 <svl_packet_wait>
|
||
|
|
c9fa: 4603 mov r3, r0
|
||
|
|
c9fc: f887 302d strb.w r3, [r7, #45] ; 0x2d
|
||
|
|
if (stat != 0)
|
||
|
|
ca00: f897 302d ldrb.w r3, [r7, #45] ; 0x2d
|
||
|
|
ca04: 2b00 cmp r3, #0
|
||
|
|
ca06: d012 beq.n ca2e <enter_bootload+0xbe>
|
||
|
|
{ // wait for either a frame or the done command
|
||
|
|
debug_printf("\t\terror receiving packet (%d)\n", stat);
|
||
|
|
ca08: f897 302d ldrb.w r3, [r7, #45] ; 0x2d
|
||
|
|
ca0c: 4619 mov r1, r3
|
||
|
|
ca0e: 4825 ldr r0, [pc, #148] ; (caa4 <enter_bootload+0x134>)
|
||
|
|
ca10: f000 f8e2 bl cbd8 <debug_printf>
|
||
|
|
retransmit = 1;
|
||
|
|
ca14: 2301 movs r3, #1
|
||
|
|
ca16: f887 302e strb.w r3, [r7, #46] ; 0x2e
|
||
|
|
am_util_delay_us(177000); //Worst case: wait 177ms for 2048 byte transfer at 115200bps to complete
|
||
|
|
ca1a: 4823 ldr r0, [pc, #140] ; (caa8 <enter_bootload+0x138>)
|
||
|
|
ca1c: f000 f978 bl cd10 <am_util_delay_us>
|
||
|
|
|
||
|
|
//Flush the buffers to remove any inbound or outbound garbage
|
||
|
|
bl_rx_ringbuf.r_offset = 0;
|
||
|
|
ca20: 4b22 ldr r3, [pc, #136] ; (caac <enter_bootload+0x13c>)
|
||
|
|
ca22: 2200 movs r2, #0
|
||
|
|
ca24: 609a str r2, [r3, #8]
|
||
|
|
bl_rx_ringbuf.w_offset = 0;
|
||
|
|
ca26: 4b21 ldr r3, [pc, #132] ; (caac <enter_bootload+0x13c>)
|
||
|
|
ca28: 2200 movs r2, #0
|
||
|
|
ca2a: 60da str r2, [r3, #12]
|
||
|
|
continue;
|
||
|
|
ca2c: e026 b.n ca7c <enter_bootload+0x10c>
|
||
|
|
}
|
||
|
|
|
||
|
|
// debug_printf("Successfully received incoming frame packet (todo: add extra details in debug)\n", stat);
|
||
|
|
|
||
|
|
if (svl_packet_incoming_frame.cmd == CMD_FRAME)
|
||
|
|
ca2e: 7e3b ldrb r3, [r7, #24]
|
||
|
|
ca30: 2b04 cmp r3, #4
|
||
|
|
ca32: d112 bne.n ca5a <enter_bootload+0xea>
|
||
|
|
{
|
||
|
|
debug_printf("\t\treceived an app frame\n");
|
||
|
|
ca34: 481e ldr r0, [pc, #120] ; (cab0 <enter_bootload+0x140>)
|
||
|
|
ca36: f000 f8cf bl cbd8 <debug_printf>
|
||
|
|
if (handle_frame_packet(&svl_packet_incoming_frame, &frame_address, &last_page_erased) != 0)
|
||
|
|
ca3a: f107 0226 add.w r2, r7, #38 ; 0x26
|
||
|
|
ca3e: f107 0128 add.w r1, r7, #40 ; 0x28
|
||
|
|
ca42: f107 0318 add.w r3, r7, #24
|
||
|
|
ca46: 4618 mov r0, r3
|
||
|
|
ca48: f000 f838 bl cabc <handle_frame_packet>
|
||
|
|
ca4c: 4603 mov r3, r0
|
||
|
|
ca4e: 2b00 cmp r3, #0
|
||
|
|
ca50: d014 beq.n ca7c <enter_bootload+0x10c>
|
||
|
|
{
|
||
|
|
// debug_printf("\t\t\tbootload error - packet could not be handled\n");
|
||
|
|
retransmit = 1;
|
||
|
|
ca52: 2301 movs r3, #1
|
||
|
|
ca54: f887 302e strb.w r3, [r7, #46] ; 0x2e
|
||
|
|
continue;
|
||
|
|
ca58: e010 b.n ca7c <enter_bootload+0x10c>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if (svl_packet_incoming_frame.cmd == CMD_DONE)
|
||
|
|
ca5a: 7e3b ldrb r3, [r7, #24]
|
||
|
|
ca5c: 2b06 cmp r3, #6
|
||
|
|
ca5e: d106 bne.n ca6e <enter_bootload+0xfe>
|
||
|
|
{
|
||
|
|
debug_printf("\t\treceived done signal!\n\n");
|
||
|
|
ca60: 4814 ldr r0, [pc, #80] ; (cab4 <enter_bootload+0x144>)
|
||
|
|
ca62: f000 f8b9 bl cbd8 <debug_printf>
|
||
|
|
done = true;
|
||
|
|
ca66: 2301 movs r3, #1
|
||
|
|
ca68: f887 302f strb.w r3, [r7, #47] ; 0x2f
|
||
|
|
ca6c: e006 b.n ca7c <enter_bootload+0x10c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
debug_printf("bootload error - unknown command\n");
|
||
|
|
ca6e: 4812 ldr r0, [pc, #72] ; (cab8 <enter_bootload+0x148>)
|
||
|
|
ca70: f000 f8b2 bl cbd8 <debug_printf>
|
||
|
|
retransmit = 1;
|
||
|
|
ca74: 2301 movs r3, #1
|
||
|
|
ca76: f887 302e strb.w r3, [r7, #46] ; 0x2e
|
||
|
|
continue;
|
||
|
|
ca7a: bf00 nop
|
||
|
|
while (!done)
|
||
|
|
ca7c: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
|
||
|
|
ca80: f083 0301 eor.w r3, r3, #1
|
||
|
|
ca84: b2db uxtb r3, r3
|
||
|
|
ca86: 2b00 cmp r3, #0
|
||
|
|
ca88: d19b bne.n c9c2 <enter_bootload+0x52>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// finish bootloading
|
||
|
|
}
|
||
|
|
ca8a: bf00 nop
|
||
|
|
ca8c: bf00 nop
|
||
|
|
ca8e: 3730 adds r7, #48 ; 0x30
|
||
|
|
ca90: 46bd mov sp, r7
|
||
|
|
ca92: bd80 pop {r7, pc}
|
||
|
|
ca94: 0000ed60 .word 0x0000ed60
|
||
|
|
ca98: 0000ec98 .word 0x0000ec98
|
||
|
|
ca9c: 0000ecac .word 0x0000ecac
|
||
|
|
caa0: 0000ecc8 .word 0x0000ecc8
|
||
|
|
caa4: 0000ece4 .word 0x0000ece4
|
||
|
|
caa8: 0002b368 .word 0x0002b368
|
||
|
|
caac: 10000210 .word 0x10000210
|
||
|
|
cab0: 0000ed04 .word 0x0000ed04
|
||
|
|
cab4: 0000ed20 .word 0x0000ed20
|
||
|
|
cab8: 0000ed3c .word 0x0000ed3c
|
||
|
|
|
||
|
|
0000cabc <handle_frame_packet>:
|
||
|
|
//
|
||
|
|
// Handle a frame packet
|
||
|
|
//
|
||
|
|
// ****************************************
|
||
|
|
uint8_t handle_frame_packet(svl_packet_t *packet, uint32_t *p_frame_address, uint16_t *p_last_page_erased)
|
||
|
|
{
|
||
|
|
cabc: b580 push {r7, lr}
|
||
|
|
cabe: b088 sub sp, #32
|
||
|
|
cac0: af00 add r7, sp, #0
|
||
|
|
cac2: 60f8 str r0, [r7, #12]
|
||
|
|
cac4: 60b9 str r1, [r7, #8]
|
||
|
|
cac6: 607a str r2, [r7, #4]
|
||
|
|
// debug_printf("\t\thandling frame\n");
|
||
|
|
uint32_t num_words = (packet->pl_len / 4);
|
||
|
|
cac8: 68fb ldr r3, [r7, #12]
|
||
|
|
caca: 891b ldrh r3, [r3, #8]
|
||
|
|
cacc: 089b lsrs r3, r3, #2
|
||
|
|
cace: b29b uxth r3, r3
|
||
|
|
cad0: 61fb str r3, [r7, #28]
|
||
|
|
|
||
|
|
debug_printf("\t\tframe_address = 0x%08X, num_words = %d\n", *(p_frame_address), num_words);
|
||
|
|
cad2: 68bb ldr r3, [r7, #8]
|
||
|
|
cad4: 681b ldr r3, [r3, #0]
|
||
|
|
cad6: 69fa ldr r2, [r7, #28]
|
||
|
|
cad8: 4619 mov r1, r3
|
||
|
|
cada: 482e ldr r0, [pc, #184] ; (cb94 <handle_frame_packet+0xd8>)
|
||
|
|
cadc: f000 f87c bl cbd8 <debug_printf>
|
||
|
|
|
||
|
|
// Check payload length is multiple of words
|
||
|
|
if ((packet->pl_len % 4))
|
||
|
|
cae0: 68fb ldr r3, [r7, #12]
|
||
|
|
cae2: 891b ldrh r3, [r3, #8]
|
||
|
|
cae4: f003 0303 and.w r3, r3, #3
|
||
|
|
cae8: b29b uxth r3, r3
|
||
|
|
caea: 2b00 cmp r3, #0
|
||
|
|
caec: d004 beq.n caf8 <handle_frame_packet+0x3c>
|
||
|
|
{
|
||
|
|
debug_printf("Error: frame packet not integer multiple of words (4 bytes per word)\n");
|
||
|
|
caee: 482a ldr r0, [pc, #168] ; (cb98 <handle_frame_packet+0xdc>)
|
||
|
|
caf0: f000 f872 bl cbd8 <debug_printf>
|
||
|
|
return 1;
|
||
|
|
caf4: 2301 movs r3, #1
|
||
|
|
caf6: e048 b.n cb8a <handle_frame_packet+0xce>
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t i32ReturnCode = 0;
|
||
|
|
caf8: 2300 movs r3, #0
|
||
|
|
cafa: 61bb str r3, [r7, #24]
|
||
|
|
uint32_t offset_address = (*(p_frame_address) + USERCODE_OFFSET);
|
||
|
|
cafc: 68bb ldr r3, [r7, #8]
|
||
|
|
cafe: 681b ldr r3, [r3, #0]
|
||
|
|
cb00: f503 3380 add.w r3, r3, #65536 ; 0x10000
|
||
|
|
cb04: 617b str r3, [r7, #20]
|
||
|
|
if ((*p_last_page_erased) < AM_HAL_FLASH_ADDR2PAGE(offset_address))
|
||
|
|
cb06: 687b ldr r3, [r7, #4]
|
||
|
|
cb08: 881b ldrh r3, [r3, #0]
|
||
|
|
cb0a: 461a mov r2, r3
|
||
|
|
cb0c: 697b ldr r3, [r7, #20]
|
||
|
|
cb0e: 0b5b lsrs r3, r3, #13
|
||
|
|
cb10: f003 033f and.w r3, r3, #63 ; 0x3f
|
||
|
|
cb14: 429a cmp r2, r3
|
||
|
|
cb16: d21b bcs.n cb50 <handle_frame_packet+0x94>
|
||
|
|
{ // Prevent erasing partially-filled pages
|
||
|
|
// debug_printf("Erasing instance %d, page %d\n\r", AM_HAL_FLASH_ADDR2INST( offset_address ), AM_HAL_FLASH_ADDR2PAGE(offset_address) );
|
||
|
|
|
||
|
|
//Erase the 8k page for this address
|
||
|
|
i32ReturnCode = am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, AM_HAL_FLASH_ADDR2INST(offset_address), AM_HAL_FLASH_ADDR2PAGE(offset_address));
|
||
|
|
cb18: 697b ldr r3, [r7, #20]
|
||
|
|
cb1a: 0cdb lsrs r3, r3, #19
|
||
|
|
cb1c: f003 0101 and.w r1, r3, #1
|
||
|
|
cb20: 697b ldr r3, [r7, #20]
|
||
|
|
cb22: 0b5b lsrs r3, r3, #13
|
||
|
|
cb24: f003 033f and.w r3, r3, #63 ; 0x3f
|
||
|
|
cb28: 461a mov r2, r3
|
||
|
|
cb2a: 481c ldr r0, [pc, #112] ; (cb9c <handle_frame_packet+0xe0>)
|
||
|
|
cb2c: f000 ffca bl dac4 <am_hal_flash_page_erase>
|
||
|
|
cb30: 61b8 str r0, [r7, #24]
|
||
|
|
*(p_last_page_erased) = AM_HAL_FLASH_ADDR2PAGE(offset_address);
|
||
|
|
cb32: 697b ldr r3, [r7, #20]
|
||
|
|
cb34: 0b5b lsrs r3, r3, #13
|
||
|
|
cb36: b29b uxth r3, r3
|
||
|
|
cb38: f003 033f and.w r3, r3, #63 ; 0x3f
|
||
|
|
cb3c: b29a uxth r2, r3
|
||
|
|
cb3e: 687b ldr r3, [r7, #4]
|
||
|
|
cb40: 801a strh r2, [r3, #0]
|
||
|
|
|
||
|
|
if (i32ReturnCode)
|
||
|
|
cb42: 69bb ldr r3, [r7, #24]
|
||
|
|
cb44: 2b00 cmp r3, #0
|
||
|
|
cb46: d003 beq.n cb50 <handle_frame_packet+0x94>
|
||
|
|
{
|
||
|
|
debug_printf("FLASH_MASS_ERASE i32ReturnCode = 0x%x.\n\r", i32ReturnCode);
|
||
|
|
cb48: 69b9 ldr r1, [r7, #24]
|
||
|
|
cb4a: 4815 ldr r0, [pc, #84] ; (cba0 <handle_frame_packet+0xe4>)
|
||
|
|
cb4c: f000 f844 bl cbd8 <debug_printf>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//Record the array
|
||
|
|
//debug_printf("Recording %d words (%d bytes) to memory\n", num_words, 4 * num_words);
|
||
|
|
i32ReturnCode = am_hal_flash_program_main(AM_HAL_FLASH_PROGRAM_KEY, (uint32_t *)packet->pl, (uint32_t *)(*(p_frame_address) + USERCODE_OFFSET), num_words);
|
||
|
|
cb50: 68fb ldr r3, [r7, #12]
|
||
|
|
cb52: 6859 ldr r1, [r3, #4]
|
||
|
|
cb54: 68bb ldr r3, [r7, #8]
|
||
|
|
cb56: 681b ldr r3, [r3, #0]
|
||
|
|
cb58: f503 3380 add.w r3, r3, #65536 ; 0x10000
|
||
|
|
cb5c: 461a mov r2, r3
|
||
|
|
cb5e: 69fb ldr r3, [r7, #28]
|
||
|
|
cb60: 480e ldr r0, [pc, #56] ; (cb9c <handle_frame_packet+0xe0>)
|
||
|
|
cb62: f000 ffb3 bl dacc <am_hal_flash_program_main>
|
||
|
|
cb66: 61b8 str r0, [r7, #24]
|
||
|
|
if (i32ReturnCode)
|
||
|
|
cb68: 69bb ldr r3, [r7, #24]
|
||
|
|
cb6a: 2b00 cmp r3, #0
|
||
|
|
cb6c: d005 beq.n cb7a <handle_frame_packet+0xbe>
|
||
|
|
{
|
||
|
|
debug_printf("FLASH_WRITE error = 0x%x.\n\r", i32ReturnCode);
|
||
|
|
cb6e: 69b9 ldr r1, [r7, #24]
|
||
|
|
cb70: 480c ldr r0, [pc, #48] ; (cba4 <handle_frame_packet+0xe8>)
|
||
|
|
cb72: f000 f831 bl cbd8 <debug_printf>
|
||
|
|
return 1;
|
||
|
|
cb76: 2301 movs r3, #1
|
||
|
|
cb78: e007 b.n cb8a <handle_frame_packet+0xce>
|
||
|
|
}
|
||
|
|
*(p_frame_address) += num_words * 4;
|
||
|
|
cb7a: 68bb ldr r3, [r7, #8]
|
||
|
|
cb7c: 681a ldr r2, [r3, #0]
|
||
|
|
cb7e: 69fb ldr r3, [r7, #28]
|
||
|
|
cb80: 009b lsls r3, r3, #2
|
||
|
|
cb82: 441a add r2, r3
|
||
|
|
cb84: 68bb ldr r3, [r7, #8]
|
||
|
|
cb86: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
// debug_printf("Array recorded to flash\n");
|
||
|
|
return 0;
|
||
|
|
cb88: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
cb8a: 4618 mov r0, r3
|
||
|
|
cb8c: 3720 adds r7, #32
|
||
|
|
cb8e: 46bd mov sp, r7
|
||
|
|
cb90: bd80 pop {r7, pc}
|
||
|
|
cb92: bf00 nop
|
||
|
|
cb94: 0000ed6c .word 0x0000ed6c
|
||
|
|
cb98: 0000ed98 .word 0x0000ed98
|
||
|
|
cb9c: 12344321 .word 0x12344321
|
||
|
|
cba0: 0000ede0 .word 0x0000ede0
|
||
|
|
cba4: 0000ee0c .word 0x0000ee0c
|
||
|
|
|
||
|
|
0000cba8 <app_start>:
|
||
|
|
//
|
||
|
|
// Jump to the application
|
||
|
|
//
|
||
|
|
// ****************************************
|
||
|
|
void app_start(void)
|
||
|
|
{
|
||
|
|
cba8: b580 push {r7, lr}
|
||
|
|
cbaa: b082 sub sp, #8
|
||
|
|
cbac: af00 add r7, sp, #0
|
||
|
|
// debug_printf("\n");
|
||
|
|
// #endif // APP_PRINT_PRETTY
|
||
|
|
// #endif // DEBUG_PRINT_APP
|
||
|
|
// #endif // DEBUG
|
||
|
|
|
||
|
|
void *entryPoint = (void *)(*((uint32_t *)(USERCODE_OFFSET + 4)));
|
||
|
|
cbae: 4b08 ldr r3, [pc, #32] ; (cbd0 <app_start+0x28>)
|
||
|
|
cbb0: 681b ldr r3, [r3, #0]
|
||
|
|
cbb2: 607b str r3, [r7, #4]
|
||
|
|
debug_printf("\nJump to App at 0x%08X\n\n", (uint32_t)entryPoint);
|
||
|
|
cbb4: 687b ldr r3, [r7, #4]
|
||
|
|
cbb6: 4619 mov r1, r3
|
||
|
|
cbb8: 4806 ldr r0, [pc, #24] ; (cbd4 <app_start+0x2c>)
|
||
|
|
cbba: f000 f80d bl cbd8 <debug_printf>
|
||
|
|
am_util_delay_ms(10); // Wait for prints to complete
|
||
|
|
cbbe: 200a movs r0, #10
|
||
|
|
cbc0: f000 f888 bl ccd4 <am_util_delay_ms>
|
||
|
|
unsetup(); // Undoes configuration to provide users with a clean slate
|
||
|
|
cbc4: f7ff fd14 bl c5f0 <unsetup>
|
||
|
|
goto *entryPoint; // Jump to start of user code
|
||
|
|
cbc8: 687b ldr r3, [r7, #4]
|
||
|
|
cbca: f043 0301 orr.w r3, r3, #1
|
||
|
|
cbce: 4718 bx r3
|
||
|
|
cbd0: 00010004 .word 0x00010004
|
||
|
|
cbd4: 0000ee28 .word 0x0000ee28
|
||
|
|
|
||
|
|
0000cbd8 <debug_printf>:
|
||
|
|
//
|
||
|
|
// Debug printf function
|
||
|
|
//
|
||
|
|
// ****************************************
|
||
|
|
void debug_printf(char *fmt, ...)
|
||
|
|
{
|
||
|
|
cbd8: b40f push {r0, r1, r2, r3}
|
||
|
|
cbda: b480 push {r7}
|
||
|
|
cbdc: af00 add r7, sp, #0
|
||
|
|
vsnprintf(debug_buffer, DEBUG_UART_BUF_LEN, (const char *)fmt, args);
|
||
|
|
va_end(args);
|
||
|
|
|
||
|
|
svl_uart_print(hUART_debug, debug_buffer);
|
||
|
|
#endif //DEBUG
|
||
|
|
}
|
||
|
|
cbde: bf00 nop
|
||
|
|
cbe0: 46bd mov sp, r7
|
||
|
|
cbe2: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
cbe6: b004 add sp, #16
|
||
|
|
cbe8: 4770 bx lr
|
||
|
|
...
|
||
|
|
|
||
|
|
0000cbec <am_uart_isr>:
|
||
|
|
//
|
||
|
|
// UART interrupt handlers
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void am_uart_isr(void)
|
||
|
|
{
|
||
|
|
cbec: b580 push {r7, lr}
|
||
|
|
cbee: b084 sub sp, #16
|
||
|
|
cbf0: af00 add r7, sp, #0
|
||
|
|
// Service the FIFOs as necessary, and clear the interrupts.
|
||
|
|
#if BL_UART_INST == 0
|
||
|
|
uint32_t ui32Status, ui32Idle;
|
||
|
|
am_hal_uart_interrupt_status_get(hUART_bl, &ui32Status, true);
|
||
|
|
cbf2: 4b18 ldr r3, [pc, #96] ; (cc54 <am_uart_isr+0x68>)
|
||
|
|
cbf4: 681b ldr r3, [r3, #0]
|
||
|
|
cbf6: f107 010c add.w r1, r7, #12
|
||
|
|
cbfa: 2201 movs r2, #1
|
||
|
|
cbfc: 4618 mov r0, r3
|
||
|
|
cbfe: f001 fefb bl e9f8 <am_hal_uart_interrupt_status_get>
|
||
|
|
am_hal_uart_interrupt_clear(hUART_bl, ui32Status);
|
||
|
|
cc02: 4b14 ldr r3, [pc, #80] ; (cc54 <am_uart_isr+0x68>)
|
||
|
|
cc04: 681b ldr r3, [r3, #0]
|
||
|
|
cc06: 68fa ldr r2, [r7, #12]
|
||
|
|
cc08: 4611 mov r1, r2
|
||
|
|
cc0a: 4618 mov r0, r3
|
||
|
|
cc0c: f001 fee2 bl e9d4 <am_hal_uart_interrupt_clear>
|
||
|
|
am_hal_uart_interrupt_service(hUART_bl, ui32Status, &ui32Idle);
|
||
|
|
cc10: 4b10 ldr r3, [pc, #64] ; (cc54 <am_uart_isr+0x68>)
|
||
|
|
cc12: 681b ldr r3, [r3, #0]
|
||
|
|
cc14: 68f9 ldr r1, [r7, #12]
|
||
|
|
cc16: f107 0208 add.w r2, r7, #8
|
||
|
|
cc1a: 4618 mov r0, r3
|
||
|
|
cc1c: f001 fe30 bl e880 <am_hal_uart_interrupt_service>
|
||
|
|
if (ui32Status & AM_HAL_UART_INT_RX)
|
||
|
|
cc20: 68fb ldr r3, [r7, #12]
|
||
|
|
cc22: f003 0310 and.w r3, r3, #16
|
||
|
|
cc26: 2b00 cmp r3, #0
|
||
|
|
cc28: d010 beq.n cc4c <am_uart_isr+0x60>
|
||
|
|
{
|
||
|
|
uint8_t c = 0x00;
|
||
|
|
cc2a: 2300 movs r3, #0
|
||
|
|
cc2c: 71fb strb r3, [r7, #7]
|
||
|
|
if (svl_uart_read(hUART_bl, (char *)&c, 1) != 0)
|
||
|
|
cc2e: 4b09 ldr r3, [pc, #36] ; (cc54 <am_uart_isr+0x68>)
|
||
|
|
cc30: 681b ldr r3, [r3, #0]
|
||
|
|
cc32: 1df9 adds r1, r7, #7
|
||
|
|
cc34: 2201 movs r2, #1
|
||
|
|
cc36: 4618 mov r0, r3
|
||
|
|
cc38: f000 fc4b bl d4d2 <svl_uart_read>
|
||
|
|
cc3c: 4603 mov r3, r0
|
||
|
|
cc3e: 2b00 cmp r3, #0
|
||
|
|
cc40: d004 beq.n cc4c <am_uart_isr+0x60>
|
||
|
|
{
|
||
|
|
art_svl_ringbuf_write(&bl_rx_ringbuf, c);
|
||
|
|
cc42: 79fb ldrb r3, [r7, #7]
|
||
|
|
cc44: 4619 mov r1, r3
|
||
|
|
cc46: 4804 ldr r0, [pc, #16] ; (cc58 <am_uart_isr+0x6c>)
|
||
|
|
cc48: f000 fbe5 bl d416 <art_svl_ringbuf_write>
|
||
|
|
am_hal_uart_interrupt_status_get(hUART_debug, &ui32Status, true);
|
||
|
|
am_hal_uart_interrupt_clear(hUART_debug, ui32Status);
|
||
|
|
am_hal_uart_interrupt_service(hUART_debug, ui32Status, &ui32Idle);
|
||
|
|
#endif // DEBUG
|
||
|
|
#endif // BL_UART_INST == 0
|
||
|
|
}
|
||
|
|
cc4c: bf00 nop
|
||
|
|
cc4e: 3710 adds r7, #16
|
||
|
|
cc50: 46bd mov sp, r7
|
||
|
|
cc52: bd80 pop {r7, pc}
|
||
|
|
cc54: 10000220 .word 0x10000220
|
||
|
|
cc58: 10000210 .word 0x10000210
|
||
|
|
|
||
|
|
0000cc5c <am_uart1_isr>:
|
||
|
|
|
||
|
|
void am_uart1_isr(void)
|
||
|
|
{
|
||
|
|
cc5c: b480 push {r7}
|
||
|
|
cc5e: af00 add r7, sp, #0
|
||
|
|
am_hal_uart_interrupt_status_get(hUART_debug, &ui32Status, true);
|
||
|
|
am_hal_uart_interrupt_clear(hUART_debug, ui32Status);
|
||
|
|
am_hal_uart_interrupt_service(hUART_debug, ui32Status, &ui32Idle);
|
||
|
|
#endif // DEBUG
|
||
|
|
#endif // BL_UART_INST == 0
|
||
|
|
}
|
||
|
|
cc60: bf00 nop
|
||
|
|
cc62: 46bd mov sp, r7
|
||
|
|
cc64: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
cc68: 4770 bx lr
|
||
|
|
...
|
||
|
|
|
||
|
|
0000cc6c <am_gpio_isr>:
|
||
|
|
//
|
||
|
|
// GPIO interrupt handler
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void am_gpio_isr(void)
|
||
|
|
{
|
||
|
|
cc6c: b580 push {r7, lr}
|
||
|
|
cc6e: af00 add r7, sp, #0
|
||
|
|
am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(BL_RX_PAD));
|
||
|
|
cc70: f04f 0000 mov.w r0, #0
|
||
|
|
cc74: f44f 3100 mov.w r1, #131072 ; 0x20000
|
||
|
|
cc78: f001 f930 bl dedc <am_hal_gpio_interrupt_clear>
|
||
|
|
if (bl_baud_ticks_index < BL_BAUD_SAMPLES)
|
||
|
|
cc7c: 4b0a ldr r3, [pc, #40] ; (cca8 <am_gpio_isr+0x3c>)
|
||
|
|
cc7e: 781b ldrb r3, [r3, #0]
|
||
|
|
cc80: b2db uxtb r3, r3
|
||
|
|
cc82: 2b04 cmp r3, #4
|
||
|
|
cc84: d80d bhi.n cca2 <am_gpio_isr+0x36>
|
||
|
|
{
|
||
|
|
bl_baud_ticks[bl_baud_ticks_index++] = CTIMER->STTMR;
|
||
|
|
cc86: 4a09 ldr r2, [pc, #36] ; (ccac <am_gpio_isr+0x40>)
|
||
|
|
cc88: 4b07 ldr r3, [pc, #28] ; (cca8 <am_gpio_isr+0x3c>)
|
||
|
|
cc8a: 781b ldrb r3, [r3, #0]
|
||
|
|
cc8c: b2db uxtb r3, r3
|
||
|
|
cc8e: 1c59 adds r1, r3, #1
|
||
|
|
cc90: b2c8 uxtb r0, r1
|
||
|
|
cc92: 4905 ldr r1, [pc, #20] ; (cca8 <am_gpio_isr+0x3c>)
|
||
|
|
cc94: 7008 strb r0, [r1, #0]
|
||
|
|
cc96: 4619 mov r1, r3
|
||
|
|
cc98: f8d2 3144 ldr.w r3, [r2, #324] ; 0x144
|
||
|
|
cc9c: 4a04 ldr r2, [pc, #16] ; (ccb0 <am_gpio_isr+0x44>)
|
||
|
|
cc9e: f842 3021 str.w r3, [r2, r1, lsl #2]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
cca2: bf00 nop
|
||
|
|
cca4: bd80 pop {r7, pc}
|
||
|
|
cca6: bf00 nop
|
||
|
|
cca8: 10000224 .word 0x10000224
|
||
|
|
ccac: 40008000 .word 0x40008000
|
||
|
|
ccb0: 10000228 .word 0x10000228
|
||
|
|
|
||
|
|
0000ccb4 <am_stimer_isr>:
|
||
|
|
//
|
||
|
|
// STimer interrupt handler
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void am_stimer_isr(void)
|
||
|
|
{
|
||
|
|
ccb4: b580 push {r7, lr}
|
||
|
|
ccb6: af00 add r7, sp, #0
|
||
|
|
am_hal_stimer_int_clear(AM_HAL_STIMER_INT_OVERFLOW);
|
||
|
|
ccb8: f44f 7080 mov.w r0, #256 ; 0x100
|
||
|
|
ccbc: f001 f9fa bl e0b4 <am_hal_stimer_int_clear>
|
||
|
|
ap3_stimer_overflows += 1;
|
||
|
|
ccc0: 4b03 ldr r3, [pc, #12] ; (ccd0 <am_stimer_isr+0x1c>)
|
||
|
|
ccc2: 681b ldr r3, [r3, #0]
|
||
|
|
ccc4: 3301 adds r3, #1
|
||
|
|
ccc6: 4a02 ldr r2, [pc, #8] ; (ccd0 <am_stimer_isr+0x1c>)
|
||
|
|
ccc8: 6013 str r3, [r2, #0]
|
||
|
|
// At the fastest rate (3MHz) the 64 bits of the stimer
|
||
|
|
// along with this overflow counter can keep track of
|
||
|
|
// the time for ~ 195,000 years without wrapping to 0
|
||
|
|
ccca: bf00 nop
|
||
|
|
cccc: bd80 pop {r7, pc}
|
||
|
|
ccce: bf00 nop
|
||
|
|
ccd0: 10000a58 .word 0x10000a58
|
||
|
|
|
||
|
|
0000ccd4 <am_util_delay_ms>:
|
||
|
|
//! @returns None
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
am_util_delay_ms(uint32_t ui32MilliSeconds)
|
||
|
|
{
|
||
|
|
ccd4: b580 push {r7, lr}
|
||
|
|
ccd6: b088 sub sp, #32
|
||
|
|
ccd8: af00 add r7, sp, #0
|
||
|
|
ccda: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t ui32Loops, ui32HFRC;
|
||
|
|
#if AM_APOLLO3_CLKGEN
|
||
|
|
am_hal_clkgen_status_t sClkgenStatus;
|
||
|
|
am_hal_clkgen_status_get(&sClkgenStatus);
|
||
|
|
ccdc: f107 030c add.w r3, r7, #12
|
||
|
|
cce0: 4618 mov r0, r3
|
||
|
|
cce2: f000 fed1 bl da88 <am_hal_clkgen_status_get>
|
||
|
|
ui32HFRC = sClkgenStatus.ui32SysclkFreq;
|
||
|
|
cce6: 68fb ldr r3, [r7, #12]
|
||
|
|
cce8: 61fb str r3, [r7, #28]
|
||
|
|
#else // AM_APOLLO3_CLKGEN
|
||
|
|
ui32HFRC = am_hal_clkgen_sysclk_get();
|
||
|
|
#endif // AM_APOLLO3_CLKGEN
|
||
|
|
ui32Loops = ui32MilliSeconds * (ui32HFRC / 3000);
|
||
|
|
ccea: 69fb ldr r3, [r7, #28]
|
||
|
|
ccec: 4a07 ldr r2, [pc, #28] ; (cd0c <am_util_delay_ms+0x38>)
|
||
|
|
ccee: fba2 2303 umull r2, r3, r2, r3
|
||
|
|
ccf2: 099a lsrs r2, r3, #6
|
||
|
|
ccf4: 687b ldr r3, [r7, #4]
|
||
|
|
ccf6: fb02 f303 mul.w r3, r2, r3
|
||
|
|
ccfa: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
//
|
||
|
|
// Call the BOOTROM cycle delay function
|
||
|
|
//
|
||
|
|
am_hal_flash_delay(ui32Loops);
|
||
|
|
ccfc: 69b8 ldr r0, [r7, #24]
|
||
|
|
ccfe: f000 ff13 bl db28 <am_hal_flash_delay>
|
||
|
|
}
|
||
|
|
cd02: bf00 nop
|
||
|
|
cd04: 3720 adds r7, #32
|
||
|
|
cd06: 46bd mov sp, r7
|
||
|
|
cd08: bd80 pop {r7, pc}
|
||
|
|
cd0a: bf00 nop
|
||
|
|
cd0c: 057619f1 .word 0x057619f1
|
||
|
|
|
||
|
|
0000cd10 <am_util_delay_us>:
|
||
|
|
//! @returns None
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
am_util_delay_us(uint32_t ui32MicroSeconds)
|
||
|
|
{
|
||
|
|
cd10: b580 push {r7, lr}
|
||
|
|
cd12: b088 sub sp, #32
|
||
|
|
cd14: af00 add r7, sp, #0
|
||
|
|
cd16: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t ui32Loops, ui32HFRC;
|
||
|
|
|
||
|
|
#if AM_APOLLO3_CLKGEN
|
||
|
|
am_hal_clkgen_status_t sClkgenStatus;
|
||
|
|
am_hal_clkgen_status_get(&sClkgenStatus);
|
||
|
|
cd18: f107 030c add.w r3, r7, #12
|
||
|
|
cd1c: 4618 mov r0, r3
|
||
|
|
cd1e: f000 feb3 bl da88 <am_hal_clkgen_status_get>
|
||
|
|
ui32HFRC = sClkgenStatus.ui32SysclkFreq;
|
||
|
|
cd22: 68fb ldr r3, [r7, #12]
|
||
|
|
cd24: 61fb str r3, [r7, #28]
|
||
|
|
#else // AM_APOLLO3_CLKGEN
|
||
|
|
ui32HFRC = am_hal_clkgen_sysclk_get();
|
||
|
|
#endif // AM_APOLLO3_CLKGEN
|
||
|
|
ui32Loops = ui32MicroSeconds * (ui32HFRC / 3000000);
|
||
|
|
cd26: 69fb ldr r3, [r7, #28]
|
||
|
|
cd28: 4a07 ldr r2, [pc, #28] ; (cd48 <am_util_delay_us+0x38>)
|
||
|
|
cd2a: fba2 2303 umull r2, r3, r2, r3
|
||
|
|
cd2e: 0c9a lsrs r2, r3, #18
|
||
|
|
cd30: 687b ldr r3, [r7, #4]
|
||
|
|
cd32: fb02 f303 mul.w r3, r2, r3
|
||
|
|
cd36: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
//
|
||
|
|
// Call the BOOTROM cycle delay function
|
||
|
|
//
|
||
|
|
am_hal_flash_delay(ui32Loops);
|
||
|
|
cd38: 69b8 ldr r0, [r7, #24]
|
||
|
|
cd3a: f000 fef5 bl db28 <am_hal_flash_delay>
|
||
|
|
}
|
||
|
|
cd3e: bf00 nop
|
||
|
|
cd40: 3720 adds r7, #32
|
||
|
|
cd42: 46bd mov sp, r7
|
||
|
|
cd44: bd80 pop {r7, pc}
|
||
|
|
cd46: bf00 nop
|
||
|
|
cd48: 165e9f81 .word 0x165e9f81
|
||
|
|
|
||
|
|
0000cd4c <Reset_Handler>:
|
||
|
|
Reset_Handler(void)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Set the vector table pointer.
|
||
|
|
//
|
||
|
|
__asm(" ldr r0, =0xE000ED08\n"
|
||
|
|
cd4c: 4818 ldr r0, [pc, #96] ; (cdb0 <zero_loop+0x2c>)
|
||
|
|
cd4e: 4919 ldr r1, [pc, #100] ; (cdb4 <zero_loop+0x30>)
|
||
|
|
cd50: 6001 str r1, [r0, #0]
|
||
|
|
" str r1, [r0]");
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set the stack pointer.
|
||
|
|
//
|
||
|
|
__asm(" ldr sp, [r1]");
|
||
|
|
cd52: f8d1 d000 ldr.w sp, [r1]
|
||
|
|
|
||
|
|
#ifndef NOFPU
|
||
|
|
//
|
||
|
|
// Enable the FPU.
|
||
|
|
//
|
||
|
|
__asm("ldr r0, =0xE000ED88\n"
|
||
|
|
cd56: 4818 ldr r0, [pc, #96] ; (cdb8 <zero_loop+0x34>)
|
||
|
|
cd58: 6801 ldr r1, [r0, #0]
|
||
|
|
cd5a: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
|
||
|
|
cd5e: 6001 str r1, [r0, #0]
|
||
|
|
cd60: f3bf 8f4f dsb sy
|
||
|
|
cd64: f3bf 8f6f isb sy
|
||
|
|
"isb\n");
|
||
|
|
#endif
|
||
|
|
//
|
||
|
|
// Copy the data segment initializers from flash to SRAM.
|
||
|
|
//
|
||
|
|
__asm(" ldr r0, =_init_data\n"
|
||
|
|
cd68: 4814 ldr r0, [pc, #80] ; (cdbc <zero_loop+0x38>)
|
||
|
|
cd6a: 4915 ldr r1, [pc, #84] ; (cdc0 <zero_loop+0x3c>)
|
||
|
|
cd6c: 4a15 ldr r2, [pc, #84] ; (cdc4 <zero_loop+0x40>)
|
||
|
|
|
||
|
|
0000cd6e <copy_loop>:
|
||
|
|
cd6e: 4291 cmp r1, r2
|
||
|
|
cd70: d004 beq.n cd7c <copy_end>
|
||
|
|
cd72: f850 3b04 ldr.w r3, [r0], #4
|
||
|
|
cd76: f841 3b04 str.w r3, [r1], #4
|
||
|
|
cd7a: e7f8 b.n cd6e <copy_loop>
|
||
|
|
|
||
|
|
0000cd7c <copy_end>:
|
||
|
|
"copy_end:\n");
|
||
|
|
|
||
|
|
//
|
||
|
|
// Zero fill the bss segment.
|
||
|
|
//
|
||
|
|
__asm(" ldr r0, =_sbss\n"
|
||
|
|
cd7c: 4812 ldr r0, [pc, #72] ; (cdc8 <zero_loop+0x44>)
|
||
|
|
cd7e: 4913 ldr r1, [pc, #76] ; (cdcc <zero_loop+0x48>)
|
||
|
|
cd80: f04f 0200 mov.w r2, #0
|
||
|
|
|
||
|
|
0000cd84 <zero_loop>:
|
||
|
|
cd84: 4288 cmp r0, r1
|
||
|
|
cd86: bfb8 it lt
|
||
|
|
cd88: f840 2b04 strlt.w r2, [r0], #4
|
||
|
|
cd8c: dbfa blt.n cd84 <zero_loop>
|
||
|
|
//
|
||
|
|
// Call Global Static Constructors for C++ support
|
||
|
|
//
|
||
|
|
extern void (*__init_array_start)(void); // symbols must be
|
||
|
|
extern void (*__init_array_end)(void); // provided by linker
|
||
|
|
for (void (**p)() = &__init_array_start; p < &__init_array_end; ++p) {
|
||
|
|
cd8e: 4c06 ldr r4, [pc, #24] ; (cda8 <zero_loop+0x24>)
|
||
|
|
cd90: e002 b.n cd98 <zero_loop+0x14>
|
||
|
|
(*p)(); // Call each function in the list
|
||
|
|
cd92: 6823 ldr r3, [r4, #0]
|
||
|
|
cd94: 4798 blx r3
|
||
|
|
for (void (**p)() = &__init_array_start; p < &__init_array_end; ++p) {
|
||
|
|
cd96: 3404 adds r4, #4
|
||
|
|
cd98: 4b04 ldr r3, [pc, #16] ; (cdac <zero_loop+0x28>)
|
||
|
|
cd9a: 429c cmp r4, r3
|
||
|
|
cd9c: d3f9 bcc.n cd92 <zero_loop+0xe>
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Call the application's entry point.
|
||
|
|
//
|
||
|
|
main();
|
||
|
|
cd9e: f7ff fb6d bl c47c <main>
|
||
|
|
|
||
|
|
//
|
||
|
|
// If main returns then execute a break point instruction
|
||
|
|
//
|
||
|
|
__asm(" bkpt ");
|
||
|
|
cda2: be00 bkpt 0x0000
|
||
|
|
}
|
||
|
|
cda4: bf00 nop
|
||
|
|
cda6: bf00 nop
|
||
|
|
cda8: 0000eb40 .word 0x0000eb40
|
||
|
|
cdac: 0000eb40 .word 0x0000eb40
|
||
|
|
cdb0: e000ed08 .word 0xe000ed08
|
||
|
|
cdb4: 0000c000 .word 0x0000c000
|
||
|
|
cdb8: e000ed88 .word 0xe000ed88
|
||
|
|
cdbc: 0000f080 .word 0x0000f080
|
||
|
|
cdc0: 10000000 .word 0x10000000
|
||
|
|
cdc4: 1000020c .word 0x1000020c
|
||
|
|
cdc8: 10000210 .word 0x10000210
|
||
|
|
cdcc: 10000b40 .word 0x10000b40
|
||
|
|
|
||
|
|
0000cdd0 <NMI_Handler>:
|
||
|
|
// by a debugger.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
NMI_Handler(void)
|
||
|
|
{
|
||
|
|
cdd0: b480 push {r7}
|
||
|
|
cdd2: af00 add r7, sp, #0
|
||
|
|
//
|
||
|
|
// Go into an infinite loop.
|
||
|
|
//
|
||
|
|
while(1)
|
||
|
|
cdd4: e7fe b.n cdd4 <NMI_Handler+0x4>
|
||
|
|
|
||
|
|
0000cdd6 <BusFault_Handler>:
|
||
|
|
// for examination by a debugger.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
HardFault_Handler(void)
|
||
|
|
{
|
||
|
|
cdd6: b480 push {r7}
|
||
|
|
cdd8: af00 add r7, sp, #0
|
||
|
|
//
|
||
|
|
// Go into an infinite loop.
|
||
|
|
//
|
||
|
|
while(1)
|
||
|
|
cdda: e7fe b.n cdda <BusFault_Handler+0x4>
|
||
|
|
|
||
|
|
0000cddc <DebugMon_Handler>:
|
||
|
|
// for examination by a debugger.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
am_default_isr(void)
|
||
|
|
{
|
||
|
|
cddc: b480 push {r7}
|
||
|
|
cdde: af00 add r7, sp, #0
|
||
|
|
//
|
||
|
|
// Go into an infinite loop.
|
||
|
|
//
|
||
|
|
while(1)
|
||
|
|
cde0: e7fe b.n cde0 <DebugMon_Handler+0x4>
|
||
|
|
...
|
||
|
|
|
||
|
|
0000cde4 <svl_packet_link_read_fn>:
|
||
|
|
}
|
||
|
|
return retval;
|
||
|
|
}
|
||
|
|
|
||
|
|
void svl_packet_link_read_fn(svl_packet_read_byte_fn_t fn, void *param)
|
||
|
|
{
|
||
|
|
cde4: b480 push {r7}
|
||
|
|
cde6: b083 sub sp, #12
|
||
|
|
cde8: af00 add r7, sp, #0
|
||
|
|
cdea: 6078 str r0, [r7, #4]
|
||
|
|
cdec: 6039 str r1, [r7, #0]
|
||
|
|
read_param = param;
|
||
|
|
cdee: 4a06 ldr r2, [pc, #24] ; (ce08 <svl_packet_link_read_fn+0x24>)
|
||
|
|
cdf0: 683b ldr r3, [r7, #0]
|
||
|
|
cdf2: 6013 str r3, [r2, #0]
|
||
|
|
read_fn = fn;
|
||
|
|
cdf4: 4a05 ldr r2, [pc, #20] ; (ce0c <svl_packet_link_read_fn+0x28>)
|
||
|
|
cdf6: 687b ldr r3, [r7, #4]
|
||
|
|
cdf8: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
cdfa: bf00 nop
|
||
|
|
cdfc: 370c adds r7, #12
|
||
|
|
cdfe: 46bd mov sp, r7
|
||
|
|
ce00: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
ce04: 4770 bx lr
|
||
|
|
ce06: bf00 nop
|
||
|
|
ce08: 10000a3c .word 0x10000a3c
|
||
|
|
ce0c: 10000a48 .word 0x10000a48
|
||
|
|
|
||
|
|
0000ce10 <svl_packet_link_write_fn>:
|
||
|
|
|
||
|
|
void svl_packet_link_write_fn(svl_packet_write_byte_fn_t fn, void *param)
|
||
|
|
{
|
||
|
|
ce10: b480 push {r7}
|
||
|
|
ce12: b083 sub sp, #12
|
||
|
|
ce14: af00 add r7, sp, #0
|
||
|
|
ce16: 6078 str r0, [r7, #4]
|
||
|
|
ce18: 6039 str r1, [r7, #0]
|
||
|
|
write_param = param;
|
||
|
|
ce1a: 4a06 ldr r2, [pc, #24] ; (ce34 <svl_packet_link_write_fn+0x24>)
|
||
|
|
ce1c: 683b ldr r3, [r7, #0]
|
||
|
|
ce1e: 6013 str r3, [r2, #0]
|
||
|
|
write_fn = fn;
|
||
|
|
ce20: 4a05 ldr r2, [pc, #20] ; (ce38 <svl_packet_link_write_fn+0x28>)
|
||
|
|
ce22: 687b ldr r3, [r7, #4]
|
||
|
|
ce24: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
ce26: bf00 nop
|
||
|
|
ce28: 370c adds r7, #12
|
||
|
|
ce2a: 46bd mov sp, r7
|
||
|
|
ce2c: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
ce30: 4770 bx lr
|
||
|
|
ce32: bf00 nop
|
||
|
|
ce34: 10000a40 .word 0x10000a40
|
||
|
|
ce38: 10000a4c .word 0x10000a4c
|
||
|
|
|
||
|
|
0000ce3c <svl_packet_link_avail_fn>:
|
||
|
|
|
||
|
|
void svl_packet_link_avail_fn(svl_packet_avail_bytes_fn_t fn, void *param)
|
||
|
|
{
|
||
|
|
ce3c: b480 push {r7}
|
||
|
|
ce3e: b083 sub sp, #12
|
||
|
|
ce40: af00 add r7, sp, #0
|
||
|
|
ce42: 6078 str r0, [r7, #4]
|
||
|
|
ce44: 6039 str r1, [r7, #0]
|
||
|
|
avail_param = param;
|
||
|
|
ce46: 4a06 ldr r2, [pc, #24] ; (ce60 <svl_packet_link_avail_fn+0x24>)
|
||
|
|
ce48: 683b ldr r3, [r7, #0]
|
||
|
|
ce4a: 6013 str r3, [r2, #0]
|
||
|
|
avail_fn = fn;
|
||
|
|
ce4c: 4a05 ldr r2, [pc, #20] ; (ce64 <svl_packet_link_avail_fn+0x28>)
|
||
|
|
ce4e: 687b ldr r3, [r7, #4]
|
||
|
|
ce50: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
ce52: bf00 nop
|
||
|
|
ce54: 370c adds r7, #12
|
||
|
|
ce56: 46bd mov sp, r7
|
||
|
|
ce58: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
ce5c: 4770 bx lr
|
||
|
|
ce5e: bf00 nop
|
||
|
|
ce60: 10000a44 .word 0x10000a44
|
||
|
|
ce64: 10000a50 .word 0x10000a50
|
||
|
|
|
||
|
|
0000ce68 <svl_packet_link_millis_fn>:
|
||
|
|
|
||
|
|
void svl_packet_link_millis_fn(svl_packet_millis_fn_t fn)
|
||
|
|
{
|
||
|
|
ce68: b480 push {r7}
|
||
|
|
ce6a: b083 sub sp, #12
|
||
|
|
ce6c: af00 add r7, sp, #0
|
||
|
|
ce6e: 6078 str r0, [r7, #4]
|
||
|
|
millis_fn = fn;
|
||
|
|
ce70: 4a04 ldr r2, [pc, #16] ; (ce84 <svl_packet_link_millis_fn+0x1c>)
|
||
|
|
ce72: 687b ldr r3, [r7, #4]
|
||
|
|
ce74: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
ce76: bf00 nop
|
||
|
|
ce78: 370c adds r7, #12
|
||
|
|
ce7a: 46bd mov sp, r7
|
||
|
|
ce7c: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
ce80: 4770 bx lr
|
||
|
|
ce82: bf00 nop
|
||
|
|
ce84: 10000a54 .word 0x10000a54
|
||
|
|
|
||
|
|
0000ce88 <svl_packet_send>:
|
||
|
|
|
||
|
|
void svl_packet_send(svl_packet_t *packet)
|
||
|
|
{
|
||
|
|
ce88: b580 push {r7, lr}
|
||
|
|
ce8a: b092 sub sp, #72 ; 0x48
|
||
|
|
ce8c: af00 add r7, sp, #0
|
||
|
|
ce8e: 6078 str r0, [r7, #4]
|
||
|
|
CRCL = 0;
|
||
|
|
ce90: 4b74 ldr r3, [pc, #464] ; (d064 <svl_packet_send+0x1dc>)
|
||
|
|
ce92: 2200 movs r2, #0
|
||
|
|
ce94: 701a strb r2, [r3, #0]
|
||
|
|
CRCH = 0;
|
||
|
|
ce96: 4b74 ldr r3, [pc, #464] ; (d068 <svl_packet_send+0x1e0>)
|
||
|
|
ce98: 2200 movs r2, #0
|
||
|
|
ce9a: 701a strb r2, [r3, #0]
|
||
|
|
updateCRC(packet->cmd); //Add this byte to CRC
|
||
|
|
ce9c: 687b ldr r3, [r7, #4]
|
||
|
|
ce9e: 781b ldrb r3, [r3, #0]
|
||
|
|
cea0: f887 3041 strb.w r3, [r7, #65] ; 0x41
|
||
|
|
uint16_t tableAddr = (num ^ CRCH);
|
||
|
|
cea4: 4b70 ldr r3, [pc, #448] ; (d068 <svl_packet_send+0x1e0>)
|
||
|
|
cea6: 781a ldrb r2, [r3, #0]
|
||
|
|
cea8: f897 3041 ldrb.w r3, [r7, #65] ; 0x41
|
||
|
|
ceac: 4053 eors r3, r2
|
||
|
|
ceae: b2db uxtb r3, r3
|
||
|
|
ceb0: 87fb strh r3, [r7, #62] ; 0x3e
|
||
|
|
CRCH = (CRC_Table[tableAddr] >> 8) ^ CRCL;
|
||
|
|
ceb2: 8ffb ldrh r3, [r7, #62] ; 0x3e
|
||
|
|
ceb4: 4a6d ldr r2, [pc, #436] ; (d06c <svl_packet_send+0x1e4>)
|
||
|
|
ceb6: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
ceba: 0a1b lsrs r3, r3, #8
|
||
|
|
cebc: b29b uxth r3, r3
|
||
|
|
cebe: b2da uxtb r2, r3
|
||
|
|
cec0: 4b68 ldr r3, [pc, #416] ; (d064 <svl_packet_send+0x1dc>)
|
||
|
|
cec2: 781b ldrb r3, [r3, #0]
|
||
|
|
cec4: 4053 eors r3, r2
|
||
|
|
cec6: b2da uxtb r2, r3
|
||
|
|
cec8: 4b67 ldr r3, [pc, #412] ; (d068 <svl_packet_send+0x1e0>)
|
||
|
|
ceca: 701a strb r2, [r3, #0]
|
||
|
|
CRCL = (CRC_Table[tableAddr] & 0x00FF);
|
||
|
|
cecc: 8ffb ldrh r3, [r7, #62] ; 0x3e
|
||
|
|
cece: 4a67 ldr r2, [pc, #412] ; (d06c <svl_packet_send+0x1e4>)
|
||
|
|
ced0: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
ced4: b2da uxtb r2, r3
|
||
|
|
ced6: 4b63 ldr r3, [pc, #396] ; (d064 <svl_packet_send+0x1dc>)
|
||
|
|
ced8: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
ceda: bf00 nop
|
||
|
|
for (uint32_t x = 0; x < packet->pl_len; x++)
|
||
|
|
cedc: 2300 movs r3, #0
|
||
|
|
cede: 647b str r3, [r7, #68] ; 0x44
|
||
|
|
cee0: e025 b.n cf2e <svl_packet_send+0xa6>
|
||
|
|
{
|
||
|
|
updateCRC(*(packet->pl + x)); //Add this byte to CRC
|
||
|
|
cee2: 687b ldr r3, [r7, #4]
|
||
|
|
cee4: 685a ldr r2, [r3, #4]
|
||
|
|
cee6: 6c7b ldr r3, [r7, #68] ; 0x44
|
||
|
|
cee8: 4413 add r3, r2
|
||
|
|
ceea: 781b ldrb r3, [r3, #0]
|
||
|
|
ceec: f887 303d strb.w r3, [r7, #61] ; 0x3d
|
||
|
|
uint16_t tableAddr = (num ^ CRCH);
|
||
|
|
cef0: 4b5d ldr r3, [pc, #372] ; (d068 <svl_packet_send+0x1e0>)
|
||
|
|
cef2: 781a ldrb r2, [r3, #0]
|
||
|
|
cef4: f897 303d ldrb.w r3, [r7, #61] ; 0x3d
|
||
|
|
cef8: 4053 eors r3, r2
|
||
|
|
cefa: b2db uxtb r3, r3
|
||
|
|
cefc: 877b strh r3, [r7, #58] ; 0x3a
|
||
|
|
CRCH = (CRC_Table[tableAddr] >> 8) ^ CRCL;
|
||
|
|
cefe: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
||
|
|
cf00: 4a5a ldr r2, [pc, #360] ; (d06c <svl_packet_send+0x1e4>)
|
||
|
|
cf02: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
cf06: 0a1b lsrs r3, r3, #8
|
||
|
|
cf08: b29b uxth r3, r3
|
||
|
|
cf0a: b2da uxtb r2, r3
|
||
|
|
cf0c: 4b55 ldr r3, [pc, #340] ; (d064 <svl_packet_send+0x1dc>)
|
||
|
|
cf0e: 781b ldrb r3, [r3, #0]
|
||
|
|
cf10: 4053 eors r3, r2
|
||
|
|
cf12: b2da uxtb r2, r3
|
||
|
|
cf14: 4b54 ldr r3, [pc, #336] ; (d068 <svl_packet_send+0x1e0>)
|
||
|
|
cf16: 701a strb r2, [r3, #0]
|
||
|
|
CRCL = (CRC_Table[tableAddr] & 0x00FF);
|
||
|
|
cf18: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
||
|
|
cf1a: 4a54 ldr r2, [pc, #336] ; (d06c <svl_packet_send+0x1e4>)
|
||
|
|
cf1c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
cf20: b2da uxtb r2, r3
|
||
|
|
cf22: 4b50 ldr r3, [pc, #320] ; (d064 <svl_packet_send+0x1dc>)
|
||
|
|
cf24: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
cf26: bf00 nop
|
||
|
|
for (uint32_t x = 0; x < packet->pl_len; x++)
|
||
|
|
cf28: 6c7b ldr r3, [r7, #68] ; 0x44
|
||
|
|
cf2a: 3301 adds r3, #1
|
||
|
|
cf2c: 647b str r3, [r7, #68] ; 0x44
|
||
|
|
cf2e: 687b ldr r3, [r7, #4]
|
||
|
|
cf30: 891b ldrh r3, [r3, #8]
|
||
|
|
cf32: 461a mov r2, r3
|
||
|
|
cf34: 6c7b ldr r3, [r7, #68] ; 0x44
|
||
|
|
cf36: 4293 cmp r3, r2
|
||
|
|
cf38: d3d3 bcc.n cee2 <svl_packet_send+0x5a>
|
||
|
|
}
|
||
|
|
|
||
|
|
svl_packet_write_byte(((packet->pl_len + 3) >> 8)); // len high byte (including command and CRC bytes)
|
||
|
|
cf3a: 687b ldr r3, [r7, #4]
|
||
|
|
cf3c: 891b ldrh r3, [r3, #8]
|
||
|
|
cf3e: 3303 adds r3, #3
|
||
|
|
cf40: 121b asrs r3, r3, #8
|
||
|
|
cf42: b2db uxtb r3, r3
|
||
|
|
cf44: f887 302b strb.w r3, [r7, #43] ; 0x2b
|
||
|
|
size_t retval = 0x00;
|
||
|
|
cf48: 2300 movs r3, #0
|
||
|
|
cf4a: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
if (write_fn != NULL)
|
||
|
|
cf4c: 4b48 ldr r3, [pc, #288] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cf4e: 681b ldr r3, [r3, #0]
|
||
|
|
cf50: 2b00 cmp r3, #0
|
||
|
|
cf52: d008 beq.n cf66 <svl_packet_send+0xde>
|
||
|
|
retval = write_fn(write_param, c);
|
||
|
|
cf54: 4b46 ldr r3, [pc, #280] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cf56: 681b ldr r3, [r3, #0]
|
||
|
|
cf58: 4a46 ldr r2, [pc, #280] ; (d074 <svl_packet_send+0x1ec>)
|
||
|
|
cf5a: 6812 ldr r2, [r2, #0]
|
||
|
|
cf5c: f897 102b ldrb.w r1, [r7, #43] ; 0x2b
|
||
|
|
cf60: 4610 mov r0, r2
|
||
|
|
cf62: 4798 blx r3
|
||
|
|
cf64: 6278 str r0, [r7, #36] ; 0x24
|
||
|
|
svl_packet_write_byte(((packet->pl_len + 3) & 0xFF)); // len low byte (including command and CRC bytes)
|
||
|
|
cf66: 687b ldr r3, [r7, #4]
|
||
|
|
cf68: 891b ldrh r3, [r3, #8]
|
||
|
|
cf6a: b2db uxtb r3, r3
|
||
|
|
cf6c: 3303 adds r3, #3
|
||
|
|
cf6e: b2db uxtb r3, r3
|
||
|
|
cf70: f887 3033 strb.w r3, [r7, #51] ; 0x33
|
||
|
|
size_t retval = 0x00;
|
||
|
|
cf74: 2300 movs r3, #0
|
||
|
|
cf76: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
if (write_fn != NULL)
|
||
|
|
cf78: 4b3d ldr r3, [pc, #244] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cf7a: 681b ldr r3, [r3, #0]
|
||
|
|
cf7c: 2b00 cmp r3, #0
|
||
|
|
cf7e: d008 beq.n cf92 <svl_packet_send+0x10a>
|
||
|
|
retval = write_fn(write_param, c);
|
||
|
|
cf80: 4b3b ldr r3, [pc, #236] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cf82: 681b ldr r3, [r3, #0]
|
||
|
|
cf84: 4a3b ldr r2, [pc, #236] ; (d074 <svl_packet_send+0x1ec>)
|
||
|
|
cf86: 6812 ldr r2, [r2, #0]
|
||
|
|
cf88: f897 1033 ldrb.w r1, [r7, #51] ; 0x33
|
||
|
|
cf8c: 4610 mov r0, r2
|
||
|
|
cf8e: 4798 blx r3
|
||
|
|
cf90: 62f8 str r0, [r7, #44] ; 0x2c
|
||
|
|
|
||
|
|
svl_packet_write_byte((packet->cmd)); // command byte
|
||
|
|
cf92: 687b ldr r3, [r7, #4]
|
||
|
|
cf94: 781b ldrb r3, [r3, #0]
|
||
|
|
cf96: f887 3039 strb.w r3, [r7, #57] ; 0x39
|
||
|
|
size_t retval = 0x00;
|
||
|
|
cf9a: 2300 movs r3, #0
|
||
|
|
cf9c: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
if (write_fn != NULL)
|
||
|
|
cf9e: 4b34 ldr r3, [pc, #208] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cfa0: 681b ldr r3, [r3, #0]
|
||
|
|
cfa2: 2b00 cmp r3, #0
|
||
|
|
cfa4: d008 beq.n cfb8 <svl_packet_send+0x130>
|
||
|
|
retval = write_fn(write_param, c);
|
||
|
|
cfa6: 4b32 ldr r3, [pc, #200] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cfa8: 681b ldr r3, [r3, #0]
|
||
|
|
cfaa: 4a32 ldr r2, [pc, #200] ; (d074 <svl_packet_send+0x1ec>)
|
||
|
|
cfac: 6812 ldr r2, [r2, #0]
|
||
|
|
cfae: f897 1039 ldrb.w r1, [r7, #57] ; 0x39
|
||
|
|
cfb2: 4610 mov r0, r2
|
||
|
|
cfb4: 4798 blx r3
|
||
|
|
cfb6: 6378 str r0, [r7, #52] ; 0x34
|
||
|
|
|
||
|
|
if ((packet->pl != NULL) && (packet->pl_len != 0))
|
||
|
|
cfb8: 687b ldr r3, [r7, #4]
|
||
|
|
cfba: 685b ldr r3, [r3, #4]
|
||
|
|
cfbc: 2b00 cmp r3, #0
|
||
|
|
cfbe: d02a beq.n d016 <svl_packet_send+0x18e>
|
||
|
|
cfc0: 687b ldr r3, [r7, #4]
|
||
|
|
cfc2: 891b ldrh r3, [r3, #8]
|
||
|
|
cfc4: 2b00 cmp r3, #0
|
||
|
|
cfc6: d026 beq.n d016 <svl_packet_send+0x18e>
|
||
|
|
{
|
||
|
|
for (uint16_t indi = 0; indi < packet->pl_len; indi++)
|
||
|
|
cfc8: 2300 movs r3, #0
|
||
|
|
cfca: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
|
||
|
|
cfce: e01c b.n d00a <svl_packet_send+0x182>
|
||
|
|
{ // payload
|
||
|
|
svl_packet_write_byte(*(packet->pl + indi));
|
||
|
|
cfd0: 687b ldr r3, [r7, #4]
|
||
|
|
cfd2: 685a ldr r2, [r3, #4]
|
||
|
|
cfd4: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
|
||
|
|
cfd8: 4413 add r3, r2
|
||
|
|
cfda: 781b ldrb r3, [r3, #0]
|
||
|
|
cfdc: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
size_t retval = 0x00;
|
||
|
|
cfe0: 2300 movs r3, #0
|
||
|
|
cfe2: 61fb str r3, [r7, #28]
|
||
|
|
if (write_fn != NULL)
|
||
|
|
cfe4: 4b22 ldr r3, [pc, #136] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cfe6: 681b ldr r3, [r3, #0]
|
||
|
|
cfe8: 2b00 cmp r3, #0
|
||
|
|
cfea: d008 beq.n cffe <svl_packet_send+0x176>
|
||
|
|
retval = write_fn(write_param, c);
|
||
|
|
cfec: 4b20 ldr r3, [pc, #128] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
cfee: 681b ldr r3, [r3, #0]
|
||
|
|
cff0: 4a20 ldr r2, [pc, #128] ; (d074 <svl_packet_send+0x1ec>)
|
||
|
|
cff2: 6812 ldr r2, [r2, #0]
|
||
|
|
cff4: f897 1023 ldrb.w r1, [r7, #35] ; 0x23
|
||
|
|
cff8: 4610 mov r0, r2
|
||
|
|
cffa: 4798 blx r3
|
||
|
|
cffc: 61f8 str r0, [r7, #28]
|
||
|
|
return retval;
|
||
|
|
cffe: bf00 nop
|
||
|
|
for (uint16_t indi = 0; indi < packet->pl_len; indi++)
|
||
|
|
d000: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
|
||
|
|
d004: 3301 adds r3, #1
|
||
|
|
d006: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
|
||
|
|
d00a: 687b ldr r3, [r7, #4]
|
||
|
|
d00c: 891b ldrh r3, [r3, #8]
|
||
|
|
d00e: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
||
|
|
d012: 429a cmp r2, r3
|
||
|
|
d014: d3dc bcc.n cfd0 <svl_packet_send+0x148>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
svl_packet_write_byte(CRCH); // CRC H
|
||
|
|
d016: 4b14 ldr r3, [pc, #80] ; (d068 <svl_packet_send+0x1e0>)
|
||
|
|
d018: 781b ldrb r3, [r3, #0]
|
||
|
|
d01a: 74fb strb r3, [r7, #19]
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d01c: 2300 movs r3, #0
|
||
|
|
d01e: 60fb str r3, [r7, #12]
|
||
|
|
if (write_fn != NULL)
|
||
|
|
d020: 4b13 ldr r3, [pc, #76] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
d022: 681b ldr r3, [r3, #0]
|
||
|
|
d024: 2b00 cmp r3, #0
|
||
|
|
d026: d007 beq.n d038 <svl_packet_send+0x1b0>
|
||
|
|
retval = write_fn(write_param, c);
|
||
|
|
d028: 4b11 ldr r3, [pc, #68] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
d02a: 681b ldr r3, [r3, #0]
|
||
|
|
d02c: 4a11 ldr r2, [pc, #68] ; (d074 <svl_packet_send+0x1ec>)
|
||
|
|
d02e: 6812 ldr r2, [r2, #0]
|
||
|
|
d030: 7cf9 ldrb r1, [r7, #19]
|
||
|
|
d032: 4610 mov r0, r2
|
||
|
|
d034: 4798 blx r3
|
||
|
|
d036: 60f8 str r0, [r7, #12]
|
||
|
|
svl_packet_write_byte(CRCL); // CRC L
|
||
|
|
d038: 4b0a ldr r3, [pc, #40] ; (d064 <svl_packet_send+0x1dc>)
|
||
|
|
d03a: 781b ldrb r3, [r3, #0]
|
||
|
|
d03c: 76fb strb r3, [r7, #27]
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d03e: 2300 movs r3, #0
|
||
|
|
d040: 617b str r3, [r7, #20]
|
||
|
|
if (write_fn != NULL)
|
||
|
|
d042: 4b0b ldr r3, [pc, #44] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
d044: 681b ldr r3, [r3, #0]
|
||
|
|
d046: 2b00 cmp r3, #0
|
||
|
|
d048: d007 beq.n d05a <svl_packet_send+0x1d2>
|
||
|
|
retval = write_fn(write_param, c);
|
||
|
|
d04a: 4b09 ldr r3, [pc, #36] ; (d070 <svl_packet_send+0x1e8>)
|
||
|
|
d04c: 681b ldr r3, [r3, #0]
|
||
|
|
d04e: 4a09 ldr r2, [pc, #36] ; (d074 <svl_packet_send+0x1ec>)
|
||
|
|
d050: 6812 ldr r2, [r2, #0]
|
||
|
|
d052: 7ef9 ldrb r1, [r7, #27]
|
||
|
|
d054: 4610 mov r0, r2
|
||
|
|
d056: 4798 blx r3
|
||
|
|
d058: 6178 str r0, [r7, #20]
|
||
|
|
}
|
||
|
|
d05a: bf00 nop
|
||
|
|
d05c: 3748 adds r7, #72 ; 0x48
|
||
|
|
d05e: 46bd mov sp, r7
|
||
|
|
d060: bd80 pop {r7, pc}
|
||
|
|
d062: bf00 nop
|
||
|
|
d064: 10000a74 .word 0x10000a74
|
||
|
|
d068: 10000a75 .word 0x10000a75
|
||
|
|
d06c: 10000000 .word 0x10000000
|
||
|
|
d070: 10000a4c .word 0x10000a4c
|
||
|
|
d074: 10000a40 .word 0x10000a40
|
||
|
|
|
||
|
|
0000d078 <svl_packet_wait>:
|
||
|
|
|
||
|
|
uint8_t svl_packet_wait(svl_packet_t *packet)
|
||
|
|
{
|
||
|
|
d078: b580 push {r7, lr}
|
||
|
|
d07a: b08c sub sp, #48 ; 0x30
|
||
|
|
d07c: af00 add r7, sp, #0
|
||
|
|
d07e: 6078 str r0, [r7, #4]
|
||
|
|
|
||
|
|
// wait for 2 bytes (the length bytes)
|
||
|
|
// wait for length bytes to come in
|
||
|
|
// make sure that 'length' bytes are enough to satisfy the desired payload length
|
||
|
|
|
||
|
|
if (packet == NULL)
|
||
|
|
d080: 687b ldr r3, [r7, #4]
|
||
|
|
d082: 2b00 cmp r3, #0
|
||
|
|
d084: d101 bne.n d08a <svl_packet_wait+0x12>
|
||
|
|
{
|
||
|
|
return (SVL_PACKET_ERR);
|
||
|
|
d086: 2301 movs r3, #1
|
||
|
|
d088: e0c1 b.n d20e <svl_packet_wait+0x196>
|
||
|
|
}
|
||
|
|
|
||
|
|
const uint8_t num_bytes_length = 2;
|
||
|
|
d08a: 2302 movs r3, #2
|
||
|
|
d08c: f887 302b strb.w r3, [r7, #43] ; 0x2b
|
||
|
|
if (svl_packet_wait_bytes(num_bytes_length))
|
||
|
|
d090: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
|
||
|
|
d094: 4618 mov r0, r3
|
||
|
|
d096: f000 f901 bl d29c <svl_packet_wait_bytes>
|
||
|
|
d09a: 4603 mov r3, r0
|
||
|
|
d09c: 2b00 cmp r3, #0
|
||
|
|
d09e: d001 beq.n d0a4 <svl_packet_wait+0x2c>
|
||
|
|
{
|
||
|
|
return (SVL_PACKET_ERR_TIMEOUT | SVL_PACKET_LEN);
|
||
|
|
d0a0: 2382 movs r3, #130 ; 0x82
|
||
|
|
d0a2: e0b4 b.n d20e <svl_packet_wait+0x196>
|
||
|
|
}
|
||
|
|
uint16_t len = svl_packet_get_uint16_t();
|
||
|
|
d0a4: f000 f8c2 bl d22c <svl_packet_get_uint16_t>
|
||
|
|
d0a8: 4603 mov r3, r0
|
||
|
|
d0aa: 853b strh r3, [r7, #40] ; 0x28
|
||
|
|
|
||
|
|
if (len == 0)
|
||
|
|
d0ac: 8d3b ldrh r3, [r7, #40] ; 0x28
|
||
|
|
d0ae: 2b00 cmp r3, #0
|
||
|
|
d0b0: d101 bne.n d0b6 <svl_packet_wait+0x3e>
|
||
|
|
{
|
||
|
|
return (SVL_PACKET_ERR_ZLP);
|
||
|
|
d0b2: 2304 movs r3, #4
|
||
|
|
d0b4: e0ab b.n d20e <svl_packet_wait+0x196>
|
||
|
|
}
|
||
|
|
if ((len - 3) > packet->max_pl_len)
|
||
|
|
d0b6: 8d3b ldrh r3, [r7, #40] ; 0x28
|
||
|
|
d0b8: 3b03 subs r3, #3
|
||
|
|
d0ba: 687a ldr r2, [r7, #4]
|
||
|
|
d0bc: 8952 ldrh r2, [r2, #10]
|
||
|
|
d0be: 4293 cmp r3, r2
|
||
|
|
d0c0: dd01 ble.n d0c6 <svl_packet_wait+0x4e>
|
||
|
|
{
|
||
|
|
return (SVL_PACKET_ERR_MEM | SVL_PACKET_PL);
|
||
|
|
d0c2: 2348 movs r3, #72 ; 0x48
|
||
|
|
d0c4: e0a3 b.n d20e <svl_packet_wait+0x196>
|
||
|
|
}
|
||
|
|
|
||
|
|
//Wait for entire packet to come in
|
||
|
|
if (svl_packet_wait_bytes(len))
|
||
|
|
d0c6: 8d3b ldrh r3, [r7, #40] ; 0x28
|
||
|
|
d0c8: 4618 mov r0, r3
|
||
|
|
d0ca: f000 f8e7 bl d29c <svl_packet_wait_bytes>
|
||
|
|
d0ce: 4603 mov r3, r0
|
||
|
|
d0d0: 2b00 cmp r3, #0
|
||
|
|
d0d2: d001 beq.n d0d8 <svl_packet_wait+0x60>
|
||
|
|
return (SVL_PACKET_ERR_TIMEOUT | SVL_PACKET_PL);
|
||
|
|
d0d4: 2342 movs r3, #66 ; 0x42
|
||
|
|
d0d6: e09a b.n d20e <svl_packet_wait+0x196>
|
||
|
|
|
||
|
|
uint8_t incoming;
|
||
|
|
CRCL = 0;
|
||
|
|
d0d8: 4b4f ldr r3, [pc, #316] ; (d218 <svl_packet_wait+0x1a0>)
|
||
|
|
d0da: 2200 movs r2, #0
|
||
|
|
d0dc: 701a strb r2, [r3, #0]
|
||
|
|
CRCH = 0;
|
||
|
|
d0de: 4b4f ldr r3, [pc, #316] ; (d21c <svl_packet_wait+0x1a4>)
|
||
|
|
d0e0: 2200 movs r2, #0
|
||
|
|
d0e2: 701a strb r2, [r3, #0]
|
||
|
|
d0e4: f107 030b add.w r3, r7, #11
|
||
|
|
d0e8: 61fb str r3, [r7, #28]
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d0ea: 2300 movs r3, #0
|
||
|
|
d0ec: 61bb str r3, [r7, #24]
|
||
|
|
if (read_fn != NULL)
|
||
|
|
d0ee: 4b4c ldr r3, [pc, #304] ; (d220 <svl_packet_wait+0x1a8>)
|
||
|
|
d0f0: 681b ldr r3, [r3, #0]
|
||
|
|
d0f2: 2b00 cmp r3, #0
|
||
|
|
d0f4: d007 beq.n d106 <svl_packet_wait+0x8e>
|
||
|
|
retval = read_fn(read_param, c);
|
||
|
|
d0f6: 4b4a ldr r3, [pc, #296] ; (d220 <svl_packet_wait+0x1a8>)
|
||
|
|
d0f8: 681b ldr r3, [r3, #0]
|
||
|
|
d0fa: 4a4a ldr r2, [pc, #296] ; (d224 <svl_packet_wait+0x1ac>)
|
||
|
|
d0fc: 6812 ldr r2, [r2, #0]
|
||
|
|
d0fe: 69f9 ldr r1, [r7, #28]
|
||
|
|
d100: 4610 mov r0, r2
|
||
|
|
d102: 4798 blx r3
|
||
|
|
d104: 61b8 str r0, [r7, #24]
|
||
|
|
|
||
|
|
//Get command byte
|
||
|
|
svl_packet_read_byte(&incoming);
|
||
|
|
packet->cmd = incoming;
|
||
|
|
d106: 7afa ldrb r2, [r7, #11]
|
||
|
|
d108: 687b ldr r3, [r7, #4]
|
||
|
|
d10a: 701a strb r2, [r3, #0]
|
||
|
|
updateCRC(incoming); //Add this byte to CRC
|
||
|
|
d10c: 7afb ldrb r3, [r7, #11]
|
||
|
|
d10e: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
uint16_t tableAddr = (num ^ CRCH);
|
||
|
|
d112: 4b42 ldr r3, [pc, #264] ; (d21c <svl_packet_wait+0x1a4>)
|
||
|
|
d114: 781a ldrb r2, [r3, #0]
|
||
|
|
d116: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
||
|
|
d11a: 4053 eors r3, r2
|
||
|
|
d11c: b2db uxtb r3, r3
|
||
|
|
d11e: 843b strh r3, [r7, #32]
|
||
|
|
CRCH = (CRC_Table[tableAddr] >> 8) ^ CRCL;
|
||
|
|
d120: 8c3b ldrh r3, [r7, #32]
|
||
|
|
d122: 4a41 ldr r2, [pc, #260] ; (d228 <svl_packet_wait+0x1b0>)
|
||
|
|
d124: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
d128: 0a1b lsrs r3, r3, #8
|
||
|
|
d12a: b29b uxth r3, r3
|
||
|
|
d12c: b2da uxtb r2, r3
|
||
|
|
d12e: 4b3a ldr r3, [pc, #232] ; (d218 <svl_packet_wait+0x1a0>)
|
||
|
|
d130: 781b ldrb r3, [r3, #0]
|
||
|
|
d132: 4053 eors r3, r2
|
||
|
|
d134: b2da uxtb r2, r3
|
||
|
|
d136: 4b39 ldr r3, [pc, #228] ; (d21c <svl_packet_wait+0x1a4>)
|
||
|
|
d138: 701a strb r2, [r3, #0]
|
||
|
|
CRCL = (CRC_Table[tableAddr] & 0x00FF);
|
||
|
|
d13a: 8c3b ldrh r3, [r7, #32]
|
||
|
|
d13c: 4a3a ldr r2, [pc, #232] ; (d228 <svl_packet_wait+0x1b0>)
|
||
|
|
d13e: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
d142: b2da uxtb r2, r3
|
||
|
|
d144: 4b34 ldr r3, [pc, #208] ; (d218 <svl_packet_wait+0x1a0>)
|
||
|
|
d146: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
d148: bf00 nop
|
||
|
|
|
||
|
|
packet->pl_len = (len - 3);
|
||
|
|
d14a: 8d3b ldrh r3, [r7, #40] ; 0x28
|
||
|
|
d14c: 3b03 subs r3, #3
|
||
|
|
d14e: b29a uxth r2, r3
|
||
|
|
d150: 687b ldr r3, [r7, #4]
|
||
|
|
d152: 811a strh r2, [r3, #8]
|
||
|
|
|
||
|
|
//Now read the data coming in
|
||
|
|
if ((packet->pl != NULL) && (packet->max_pl_len != 0))
|
||
|
|
d154: 687b ldr r3, [r7, #4]
|
||
|
|
d156: 685b ldr r3, [r3, #4]
|
||
|
|
d158: 2b00 cmp r3, #0
|
||
|
|
d15a: d043 beq.n d1e4 <svl_packet_wait+0x16c>
|
||
|
|
d15c: 687b ldr r3, [r7, #4]
|
||
|
|
d15e: 895b ldrh r3, [r3, #10]
|
||
|
|
d160: 2b00 cmp r3, #0
|
||
|
|
d162: d03f beq.n d1e4 <svl_packet_wait+0x16c>
|
||
|
|
{
|
||
|
|
for (uint32_t x = 0; x < packet->pl_len; x++)
|
||
|
|
d164: 2300 movs r3, #0
|
||
|
|
d166: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
d168: e036 b.n d1d8 <svl_packet_wait+0x160>
|
||
|
|
d16a: f107 030b add.w r3, r7, #11
|
||
|
|
d16e: 613b str r3, [r7, #16]
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d170: 2300 movs r3, #0
|
||
|
|
d172: 60fb str r3, [r7, #12]
|
||
|
|
if (read_fn != NULL)
|
||
|
|
d174: 4b2a ldr r3, [pc, #168] ; (d220 <svl_packet_wait+0x1a8>)
|
||
|
|
d176: 681b ldr r3, [r3, #0]
|
||
|
|
d178: 2b00 cmp r3, #0
|
||
|
|
d17a: d007 beq.n d18c <svl_packet_wait+0x114>
|
||
|
|
retval = read_fn(read_param, c);
|
||
|
|
d17c: 4b28 ldr r3, [pc, #160] ; (d220 <svl_packet_wait+0x1a8>)
|
||
|
|
d17e: 681b ldr r3, [r3, #0]
|
||
|
|
d180: 4a28 ldr r2, [pc, #160] ; (d224 <svl_packet_wait+0x1ac>)
|
||
|
|
d182: 6812 ldr r2, [r2, #0]
|
||
|
|
d184: 6939 ldr r1, [r7, #16]
|
||
|
|
d186: 4610 mov r0, r2
|
||
|
|
d188: 4798 blx r3
|
||
|
|
d18a: 60f8 str r0, [r7, #12]
|
||
|
|
{
|
||
|
|
svl_packet_read_byte(&incoming);
|
||
|
|
|
||
|
|
updateCRC(incoming); //Add this byte to CRC
|
||
|
|
d18c: 7afb ldrb r3, [r7, #11]
|
||
|
|
d18e: 75fb strb r3, [r7, #23]
|
||
|
|
uint16_t tableAddr = (num ^ CRCH);
|
||
|
|
d190: 4b22 ldr r3, [pc, #136] ; (d21c <svl_packet_wait+0x1a4>)
|
||
|
|
d192: 781a ldrb r2, [r3, #0]
|
||
|
|
d194: 7dfb ldrb r3, [r7, #23]
|
||
|
|
d196: 4053 eors r3, r2
|
||
|
|
d198: b2db uxtb r3, r3
|
||
|
|
d19a: 82bb strh r3, [r7, #20]
|
||
|
|
CRCH = (CRC_Table[tableAddr] >> 8) ^ CRCL;
|
||
|
|
d19c: 8abb ldrh r3, [r7, #20]
|
||
|
|
d19e: 4a22 ldr r2, [pc, #136] ; (d228 <svl_packet_wait+0x1b0>)
|
||
|
|
d1a0: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
d1a4: 0a1b lsrs r3, r3, #8
|
||
|
|
d1a6: b29b uxth r3, r3
|
||
|
|
d1a8: b2da uxtb r2, r3
|
||
|
|
d1aa: 4b1b ldr r3, [pc, #108] ; (d218 <svl_packet_wait+0x1a0>)
|
||
|
|
d1ac: 781b ldrb r3, [r3, #0]
|
||
|
|
d1ae: 4053 eors r3, r2
|
||
|
|
d1b0: b2da uxtb r2, r3
|
||
|
|
d1b2: 4b1a ldr r3, [pc, #104] ; (d21c <svl_packet_wait+0x1a4>)
|
||
|
|
d1b4: 701a strb r2, [r3, #0]
|
||
|
|
CRCL = (CRC_Table[tableAddr] & 0x00FF);
|
||
|
|
d1b6: 8abb ldrh r3, [r7, #20]
|
||
|
|
d1b8: 4a1b ldr r2, [pc, #108] ; (d228 <svl_packet_wait+0x1b0>)
|
||
|
|
d1ba: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
||
|
|
d1be: b2da uxtb r2, r3
|
||
|
|
d1c0: 4b15 ldr r3, [pc, #84] ; (d218 <svl_packet_wait+0x1a0>)
|
||
|
|
d1c2: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
d1c4: bf00 nop
|
||
|
|
|
||
|
|
*(packet->pl + x) = incoming; //Fill payload with data
|
||
|
|
d1c6: 687b ldr r3, [r7, #4]
|
||
|
|
d1c8: 685a ldr r2, [r3, #4]
|
||
|
|
d1ca: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
d1cc: 4413 add r3, r2
|
||
|
|
d1ce: 7afa ldrb r2, [r7, #11]
|
||
|
|
d1d0: 701a strb r2, [r3, #0]
|
||
|
|
for (uint32_t x = 0; x < packet->pl_len; x++)
|
||
|
|
d1d2: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
d1d4: 3301 adds r3, #1
|
||
|
|
d1d6: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
d1d8: 687b ldr r3, [r7, #4]
|
||
|
|
d1da: 891b ldrh r3, [r3, #8]
|
||
|
|
d1dc: 461a mov r2, r3
|
||
|
|
d1de: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
d1e0: 4293 cmp r3, r2
|
||
|
|
d1e2: d3c2 bcc.n d16a <svl_packet_wait+0xf2>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
uint16_t crc = svl_packet_get_uint16_t(); //Read final two bytes into CRC
|
||
|
|
d1e4: f000 f822 bl d22c <svl_packet_get_uint16_t>
|
||
|
|
d1e8: 4603 mov r3, r0
|
||
|
|
d1ea: 84fb strh r3, [r7, #38] ; 0x26
|
||
|
|
|
||
|
|
uint16_t check = ((uint16_t)CRCH << 8) | CRCL;
|
||
|
|
d1ec: 4b0b ldr r3, [pc, #44] ; (d21c <svl_packet_wait+0x1a4>)
|
||
|
|
d1ee: 781b ldrb r3, [r3, #0]
|
||
|
|
d1f0: 021b lsls r3, r3, #8
|
||
|
|
d1f2: b21a sxth r2, r3
|
||
|
|
d1f4: 4b08 ldr r3, [pc, #32] ; (d218 <svl_packet_wait+0x1a0>)
|
||
|
|
d1f6: 781b ldrb r3, [r3, #0]
|
||
|
|
d1f8: b21b sxth r3, r3
|
||
|
|
d1fa: 4313 orrs r3, r2
|
||
|
|
d1fc: b21b sxth r3, r3
|
||
|
|
d1fe: 84bb strh r3, [r7, #36] ; 0x24
|
||
|
|
|
||
|
|
if (crc != check)
|
||
|
|
d200: 8cfa ldrh r2, [r7, #38] ; 0x26
|
||
|
|
d202: 8cbb ldrh r3, [r7, #36] ; 0x24
|
||
|
|
d204: 429a cmp r2, r3
|
||
|
|
d206: d001 beq.n d20c <svl_packet_wait+0x194>
|
||
|
|
{
|
||
|
|
return (SVL_PACKET_ERR_CRC);
|
||
|
|
d208: 2310 movs r3, #16
|
||
|
|
d20a: e000 b.n d20e <svl_packet_wait+0x196>
|
||
|
|
}
|
||
|
|
|
||
|
|
return (SVL_PACKET_OK);
|
||
|
|
d20c: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
d20e: 4618 mov r0, r3
|
||
|
|
d210: 3730 adds r7, #48 ; 0x30
|
||
|
|
d212: 46bd mov sp, r7
|
||
|
|
d214: bd80 pop {r7, pc}
|
||
|
|
d216: bf00 nop
|
||
|
|
d218: 10000a74 .word 0x10000a74
|
||
|
|
d21c: 10000a75 .word 0x10000a75
|
||
|
|
d220: 10000a48 .word 0x10000a48
|
||
|
|
d224: 10000a3c .word 0x10000a3c
|
||
|
|
d228: 10000000 .word 0x10000000
|
||
|
|
|
||
|
|
0000d22c <svl_packet_get_uint16_t>:
|
||
|
|
|
||
|
|
uint16_t svl_packet_get_uint16_t(void)
|
||
|
|
{
|
||
|
|
d22c: b580 push {r7, lr}
|
||
|
|
d22e: b086 sub sp, #24
|
||
|
|
d230: af00 add r7, sp, #0
|
||
|
|
uint8_t h = 0x00;
|
||
|
|
d232: 2300 movs r3, #0
|
||
|
|
d234: 71fb strb r3, [r7, #7]
|
||
|
|
uint8_t l = 0x00;
|
||
|
|
d236: 2300 movs r3, #0
|
||
|
|
d238: 71bb strb r3, [r7, #6]
|
||
|
|
d23a: 1dfb adds r3, r7, #7
|
||
|
|
d23c: 60fb str r3, [r7, #12]
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d23e: 2300 movs r3, #0
|
||
|
|
d240: 60bb str r3, [r7, #8]
|
||
|
|
if (read_fn != NULL)
|
||
|
|
d242: 4b14 ldr r3, [pc, #80] ; (d294 <svl_packet_get_uint16_t+0x68>)
|
||
|
|
d244: 681b ldr r3, [r3, #0]
|
||
|
|
d246: 2b00 cmp r3, #0
|
||
|
|
d248: d007 beq.n d25a <svl_packet_get_uint16_t+0x2e>
|
||
|
|
retval = read_fn(read_param, c);
|
||
|
|
d24a: 4b12 ldr r3, [pc, #72] ; (d294 <svl_packet_get_uint16_t+0x68>)
|
||
|
|
d24c: 681b ldr r3, [r3, #0]
|
||
|
|
d24e: 4a12 ldr r2, [pc, #72] ; (d298 <svl_packet_get_uint16_t+0x6c>)
|
||
|
|
d250: 6812 ldr r2, [r2, #0]
|
||
|
|
d252: 68f9 ldr r1, [r7, #12]
|
||
|
|
d254: 4610 mov r0, r2
|
||
|
|
d256: 4798 blx r3
|
||
|
|
d258: 60b8 str r0, [r7, #8]
|
||
|
|
d25a: 1dbb adds r3, r7, #6
|
||
|
|
d25c: 617b str r3, [r7, #20]
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d25e: 2300 movs r3, #0
|
||
|
|
d260: 613b str r3, [r7, #16]
|
||
|
|
if (read_fn != NULL)
|
||
|
|
d262: 4b0c ldr r3, [pc, #48] ; (d294 <svl_packet_get_uint16_t+0x68>)
|
||
|
|
d264: 681b ldr r3, [r3, #0]
|
||
|
|
d266: 2b00 cmp r3, #0
|
||
|
|
d268: d007 beq.n d27a <svl_packet_get_uint16_t+0x4e>
|
||
|
|
retval = read_fn(read_param, c);
|
||
|
|
d26a: 4b0a ldr r3, [pc, #40] ; (d294 <svl_packet_get_uint16_t+0x68>)
|
||
|
|
d26c: 681b ldr r3, [r3, #0]
|
||
|
|
d26e: 4a0a ldr r2, [pc, #40] ; (d298 <svl_packet_get_uint16_t+0x6c>)
|
||
|
|
d270: 6812 ldr r2, [r2, #0]
|
||
|
|
d272: 6979 ldr r1, [r7, #20]
|
||
|
|
d274: 4610 mov r0, r2
|
||
|
|
d276: 4798 blx r3
|
||
|
|
d278: 6138 str r0, [r7, #16]
|
||
|
|
svl_packet_read_byte(&h);
|
||
|
|
svl_packet_read_byte(&l);
|
||
|
|
return (((uint16_t)h << 8) | (l & 0xFF));
|
||
|
|
d27a: 79fb ldrb r3, [r7, #7]
|
||
|
|
d27c: 021b lsls r3, r3, #8
|
||
|
|
d27e: b21a sxth r2, r3
|
||
|
|
d280: 79bb ldrb r3, [r7, #6]
|
||
|
|
d282: b21b sxth r3, r3
|
||
|
|
d284: 4313 orrs r3, r2
|
||
|
|
d286: b21b sxth r3, r3
|
||
|
|
d288: b29b uxth r3, r3
|
||
|
|
}
|
||
|
|
d28a: 4618 mov r0, r3
|
||
|
|
d28c: 3718 adds r7, #24
|
||
|
|
d28e: 46bd mov sp, r7
|
||
|
|
d290: bd80 pop {r7, pc}
|
||
|
|
d292: bf00 nop
|
||
|
|
d294: 10000a48 .word 0x10000a48
|
||
|
|
d298: 10000a3c .word 0x10000a3c
|
||
|
|
|
||
|
|
0000d29c <svl_packet_wait_bytes>:
|
||
|
|
|
||
|
|
uint8_t svl_packet_wait_bytes(uint32_t num)
|
||
|
|
{
|
||
|
|
d29c: b580 push {r7, lr}
|
||
|
|
d29e: b088 sub sp, #32
|
||
|
|
d2a0: af00 add r7, sp, #0
|
||
|
|
d2a2: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t timeout_ms = 500;
|
||
|
|
d2a4: f44f 73fa mov.w r3, #500 ; 0x1f4
|
||
|
|
d2a8: 61fb str r3, [r7, #28]
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d2aa: 2300 movs r3, #0
|
||
|
|
d2ac: 613b str r3, [r7, #16]
|
||
|
|
if (millis_fn != NULL)
|
||
|
|
d2ae: 4b1b ldr r3, [pc, #108] ; (d31c <svl_packet_wait_bytes+0x80>)
|
||
|
|
d2b0: 681b ldr r3, [r3, #0]
|
||
|
|
d2b2: 2b00 cmp r3, #0
|
||
|
|
d2b4: d003 beq.n d2be <svl_packet_wait_bytes+0x22>
|
||
|
|
retval = millis_fn();
|
||
|
|
d2b6: 4b19 ldr r3, [pc, #100] ; (d31c <svl_packet_wait_bytes+0x80>)
|
||
|
|
d2b8: 681b ldr r3, [r3, #0]
|
||
|
|
d2ba: 4798 blx r3
|
||
|
|
d2bc: 6138 str r0, [r7, #16]
|
||
|
|
return retval;
|
||
|
|
d2be: 693b ldr r3, [r7, #16]
|
||
|
|
uint32_t start = svl_packet_millis();
|
||
|
|
d2c0: 61bb str r3, [r7, #24]
|
||
|
|
uint32_t avail = 0;
|
||
|
|
d2c2: 2300 movs r3, #0
|
||
|
|
d2c4: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
while ((svl_packet_millis() - start) < timeout_ms)
|
||
|
|
d2c6: e014 b.n d2f2 <svl_packet_wait_bytes+0x56>
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d2c8: 2300 movs r3, #0
|
||
|
|
d2ca: 60fb str r3, [r7, #12]
|
||
|
|
if (avail_fn != NULL)
|
||
|
|
d2cc: 4b14 ldr r3, [pc, #80] ; (d320 <svl_packet_wait_bytes+0x84>)
|
||
|
|
d2ce: 681b ldr r3, [r3, #0]
|
||
|
|
d2d0: 2b00 cmp r3, #0
|
||
|
|
d2d2: d006 beq.n d2e2 <svl_packet_wait_bytes+0x46>
|
||
|
|
retval = avail_fn(avail_param);
|
||
|
|
d2d4: 4b12 ldr r3, [pc, #72] ; (d320 <svl_packet_wait_bytes+0x84>)
|
||
|
|
d2d6: 681b ldr r3, [r3, #0]
|
||
|
|
d2d8: 4a12 ldr r2, [pc, #72] ; (d324 <svl_packet_wait_bytes+0x88>)
|
||
|
|
d2da: 6812 ldr r2, [r2, #0]
|
||
|
|
d2dc: 4610 mov r0, r2
|
||
|
|
d2de: 4798 blx r3
|
||
|
|
d2e0: 60f8 str r0, [r7, #12]
|
||
|
|
return retval;
|
||
|
|
d2e2: 68fb ldr r3, [r7, #12]
|
||
|
|
{
|
||
|
|
avail = svl_packet_avail_bytes();
|
||
|
|
d2e4: 617b str r3, [r7, #20]
|
||
|
|
if (avail >= num)
|
||
|
|
d2e6: 697a ldr r2, [r7, #20]
|
||
|
|
d2e8: 687b ldr r3, [r7, #4]
|
||
|
|
d2ea: 429a cmp r2, r3
|
||
|
|
d2ec: d301 bcc.n d2f2 <svl_packet_wait_bytes+0x56>
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
d2ee: 2300 movs r3, #0
|
||
|
|
d2f0: e010 b.n d314 <svl_packet_wait_bytes+0x78>
|
||
|
|
size_t retval = 0x00;
|
||
|
|
d2f2: 2300 movs r3, #0
|
||
|
|
d2f4: 60bb str r3, [r7, #8]
|
||
|
|
if (millis_fn != NULL)
|
||
|
|
d2f6: 4b09 ldr r3, [pc, #36] ; (d31c <svl_packet_wait_bytes+0x80>)
|
||
|
|
d2f8: 681b ldr r3, [r3, #0]
|
||
|
|
d2fa: 2b00 cmp r3, #0
|
||
|
|
d2fc: d003 beq.n d306 <svl_packet_wait_bytes+0x6a>
|
||
|
|
retval = millis_fn();
|
||
|
|
d2fe: 4b07 ldr r3, [pc, #28] ; (d31c <svl_packet_wait_bytes+0x80>)
|
||
|
|
d300: 681b ldr r3, [r3, #0]
|
||
|
|
d302: 4798 blx r3
|
||
|
|
d304: 60b8 str r0, [r7, #8]
|
||
|
|
return retval;
|
||
|
|
d306: 68ba ldr r2, [r7, #8]
|
||
|
|
while ((svl_packet_millis() - start) < timeout_ms)
|
||
|
|
d308: 69bb ldr r3, [r7, #24]
|
||
|
|
d30a: 1ad3 subs r3, r2, r3
|
||
|
|
d30c: 69fa ldr r2, [r7, #28]
|
||
|
|
d30e: 429a cmp r2, r3
|
||
|
|
d310: d8da bhi.n d2c8 <svl_packet_wait_bytes+0x2c>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// debug_printf("only got %d bytes...\n",avail);
|
||
|
|
return 1;
|
||
|
|
d312: 2301 movs r3, #1
|
||
|
|
d314: 4618 mov r0, r3
|
||
|
|
d316: 3720 adds r7, #32
|
||
|
|
d318: 46bd mov sp, r7
|
||
|
|
d31a: bd80 pop {r7, pc}
|
||
|
|
d31c: 10000a54 .word 0x10000a54
|
||
|
|
d320: 10000a50 .word 0x10000a50
|
||
|
|
d324: 10000a44 .word 0x10000a44
|
||
|
|
|
||
|
|
0000d328 <art_svl_ringbuf_init>:
|
||
|
|
#include "svl_ringbuf.h"
|
||
|
|
|
||
|
|
size_t art_svl_ringbuf_init( void* vrb, uint8_t* buf, size_t len ){
|
||
|
|
d328: b480 push {r7}
|
||
|
|
d32a: b087 sub sp, #28
|
||
|
|
d32c: af00 add r7, sp, #0
|
||
|
|
d32e: 60f8 str r0, [r7, #12]
|
||
|
|
d330: 60b9 str r1, [r7, #8]
|
||
|
|
d332: 607a str r2, [r7, #4]
|
||
|
|
if( vrb == NULL ){ return 0; }
|
||
|
|
d334: 68fb ldr r3, [r7, #12]
|
||
|
|
d336: 2b00 cmp r3, #0
|
||
|
|
d338: d101 bne.n d33e <art_svl_ringbuf_init+0x16>
|
||
|
|
d33a: 2300 movs r3, #0
|
||
|
|
d33c: e00f b.n d35e <art_svl_ringbuf_init+0x36>
|
||
|
|
art_svl_ringbuf_t* rb = (art_svl_ringbuf_t*)vrb;
|
||
|
|
d33e: 68fb ldr r3, [r7, #12]
|
||
|
|
d340: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
rb->buf = buf;
|
||
|
|
d342: 697b ldr r3, [r7, #20]
|
||
|
|
d344: 68ba ldr r2, [r7, #8]
|
||
|
|
d346: 601a str r2, [r3, #0]
|
||
|
|
rb->len = len;
|
||
|
|
d348: 697b ldr r3, [r7, #20]
|
||
|
|
d34a: 687a ldr r2, [r7, #4]
|
||
|
|
d34c: 605a str r2, [r3, #4]
|
||
|
|
rb->r_offset = 0;
|
||
|
|
d34e: 697b ldr r3, [r7, #20]
|
||
|
|
d350: 2200 movs r2, #0
|
||
|
|
d352: 609a str r2, [r3, #8]
|
||
|
|
rb->w_offset = 0;
|
||
|
|
d354: 697b ldr r3, [r7, #20]
|
||
|
|
d356: 2200 movs r2, #0
|
||
|
|
d358: 60da str r2, [r3, #12]
|
||
|
|
|
||
|
|
return rb->len;
|
||
|
|
d35a: 697b ldr r3, [r7, #20]
|
||
|
|
d35c: 685b ldr r3, [r3, #4]
|
||
|
|
}
|
||
|
|
d35e: 4618 mov r0, r3
|
||
|
|
d360: 371c adds r7, #28
|
||
|
|
d362: 46bd mov sp, r7
|
||
|
|
d364: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
d368: 4770 bx lr
|
||
|
|
|
||
|
|
0000d36a <art_svl_ringbuf_available>:
|
||
|
|
|
||
|
|
size_t art_svl_ringbuf_available( void* vrb ){
|
||
|
|
d36a: b480 push {r7}
|
||
|
|
d36c: b085 sub sp, #20
|
||
|
|
d36e: af00 add r7, sp, #0
|
||
|
|
d370: 6078 str r0, [r7, #4]
|
||
|
|
if( vrb == NULL ){ return 0; }
|
||
|
|
d372: 687b ldr r3, [r7, #4]
|
||
|
|
d374: 2b00 cmp r3, #0
|
||
|
|
d376: d101 bne.n d37c <art_svl_ringbuf_available+0x12>
|
||
|
|
d378: 2300 movs r3, #0
|
||
|
|
d37a: e01a b.n d3b2 <art_svl_ringbuf_available+0x48>
|
||
|
|
art_svl_ringbuf_t* rb = (art_svl_ringbuf_t*)vrb;
|
||
|
|
d37c: 687b ldr r3, [r7, #4]
|
||
|
|
d37e: 60bb str r3, [r7, #8]
|
||
|
|
|
||
|
|
size_t avail = 0x00;
|
||
|
|
d380: 2300 movs r3, #0
|
||
|
|
d382: 60fb str r3, [r7, #12]
|
||
|
|
if((rb->w_offset) >= (rb->r_offset)){
|
||
|
|
d384: 68bb ldr r3, [r7, #8]
|
||
|
|
d386: 68da ldr r2, [r3, #12]
|
||
|
|
d388: 68bb ldr r3, [r7, #8]
|
||
|
|
d38a: 689b ldr r3, [r3, #8]
|
||
|
|
d38c: 429a cmp r2, r3
|
||
|
|
d38e: d306 bcc.n d39e <art_svl_ringbuf_available+0x34>
|
||
|
|
avail = rb->w_offset - rb->r_offset;
|
||
|
|
d390: 68bb ldr r3, [r7, #8]
|
||
|
|
d392: 68da ldr r2, [r3, #12]
|
||
|
|
d394: 68bb ldr r3, [r7, #8]
|
||
|
|
d396: 689b ldr r3, [r3, #8]
|
||
|
|
d398: 1ad3 subs r3, r2, r3
|
||
|
|
d39a: 60fb str r3, [r7, #12]
|
||
|
|
d39c: e008 b.n d3b0 <art_svl_ringbuf_available+0x46>
|
||
|
|
}else{
|
||
|
|
avail = rb->len - (rb->r_offset - rb->w_offset);
|
||
|
|
d39e: 68bb ldr r3, [r7, #8]
|
||
|
|
d3a0: 685a ldr r2, [r3, #4]
|
||
|
|
d3a2: 68bb ldr r3, [r7, #8]
|
||
|
|
d3a4: 68d9 ldr r1, [r3, #12]
|
||
|
|
d3a6: 68bb ldr r3, [r7, #8]
|
||
|
|
d3a8: 689b ldr r3, [r3, #8]
|
||
|
|
d3aa: 1acb subs r3, r1, r3
|
||
|
|
d3ac: 4413 add r3, r2
|
||
|
|
d3ae: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
return avail;
|
||
|
|
d3b0: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
d3b2: 4618 mov r0, r3
|
||
|
|
d3b4: 3714 adds r7, #20
|
||
|
|
d3b6: 46bd mov sp, r7
|
||
|
|
d3b8: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
d3bc: 4770 bx lr
|
||
|
|
|
||
|
|
0000d3be <art_svl_ringbuf_bytes_free>:
|
||
|
|
|
||
|
|
size_t art_svl_ringbuf_bytes_free( void* vrb ){
|
||
|
|
d3be: b480 push {r7}
|
||
|
|
d3c0: b085 sub sp, #20
|
||
|
|
d3c2: af00 add r7, sp, #0
|
||
|
|
d3c4: 6078 str r0, [r7, #4]
|
||
|
|
if( vrb == NULL ){ return 0; }
|
||
|
|
d3c6: 687b ldr r3, [r7, #4]
|
||
|
|
d3c8: 2b00 cmp r3, #0
|
||
|
|
d3ca: d101 bne.n d3d0 <art_svl_ringbuf_bytes_free+0x12>
|
||
|
|
d3cc: 2300 movs r3, #0
|
||
|
|
d3ce: e01c b.n d40a <art_svl_ringbuf_bytes_free+0x4c>
|
||
|
|
art_svl_ringbuf_t* rb = (art_svl_ringbuf_t*)vrb;
|
||
|
|
d3d0: 687b ldr r3, [r7, #4]
|
||
|
|
d3d2: 60bb str r3, [r7, #8]
|
||
|
|
|
||
|
|
size_t friegh = 0x00;
|
||
|
|
d3d4: 2300 movs r3, #0
|
||
|
|
d3d6: 60fb str r3, [r7, #12]
|
||
|
|
if((rb->w_offset) >= (rb->r_offset)){
|
||
|
|
d3d8: 68bb ldr r3, [r7, #8]
|
||
|
|
d3da: 68da ldr r2, [r3, #12]
|
||
|
|
d3dc: 68bb ldr r3, [r7, #8]
|
||
|
|
d3de: 689b ldr r3, [r3, #8]
|
||
|
|
d3e0: 429a cmp r2, r3
|
||
|
|
d3e2: d30a bcc.n d3fa <art_svl_ringbuf_bytes_free+0x3c>
|
||
|
|
friegh = rb->len - rb->w_offset + rb->r_offset -1;
|
||
|
|
d3e4: 68bb ldr r3, [r7, #8]
|
||
|
|
d3e6: 685a ldr r2, [r3, #4]
|
||
|
|
d3e8: 68bb ldr r3, [r7, #8]
|
||
|
|
d3ea: 68db ldr r3, [r3, #12]
|
||
|
|
d3ec: 1ad2 subs r2, r2, r3
|
||
|
|
d3ee: 68bb ldr r3, [r7, #8]
|
||
|
|
d3f0: 689b ldr r3, [r3, #8]
|
||
|
|
d3f2: 4413 add r3, r2
|
||
|
|
d3f4: 3b01 subs r3, #1
|
||
|
|
d3f6: 60fb str r3, [r7, #12]
|
||
|
|
d3f8: e006 b.n d408 <art_svl_ringbuf_bytes_free+0x4a>
|
||
|
|
}else{
|
||
|
|
friegh = rb->r_offset - rb->w_offset - 1;
|
||
|
|
d3fa: 68bb ldr r3, [r7, #8]
|
||
|
|
d3fc: 689a ldr r2, [r3, #8]
|
||
|
|
d3fe: 68bb ldr r3, [r7, #8]
|
||
|
|
d400: 68db ldr r3, [r3, #12]
|
||
|
|
d402: 1ad3 subs r3, r2, r3
|
||
|
|
d404: 3b01 subs r3, #1
|
||
|
|
d406: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
return friegh;
|
||
|
|
d408: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
d40a: 4618 mov r0, r3
|
||
|
|
d40c: 3714 adds r7, #20
|
||
|
|
d40e: 46bd mov sp, r7
|
||
|
|
d410: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
d414: 4770 bx lr
|
||
|
|
|
||
|
|
0000d416 <art_svl_ringbuf_write>:
|
||
|
|
|
||
|
|
size_t art_svl_ringbuf_write( void* vrb, uint8_t c ){
|
||
|
|
d416: b580 push {r7, lr}
|
||
|
|
d418: b084 sub sp, #16
|
||
|
|
d41a: af00 add r7, sp, #0
|
||
|
|
d41c: 6078 str r0, [r7, #4]
|
||
|
|
d41e: 460b mov r3, r1
|
||
|
|
d420: 70fb strb r3, [r7, #3]
|
||
|
|
if( vrb == NULL ){ return 0; }
|
||
|
|
d422: 687b ldr r3, [r7, #4]
|
||
|
|
d424: 2b00 cmp r3, #0
|
||
|
|
d426: d101 bne.n d42c <art_svl_ringbuf_write+0x16>
|
||
|
|
d428: 2300 movs r3, #0
|
||
|
|
d42a: e01f b.n d46c <art_svl_ringbuf_write+0x56>
|
||
|
|
art_svl_ringbuf_t* rb = (art_svl_ringbuf_t*)vrb;
|
||
|
|
d42c: 687b ldr r3, [r7, #4]
|
||
|
|
d42e: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if(art_svl_ringbuf_bytes_free(rb) > 0){
|
||
|
|
d430: 68f8 ldr r0, [r7, #12]
|
||
|
|
d432: f7ff ffc4 bl d3be <art_svl_ringbuf_bytes_free>
|
||
|
|
d436: 4603 mov r3, r0
|
||
|
|
d438: 2b00 cmp r3, #0
|
||
|
|
d43a: d016 beq.n d46a <art_svl_ringbuf_write+0x54>
|
||
|
|
*(rb->buf + rb->w_offset) = c;
|
||
|
|
d43c: 68fb ldr r3, [r7, #12]
|
||
|
|
d43e: 681a ldr r2, [r3, #0]
|
||
|
|
d440: 68fb ldr r3, [r7, #12]
|
||
|
|
d442: 68db ldr r3, [r3, #12]
|
||
|
|
d444: 4413 add r3, r2
|
||
|
|
d446: 78fa ldrb r2, [r7, #3]
|
||
|
|
d448: 701a strb r2, [r3, #0]
|
||
|
|
rb->w_offset++;
|
||
|
|
d44a: 68fb ldr r3, [r7, #12]
|
||
|
|
d44c: 68db ldr r3, [r3, #12]
|
||
|
|
d44e: 1c5a adds r2, r3, #1
|
||
|
|
d450: 68fb ldr r3, [r7, #12]
|
||
|
|
d452: 60da str r2, [r3, #12]
|
||
|
|
if(rb->w_offset >= rb->len){
|
||
|
|
d454: 68fb ldr r3, [r7, #12]
|
||
|
|
d456: 68da ldr r2, [r3, #12]
|
||
|
|
d458: 68fb ldr r3, [r7, #12]
|
||
|
|
d45a: 685b ldr r3, [r3, #4]
|
||
|
|
d45c: 429a cmp r2, r3
|
||
|
|
d45e: d302 bcc.n d466 <art_svl_ringbuf_write+0x50>
|
||
|
|
rb->w_offset = 0;
|
||
|
|
d460: 68fb ldr r3, [r7, #12]
|
||
|
|
d462: 2200 movs r2, #0
|
||
|
|
d464: 60da str r2, [r3, #12]
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
d466: 2301 movs r3, #1
|
||
|
|
d468: e000 b.n d46c <art_svl_ringbuf_write+0x56>
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
d46a: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
d46c: 4618 mov r0, r3
|
||
|
|
d46e: 3710 adds r7, #16
|
||
|
|
d470: 46bd mov sp, r7
|
||
|
|
d472: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0000d474 <art_svl_ringbuf_read>:
|
||
|
|
|
||
|
|
size_t art_svl_ringbuf_read( void* vrb, uint8_t* c ){
|
||
|
|
d474: b580 push {r7, lr}
|
||
|
|
d476: b084 sub sp, #16
|
||
|
|
d478: af00 add r7, sp, #0
|
||
|
|
d47a: 6078 str r0, [r7, #4]
|
||
|
|
d47c: 6039 str r1, [r7, #0]
|
||
|
|
if( vrb == NULL ){ return 0; }
|
||
|
|
d47e: 687b ldr r3, [r7, #4]
|
||
|
|
d480: 2b00 cmp r3, #0
|
||
|
|
d482: d101 bne.n d488 <art_svl_ringbuf_read+0x14>
|
||
|
|
d484: 2300 movs r3, #0
|
||
|
|
d486: e020 b.n d4ca <art_svl_ringbuf_read+0x56>
|
||
|
|
art_svl_ringbuf_t* rb = (art_svl_ringbuf_t*)vrb;
|
||
|
|
d488: 687b ldr r3, [r7, #4]
|
||
|
|
d48a: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if(art_svl_ringbuf_available(rb) > 0){
|
||
|
|
d48c: 68f8 ldr r0, [r7, #12]
|
||
|
|
d48e: f7ff ff6c bl d36a <art_svl_ringbuf_available>
|
||
|
|
d492: 4603 mov r3, r0
|
||
|
|
d494: 2b00 cmp r3, #0
|
||
|
|
d496: d017 beq.n d4c8 <art_svl_ringbuf_read+0x54>
|
||
|
|
*c = *(rb->buf + rb->r_offset);
|
||
|
|
d498: 68fb ldr r3, [r7, #12]
|
||
|
|
d49a: 681a ldr r2, [r3, #0]
|
||
|
|
d49c: 68fb ldr r3, [r7, #12]
|
||
|
|
d49e: 689b ldr r3, [r3, #8]
|
||
|
|
d4a0: 4413 add r3, r2
|
||
|
|
d4a2: 781a ldrb r2, [r3, #0]
|
||
|
|
d4a4: 683b ldr r3, [r7, #0]
|
||
|
|
d4a6: 701a strb r2, [r3, #0]
|
||
|
|
rb->r_offset++;
|
||
|
|
d4a8: 68fb ldr r3, [r7, #12]
|
||
|
|
d4aa: 689b ldr r3, [r3, #8]
|
||
|
|
d4ac: 1c5a adds r2, r3, #1
|
||
|
|
d4ae: 68fb ldr r3, [r7, #12]
|
||
|
|
d4b0: 609a str r2, [r3, #8]
|
||
|
|
if(rb->r_offset >= rb->len){
|
||
|
|
d4b2: 68fb ldr r3, [r7, #12]
|
||
|
|
d4b4: 689a ldr r2, [r3, #8]
|
||
|
|
d4b6: 68fb ldr r3, [r7, #12]
|
||
|
|
d4b8: 685b ldr r3, [r3, #4]
|
||
|
|
d4ba: 429a cmp r2, r3
|
||
|
|
d4bc: d302 bcc.n d4c4 <art_svl_ringbuf_read+0x50>
|
||
|
|
rb->r_offset = 0;
|
||
|
|
d4be: 68fb ldr r3, [r7, #12]
|
||
|
|
d4c0: 2200 movs r2, #0
|
||
|
|
d4c2: 609a str r2, [r3, #8]
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
d4c4: 2301 movs r3, #1
|
||
|
|
d4c6: e000 b.n d4ca <art_svl_ringbuf_read+0x56>
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
d4c8: 2300 movs r3, #0
|
||
|
|
d4ca: 4618 mov r0, r3
|
||
|
|
d4cc: 3710 adds r7, #16
|
||
|
|
d4ce: 46bd mov sp, r7
|
||
|
|
d4d0: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0000d4d2 <svl_uart_read>:
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// UART read buffer
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
size_t svl_uart_read(void *pHandle, char* buf, size_t len){
|
||
|
|
d4d2: b580 push {r7, lr}
|
||
|
|
d4d4: b08a sub sp, #40 ; 0x28
|
||
|
|
d4d6: af00 add r7, sp, #0
|
||
|
|
d4d8: 60f8 str r0, [r7, #12]
|
||
|
|
d4da: 60b9 str r1, [r7, #8]
|
||
|
|
d4dc: 607a str r2, [r7, #4]
|
||
|
|
uint32_t ui32BytesRead = 0x00;
|
||
|
|
d4de: 2300 movs r3, #0
|
||
|
|
d4e0: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
am_hal_uart_transfer_t sRead = {
|
||
|
|
d4e2: 2301 movs r3, #1
|
||
|
|
d4e4: 613b str r3, [r7, #16]
|
||
|
|
d4e6: 68bb ldr r3, [r7, #8]
|
||
|
|
d4e8: 617b str r3, [r7, #20]
|
||
|
|
d4ea: 687b ldr r3, [r7, #4]
|
||
|
|
d4ec: 61bb str r3, [r7, #24]
|
||
|
|
d4ee: 2300 movs r3, #0
|
||
|
|
d4f0: 61fb str r3, [r7, #28]
|
||
|
|
d4f2: f107 0324 add.w r3, r7, #36 ; 0x24
|
||
|
|
d4f6: 623b str r3, [r7, #32]
|
||
|
|
.pui8Data = (uint8_t*)buf,
|
||
|
|
.ui32NumBytes = len,
|
||
|
|
.ui32TimeoutMs = 0,
|
||
|
|
.pui32BytesTransferred = &ui32BytesRead,
|
||
|
|
};
|
||
|
|
am_hal_uart_transfer(pHandle, &sRead);
|
||
|
|
d4f8: f107 0310 add.w r3, r7, #16
|
||
|
|
d4fc: 4619 mov r1, r3
|
||
|
|
d4fe: 68f8 ldr r0, [r7, #12]
|
||
|
|
d500: f000 ffb4 bl e46c <am_hal_uart_transfer>
|
||
|
|
return ui32BytesRead;
|
||
|
|
d504: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
d506: 4618 mov r0, r3
|
||
|
|
d508: 3728 adds r7, #40 ; 0x28
|
||
|
|
d50a: 46bd mov sp, r7
|
||
|
|
d50c: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0000d50e <svl_uart_write>:
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// UART write buffer
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
size_t svl_uart_write(void *pHandle, char* buf, size_t len){
|
||
|
|
d50e: b580 push {r7, lr}
|
||
|
|
d510: b08a sub sp, #40 ; 0x28
|
||
|
|
d512: af00 add r7, sp, #0
|
||
|
|
d514: 60f8 str r0, [r7, #12]
|
||
|
|
d516: 60b9 str r1, [r7, #8]
|
||
|
|
d518: 607a str r2, [r7, #4]
|
||
|
|
uint32_t ui32BytesWritten = 0;
|
||
|
|
d51a: 2300 movs r3, #0
|
||
|
|
d51c: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
const am_hal_uart_transfer_t sUartWrite =
|
||
|
|
d51e: 2300 movs r3, #0
|
||
|
|
d520: 613b str r3, [r7, #16]
|
||
|
|
d522: 68bb ldr r3, [r7, #8]
|
||
|
|
d524: 617b str r3, [r7, #20]
|
||
|
|
d526: 687b ldr r3, [r7, #4]
|
||
|
|
d528: 61bb str r3, [r7, #24]
|
||
|
|
d52a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
|
||
|
|
d52e: 61fb str r3, [r7, #28]
|
||
|
|
d530: f107 0324 add.w r3, r7, #36 ; 0x24
|
||
|
|
d534: 623b str r3, [r7, #32]
|
||
|
|
.ui32NumBytes = len,
|
||
|
|
.ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER,
|
||
|
|
.pui32BytesTransferred = &ui32BytesWritten,
|
||
|
|
};
|
||
|
|
|
||
|
|
am_hal_uart_transfer(pHandle, &sUartWrite);
|
||
|
|
d536: f107 0310 add.w r3, r7, #16
|
||
|
|
d53a: 4619 mov r1, r3
|
||
|
|
d53c: 68f8 ldr r0, [r7, #12]
|
||
|
|
d53e: f000 ff95 bl e46c <am_hal_uart_transfer>
|
||
|
|
|
||
|
|
return ui32BytesWritten;
|
||
|
|
d542: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
d544: 4618 mov r0, r3
|
||
|
|
d546: 3728 adds r7, #40 ; 0x28
|
||
|
|
d548: 46bd mov sp, r7
|
||
|
|
d54a: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0000d54c <svl_uart_write_byte>:
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// UART write byte
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
size_t svl_uart_write_byte(void *pHandle, uint8_t c){
|
||
|
|
d54c: b580 push {r7, lr}
|
||
|
|
d54e: b082 sub sp, #8
|
||
|
|
d550: af00 add r7, sp, #0
|
||
|
|
d552: 6078 str r0, [r7, #4]
|
||
|
|
d554: 460b mov r3, r1
|
||
|
|
d556: 70fb strb r3, [r7, #3]
|
||
|
|
return svl_uart_write(pHandle, (char*)&c, 1);
|
||
|
|
d558: 1cfb adds r3, r7, #3
|
||
|
|
d55a: 2201 movs r2, #1
|
||
|
|
d55c: 4619 mov r1, r3
|
||
|
|
d55e: 6878 ldr r0, [r7, #4]
|
||
|
|
d560: f7ff ffd5 bl d50e <svl_uart_write>
|
||
|
|
d564: 4603 mov r3, r0
|
||
|
|
}
|
||
|
|
d566: 4618 mov r0, r3
|
||
|
|
d568: 3708 adds r7, #8
|
||
|
|
d56a: 46bd mov sp, r7
|
||
|
|
d56c: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
0000d570 <_fill_ticks>:
|
||
|
|
|
||
|
|
volatile uint32_t ap3_stimer_overflows = 0x00;
|
||
|
|
uint64_t ticks = 0;
|
||
|
|
|
||
|
|
void _fill_ticks(void)
|
||
|
|
{
|
||
|
|
d570: b5b0 push {r4, r5, r7, lr}
|
||
|
|
d572: af00 add r7, sp, #0
|
||
|
|
ticks = ap3_stimer_overflows;
|
||
|
|
d574: 4b12 ldr r3, [pc, #72] ; (d5c0 <_fill_ticks+0x50>)
|
||
|
|
d576: 681b ldr r3, [r3, #0]
|
||
|
|
d578: 461a mov r2, r3
|
||
|
|
d57a: f04f 0300 mov.w r3, #0
|
||
|
|
d57e: 4911 ldr r1, [pc, #68] ; (d5c4 <_fill_ticks+0x54>)
|
||
|
|
d580: e9c1 2300 strd r2, r3, [r1]
|
||
|
|
ticks <<= 32;
|
||
|
|
d584: 4b0f ldr r3, [pc, #60] ; (d5c4 <_fill_ticks+0x54>)
|
||
|
|
d586: e9d3 0100 ldrd r0, r1, [r3]
|
||
|
|
d58a: f04f 0200 mov.w r2, #0
|
||
|
|
d58e: f04f 0300 mov.w r3, #0
|
||
|
|
d592: 0003 movs r3, r0
|
||
|
|
d594: 2200 movs r2, #0
|
||
|
|
d596: 490b ldr r1, [pc, #44] ; (d5c4 <_fill_ticks+0x54>)
|
||
|
|
d598: e9c1 2300 strd r2, r3, [r1]
|
||
|
|
ticks |= (am_hal_stimer_counter_get() & 0xFFFFFFFF);
|
||
|
|
d59c: f000 fd70 bl e080 <am_hal_stimer_counter_get>
|
||
|
|
d5a0: 4603 mov r3, r0
|
||
|
|
d5a2: 4618 mov r0, r3
|
||
|
|
d5a4: f04f 0100 mov.w r1, #0
|
||
|
|
d5a8: 4b06 ldr r3, [pc, #24] ; (d5c4 <_fill_ticks+0x54>)
|
||
|
|
d5aa: e9d3 2300 ldrd r2, r3, [r3]
|
||
|
|
d5ae: ea40 0402 orr.w r4, r0, r2
|
||
|
|
d5b2: ea41 0503 orr.w r5, r1, r3
|
||
|
|
d5b6: 4b03 ldr r3, [pc, #12] ; (d5c4 <_fill_ticks+0x54>)
|
||
|
|
d5b8: e9c3 4500 strd r4, r5, [r3]
|
||
|
|
}
|
||
|
|
d5bc: bf00 nop
|
||
|
|
d5be: bdb0 pop {r4, r5, r7, pc}
|
||
|
|
d5c0: 10000a58 .word 0x10000a58
|
||
|
|
d5c4: 10000a60 .word 0x10000a60
|
||
|
|
|
||
|
|
0000d5c8 <millis>:
|
||
|
|
|
||
|
|
size_t millis(void){
|
||
|
|
d5c8: b580 push {r7, lr}
|
||
|
|
d5ca: af00 add r7, sp, #0
|
||
|
|
_fill_ticks();
|
||
|
|
d5cc: f7ff ffd0 bl d570 <_fill_ticks>
|
||
|
|
return (uint32_t)(ticks / AP3_STIMER_FREQ_KHZ);
|
||
|
|
d5d0: 4b06 ldr r3, [pc, #24] ; (d5ec <millis+0x24>)
|
||
|
|
d5d2: e9d3 0100 ldrd r0, r1, [r3]
|
||
|
|
d5d6: f640 32b8 movw r2, #3000 ; 0xbb8
|
||
|
|
d5da: f04f 0300 mov.w r3, #0
|
||
|
|
d5de: f7fe fd8f bl c100 <__aeabi_uldivmod>
|
||
|
|
d5e2: 4602 mov r2, r0
|
||
|
|
d5e4: 460b mov r3, r1
|
||
|
|
d5e6: 4613 mov r3, r2
|
||
|
|
}
|
||
|
|
d5e8: 4618 mov r0, r3
|
||
|
|
d5ea: bd80 pop {r7, pc}
|
||
|
|
d5ec: 10000a60 .word 0x10000a60
|
||
|
|
|
||
|
|
0000d5f0 <enable_burst_mode>:
|
||
|
|
//
|
||
|
|
// Burst mode
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
bool enable_burst_mode(void)
|
||
|
|
{
|
||
|
|
d5f0: b580 push {r7, lr}
|
||
|
|
d5f2: b082 sub sp, #8
|
||
|
|
d5f4: af00 add r7, sp, #0
|
||
|
|
// Check that the Burst Feature is available.
|
||
|
|
am_hal_burst_avail_e eBurstModeAvailable;
|
||
|
|
if (AM_HAL_STATUS_SUCCESS != am_hal_burst_mode_initialize(&eBurstModeAvailable))
|
||
|
|
d5f6: 1dfb adds r3, r7, #7
|
||
|
|
d5f8: 4618 mov r0, r3
|
||
|
|
d5fa: f000 f8dd bl d7b8 <am_hal_burst_mode_initialize>
|
||
|
|
d5fe: 4603 mov r3, r0
|
||
|
|
d600: 2b00 cmp r3, #0
|
||
|
|
d602: d001 beq.n d608 <enable_burst_mode+0x18>
|
||
|
|
{
|
||
|
|
return (false);
|
||
|
|
d604: 2300 movs r3, #0
|
||
|
|
d606: e009 b.n d61c <enable_burst_mode+0x2c>
|
||
|
|
}
|
||
|
|
|
||
|
|
// Put the MCU into "Burst" mode.
|
||
|
|
am_hal_burst_mode_e eBurstMode;
|
||
|
|
if (AM_HAL_STATUS_SUCCESS != am_hal_burst_mode_enable(&eBurstMode))
|
||
|
|
d608: 1dbb adds r3, r7, #6
|
||
|
|
d60a: 4618 mov r0, r3
|
||
|
|
d60c: f000 f916 bl d83c <am_hal_burst_mode_enable>
|
||
|
|
d610: 4603 mov r3, r0
|
||
|
|
d612: 2b00 cmp r3, #0
|
||
|
|
d614: d001 beq.n d61a <enable_burst_mode+0x2a>
|
||
|
|
{
|
||
|
|
return (false);
|
||
|
|
d616: 2300 movs r3, #0
|
||
|
|
d618: e000 b.n d61c <enable_burst_mode+0x2c>
|
||
|
|
}
|
||
|
|
return (true);
|
||
|
|
d61a: 2301 movs r3, #1
|
||
|
|
}
|
||
|
|
d61c: 4618 mov r0, r3
|
||
|
|
d61e: 3708 adds r7, #8
|
||
|
|
d620: 46bd mov sp, r7
|
||
|
|
d622: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0000d624 <disable_burst_mode>:
|
||
|
|
|
||
|
|
//Turns main processor from 96MHz to 48MHz
|
||
|
|
//Returns false if disable fails
|
||
|
|
bool disable_burst_mode(void)
|
||
|
|
{
|
||
|
|
d624: b580 push {r7, lr}
|
||
|
|
d626: b082 sub sp, #8
|
||
|
|
d628: af00 add r7, sp, #0
|
||
|
|
am_hal_burst_mode_e eBurstMode;
|
||
|
|
if (AM_HAL_STATUS_SUCCESS == am_hal_burst_mode_disable(&eBurstMode))
|
||
|
|
d62a: 1dfb adds r3, r7, #7
|
||
|
|
d62c: 4618 mov r0, r3
|
||
|
|
d62e: f000 f935 bl d89c <am_hal_burst_mode_disable>
|
||
|
|
d632: 4603 mov r3, r0
|
||
|
|
d634: 2b00 cmp r3, #0
|
||
|
|
d636: d104 bne.n d642 <disable_burst_mode+0x1e>
|
||
|
|
{
|
||
|
|
if (AM_HAL_NORMAL_MODE != eBurstMode)
|
||
|
|
d638: 79fb ldrb r3, [r7, #7]
|
||
|
|
d63a: 2b01 cmp r3, #1
|
||
|
|
d63c: d003 beq.n d646 <disable_burst_mode+0x22>
|
||
|
|
{
|
||
|
|
return (false);
|
||
|
|
d63e: 2300 movs r3, #0
|
||
|
|
d640: e002 b.n d648 <disable_burst_mode+0x24>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return (false);
|
||
|
|
d642: 2300 movs r3, #0
|
||
|
|
d644: e000 b.n d648 <disable_burst_mode+0x24>
|
||
|
|
}
|
||
|
|
return (true);
|
||
|
|
d646: 2301 movs r3, #1
|
||
|
|
}
|
||
|
|
d648: 4618 mov r0, r3
|
||
|
|
d64a: 3708 adds r7, #8
|
||
|
|
d64c: 46bd mov sp, r7
|
||
|
|
d64e: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0000d650 <ap3_gpio_enable_interrupts>:
|
||
|
|
|
||
|
|
#define GPIOCFG_FLD_INTD_S 3
|
||
|
|
#define GPIOCFG_FLD_OUTCFG_S 1
|
||
|
|
#define GPIOCFG_FLD_INCFG_S 0
|
||
|
|
|
||
|
|
uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, uint32_t eIntDir){
|
||
|
|
d650: b580 push {r7, lr}
|
||
|
|
d652: b08a sub sp, #40 ; 0x28
|
||
|
|
d654: af00 add r7, sp, #0
|
||
|
|
d656: 6078 str r0, [r7, #4]
|
||
|
|
d658: 6039 str r1, [r7, #0]
|
||
|
|
uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg;
|
||
|
|
bool bClearEnable = false;
|
||
|
|
d65a: 2300 movs r3, #0
|
||
|
|
d65c: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
||
|
|
|
||
|
|
|
||
|
|
ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0;
|
||
|
|
d660: 2300 movs r3, #0
|
||
|
|
d662: 623b str r3, [r7, #32]
|
||
|
|
d664: 6a3b ldr r3, [r7, #32]
|
||
|
|
d666: 61fb str r3, [r7, #28]
|
||
|
|
d668: 69fb ldr r3, [r7, #28]
|
||
|
|
d66a: 61bb str r3, [r7, #24]
|
||
|
|
ui32GPCfg |= (((eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | (((eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S);
|
||
|
|
d66c: 683b ldr r3, [r7, #0]
|
||
|
|
d66e: 00db lsls r3, r3, #3
|
||
|
|
d670: f003 0208 and.w r2, r3, #8
|
||
|
|
d674: 683b ldr r3, [r7, #0]
|
||
|
|
d676: 085b lsrs r3, r3, #1
|
||
|
|
d678: f003 0301 and.w r3, r3, #1
|
||
|
|
d67c: 4313 orrs r3, r2
|
||
|
|
d67e: 69ba ldr r2, [r7, #24]
|
||
|
|
d680: 4313 orrs r3, r2
|
||
|
|
d682: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
uint32_t ui32GPCfgAddr;
|
||
|
|
uint32_t ui32GPCfgClearMask;
|
||
|
|
uint32_t ui32GPCfgShft;
|
||
|
|
|
||
|
|
ui32GPCfgShft = ((ui32Pin & 0x7) << 2);
|
||
|
|
d684: 687b ldr r3, [r7, #4]
|
||
|
|
d686: 009b lsls r3, r3, #2
|
||
|
|
d688: f003 031c and.w r3, r3, #28
|
||
|
|
d68c: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3);
|
||
|
|
d68e: 687b ldr r3, [r7, #4]
|
||
|
|
d690: 085b lsrs r3, r3, #1
|
||
|
|
d692: f023 0203 bic.w r2, r3, #3
|
||
|
|
d696: 4b1d ldr r3, [pc, #116] ; (d70c <ap3_gpio_enable_interrupts+0xbc>)
|
||
|
|
d698: 4413 add r3, r2
|
||
|
|
d69a: 613b str r3, [r7, #16]
|
||
|
|
ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft);
|
||
|
|
d69c: 220f movs r2, #15
|
||
|
|
d69e: 697b ldr r3, [r7, #20]
|
||
|
|
d6a0: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
d6a4: 43db mvns r3, r3
|
||
|
|
d6a6: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
ui32GPCfg <<= ui32GPCfgShft;
|
||
|
|
d6a8: 69ba ldr r2, [r7, #24]
|
||
|
|
d6aa: 697b ldr r3, [r7, #20]
|
||
|
|
d6ac: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
d6b0: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
AM_CRITICAL_BEGIN
|
||
|
|
d6b2: f000 fc35 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
d6b6: 4603 mov r3, r0
|
||
|
|
d6b8: 60bb str r3, [r7, #8]
|
||
|
|
|
||
|
|
if (bClearEnable)
|
||
|
|
d6ba: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
||
|
|
d6be: 2b00 cmp r3, #0
|
||
|
|
d6c0: d00c beq.n d6dc <ap3_gpio_enable_interrupts+0x8c>
|
||
|
|
{
|
||
|
|
am_hal_gpio_output_tristate_disable(ui32Pin);
|
||
|
|
d6c2: 687b ldr r3, [r7, #4]
|
||
|
|
d6c4: f003 021f and.w r2, r3, #31
|
||
|
|
d6c8: 687b ldr r3, [r7, #4]
|
||
|
|
d6ca: 08db lsrs r3, r3, #3
|
||
|
|
d6cc: f003 0104 and.w r1, r3, #4
|
||
|
|
d6d0: 4b0f ldr r3, [pc, #60] ; (d710 <ap3_gpio_enable_interrupts+0xc0>)
|
||
|
|
d6d2: 440b add r3, r1
|
||
|
|
d6d4: 4619 mov r1, r3
|
||
|
|
d6d6: 2301 movs r3, #1
|
||
|
|
d6d8: 4093 lsls r3, r2
|
||
|
|
d6da: 600b str r3, [r1, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key;
|
||
|
|
d6dc: 4b0d ldr r3, [pc, #52] ; (d714 <ap3_gpio_enable_interrupts+0xc4>)
|
||
|
|
d6de: 2273 movs r2, #115 ; 0x73
|
||
|
|
d6e0: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
|
||
|
|
// Here's where the magic happens
|
||
|
|
AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg;
|
||
|
|
d6e2: 693b ldr r3, [r7, #16]
|
||
|
|
d6e4: 681a ldr r2, [r3, #0]
|
||
|
|
d6e6: 68fb ldr r3, [r7, #12]
|
||
|
|
d6e8: ea02 0103 and.w r1, r2, r3
|
||
|
|
d6ec: 693b ldr r3, [r7, #16]
|
||
|
|
d6ee: 69ba ldr r2, [r7, #24]
|
||
|
|
d6f0: 430a orrs r2, r1
|
||
|
|
d6f2: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
GPIO->PADKEY = 0;
|
||
|
|
d6f4: 4b07 ldr r3, [pc, #28] ; (d714 <ap3_gpio_enable_interrupts+0xc4>)
|
||
|
|
d6f6: 2200 movs r2, #0
|
||
|
|
d6f8: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
|
||
|
|
AM_CRITICAL_END
|
||
|
|
d6fa: 68bb ldr r3, [r7, #8]
|
||
|
|
d6fc: 4618 mov r0, r3
|
||
|
|
d6fe: f000 fc13 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
|
||
|
|
return AM_HAL_STATUS_SUCCESS;
|
||
|
|
d702: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
d704: 4618 mov r0, r3
|
||
|
|
d706: 3728 adds r7, #40 ; 0x28
|
||
|
|
d708: 46bd mov sp, r7
|
||
|
|
d70a: bd80 pop {r7, pc}
|
||
|
|
d70c: 40010040 .word 0x40010040
|
||
|
|
d710: 400100b4 .word 0x400100b4
|
||
|
|
d714: 40010000 .word 0x40010000
|
||
|
|
|
||
|
|
0000d718 <memset>:
|
||
|
|
d718: b4f0 push {r4, r5, r6, r7}
|
||
|
|
d71a: 0786 lsls r6, r0, #30
|
||
|
|
d71c: d046 beq.n d7ac <memset+0x94>
|
||
|
|
d71e: 1e54 subs r4, r2, #1
|
||
|
|
d720: 2a00 cmp r2, #0
|
||
|
|
d722: d03c beq.n d79e <memset+0x86>
|
||
|
|
d724: b2ca uxtb r2, r1
|
||
|
|
d726: 4603 mov r3, r0
|
||
|
|
d728: e001 b.n d72e <memset+0x16>
|
||
|
|
d72a: 3c01 subs r4, #1
|
||
|
|
d72c: d337 bcc.n d79e <memset+0x86>
|
||
|
|
d72e: f803 2b01 strb.w r2, [r3], #1
|
||
|
|
d732: 079d lsls r5, r3, #30
|
||
|
|
d734: d1f9 bne.n d72a <memset+0x12>
|
||
|
|
d736: 2c03 cmp r4, #3
|
||
|
|
d738: d92a bls.n d790 <memset+0x78>
|
||
|
|
d73a: b2cd uxtb r5, r1
|
||
|
|
d73c: ea45 2505 orr.w r5, r5, r5, lsl #8
|
||
|
|
d740: 2c0f cmp r4, #15
|
||
|
|
d742: ea45 4505 orr.w r5, r5, r5, lsl #16
|
||
|
|
d746: d934 bls.n d7b2 <memset+0x9a>
|
||
|
|
d748: f1a4 0210 sub.w r2, r4, #16
|
||
|
|
d74c: f022 0c0f bic.w ip, r2, #15
|
||
|
|
d750: f103 0720 add.w r7, r3, #32
|
||
|
|
d754: 0916 lsrs r6, r2, #4
|
||
|
|
d756: 4467 add r7, ip
|
||
|
|
d758: f103 0210 add.w r2, r3, #16
|
||
|
|
d75c: e942 5504 strd r5, r5, [r2, #-16]
|
||
|
|
d760: e942 5502 strd r5, r5, [r2, #-8]
|
||
|
|
d764: 3210 adds r2, #16
|
||
|
|
d766: 42ba cmp r2, r7
|
||
|
|
d768: d1f8 bne.n d75c <memset+0x44>
|
||
|
|
d76a: 1c72 adds r2, r6, #1
|
||
|
|
d76c: f014 0f0c tst.w r4, #12
|
||
|
|
d770: eb03 1202 add.w r2, r3, r2, lsl #4
|
||
|
|
d774: f004 060f and.w r6, r4, #15
|
||
|
|
d778: d013 beq.n d7a2 <memset+0x8a>
|
||
|
|
d77a: 1f33 subs r3, r6, #4
|
||
|
|
d77c: f023 0303 bic.w r3, r3, #3
|
||
|
|
d780: 3304 adds r3, #4
|
||
|
|
d782: 4413 add r3, r2
|
||
|
|
d784: f842 5b04 str.w r5, [r2], #4
|
||
|
|
d788: 4293 cmp r3, r2
|
||
|
|
d78a: d1fb bne.n d784 <memset+0x6c>
|
||
|
|
d78c: f006 0403 and.w r4, r6, #3
|
||
|
|
d790: b12c cbz r4, d79e <memset+0x86>
|
||
|
|
d792: b2ca uxtb r2, r1
|
||
|
|
d794: 441c add r4, r3
|
||
|
|
d796: f803 2b01 strb.w r2, [r3], #1
|
||
|
|
d79a: 429c cmp r4, r3
|
||
|
|
d79c: d1fb bne.n d796 <memset+0x7e>
|
||
|
|
d79e: bcf0 pop {r4, r5, r6, r7}
|
||
|
|
d7a0: 4770 bx lr
|
||
|
|
d7a2: 4634 mov r4, r6
|
||
|
|
d7a4: 4613 mov r3, r2
|
||
|
|
d7a6: 2c00 cmp r4, #0
|
||
|
|
d7a8: d1f3 bne.n d792 <memset+0x7a>
|
||
|
|
d7aa: e7f8 b.n d79e <memset+0x86>
|
||
|
|
d7ac: 4614 mov r4, r2
|
||
|
|
d7ae: 4603 mov r3, r0
|
||
|
|
d7b0: e7c1 b.n d736 <memset+0x1e>
|
||
|
|
d7b2: 461a mov r2, r3
|
||
|
|
d7b4: 4626 mov r6, r4
|
||
|
|
d7b6: e7e0 b.n d77a <memset+0x62>
|
||
|
|
|
||
|
|
0000d7b8 <am_hal_burst_mode_initialize>:
|
||
|
|
d7b8: b570 push {r4, r5, r6, lr}
|
||
|
|
d7ba: 4b1c ldr r3, [pc, #112] ; (d82c <am_hal_burst_mode_initialize+0x74>)
|
||
|
|
d7bc: 695b ldr r3, [r3, #20]
|
||
|
|
d7be: 4604 mov r4, r0
|
||
|
|
d7c0: 07d8 lsls r0, r3, #31
|
||
|
|
d7c2: b082 sub sp, #8
|
||
|
|
d7c4: d521 bpl.n d80a <am_hal_burst_mode_initialize+0x52>
|
||
|
|
d7c6: 4b1a ldr r3, [pc, #104] ; (d830 <am_hal_burst_mode_initialize+0x78>)
|
||
|
|
d7c8: 6a9a ldr r2, [r3, #40] ; 0x28
|
||
|
|
d7ca: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
|
||
|
|
d7ce: 629a str r2, [r3, #40] ; 0x28
|
||
|
|
d7d0: 681b ldr r3, [r3, #0]
|
||
|
|
d7d2: 07d9 lsls r1, r3, #31
|
||
|
|
d7d4: d427 bmi.n d826 <am_hal_burst_mode_initialize+0x6e>
|
||
|
|
d7d6: 4d15 ldr r5, [pc, #84] ; (d82c <am_hal_burst_mode_initialize+0x74>)
|
||
|
|
d7d8: 4916 ldr r1, [pc, #88] ; (d834 <am_hal_burst_mode_initialize+0x7c>)
|
||
|
|
d7da: 7e2a ldrb r2, [r5, #24]
|
||
|
|
d7dc: 2601 movs r6, #1
|
||
|
|
d7de: f042 0210 orr.w r2, r2, #16
|
||
|
|
d7e2: 2320 movs r3, #32
|
||
|
|
d7e4: 762a strb r2, [r5, #24]
|
||
|
|
d7e6: f242 7010 movw r0, #10000 ; 0x2710
|
||
|
|
d7ea: 461a mov r2, r3
|
||
|
|
d7ec: 9600 str r6, [sp, #0]
|
||
|
|
d7ee: f000 f9ab bl db48 <am_hal_flash_delay_status_check>
|
||
|
|
d7f2: b990 cbnz r0, d81a <am_hal_burst_mode_initialize+0x62>
|
||
|
|
d7f4: 69ab ldr r3, [r5, #24]
|
||
|
|
d7f6: 065a lsls r2, r3, #25
|
||
|
|
d7f8: d507 bpl.n d80a <am_hal_burst_mode_initialize+0x52>
|
||
|
|
d7fa: 69ab ldr r3, [r5, #24]
|
||
|
|
d7fc: 069b lsls r3, r3, #26
|
||
|
|
d7fe: d504 bpl.n d80a <am_hal_burst_mode_initialize+0x52>
|
||
|
|
d800: 4b0d ldr r3, [pc, #52] ; (d838 <am_hal_burst_mode_initialize+0x80>)
|
||
|
|
d802: 701e strb r6, [r3, #0]
|
||
|
|
d804: 7020 strb r0, [r4, #0]
|
||
|
|
d806: b002 add sp, #8
|
||
|
|
d808: bd70 pop {r4, r5, r6, pc}
|
||
|
|
d80a: 4a0b ldr r2, [pc, #44] ; (d838 <am_hal_burst_mode_initialize+0x80>)
|
||
|
|
d80c: 2100 movs r1, #0
|
||
|
|
d80e: 2301 movs r3, #1
|
||
|
|
d810: 2007 movs r0, #7
|
||
|
|
d812: 7011 strb r1, [r2, #0]
|
||
|
|
d814: 7023 strb r3, [r4, #0]
|
||
|
|
d816: b002 add sp, #8
|
||
|
|
d818: bd70 pop {r4, r5, r6, pc}
|
||
|
|
d81a: 4b07 ldr r3, [pc, #28] ; (d838 <am_hal_burst_mode_initialize+0x80>)
|
||
|
|
d81c: 2200 movs r2, #0
|
||
|
|
d81e: 701a strb r2, [r3, #0]
|
||
|
|
d820: 7026 strb r6, [r4, #0]
|
||
|
|
d822: b002 add sp, #8
|
||
|
|
d824: bd70 pop {r4, r5, r6, pc}
|
||
|
|
d826: f000 fbd9 bl dfdc <am_hal_pwrctrl_blebuck_trim>
|
||
|
|
d82a: e7d4 b.n d7d6 <am_hal_burst_mode_initialize+0x1e>
|
||
|
|
d82c: 40020000 .word 0x40020000
|
||
|
|
d830: 40021000 .word 0x40021000
|
||
|
|
d834: 40020018 .word 0x40020018
|
||
|
|
d838: 10000a68 .word 0x10000a68
|
||
|
|
|
||
|
|
0000d83c <am_hal_burst_mode_enable>:
|
||
|
|
d83c: b570 push {r4, r5, r6, lr}
|
||
|
|
d83e: 4b15 ldr r3, [pc, #84] ; (d894 <am_hal_burst_mode_enable+0x58>)
|
||
|
|
d840: 781b ldrb r3, [r3, #0]
|
||
|
|
d842: b082 sub sp, #8
|
||
|
|
d844: 4604 mov r4, r0
|
||
|
|
d846: b1db cbz r3, d880 <am_hal_burst_mode_enable+0x44>
|
||
|
|
d848: f04f 2540 mov.w r5, #1073758208 ; 0x40004000
|
||
|
|
d84c: 2601 movs r6, #1
|
||
|
|
d84e: f895 2034 ldrb.w r2, [r5, #52] ; 0x34
|
||
|
|
d852: 4911 ldr r1, [pc, #68] ; (d898 <am_hal_burst_mode_enable+0x5c>)
|
||
|
|
d854: 4332 orrs r2, r6
|
||
|
|
d856: 2304 movs r3, #4
|
||
|
|
d858: f885 2034 strb.w r2, [r5, #52] ; 0x34
|
||
|
|
d85c: f242 7010 movw r0, #10000 ; 0x2710
|
||
|
|
d860: 461a mov r2, r3
|
||
|
|
d862: 9600 str r6, [sp, #0]
|
||
|
|
d864: f000 f970 bl db48 <am_hal_flash_delay_status_check>
|
||
|
|
d868: b938 cbnz r0, d87a <am_hal_burst_mode_enable+0x3e>
|
||
|
|
d86a: 6b6b ldr r3, [r5, #52] ; 0x34
|
||
|
|
d86c: 079b lsls r3, r3, #30
|
||
|
|
d86e: d50c bpl.n d88a <am_hal_burst_mode_enable+0x4e>
|
||
|
|
d870: 6b6b ldr r3, [r5, #52] ; 0x34
|
||
|
|
d872: f013 0f04 tst.w r3, #4
|
||
|
|
d876: bf18 it ne
|
||
|
|
d878: 4606 movne r6, r0
|
||
|
|
d87a: 7026 strb r6, [r4, #0]
|
||
|
|
d87c: b002 add sp, #8
|
||
|
|
d87e: bd70 pop {r4, r5, r6, pc}
|
||
|
|
d880: 2301 movs r3, #1
|
||
|
|
d882: 7003 strb r3, [r0, #0]
|
||
|
|
d884: 2007 movs r0, #7
|
||
|
|
d886: b002 add sp, #8
|
||
|
|
d888: bd70 pop {r4, r5, r6, pc}
|
||
|
|
d88a: 4630 mov r0, r6
|
||
|
|
d88c: 7026 strb r6, [r4, #0]
|
||
|
|
d88e: b002 add sp, #8
|
||
|
|
d890: bd70 pop {r4, r5, r6, pc}
|
||
|
|
d892: bf00 nop
|
||
|
|
d894: 10000a68 .word 0x10000a68
|
||
|
|
d898: 40004034 .word 0x40004034
|
||
|
|
|
||
|
|
0000d89c <am_hal_burst_mode_disable>:
|
||
|
|
d89c: b530 push {r4, r5, lr}
|
||
|
|
d89e: b085 sub sp, #20
|
||
|
|
d8a0: 4605 mov r5, r0
|
||
|
|
d8a2: f000 fb3d bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
d8a6: 2100 movs r1, #0
|
||
|
|
d8a8: 4603 mov r3, r0
|
||
|
|
d8aa: 4810 ldr r0, [pc, #64] ; (d8ec <am_hal_burst_mode_disable+0x50>)
|
||
|
|
d8ac: 9303 str r3, [sp, #12]
|
||
|
|
d8ae: f000 f985 bl dbbc <am_hal_flash_store_ui32>
|
||
|
|
d8b2: 9803 ldr r0, [sp, #12]
|
||
|
|
d8b4: f000 fb38 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
d8b8: 4b0d ldr r3, [pc, #52] ; (d8f0 <am_hal_burst_mode_disable+0x54>)
|
||
|
|
d8ba: 490c ldr r1, [pc, #48] ; (d8ec <am_hal_burst_mode_disable+0x50>)
|
||
|
|
d8bc: 6a9a ldr r2, [r3, #40] ; 0x28
|
||
|
|
d8be: 2401 movs r4, #1
|
||
|
|
d8c0: f36f 72df bfc r2, #31, #1
|
||
|
|
d8c4: 629a str r2, [r3, #40] ; 0x28
|
||
|
|
d8c6: f242 7010 movw r0, #10000 ; 0x2710
|
||
|
|
d8ca: 2300 movs r3, #0
|
||
|
|
d8cc: 9400 str r4, [sp, #0]
|
||
|
|
d8ce: 2204 movs r2, #4
|
||
|
|
d8d0: f000 f93a bl db48 <am_hal_flash_delay_status_check>
|
||
|
|
d8d4: b930 cbnz r0, d8e4 <am_hal_burst_mode_disable+0x48>
|
||
|
|
d8d6: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
d8da: 6b5b ldr r3, [r3, #52] ; 0x34
|
||
|
|
d8dc: f013 0f04 tst.w r3, #4
|
||
|
|
d8e0: bf18 it ne
|
||
|
|
d8e2: 4604 movne r4, r0
|
||
|
|
d8e4: 702c strb r4, [r5, #0]
|
||
|
|
d8e6: b005 add sp, #20
|
||
|
|
d8e8: bd30 pop {r4, r5, pc}
|
||
|
|
d8ea: bf00 nop
|
||
|
|
d8ec: 40004034 .word 0x40004034
|
||
|
|
d8f0: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
0000d8f4 <am_hal_cachectrl_config>:
|
||
|
|
d8f4: b530 push {r4, r5, lr}
|
||
|
|
d8f6: b083 sub sp, #12
|
||
|
|
d8f8: 4604 mov r4, r0
|
||
|
|
d8fa: f000 fb11 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
d8fe: 4d0e ldr r5, [pc, #56] ; (d938 <am_hal_cachectrl_config+0x44>)
|
||
|
|
d900: 9001 str r0, [sp, #4]
|
||
|
|
d902: 682b ldr r3, [r5, #0]
|
||
|
|
d904: f423 7340 bic.w r3, r3, #768 ; 0x300
|
||
|
|
d908: 602b str r3, [r5, #0]
|
||
|
|
d90a: 9801 ldr r0, [sp, #4]
|
||
|
|
d90c: f000 fb0c bl df28 <am_hal_interrupt_master_set>
|
||
|
|
d910: 7863 ldrb r3, [r4, #1]
|
||
|
|
d912: 7822 ldrb r2, [r4, #0]
|
||
|
|
d914: 78a1 ldrb r1, [r4, #2]
|
||
|
|
d916: 021b lsls r3, r3, #8
|
||
|
|
d918: f403 7340 and.w r3, r3, #768 ; 0x300
|
||
|
|
d91c: 0112 lsls r2, r2, #4
|
||
|
|
d91e: ea43 0341 orr.w r3, r3, r1, lsl #1
|
||
|
|
d922: b2d2 uxtb r2, r2
|
||
|
|
d924: 4313 orrs r3, r2
|
||
|
|
d926: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
||
|
|
d92a: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
||
|
|
d92e: 2000 movs r0, #0
|
||
|
|
d930: 602b str r3, [r5, #0]
|
||
|
|
d932: b003 add sp, #12
|
||
|
|
d934: bd30 pop {r4, r5, pc}
|
||
|
|
d936: bf00 nop
|
||
|
|
d938: 40018000 .word 0x40018000
|
||
|
|
|
||
|
|
0000d93c <am_hal_cachectrl_enable>:
|
||
|
|
d93c: 4a03 ldr r2, [pc, #12] ; (d94c <am_hal_cachectrl_enable+0x10>)
|
||
|
|
d93e: 6813 ldr r3, [r2, #0]
|
||
|
|
d940: f043 0301 orr.w r3, r3, #1
|
||
|
|
d944: 6013 str r3, [r2, #0]
|
||
|
|
d946: 2000 movs r0, #0
|
||
|
|
d948: 4770 bx lr
|
||
|
|
d94a: bf00 nop
|
||
|
|
d94c: 40018000 .word 0x40018000
|
||
|
|
|
||
|
|
0000d950 <am_hal_clkgen_control>:
|
||
|
|
d950: 4b49 ldr r3, [pc, #292] ; (da78 <am_hal_clkgen_control+0x128>)
|
||
|
|
d952: 681a ldr r2, [r3, #0]
|
||
|
|
d954: b912 cbnz r2, d95c <am_hal_clkgen_control+0xc>
|
||
|
|
d956: 4a49 ldr r2, [pc, #292] ; (da7c <am_hal_clkgen_control+0x12c>)
|
||
|
|
d958: 6812 ldr r2, [r2, #0]
|
||
|
|
d95a: 601a str r2, [r3, #0]
|
||
|
|
d95c: 2809 cmp r0, #9
|
||
|
|
d95e: f200 8089 bhi.w da74 <am_hal_clkgen_control+0x124>
|
||
|
|
d962: e8df f000 tbb [pc, r0]
|
||
|
|
d966: 160d .short 0x160d
|
||
|
|
d968: 423a261e .word 0x423a261e
|
||
|
|
d96c: 055c544c .word 0x055c544c
|
||
|
|
d970: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
d974: 2000 movs r0, #0
|
||
|
|
d976: 6a1a ldr r2, [r3, #32]
|
||
|
|
d978: f36f 0200 bfc r2, #0, #1
|
||
|
|
d97c: 621a str r2, [r3, #32]
|
||
|
|
d97e: 4770 bx lr
|
||
|
|
d980: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
d984: 2200 movs r2, #0
|
||
|
|
d986: 2147 movs r1, #71 ; 0x47
|
||
|
|
d988: 6159 str r1, [r3, #20]
|
||
|
|
d98a: 4610 mov r0, r2
|
||
|
|
d98c: 619a str r2, [r3, #24]
|
||
|
|
d98e: 615a str r2, [r3, #20]
|
||
|
|
d990: 4770 bx lr
|
||
|
|
d992: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
d996: 2000 movs r0, #0
|
||
|
|
d998: 899a ldrh r2, [r3, #12]
|
||
|
|
d99a: f36f 0200 bfc r2, #0, #1
|
||
|
|
d99e: 819a strh r2, [r3, #12]
|
||
|
|
d9a0: 4770 bx lr
|
||
|
|
d9a2: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
d9a6: 2000 movs r0, #0
|
||
|
|
d9a8: 899a ldrh r2, [r3, #12]
|
||
|
|
d9aa: f36f 0241 bfc r2, #1, #1
|
||
|
|
d9ae: 819a strh r2, [r3, #12]
|
||
|
|
d9b0: 4770 bx lr
|
||
|
|
d9b2: 4a33 ldr r2, [pc, #204] ; (da80 <am_hal_clkgen_control+0x130>)
|
||
|
|
d9b4: 68d3 ldr r3, [r2, #12]
|
||
|
|
d9b6: b2db uxtb r3, r3
|
||
|
|
d9b8: 2b21 cmp r3, #33 ; 0x21
|
||
|
|
d9ba: d106 bne.n d9ca <am_hal_clkgen_control+0x7a>
|
||
|
|
d9bc: f8b2 3120 ldrh.w r3, [r2, #288] ; 0x120
|
||
|
|
d9c0: 2101 movs r1, #1
|
||
|
|
d9c2: f361 2309 bfi r3, r1, #8, #2
|
||
|
|
d9c6: f8a2 3120 strh.w r3, [r2, #288] ; 0x120
|
||
|
|
d9ca: f04f 2240 mov.w r2, #1073758208 ; 0x40004000
|
||
|
|
d9ce: 2000 movs r0, #0
|
||
|
|
d9d0: 8993 ldrh r3, [r2, #12]
|
||
|
|
d9d2: f043 0301 orr.w r3, r3, #1
|
||
|
|
d9d6: 8193 strh r3, [r2, #12]
|
||
|
|
d9d8: 4770 bx lr
|
||
|
|
d9da: f04f 2240 mov.w r2, #1073758208 ; 0x40004000
|
||
|
|
d9de: 2000 movs r0, #0
|
||
|
|
d9e0: 8993 ldrh r3, [r2, #12]
|
||
|
|
d9e2: f043 0302 orr.w r3, r3, #2
|
||
|
|
d9e6: 8193 strh r3, [r2, #12]
|
||
|
|
d9e8: 4770 bx lr
|
||
|
|
d9ea: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
d9ee: 2200 movs r2, #0
|
||
|
|
d9f0: 2047 movs r0, #71 ; 0x47
|
||
|
|
d9f2: 2101 movs r1, #1
|
||
|
|
d9f4: 6158 str r0, [r3, #20]
|
||
|
|
d9f6: 6199 str r1, [r3, #24]
|
||
|
|
d9f8: 4610 mov r0, r2
|
||
|
|
d9fa: 615a str r2, [r3, #20]
|
||
|
|
d9fc: 4770 bx lr
|
||
|
|
d9fe: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
da02: 2000 movs r0, #0
|
||
|
|
da04: 899a ldrh r2, [r3, #12]
|
||
|
|
da06: f36f 12c7 bfc r2, #7, #1
|
||
|
|
da0a: 819a strh r2, [r3, #12]
|
||
|
|
da0c: 4770 bx lr
|
||
|
|
da0e: f04f 2240 mov.w r2, #1073758208 ; 0x40004000
|
||
|
|
da12: 2000 movs r0, #0
|
||
|
|
da14: 8993 ldrh r3, [r2, #12]
|
||
|
|
da16: f043 0380 orr.w r3, r3, #128 ; 0x80
|
||
|
|
da1a: 8193 strh r3, [r2, #12]
|
||
|
|
da1c: 4770 bx lr
|
||
|
|
da1e: 4a18 ldr r2, [pc, #96] ; (da80 <am_hal_clkgen_control+0x130>)
|
||
|
|
da20: 68d3 ldr r3, [r2, #12]
|
||
|
|
da22: b2db uxtb r3, r3
|
||
|
|
da24: 2b21 cmp r3, #33 ; 0x21
|
||
|
|
da26: d00a beq.n da3e <am_hal_clkgen_control+0xee>
|
||
|
|
da28: b139 cbz r1, da3a <am_hal_clkgen_control+0xea>
|
||
|
|
da2a: 680b ldr r3, [r1, #0]
|
||
|
|
da2c: f043 0301 orr.w r3, r3, #1
|
||
|
|
da30: f04f 2240 mov.w r2, #1073758208 ; 0x40004000
|
||
|
|
da34: 2000 movs r0, #0
|
||
|
|
da36: 6213 str r3, [r2, #32]
|
||
|
|
da38: 4770 bx lr
|
||
|
|
da3a: 4b12 ldr r3, [pc, #72] ; (da84 <am_hal_clkgen_control+0x134>)
|
||
|
|
da3c: e7f8 b.n da30 <am_hal_clkgen_control+0xe0>
|
||
|
|
da3e: b500 push {lr}
|
||
|
|
da40: b083 sub sp, #12
|
||
|
|
da42: f44f 507a mov.w r0, #16000 ; 0x3e80
|
||
|
|
da46: 9101 str r1, [sp, #4]
|
||
|
|
da48: f8b2 3120 ldrh.w r3, [r2, #288] ; 0x120
|
||
|
|
da4c: f443 7340 orr.w r3, r3, #768 ; 0x300
|
||
|
|
da50: f8a2 3120 strh.w r3, [r2, #288] ; 0x120
|
||
|
|
da54: f000 f868 bl db28 <am_hal_flash_delay>
|
||
|
|
da58: 9901 ldr r1, [sp, #4]
|
||
|
|
da5a: b149 cbz r1, da70 <am_hal_clkgen_control+0x120>
|
||
|
|
da5c: 680b ldr r3, [r1, #0]
|
||
|
|
da5e: f043 0301 orr.w r3, r3, #1
|
||
|
|
da62: f04f 2240 mov.w r2, #1073758208 ; 0x40004000
|
||
|
|
da66: 2000 movs r0, #0
|
||
|
|
da68: 6213 str r3, [r2, #32]
|
||
|
|
da6a: b003 add sp, #12
|
||
|
|
da6c: f85d fb04 ldr.w pc, [sp], #4
|
||
|
|
da70: 4b04 ldr r3, [pc, #16] ; (da84 <am_hal_clkgen_control+0x134>)
|
||
|
|
da72: e7f6 b.n da62 <am_hal_clkgen_control+0x112>
|
||
|
|
da74: 2006 movs r0, #6
|
||
|
|
da76: 4770 bx lr
|
||
|
|
da78: 10000a6c .word 0x10000a6c
|
||
|
|
da7c: 4ffff000 .word 0x4ffff000
|
||
|
|
da80: 40020000 .word 0x40020000
|
||
|
|
da84: 0025b801 .word 0x0025b801
|
||
|
|
|
||
|
|
0000da88 <am_hal_clkgen_status_get>:
|
||
|
|
da88: b1a8 cbz r0, dab6 <am_hal_clkgen_status_get+0x2e>
|
||
|
|
da8a: b410 push {r4}
|
||
|
|
da8c: f04f 2240 mov.w r2, #1073758208 ; 0x40004000
|
||
|
|
da90: 490a ldr r1, [pc, #40] ; (dabc <am_hal_clkgen_status_get+0x34>)
|
||
|
|
da92: 6994 ldr r4, [r2, #24]
|
||
|
|
da94: 4b0a ldr r3, [pc, #40] ; (dac0 <am_hal_clkgen_status_get+0x38>)
|
||
|
|
da96: f014 0f01 tst.w r4, #1
|
||
|
|
da9a: bf08 it eq
|
||
|
|
da9c: 460b moveq r3, r1
|
||
|
|
da9e: 6003 str r3, [r0, #0]
|
||
|
|
daa0: 69d3 ldr r3, [r2, #28]
|
||
|
|
daa2: f85d 4b04 ldr.w r4, [sp], #4
|
||
|
|
daa6: f003 0201 and.w r2, r3, #1
|
||
|
|
daaa: f3c3 0340 ubfx r3, r3, #1, #1
|
||
|
|
daae: 6042 str r2, [r0, #4]
|
||
|
|
dab0: 7203 strb r3, [r0, #8]
|
||
|
|
dab2: 2000 movs r0, #0
|
||
|
|
dab4: 4770 bx lr
|
||
|
|
dab6: 2006 movs r0, #6
|
||
|
|
dab8: 4770 bx lr
|
||
|
|
daba: bf00 nop
|
||
|
|
dabc: 02dc6c00 .word 0x02dc6c00
|
||
|
|
dac0: 016e3600 .word 0x016e3600
|
||
|
|
|
||
|
|
0000dac4 <am_hal_flash_page_erase>:
|
||
|
|
dac4: 4b00 ldr r3, [pc, #0] ; (dac8 <am_hal_flash_page_erase+0x4>)
|
||
|
|
dac6: 4718 bx r3
|
||
|
|
dac8: 08000051 .word 0x08000051
|
||
|
|
|
||
|
|
0000dacc <am_hal_flash_program_main>:
|
||
|
|
dacc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
||
|
|
dad0: 4e12 ldr r6, [pc, #72] ; (db1c <am_hal_flash_program_main+0x50>)
|
||
|
|
dad2: eb01 0583 add.w r5, r1, r3, lsl #2
|
||
|
|
dad6: 42b5 cmp r5, r6
|
||
|
|
dad8: b082 sub sp, #8
|
||
|
|
dada: d004 beq.n dae6 <am_hal_flash_program_main+0x1a>
|
||
|
|
dadc: 4c10 ldr r4, [pc, #64] ; (db20 <am_hal_flash_program_main+0x54>)
|
||
|
|
dade: 47a0 blx r4
|
||
|
|
dae0: b002 add sp, #8
|
||
|
|
dae2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
dae6: 2b01 cmp r3, #1
|
||
|
|
dae8: 461c mov r4, r3
|
||
|
|
daea: 4680 mov r8, r0
|
||
|
|
daec: 4617 mov r7, r2
|
||
|
|
daee: d904 bls.n dafa <am_hal_flash_program_main+0x2e>
|
||
|
|
daf0: 4d0b ldr r5, [pc, #44] ; (db20 <am_hal_flash_program_main+0x54>)
|
||
|
|
daf2: 3b01 subs r3, #1
|
||
|
|
daf4: 47a8 blx r5
|
||
|
|
daf6: 2800 cmp r0, #0
|
||
|
|
daf8: d1f2 bne.n dae0 <am_hal_flash_program_main+0x14>
|
||
|
|
dafa: 4b0a ldr r3, [pc, #40] ; (db24 <am_hal_flash_program_main+0x58>)
|
||
|
|
dafc: 4d08 ldr r5, [pc, #32] ; (db20 <am_hal_flash_program_main+0x54>)
|
||
|
|
dafe: 681b ldr r3, [r3, #0]
|
||
|
|
db00: 9301 str r3, [sp, #4]
|
||
|
|
db02: f104 4280 add.w r2, r4, #1073741824 ; 0x40000000
|
||
|
|
db06: 3a01 subs r2, #1
|
||
|
|
db08: eb07 0282 add.w r2, r7, r2, lsl #2
|
||
|
|
db0c: 4640 mov r0, r8
|
||
|
|
db0e: 2301 movs r3, #1
|
||
|
|
db10: a901 add r1, sp, #4
|
||
|
|
db12: 47a8 blx r5
|
||
|
|
db14: b002 add sp, #8
|
||
|
|
db16: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
db1a: bf00 nop
|
||
|
|
db1c: 10060000 .word 0x10060000
|
||
|
|
db20: 08000055 .word 0x08000055
|
||
|
|
db24: 1005fffc .word 0x1005fffc
|
||
|
|
|
||
|
|
0000db28 <am_hal_flash_delay>:
|
||
|
|
db28: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
db2c: 6b5b ldr r3, [r3, #52] ; 0x34
|
||
|
|
db2e: 075b lsls r3, r3, #29
|
||
|
|
db30: bf46 itte mi
|
||
|
|
db32: 0040 lslmi r0, r0, #1
|
||
|
|
db34: 230e movmi r3, #14
|
||
|
|
db36: 230b movpl r3, #11
|
||
|
|
db38: 4298 cmp r0, r3
|
||
|
|
db3a: d902 bls.n db42 <am_hal_flash_delay+0x1a>
|
||
|
|
db3c: 1ac0 subs r0, r0, r3
|
||
|
|
db3e: 4b01 ldr r3, [pc, #4] ; (db44 <am_hal_flash_delay+0x1c>)
|
||
|
|
db40: 4718 bx r3
|
||
|
|
db42: 4770 bx lr
|
||
|
|
db44: 0800009d .word 0x0800009d
|
||
|
|
|
||
|
|
0000db48 <am_hal_flash_delay_status_check>:
|
||
|
|
db48: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
||
|
|
db4c: f89d c020 ldrb.w ip, [sp, #32]
|
||
|
|
db50: 4604 mov r4, r0
|
||
|
|
db52: 460d mov r5, r1
|
||
|
|
db54: 4616 mov r6, r2
|
||
|
|
db56: 461f mov r7, r3
|
||
|
|
db58: f1bc 0f00 cmp.w ip, #0
|
||
|
|
db5c: d015 beq.n db8a <am_hal_flash_delay_status_check+0x42>
|
||
|
|
db5e: f8df 8058 ldr.w r8, [pc, #88] ; dbb8 <am_hal_flash_delay_status_check+0x70>
|
||
|
|
db62: f04f 2940 mov.w r9, #1073758208 ; 0x40004000
|
||
|
|
db66: e009 b.n db7c <am_hal_flash_delay_status_check+0x34>
|
||
|
|
db68: b31c cbz r4, dbb2 <am_hal_flash_delay_status_check+0x6a>
|
||
|
|
db6a: f8d9 3034 ldr.w r3, [r9, #52] ; 0x34
|
||
|
|
db6e: f013 0f04 tst.w r3, #4
|
||
|
|
db72: bf0c ite eq
|
||
|
|
db74: 2005 moveq r0, #5
|
||
|
|
db76: 2012 movne r0, #18
|
||
|
|
db78: 3c01 subs r4, #1
|
||
|
|
db7a: 47c0 blx r8
|
||
|
|
db7c: 6828 ldr r0, [r5, #0]
|
||
|
|
db7e: 4030 ands r0, r6
|
||
|
|
db80: 42b8 cmp r0, r7
|
||
|
|
db82: d1f1 bne.n db68 <am_hal_flash_delay_status_check+0x20>
|
||
|
|
db84: 2000 movs r0, #0
|
||
|
|
db86: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
||
|
|
db8a: f8df 902c ldr.w r9, [pc, #44] ; dbb8 <am_hal_flash_delay_status_check+0x70>
|
||
|
|
db8e: f04f 2840 mov.w r8, #1073758208 ; 0x40004000
|
||
|
|
db92: e009 b.n dba8 <am_hal_flash_delay_status_check+0x60>
|
||
|
|
db94: b16c cbz r4, dbb2 <am_hal_flash_delay_status_check+0x6a>
|
||
|
|
db96: f8d8 3034 ldr.w r3, [r8, #52] ; 0x34
|
||
|
|
db9a: f013 0f04 tst.w r3, #4
|
||
|
|
db9e: bf0c ite eq
|
||
|
|
dba0: 2005 moveq r0, #5
|
||
|
|
dba2: 2012 movne r0, #18
|
||
|
|
dba4: 3c01 subs r4, #1
|
||
|
|
dba6: 47c8 blx r9
|
||
|
|
dba8: 6828 ldr r0, [r5, #0]
|
||
|
|
dbaa: 4030 ands r0, r6
|
||
|
|
dbac: 42b8 cmp r0, r7
|
||
|
|
dbae: d0f1 beq.n db94 <am_hal_flash_delay_status_check+0x4c>
|
||
|
|
dbb0: e7e8 b.n db84 <am_hal_flash_delay_status_check+0x3c>
|
||
|
|
dbb2: 2004 movs r0, #4
|
||
|
|
dbb4: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
||
|
|
dbb8: 0800009d .word 0x0800009d
|
||
|
|
|
||
|
|
0000dbbc <am_hal_flash_store_ui32>:
|
||
|
|
dbbc: 4b01 ldr r3, [pc, #4] ; (dbc4 <am_hal_flash_store_ui32+0x8>)
|
||
|
|
dbbe: f043 0301 orr.w r3, r3, #1
|
||
|
|
dbc2: 4718 bx r3
|
||
|
|
dbc4: 10000200 .word 0x10000200
|
||
|
|
|
||
|
|
0000dbc8 <am_hal_gpio_pinconfig>:
|
||
|
|
dbc8: 2831 cmp r0, #49 ; 0x31
|
||
|
|
dbca: f200 80bc bhi.w dd46 <am_hal_gpio_pinconfig+0x17e>
|
||
|
|
dbce: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
||
|
|
dbd2: 4604 mov r4, r0
|
||
|
|
dbd4: f011 07e0 ands.w r7, r1, #224 ; 0xe0
|
||
|
|
dbd8: f001 0007 and.w r0, r1, #7
|
||
|
|
dbdc: b085 sub sp, #20
|
||
|
|
dbde: ea4f 02c0 mov.w r2, r0, lsl #3
|
||
|
|
dbe2: f3c1 03c1 ubfx r3, r1, #3, #2
|
||
|
|
dbe6: d00f beq.n dc08 <am_hal_gpio_pinconfig+0x40>
|
||
|
|
dbe8: f3c1 1642 ubfx r6, r1, #5, #3
|
||
|
|
dbec: 1db5 adds r5, r6, #6
|
||
|
|
dbee: f005 0507 and.w r5, r5, #7
|
||
|
|
dbf2: 2d03 cmp r5, #3
|
||
|
|
dbf4: f042 0201 orr.w r2, r2, #1
|
||
|
|
dbf8: f240 80a7 bls.w dd4a <am_hal_gpio_pinconfig+0x182>
|
||
|
|
dbfc: 2fc0 cmp r7, #192 ; 0xc0
|
||
|
|
dbfe: f000 80eb beq.w ddd8 <am_hal_gpio_pinconfig+0x210>
|
||
|
|
dc02: 2f20 cmp r7, #32
|
||
|
|
dc04: f000 80ed beq.w dde2 <am_hal_gpio_pinconfig+0x21a>
|
||
|
|
dc08: b163 cbz r3, dc24 <am_hal_gpio_pinconfig+0x5c>
|
||
|
|
dc0a: 2b01 cmp r3, #1
|
||
|
|
dc0c: f000 80dd beq.w ddca <am_hal_gpio_pinconfig+0x202>
|
||
|
|
dc10: 2b02 cmp r3, #2
|
||
|
|
dc12: f040 80c3 bne.w dd9c <am_hal_gpio_pinconfig+0x1d4>
|
||
|
|
dc16: 4b7e ldr r3, [pc, #504] ; (de10 <am_hal_gpio_pinconfig+0x248>)
|
||
|
|
dc18: 5d1b ldrb r3, [r3, r4]
|
||
|
|
dc1a: 075b lsls r3, r3, #29
|
||
|
|
dc1c: f140 80be bpl.w dd9c <am_hal_gpio_pinconfig+0x1d4>
|
||
|
|
dc20: f042 0280 orr.w r2, r2, #128 ; 0x80
|
||
|
|
dc24: 4b7b ldr r3, [pc, #492] ; (de14 <am_hal_gpio_pinconfig+0x24c>)
|
||
|
|
dc26: 4d7c ldr r5, [pc, #496] ; (de18 <am_hal_gpio_pinconfig+0x250>)
|
||
|
|
dc28: 5d1b ldrb r3, [r3, r4]
|
||
|
|
dc2a: 5d2d ldrb r5, [r5, r4]
|
||
|
|
dc2c: 4103 asrs r3, r0
|
||
|
|
dc2e: 005b lsls r3, r3, #1
|
||
|
|
dc30: f003 0302 and.w r3, r3, #2
|
||
|
|
dc34: 4285 cmp r5, r0
|
||
|
|
dc36: ea43 0302 orr.w r3, r3, r2
|
||
|
|
dc3a: f000 8091 beq.w dd60 <am_hal_gpio_pinconfig+0x198>
|
||
|
|
dc3e: f3c1 2607 ubfx r6, r1, #8, #8
|
||
|
|
dc42: f3c1 2581 ubfx r5, r1, #10, #2
|
||
|
|
dc46: f3c1 3080 ubfx r0, r1, #14, #1
|
||
|
|
dc4a: 0a8a lsrs r2, r1, #10
|
||
|
|
dc4c: f006 070c and.w r7, r6, #12
|
||
|
|
dc50: ea40 0045 orr.w r0, r0, r5, lsl #1
|
||
|
|
dc54: f002 0208 and.w r2, r2, #8
|
||
|
|
dc58: f3c1 3500 ubfx r5, r1, #12, #1
|
||
|
|
dc5c: 2f04 cmp r7, #4
|
||
|
|
dc5e: ea42 0200 orr.w r2, r2, r0
|
||
|
|
dc62: ea43 0345 orr.w r3, r3, r5, lsl #1
|
||
|
|
dc66: 4628 mov r0, r5
|
||
|
|
dc68: f000 80ac beq.w ddc4 <am_hal_gpio_pinconfig+0x1fc>
|
||
|
|
dc6c: 486b ldr r0, [pc, #428] ; (de1c <am_hal_gpio_pinconfig+0x254>)
|
||
|
|
dc6e: 6800 ldr r0, [r0, #0]
|
||
|
|
dc70: eba1 0800 sub.w r8, r1, r0
|
||
|
|
dc74: fab8 f888 clz r8, r8
|
||
|
|
dc78: ea4f 1858 mov.w r8, r8, lsr #5
|
||
|
|
dc7c: f016 0f60 tst.w r6, #96 ; 0x60
|
||
|
|
dc80: bf04 itt eq
|
||
|
|
dc82: f3c1 30c0 ubfxeq r0, r1, #15, #1
|
||
|
|
dc86: f360 0200 bfieq r2, r0, #0, #1
|
||
|
|
dc8a: 00a6 lsls r6, r4, #2
|
||
|
|
dc8c: f3c1 2101 ubfx r1, r1, #8, #2
|
||
|
|
dc90: 2902 cmp r1, #2
|
||
|
|
dc92: ea4f 05c4 mov.w r5, r4, lsl #3
|
||
|
|
dc96: f000 808e beq.w ddb6 <am_hal_gpio_pinconfig+0x1ee>
|
||
|
|
dc9a: 2903 cmp r1, #3
|
||
|
|
dc9c: f000 8082 beq.w dda4 <am_hal_gpio_pinconfig+0x1dc>
|
||
|
|
dca0: 2901 cmp r1, #1
|
||
|
|
dca2: bf08 it eq
|
||
|
|
dca4: f043 0304 orreq.w r3, r3, #4
|
||
|
|
dca8: f005 0518 and.w r5, r5, #24
|
||
|
|
dcac: f04f 0900 mov.w r9, #0
|
||
|
|
dcb0: f006 061c and.w r6, r6, #28
|
||
|
|
dcb4: 210f movs r1, #15
|
||
|
|
dcb6: 40b1 lsls r1, r6
|
||
|
|
dcb8: 27ff movs r7, #255 ; 0xff
|
||
|
|
dcba: fa02 f606 lsl.w r6, r2, r6
|
||
|
|
dcbe: 43ca mvns r2, r1
|
||
|
|
dcc0: 40af lsls r7, r5
|
||
|
|
dcc2: 9201 str r2, [sp, #4]
|
||
|
|
dcc4: fa03 f505 lsl.w r5, r3, r5
|
||
|
|
dcc8: f000 f92a bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
dccc: f024 0b03 bic.w fp, r4, #3
|
||
|
|
dcd0: ea4f 0a54 mov.w sl, r4, lsr #1
|
||
|
|
dcd4: f10b 4c80 add.w ip, fp, #1073741824 ; 0x40000000
|
||
|
|
dcd8: 4b51 ldr r3, [pc, #324] ; (de20 <am_hal_gpio_pinconfig+0x258>)
|
||
|
|
dcda: 4952 ldr r1, [pc, #328] ; (de24 <am_hal_gpio_pinconfig+0x25c>)
|
||
|
|
dcdc: 9a01 ldr r2, [sp, #4]
|
||
|
|
dcde: 9003 str r0, [sp, #12]
|
||
|
|
dce0: 43ff mvns r7, r7
|
||
|
|
dce2: f02a 0a03 bic.w sl, sl, #3
|
||
|
|
dce6: f50c 3c80 add.w ip, ip, #65536 ; 0x10000
|
||
|
|
dcea: f1b8 0f00 cmp.w r8, #0
|
||
|
|
dcee: d00b beq.n dd08 <am_hal_gpio_pinconfig+0x140>
|
||
|
|
dcf0: ea4f 0ed4 mov.w lr, r4, lsr #3
|
||
|
|
dcf4: f004 081f and.w r8, r4, #31
|
||
|
|
dcf8: 484b ldr r0, [pc, #300] ; (de28 <am_hal_gpio_pinconfig+0x260>)
|
||
|
|
dcfa: f00e 0e04 and.w lr, lr, #4
|
||
|
|
dcfe: 2401 movs r4, #1
|
||
|
|
dd00: fa04 f408 lsl.w r4, r4, r8
|
||
|
|
dd04: f84e 4000 str.w r4, [lr, r0]
|
||
|
|
dd08: 4848 ldr r0, [pc, #288] ; (de2c <am_hal_gpio_pinconfig+0x264>)
|
||
|
|
dd0a: 2473 movs r4, #115 ; 0x73
|
||
|
|
dd0c: 6604 str r4, [r0, #96] ; 0x60
|
||
|
|
dd0e: f8dc 4000 ldr.w r4, [ip]
|
||
|
|
dd12: 403c ands r4, r7
|
||
|
|
dd14: 4325 orrs r5, r4
|
||
|
|
dd16: f8cc 5000 str.w r5, [ip]
|
||
|
|
dd1a: f85a 4003 ldr.w r4, [sl, r3]
|
||
|
|
dd1e: 4022 ands r2, r4
|
||
|
|
dd20: 4332 orrs r2, r6
|
||
|
|
dd22: f84a 2003 str.w r2, [sl, r3]
|
||
|
|
dd26: f85b 3001 ldr.w r3, [fp, r1]
|
||
|
|
dd2a: 401f ands r7, r3
|
||
|
|
dd2c: 2400 movs r4, #0
|
||
|
|
dd2e: ea47 0709 orr.w r7, r7, r9
|
||
|
|
dd32: f84b 7001 str.w r7, [fp, r1]
|
||
|
|
dd36: 6604 str r4, [r0, #96] ; 0x60
|
||
|
|
dd38: 9803 ldr r0, [sp, #12]
|
||
|
|
dd3a: f000 f8f5 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
dd3e: 4620 mov r0, r4
|
||
|
|
dd40: b005 add sp, #20
|
||
|
|
dd42: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
||
|
|
dd46: 2006 movs r0, #6
|
||
|
|
dd48: 4770 bx lr
|
||
|
|
dd4a: 4d31 ldr r5, [pc, #196] ; (de10 <am_hal_gpio_pinconfig+0x248>)
|
||
|
|
dd4c: 5d2d ldrb r5, [r5, r4]
|
||
|
|
dd4e: 3e02 subs r6, #2
|
||
|
|
dd50: ea42 1286 orr.w r2, r2, r6, lsl #6
|
||
|
|
dd54: 07ee lsls r6, r5, #31
|
||
|
|
dd56: d547 bpl.n dde8 <am_hal_gpio_pinconfig+0x220>
|
||
|
|
dd58: 2b00 cmp r3, #0
|
||
|
|
dd5a: f43f af63 beq.w dc24 <am_hal_gpio_pinconfig+0x5c>
|
||
|
|
dd5e: e754 b.n dc0a <am_hal_gpio_pinconfig+0x42>
|
||
|
|
dd60: f3c1 4202 ubfx r2, r1, #16, #3
|
||
|
|
dd64: 2a07 cmp r2, #7
|
||
|
|
dd66: d041 beq.n ddec <am_hal_gpio_pinconfig+0x224>
|
||
|
|
dd68: 4d31 ldr r5, [pc, #196] ; (de30 <am_hal_gpio_pinconfig+0x268>)
|
||
|
|
dd6a: 4610 mov r0, r2
|
||
|
|
dd6c: f815 6024 ldrb.w r6, [r5, r4, lsl #2]
|
||
|
|
dd70: f3c1 42c1 ubfx r2, r1, #19, #2
|
||
|
|
dd74: ea42 1000 orr.w r0, r2, r0, lsl #4
|
||
|
|
dd78: 4286 cmp r6, r0
|
||
|
|
dd7a: d039 beq.n ddf0 <am_hal_gpio_pinconfig+0x228>
|
||
|
|
dd7c: eb05 0584 add.w r5, r5, r4, lsl #2
|
||
|
|
dd80: 00a6 lsls r6, r4, #2
|
||
|
|
dd82: 786a ldrb r2, [r5, #1]
|
||
|
|
dd84: 4282 cmp r2, r0
|
||
|
|
dd86: d03d beq.n de04 <am_hal_gpio_pinconfig+0x23c>
|
||
|
|
dd88: 78aa ldrb r2, [r5, #2]
|
||
|
|
dd8a: 4282 cmp r2, r0
|
||
|
|
dd8c: d03c beq.n de08 <am_hal_gpio_pinconfig+0x240>
|
||
|
|
dd8e: 78ea ldrb r2, [r5, #3]
|
||
|
|
dd90: 4282 cmp r2, r0
|
||
|
|
dd92: d03b beq.n de0c <am_hal_gpio_pinconfig+0x244>
|
||
|
|
dd94: 4827 ldr r0, [pc, #156] ; (de34 <am_hal_gpio_pinconfig+0x26c>)
|
||
|
|
dd96: b005 add sp, #20
|
||
|
|
dd98: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
||
|
|
dd9c: 4826 ldr r0, [pc, #152] ; (de38 <am_hal_gpio_pinconfig+0x270>)
|
||
|
|
dd9e: b005 add sp, #20
|
||
|
|
dda0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
||
|
|
dda4: f005 0518 and.w r5, r5, #24
|
||
|
|
dda8: f04f 0901 mov.w r9, #1
|
||
|
|
ddac: f043 0304 orr.w r3, r3, #4
|
||
|
|
ddb0: fa09 f905 lsl.w r9, r9, r5
|
||
|
|
ddb4: e77c b.n dcb0 <am_hal_gpio_pinconfig+0xe8>
|
||
|
|
ddb6: f005 0518 and.w r5, r5, #24
|
||
|
|
ddba: f04f 0901 mov.w r9, #1
|
||
|
|
ddbe: fa09 f905 lsl.w r9, r9, r5
|
||
|
|
ddc2: e775 b.n dcb0 <am_hal_gpio_pinconfig+0xe8>
|
||
|
|
ddc4: f04f 0801 mov.w r8, #1
|
||
|
|
ddc8: e758 b.n dc7c <am_hal_gpio_pinconfig+0xb4>
|
||
|
|
ddca: 4b11 ldr r3, [pc, #68] ; (de10 <am_hal_gpio_pinconfig+0x248>)
|
||
|
|
ddcc: 5d1b ldrb r3, [r3, r4]
|
||
|
|
ddce: 079d lsls r5, r3, #30
|
||
|
|
ddd0: d5e4 bpl.n dd9c <am_hal_gpio_pinconfig+0x1d4>
|
||
|
|
ddd2: f042 0240 orr.w r2, r2, #64 ; 0x40
|
||
|
|
ddd6: e725 b.n dc24 <am_hal_gpio_pinconfig+0x5c>
|
||
|
|
ddd8: 2c14 cmp r4, #20
|
||
|
|
ddda: f43f af15 beq.w dc08 <am_hal_gpio_pinconfig+0x40>
|
||
|
|
ddde: 4817 ldr r0, [pc, #92] ; (de3c <am_hal_gpio_pinconfig+0x274>)
|
||
|
|
dde0: e7ae b.n dd40 <am_hal_gpio_pinconfig+0x178>
|
||
|
|
dde2: 2c14 cmp r4, #20
|
||
|
|
dde4: f47f af10 bne.w dc08 <am_hal_gpio_pinconfig+0x40>
|
||
|
|
dde8: 4815 ldr r0, [pc, #84] ; (de40 <am_hal_gpio_pinconfig+0x278>)
|
||
|
|
ddea: e7a9 b.n dd40 <am_hal_gpio_pinconfig+0x178>
|
||
|
|
ddec: 4815 ldr r0, [pc, #84] ; (de44 <am_hal_gpio_pinconfig+0x27c>)
|
||
|
|
ddee: e7a7 b.n dd40 <am_hal_gpio_pinconfig+0x178>
|
||
|
|
ddf0: 2200 movs r2, #0
|
||
|
|
ddf2: 00a6 lsls r6, r4, #2
|
||
|
|
ddf4: 0052 lsls r2, r2, #1
|
||
|
|
ddf6: f3c1 5040 ubfx r0, r1, #21, #1
|
||
|
|
ddfa: ea42 02c0 orr.w r2, r2, r0, lsl #3
|
||
|
|
ddfe: f04f 0800 mov.w r8, #0
|
||
|
|
de02: e743 b.n dc8c <am_hal_gpio_pinconfig+0xc4>
|
||
|
|
de04: 2201 movs r2, #1
|
||
|
|
de06: e7f5 b.n ddf4 <am_hal_gpio_pinconfig+0x22c>
|
||
|
|
de08: 2202 movs r2, #2
|
||
|
|
de0a: e7f3 b.n ddf4 <am_hal_gpio_pinconfig+0x22c>
|
||
|
|
de0c: 2203 movs r2, #3
|
||
|
|
de0e: e7f1 b.n ddf4 <am_hal_gpio_pinconfig+0x22c>
|
||
|
|
de10: 0000ee50 .word 0x0000ee50
|
||
|
|
de14: 0000ee84 .word 0x0000ee84
|
||
|
|
de18: 0000ef80 .word 0x0000ef80
|
||
|
|
de1c: 0000ee48 .word 0x0000ee48
|
||
|
|
de20: 40010040 .word 0x40010040
|
||
|
|
de24: 400100e0 .word 0x400100e0
|
||
|
|
de28: 400100b4 .word 0x400100b4
|
||
|
|
de2c: 40010000 .word 0x40010000
|
||
|
|
de30: 0000eeb8 .word 0x0000eeb8
|
||
|
|
de34: 08000104 .word 0x08000104
|
||
|
|
de38: 08000102 .word 0x08000102
|
||
|
|
de3c: 08000101 .word 0x08000101
|
||
|
|
de40: 08000100 .word 0x08000100
|
||
|
|
de44: 08000103 .word 0x08000103
|
||
|
|
|
||
|
|
0000de48 <am_hal_gpio_interrupt_enable>:
|
||
|
|
de48: b570 push {r4, r5, r6, lr}
|
||
|
|
de4a: 0c8b lsrs r3, r1, #18
|
||
|
|
de4c: 2500 movs r5, #0
|
||
|
|
de4e: 462a mov r2, r5
|
||
|
|
de50: 049b lsls r3, r3, #18
|
||
|
|
de52: 4313 orrs r3, r2
|
||
|
|
de54: b082 sub sp, #8
|
||
|
|
de56: d115 bne.n de84 <am_hal_gpio_interrupt_enable+0x3c>
|
||
|
|
de58: 460c mov r4, r1
|
||
|
|
de5a: 4606 mov r6, r0
|
||
|
|
de5c: f000 f860 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
de60: 4b0a ldr r3, [pc, #40] ; (de8c <am_hal_gpio_interrupt_enable+0x44>)
|
||
|
|
de62: 9001 str r0, [sp, #4]
|
||
|
|
de64: f8d3 0200 ldr.w r0, [r3, #512] ; 0x200
|
||
|
|
de68: 4330 orrs r0, r6
|
||
|
|
de6a: f8c3 0200 str.w r0, [r3, #512] ; 0x200
|
||
|
|
de6e: f8d3 1210 ldr.w r1, [r3, #528] ; 0x210
|
||
|
|
de72: 430c orrs r4, r1
|
||
|
|
de74: f8c3 4210 str.w r4, [r3, #528] ; 0x210
|
||
|
|
de78: 9801 ldr r0, [sp, #4]
|
||
|
|
de7a: f000 f855 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
de7e: 4628 mov r0, r5
|
||
|
|
de80: b002 add sp, #8
|
||
|
|
de82: bd70 pop {r4, r5, r6, pc}
|
||
|
|
de84: 2005 movs r0, #5
|
||
|
|
de86: b002 add sp, #8
|
||
|
|
de88: bd70 pop {r4, r5, r6, pc}
|
||
|
|
de8a: bf00 nop
|
||
|
|
de8c: 40010000 .word 0x40010000
|
||
|
|
|
||
|
|
0000de90 <am_hal_gpio_interrupt_disable>:
|
||
|
|
de90: b570 push {r4, r5, r6, lr}
|
||
|
|
de92: 0c8b lsrs r3, r1, #18
|
||
|
|
de94: 2500 movs r5, #0
|
||
|
|
de96: 462a mov r2, r5
|
||
|
|
de98: 049b lsls r3, r3, #18
|
||
|
|
de9a: 4313 orrs r3, r2
|
||
|
|
de9c: b082 sub sp, #8
|
||
|
|
de9e: d117 bne.n ded0 <am_hal_gpio_interrupt_disable+0x40>
|
||
|
|
dea0: 460c mov r4, r1
|
||
|
|
dea2: 4606 mov r6, r0
|
||
|
|
dea4: f000 f83c bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
dea8: 4b0b ldr r3, [pc, #44] ; (ded8 <am_hal_gpio_interrupt_disable+0x48>)
|
||
|
|
deaa: 9001 str r0, [sp, #4]
|
||
|
|
deac: f8d3 0200 ldr.w r0, [r3, #512] ; 0x200
|
||
|
|
deb0: ea20 0006 bic.w r0, r0, r6
|
||
|
|
deb4: f8c3 0200 str.w r0, [r3, #512] ; 0x200
|
||
|
|
deb8: f8d3 1210 ldr.w r1, [r3, #528] ; 0x210
|
||
|
|
debc: ea21 0404 bic.w r4, r1, r4
|
||
|
|
dec0: f8c3 4210 str.w r4, [r3, #528] ; 0x210
|
||
|
|
dec4: 9801 ldr r0, [sp, #4]
|
||
|
|
dec6: f000 f82f bl df28 <am_hal_interrupt_master_set>
|
||
|
|
deca: 4628 mov r0, r5
|
||
|
|
decc: b002 add sp, #8
|
||
|
|
dece: bd70 pop {r4, r5, r6, pc}
|
||
|
|
ded0: 2005 movs r0, #5
|
||
|
|
ded2: b002 add sp, #8
|
||
|
|
ded4: bd70 pop {r4, r5, r6, pc}
|
||
|
|
ded6: bf00 nop
|
||
|
|
ded8: 40010000 .word 0x40010000
|
||
|
|
|
||
|
|
0000dedc <am_hal_gpio_interrupt_clear>:
|
||
|
|
dedc: b570 push {r4, r5, r6, lr}
|
||
|
|
dede: 0c8b lsrs r3, r1, #18
|
||
|
|
dee0: 2500 movs r5, #0
|
||
|
|
dee2: 462a mov r2, r5
|
||
|
|
dee4: 049b lsls r3, r3, #18
|
||
|
|
dee6: 4313 orrs r3, r2
|
||
|
|
dee8: b082 sub sp, #8
|
||
|
|
deea: d10f bne.n df0c <am_hal_gpio_interrupt_clear+0x30>
|
||
|
|
deec: 460c mov r4, r1
|
||
|
|
deee: 4606 mov r6, r0
|
||
|
|
def0: f000 f816 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
def4: 4b07 ldr r3, [pc, #28] ; (df14 <am_hal_gpio_interrupt_clear+0x38>)
|
||
|
|
def6: 9001 str r0, [sp, #4]
|
||
|
|
def8: f8c3 6208 str.w r6, [r3, #520] ; 0x208
|
||
|
|
defc: f8c3 4218 str.w r4, [r3, #536] ; 0x218
|
||
|
|
df00: 9801 ldr r0, [sp, #4]
|
||
|
|
df02: f000 f811 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
df06: 4628 mov r0, r5
|
||
|
|
df08: b002 add sp, #8
|
||
|
|
df0a: bd70 pop {r4, r5, r6, pc}
|
||
|
|
df0c: 2005 movs r0, #5
|
||
|
|
df0e: b002 add sp, #8
|
||
|
|
df10: bd70 pop {r4, r5, r6, pc}
|
||
|
|
df12: bf00 nop
|
||
|
|
df14: 40010000 .word 0x40010000
|
||
|
|
|
||
|
|
0000df18 <am_hal_interrupt_master_enable>:
|
||
|
|
df18: f3ef 8010 mrs r0, PRIMASK
|
||
|
|
df1c: b662 cpsie i
|
||
|
|
df1e: 4770 bx lr
|
||
|
|
|
||
|
|
0000df20 <am_hal_interrupt_master_disable>:
|
||
|
|
df20: f3ef 8010 mrs r0, PRIMASK
|
||
|
|
df24: b672 cpsid i
|
||
|
|
df26: 4770 bx lr
|
||
|
|
|
||
|
|
0000df28 <am_hal_interrupt_master_set>:
|
||
|
|
df28: f380 8810 msr PRIMASK, r0
|
||
|
|
df2c: 4770 bx lr
|
||
|
|
df2e: bf00 nop
|
||
|
|
|
||
|
|
0000df30 <am_hal_pwrctrl_periph_enable>:
|
||
|
|
df30: b570 push {r4, r5, r6, lr}
|
||
|
|
df32: b082 sub sp, #8
|
||
|
|
df34: 4604 mov r4, r0
|
||
|
|
df36: f7ff fff3 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
df3a: eb04 0444 add.w r4, r4, r4, lsl #1
|
||
|
|
df3e: 4e0f ldr r6, [pc, #60] ; (df7c <am_hal_pwrctrl_periph_enable+0x4c>)
|
||
|
|
df40: 4d0f ldr r5, [pc, #60] ; (df80 <am_hal_pwrctrl_periph_enable+0x50>)
|
||
|
|
df42: 9001 str r0, [sp, #4]
|
||
|
|
df44: 00a4 lsls r4, r4, #2
|
||
|
|
df46: 68b3 ldr r3, [r6, #8]
|
||
|
|
df48: 592a ldr r2, [r5, r4]
|
||
|
|
df4a: 4313 orrs r3, r2
|
||
|
|
df4c: 60b3 str r3, [r6, #8]
|
||
|
|
df4e: 9801 ldr r0, [sp, #4]
|
||
|
|
df50: 442c add r4, r5
|
||
|
|
df52: f7ff ffe9 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
df56: 20a0 movs r0, #160 ; 0xa0
|
||
|
|
df58: f7ff fde6 bl db28 <am_hal_flash_delay>
|
||
|
|
df5c: 69b3 ldr r3, [r6, #24]
|
||
|
|
df5e: 6864 ldr r4, [r4, #4]
|
||
|
|
df60: 4223 tst r3, r4
|
||
|
|
df62: d103 bne.n df6c <am_hal_pwrctrl_periph_enable+0x3c>
|
||
|
|
df64: 20a0 movs r0, #160 ; 0xa0
|
||
|
|
df66: f7ff fddf bl db28 <am_hal_flash_delay>
|
||
|
|
df6a: 69b3 ldr r3, [r6, #24]
|
||
|
|
df6c: 4b03 ldr r3, [pc, #12] ; (df7c <am_hal_pwrctrl_periph_enable+0x4c>)
|
||
|
|
df6e: 699b ldr r3, [r3, #24]
|
||
|
|
df70: 4223 tst r3, r4
|
||
|
|
df72: bf0c ite eq
|
||
|
|
df74: 2001 moveq r0, #1
|
||
|
|
df76: 2000 movne r0, #0
|
||
|
|
df78: b002 add sp, #8
|
||
|
|
df7a: bd70 pop {r4, r5, r6, pc}
|
||
|
|
df7c: 40021000 .word 0x40021000
|
||
|
|
df80: 0000efb4 .word 0x0000efb4
|
||
|
|
|
||
|
|
0000df84 <am_hal_pwrctrl_periph_disable>:
|
||
|
|
df84: b570 push {r4, r5, r6, lr}
|
||
|
|
df86: b082 sub sp, #8
|
||
|
|
df88: 4604 mov r4, r0
|
||
|
|
df8a: f7ff ffc9 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
df8e: eb04 0444 add.w r4, r4, r4, lsl #1
|
||
|
|
df92: 4e10 ldr r6, [pc, #64] ; (dfd4 <am_hal_pwrctrl_periph_disable+0x50>)
|
||
|
|
df94: 4d10 ldr r5, [pc, #64] ; (dfd8 <am_hal_pwrctrl_periph_disable+0x54>)
|
||
|
|
df96: 9001 str r0, [sp, #4]
|
||
|
|
df98: 00a4 lsls r4, r4, #2
|
||
|
|
df9a: 68b3 ldr r3, [r6, #8]
|
||
|
|
df9c: 592a ldr r2, [r5, r4]
|
||
|
|
df9e: ea23 0302 bic.w r3, r3, r2
|
||
|
|
dfa2: 60b3 str r3, [r6, #8]
|
||
|
|
dfa4: 9801 ldr r0, [sp, #4]
|
||
|
|
dfa6: 442c add r4, r5
|
||
|
|
dfa8: f7ff ffbe bl df28 <am_hal_interrupt_master_set>
|
||
|
|
dfac: 20a0 movs r0, #160 ; 0xa0
|
||
|
|
dfae: f7ff fdbb bl db28 <am_hal_flash_delay>
|
||
|
|
dfb2: 69b3 ldr r3, [r6, #24]
|
||
|
|
dfb4: 6864 ldr r4, [r4, #4]
|
||
|
|
dfb6: 4223 tst r3, r4
|
||
|
|
dfb8: d003 beq.n dfc2 <am_hal_pwrctrl_periph_disable+0x3e>
|
||
|
|
dfba: 20a0 movs r0, #160 ; 0xa0
|
||
|
|
dfbc: f7ff fdb4 bl db28 <am_hal_flash_delay>
|
||
|
|
dfc0: 69b3 ldr r3, [r6, #24]
|
||
|
|
dfc2: 4b04 ldr r3, [pc, #16] ; (dfd4 <am_hal_pwrctrl_periph_disable+0x50>)
|
||
|
|
dfc4: 699b ldr r3, [r3, #24]
|
||
|
|
dfc6: 4223 tst r3, r4
|
||
|
|
dfc8: bf14 ite ne
|
||
|
|
dfca: 2001 movne r0, #1
|
||
|
|
dfcc: 2000 moveq r0, #0
|
||
|
|
dfce: b002 add sp, #8
|
||
|
|
dfd0: bd70 pop {r4, r5, r6, pc}
|
||
|
|
dfd2: bf00 nop
|
||
|
|
dfd4: 40021000 .word 0x40021000
|
||
|
|
dfd8: 0000efb4 .word 0x0000efb4
|
||
|
|
|
||
|
|
0000dfdc <am_hal_pwrctrl_blebuck_trim>:
|
||
|
|
dfdc: b510 push {r4, lr}
|
||
|
|
dfde: 4c12 ldr r4, [pc, #72] ; (e028 <am_hal_pwrctrl_blebuck_trim+0x4c>)
|
||
|
|
dfe0: 68e3 ldr r3, [r4, #12]
|
||
|
|
dfe2: b2db uxtb r3, r3
|
||
|
|
dfe4: 2b11 cmp r3, #17
|
||
|
|
dfe6: b082 sub sp, #8
|
||
|
|
dfe8: d801 bhi.n dfee <am_hal_pwrctrl_blebuck_trim+0x12>
|
||
|
|
dfea: b002 add sp, #8
|
||
|
|
dfec: bd10 pop {r4, pc}
|
||
|
|
dfee: f7ff ff97 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
dff2: 9001 str r0, [sp, #4]
|
||
|
|
dff4: f8d4 3368 ldr.w r3, [r4, #872] ; 0x368
|
||
|
|
dff8: 2219 movs r2, #25
|
||
|
|
dffa: f362 138b bfi r3, r2, #6, #6
|
||
|
|
dffe: f8c4 3368 str.w r3, [r4, #872] ; 0x368
|
||
|
|
e002: f8d4 2368 ldr.w r2, [r4, #872] ; 0x368
|
||
|
|
e006: 230c movs r3, #12
|
||
|
|
e008: f363 0205 bfi r2, r3, #0, #6
|
||
|
|
e00c: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
|
||
|
|
e010: f8c4 2368 str.w r2, [r4, #872] ; 0x368
|
||
|
|
e014: 6bda ldr r2, [r3, #60] ; 0x3c
|
||
|
|
e016: f36f 5296 bfc r2, #22, #1
|
||
|
|
e01a: 63da str r2, [r3, #60] ; 0x3c
|
||
|
|
e01c: 9801 ldr r0, [sp, #4]
|
||
|
|
e01e: b002 add sp, #8
|
||
|
|
e020: e8bd 4010 ldmia.w sp!, {r4, lr}
|
||
|
|
e024: f7ff bf80 b.w df28 <am_hal_interrupt_master_set>
|
||
|
|
e028: 40020000 .word 0x40020000
|
||
|
|
|
||
|
|
0000e02c <am_hal_reset_control>:
|
||
|
|
e02c: 2803 cmp r0, #3
|
||
|
|
e02e: d819 bhi.n e064 <am_hal_reset_control+0x38>
|
||
|
|
e030: e8df f000 tbb [pc, r0]
|
||
|
|
e034: 02140e08 .word 0x02140e08
|
||
|
|
e038: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
|
||
|
|
e03c: 2201 movs r2, #1
|
||
|
|
e03e: 615a str r2, [r3, #20]
|
||
|
|
e040: 2000 movs r0, #0
|
||
|
|
e042: 4770 bx lr
|
||
|
|
e044: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
|
||
|
|
e048: 22d4 movs r2, #212 ; 0xd4
|
||
|
|
e04a: 609a str r2, [r3, #8]
|
||
|
|
e04c: 2000 movs r0, #0
|
||
|
|
e04e: 4770 bx lr
|
||
|
|
e050: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
|
||
|
|
e054: 221b movs r2, #27
|
||
|
|
e056: 605a str r2, [r3, #4]
|
||
|
|
e058: 2000 movs r0, #0
|
||
|
|
e05a: 4770 bx lr
|
||
|
|
e05c: 4b02 ldr r3, [pc, #8] ; (e068 <am_hal_reset_control+0x3c>)
|
||
|
|
e05e: 2000 movs r0, #0
|
||
|
|
e060: 6018 str r0, [r3, #0]
|
||
|
|
e062: 4770 bx lr
|
||
|
|
e064: 2006 movs r0, #6
|
||
|
|
e066: 4770 bx lr
|
||
|
|
e068: 4ffff000 .word 0x4ffff000
|
||
|
|
|
||
|
|
0000e06c <am_hal_stimer_config>:
|
||
|
|
e06c: 4a03 ldr r2, [pc, #12] ; (e07c <am_hal_stimer_config+0x10>)
|
||
|
|
e06e: 4603 mov r3, r0
|
||
|
|
e070: f8d2 0140 ldr.w r0, [r2, #320] ; 0x140
|
||
|
|
e074: f8c2 3140 str.w r3, [r2, #320] ; 0x140
|
||
|
|
e078: 4770 bx lr
|
||
|
|
e07a: bf00 nop
|
||
|
|
e07c: 40008000 .word 0x40008000
|
||
|
|
|
||
|
|
0000e080 <am_hal_stimer_counter_get>:
|
||
|
|
e080: 4b01 ldr r3, [pc, #4] ; (e088 <am_hal_stimer_counter_get+0x8>)
|
||
|
|
e082: f8d3 0144 ldr.w r0, [r3, #324] ; 0x144
|
||
|
|
e086: 4770 bx lr
|
||
|
|
e088: 40008000 .word 0x40008000
|
||
|
|
|
||
|
|
0000e08c <am_hal_stimer_int_enable>:
|
||
|
|
e08c: 4a03 ldr r2, [pc, #12] ; (e09c <am_hal_stimer_int_enable+0x10>)
|
||
|
|
e08e: f8d2 3300 ldr.w r3, [r2, #768] ; 0x300
|
||
|
|
e092: 4318 orrs r0, r3
|
||
|
|
e094: f8c2 0300 str.w r0, [r2, #768] ; 0x300
|
||
|
|
e098: 4770 bx lr
|
||
|
|
e09a: bf00 nop
|
||
|
|
e09c: 40008000 .word 0x40008000
|
||
|
|
|
||
|
|
0000e0a0 <am_hal_stimer_int_disable>:
|
||
|
|
e0a0: 4a03 ldr r2, [pc, #12] ; (e0b0 <am_hal_stimer_int_disable+0x10>)
|
||
|
|
e0a2: f8d2 3300 ldr.w r3, [r2, #768] ; 0x300
|
||
|
|
e0a6: ea23 0000 bic.w r0, r3, r0
|
||
|
|
e0aa: f8c2 0300 str.w r0, [r2, #768] ; 0x300
|
||
|
|
e0ae: 4770 bx lr
|
||
|
|
e0b0: 40008000 .word 0x40008000
|
||
|
|
|
||
|
|
0000e0b4 <am_hal_stimer_int_clear>:
|
||
|
|
e0b4: 4b01 ldr r3, [pc, #4] ; (e0bc <am_hal_stimer_int_clear+0x8>)
|
||
|
|
e0b6: f8c3 0308 str.w r0, [r3, #776] ; 0x308
|
||
|
|
e0ba: 4770 bx lr
|
||
|
|
e0bc: 40008000 .word 0x40008000
|
||
|
|
|
||
|
|
0000e0c0 <am_hal_sysctrl_sleep>:
|
||
|
|
e0c0: b510 push {r4, lr}
|
||
|
|
e0c2: b082 sub sp, #8
|
||
|
|
e0c4: 4604 mov r4, r0
|
||
|
|
e0c6: f7ff ff2b bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e0ca: 9001 str r0, [sp, #4]
|
||
|
|
e0cc: b124 cbz r4, e0d8 <am_hal_sysctrl_sleep+0x18>
|
||
|
|
e0ce: 4b12 ldr r3, [pc, #72] ; (e118 <am_hal_sysctrl_sleep+0x58>)
|
||
|
|
e0d0: f8d3 3250 ldr.w r3, [r3, #592] ; 0x250
|
||
|
|
e0d4: 07db lsls r3, r3, #31
|
||
|
|
e0d6: d513 bpl.n e100 <am_hal_sysctrl_sleep+0x40>
|
||
|
|
e0d8: 4a10 ldr r2, [pc, #64] ; (e11c <am_hal_sysctrl_sleep+0x5c>)
|
||
|
|
e0da: 6913 ldr r3, [r2, #16]
|
||
|
|
e0dc: f023 0304 bic.w r3, r3, #4
|
||
|
|
e0e0: 6113 str r3, [r2, #16]
|
||
|
|
e0e2: f3bf 8f4f dsb sy
|
||
|
|
e0e6: 4a0e ldr r2, [pc, #56] ; (e120 <am_hal_sysctrl_sleep+0x60>)
|
||
|
|
e0e8: 4b0e ldr r3, [pc, #56] ; (e124 <am_hal_sysctrl_sleep+0x64>)
|
||
|
|
e0ea: 6812 ldr r2, [r2, #0]
|
||
|
|
e0ec: 601a str r2, [r3, #0]
|
||
|
|
e0ee: bf30 wfi
|
||
|
|
e0f0: f3bf 8f6f isb sy
|
||
|
|
e0f4: 9801 ldr r0, [sp, #4]
|
||
|
|
e0f6: b002 add sp, #8
|
||
|
|
e0f8: e8bd 4010 ldmia.w sp!, {r4, lr}
|
||
|
|
e0fc: f7ff bf14 b.w df28 <am_hal_interrupt_master_set>
|
||
|
|
e100: 4b09 ldr r3, [pc, #36] ; (e128 <am_hal_sysctrl_sleep+0x68>)
|
||
|
|
e102: 681a ldr r2, [r3, #0]
|
||
|
|
e104: b912 cbnz r2, e10c <am_hal_sysctrl_sleep+0x4c>
|
||
|
|
e106: 4a09 ldr r2, [pc, #36] ; (e12c <am_hal_sysctrl_sleep+0x6c>)
|
||
|
|
e108: 6812 ldr r2, [r2, #0]
|
||
|
|
e10a: 601a str r2, [r3, #0]
|
||
|
|
e10c: 4a03 ldr r2, [pc, #12] ; (e11c <am_hal_sysctrl_sleep+0x5c>)
|
||
|
|
e10e: 6913 ldr r3, [r2, #16]
|
||
|
|
e110: f043 0304 orr.w r3, r3, #4
|
||
|
|
e114: 6113 str r3, [r2, #16]
|
||
|
|
e116: e7e4 b.n e0e2 <am_hal_sysctrl_sleep+0x22>
|
||
|
|
e118: 40020000 .word 0x40020000
|
||
|
|
e11c: e000ed00 .word 0xe000ed00
|
||
|
|
e120: 5fff0000 .word 0x5fff0000
|
||
|
|
e124: 10000a70 .word 0x10000a70
|
||
|
|
e128: 10000a6c .word 0x10000a6c
|
||
|
|
e12c: 4ffff000 .word 0x4ffff000
|
||
|
|
|
||
|
|
0000e130 <am_hal_uart_initialize>:
|
||
|
|
e130: 2801 cmp r0, #1
|
||
|
|
e132: d819 bhi.n e168 <am_hal_uart_initialize+0x38>
|
||
|
|
e134: b1e9 cbz r1, e172 <am_hal_uart_initialize+0x42>
|
||
|
|
e136: b4f0 push {r4, r5, r6, r7}
|
||
|
|
e138: 2264 movs r2, #100 ; 0x64
|
||
|
|
e13a: 4d0f ldr r5, [pc, #60] ; (e178 <am_hal_uart_initialize+0x48>)
|
||
|
|
e13c: fb02 f200 mul.w r2, r2, r0
|
||
|
|
e140: 18ac adds r4, r5, r2
|
||
|
|
e142: 78e3 ldrb r3, [r4, #3]
|
||
|
|
e144: f3c3 0700 ubfx r7, r3, #0, #1
|
||
|
|
e148: f013 0301 ands.w r3, r3, #1
|
||
|
|
e14c: d10e bne.n e16c <am_hal_uart_initialize+0x3c>
|
||
|
|
e14e: 6260 str r0, [r4, #36] ; 0x24
|
||
|
|
e150: 58ae ldr r6, [r5, r2]
|
||
|
|
e152: 480a ldr r0, [pc, #40] ; (e17c <am_hal_uart_initialize+0x4c>)
|
||
|
|
e154: f006 467e and.w r6, r6, #4261412864 ; 0xfe000000
|
||
|
|
e158: 4330 orrs r0, r6
|
||
|
|
e15a: 50a8 str r0, [r5, r2]
|
||
|
|
e15c: 7127 strb r7, [r4, #4]
|
||
|
|
e15e: 6623 str r3, [r4, #96] ; 0x60
|
||
|
|
e160: 4618 mov r0, r3
|
||
|
|
e162: 600c str r4, [r1, #0]
|
||
|
|
e164: bcf0 pop {r4, r5, r6, r7}
|
||
|
|
e166: 4770 bx lr
|
||
|
|
e168: 2005 movs r0, #5
|
||
|
|
e16a: 4770 bx lr
|
||
|
|
e16c: 2007 movs r0, #7
|
||
|
|
e16e: bcf0 pop {r4, r5, r6, r7}
|
||
|
|
e170: 4770 bx lr
|
||
|
|
e172: 2006 movs r0, #6
|
||
|
|
e174: 4770 bx lr
|
||
|
|
e176: bf00 nop
|
||
|
|
e178: 10000a78 .word 0x10000a78
|
||
|
|
e17c: 01ea9e06 .word 0x01ea9e06
|
||
|
|
|
||
|
|
0000e180 <am_hal_uart_power_control>:
|
||
|
|
e180: b5f0 push {r4, r5, r6, r7, lr}
|
||
|
|
e182: 4604 mov r4, r0
|
||
|
|
e184: 6800 ldr r0, [r0, #0]
|
||
|
|
e186: 4b39 ldr r3, [pc, #228] ; (e26c <am_hal_uart_power_control+0xec>)
|
||
|
|
e188: f020 467e bic.w r6, r0, #4261412864 ; 0xfe000000
|
||
|
|
e18c: 429e cmp r6, r3
|
||
|
|
e18e: b085 sub sp, #20
|
||
|
|
e190: d13f bne.n e212 <am_hal_uart_power_control+0x92>
|
||
|
|
e192: 6a65 ldr r5, [r4, #36] ; 0x24
|
||
|
|
e194: f105 0008 add.w r0, r5, #8
|
||
|
|
e198: b2c7 uxtb r7, r0
|
||
|
|
e19a: b1a1 cbz r1, e1c6 <am_hal_uart_power_control+0x46>
|
||
|
|
e19c: 3901 subs r1, #1
|
||
|
|
e19e: 2901 cmp r1, #1
|
||
|
|
e1a0: d80e bhi.n e1c0 <am_hal_uart_power_control+0x40>
|
||
|
|
e1a2: 2a00 cmp r2, #0
|
||
|
|
e1a4: d138 bne.n e218 <am_hal_uart_power_control+0x98>
|
||
|
|
e1a6: f505 2580 add.w r5, r5, #262144 ; 0x40000
|
||
|
|
e1aa: 351c adds r5, #28
|
||
|
|
e1ac: 032d lsls r5, r5, #12
|
||
|
|
e1ae: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
|
||
|
|
e1b2: 646b str r3, [r5, #68] ; 0x44
|
||
|
|
e1b4: 4638 mov r0, r7
|
||
|
|
e1b6: f7ff fee5 bl df84 <am_hal_pwrctrl_periph_disable>
|
||
|
|
e1ba: 2000 movs r0, #0
|
||
|
|
e1bc: b005 add sp, #20
|
||
|
|
e1be: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
e1c0: 2006 movs r0, #6
|
||
|
|
e1c2: b005 add sp, #20
|
||
|
|
e1c4: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
e1c6: 2a00 cmp r2, #0
|
||
|
|
e1c8: d047 beq.n e25a <am_hal_uart_power_control+0xda>
|
||
|
|
e1ca: 7923 ldrb r3, [r4, #4]
|
||
|
|
e1cc: 2b00 cmp r3, #0
|
||
|
|
e1ce: d04b beq.n e268 <am_hal_uart_power_control+0xe8>
|
||
|
|
e1d0: 4638 mov r0, r7
|
||
|
|
e1d2: f505 2580 add.w r5, r5, #262144 ; 0x40000
|
||
|
|
e1d6: 9101 str r1, [sp, #4]
|
||
|
|
e1d8: 351c adds r5, #28
|
||
|
|
e1da: f7ff fea9 bl df30 <am_hal_pwrctrl_periph_enable>
|
||
|
|
e1de: f7ff fe9f bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e1e2: e9d4 3602 ldrd r3, r6, [r4, #8]
|
||
|
|
e1e6: 032d lsls r5, r5, #12
|
||
|
|
e1e8: 9002 str r0, [sp, #8]
|
||
|
|
e1ea: 6922 ldr r2, [r4, #16]
|
||
|
|
e1ec: 622b str r3, [r5, #32]
|
||
|
|
e1ee: 6963 ldr r3, [r4, #20]
|
||
|
|
e1f0: 69a0 ldr r0, [r4, #24]
|
||
|
|
e1f2: 626e str r6, [r5, #36] ; 0x24
|
||
|
|
e1f4: 62aa str r2, [r5, #40] ; 0x28
|
||
|
|
e1f6: 69e2 ldr r2, [r4, #28]
|
||
|
|
e1f8: 62eb str r3, [r5, #44] ; 0x2c
|
||
|
|
e1fa: 6a23 ldr r3, [r4, #32]
|
||
|
|
e1fc: 9901 ldr r1, [sp, #4]
|
||
|
|
e1fe: 6328 str r0, [r5, #48] ; 0x30
|
||
|
|
e200: 636a str r2, [r5, #52] ; 0x34
|
||
|
|
e202: 63ab str r3, [r5, #56] ; 0x38
|
||
|
|
e204: 9802 ldr r0, [sp, #8]
|
||
|
|
e206: 7121 strb r1, [r4, #4]
|
||
|
|
e208: f7ff fe8e bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e20c: 9901 ldr r1, [sp, #4]
|
||
|
|
e20e: 4608 mov r0, r1
|
||
|
|
e210: e7d7 b.n e1c2 <am_hal_uart_power_control+0x42>
|
||
|
|
e212: 2002 movs r0, #2
|
||
|
|
e214: b005 add sp, #20
|
||
|
|
e216: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
e218: f7ff fe82 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e21c: f505 2580 add.w r5, r5, #262144 ; 0x40000
|
||
|
|
e220: 351c adds r5, #28
|
||
|
|
e222: 032d lsls r5, r5, #12
|
||
|
|
e224: 9003 str r0, [sp, #12]
|
||
|
|
e226: 6a2a ldr r2, [r5, #32]
|
||
|
|
e228: 6a6b ldr r3, [r5, #36] ; 0x24
|
||
|
|
e22a: 60a2 str r2, [r4, #8]
|
||
|
|
e22c: 6aaa ldr r2, [r5, #40] ; 0x28
|
||
|
|
e22e: 60e3 str r3, [r4, #12]
|
||
|
|
e230: 6aeb ldr r3, [r5, #44] ; 0x2c
|
||
|
|
e232: 6b29 ldr r1, [r5, #48] ; 0x30
|
||
|
|
e234: 6163 str r3, [r4, #20]
|
||
|
|
e236: 6b6b ldr r3, [r5, #52] ; 0x34
|
||
|
|
e238: 6122 str r2, [r4, #16]
|
||
|
|
e23a: 6baa ldr r2, [r5, #56] ; 0x38
|
||
|
|
e23c: 61e3 str r3, [r4, #28]
|
||
|
|
e23e: 2301 movs r3, #1
|
||
|
|
e240: 7123 strb r3, [r4, #4]
|
||
|
|
e242: 9803 ldr r0, [sp, #12]
|
||
|
|
e244: 61a1 str r1, [r4, #24]
|
||
|
|
e246: 6222 str r2, [r4, #32]
|
||
|
|
e248: f7ff fe6e bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e24c: 6823 ldr r3, [r4, #0]
|
||
|
|
e24e: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e252: 42b3 cmp r3, r6
|
||
|
|
e254: d1ae bne.n e1b4 <am_hal_uart_power_control+0x34>
|
||
|
|
e256: 6a65 ldr r5, [r4, #36] ; 0x24
|
||
|
|
e258: e7a5 b.n e1a6 <am_hal_uart_power_control+0x26>
|
||
|
|
e25a: 4638 mov r0, r7
|
||
|
|
e25c: 9201 str r2, [sp, #4]
|
||
|
|
e25e: f7ff fe67 bl df30 <am_hal_pwrctrl_periph_enable>
|
||
|
|
e262: 9a01 ldr r2, [sp, #4]
|
||
|
|
e264: 4610 mov r0, r2
|
||
|
|
e266: e7ac b.n e1c2 <am_hal_uart_power_control+0x42>
|
||
|
|
e268: 2007 movs r0, #7
|
||
|
|
e26a: e7aa b.n e1c2 <am_hal_uart_power_control+0x42>
|
||
|
|
e26c: 01ea9e06 .word 0x01ea9e06
|
||
|
|
|
||
|
|
0000e270 <am_hal_uart_configure>:
|
||
|
|
e270: 6803 ldr r3, [r0, #0]
|
||
|
|
e272: 4a78 ldr r2, [pc, #480] ; (e454 <am_hal_uart_configure+0x1e4>)
|
||
|
|
e274: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e278: 4293 cmp r3, r2
|
||
|
|
e27a: d001 beq.n e280 <am_hal_uart_configure+0x10>
|
||
|
|
e27c: 2002 movs r0, #2
|
||
|
|
e27e: 4770 bx lr
|
||
|
|
e280: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
||
|
|
e284: 6a44 ldr r4, [r0, #36] ; 0x24
|
||
|
|
e286: f504 2480 add.w r4, r4, #262144 ; 0x40000
|
||
|
|
e28a: 341c adds r4, #28
|
||
|
|
e28c: 0324 lsls r4, r4, #12
|
||
|
|
e28e: 2700 movs r7, #0
|
||
|
|
e290: b084 sub sp, #16
|
||
|
|
e292: 6327 str r7, [r4, #48] ; 0x30
|
||
|
|
e294: 460e mov r6, r1
|
||
|
|
e296: 4605 mov r5, r0
|
||
|
|
e298: f7ff fe42 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e29c: 9001 str r0, [sp, #4]
|
||
|
|
e29e: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e2a0: f043 0308 orr.w r3, r3, #8
|
||
|
|
e2a4: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e2a6: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e2a8: 2201 movs r2, #1
|
||
|
|
e2aa: f362 1306 bfi r3, r2, #4, #3
|
||
|
|
e2ae: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e2b0: 9801 ldr r0, [sp, #4]
|
||
|
|
e2b2: f7ff fe39 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e2b6: f7ff fe33 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e2ba: 9002 str r0, [sp, #8]
|
||
|
|
e2bc: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e2be: f367 0300 bfi r3, r7, #0, #1
|
||
|
|
e2c2: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e2c4: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e2c6: f367 2349 bfi r3, r7, #9, #1
|
||
|
|
e2ca: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e2cc: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e2ce: f367 2308 bfi r3, r7, #8, #1
|
||
|
|
e2d2: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e2d4: 9802 ldr r0, [sp, #8]
|
||
|
|
e2d6: f7ff fe27 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e2da: 4b5f ldr r3, [pc, #380] ; (e458 <am_hal_uart_configure+0x1e8>)
|
||
|
|
e2dc: 6832 ldr r2, [r6, #0]
|
||
|
|
e2de: 68db ldr r3, [r3, #12]
|
||
|
|
e2e0: b2db uxtb r3, r3
|
||
|
|
e2e2: 2b12 cmp r3, #18
|
||
|
|
e2e4: d076 beq.n e3d4 <am_hal_uart_configure+0x164>
|
||
|
|
e2e6: 4b5c ldr r3, [pc, #368] ; (e458 <am_hal_uart_configure+0x1e8>)
|
||
|
|
e2e8: 68db ldr r3, [r3, #12]
|
||
|
|
e2ea: b2db uxtb r3, r3
|
||
|
|
e2ec: 2b20 cmp r3, #32
|
||
|
|
e2ee: d902 bls.n e2f6 <am_hal_uart_configure+0x86>
|
||
|
|
e2f0: 4b5a ldr r3, [pc, #360] ; (e45c <am_hal_uart_configure+0x1ec>)
|
||
|
|
e2f2: 429a cmp r2, r3
|
||
|
|
e2f4: d871 bhi.n e3da <am_hal_uart_configure+0x16a>
|
||
|
|
e2f6: 6b23 ldr r3, [r4, #48] ; 0x30
|
||
|
|
e2f8: f3c3 1302 ubfx r3, r3, #4, #3
|
||
|
|
e2fc: 3b01 subs r3, #1
|
||
|
|
e2fe: b2db uxtb r3, r3
|
||
|
|
e300: 2b03 cmp r3, #3
|
||
|
|
e302: d86c bhi.n e3de <am_hal_uart_configure+0x16e>
|
||
|
|
e304: 4956 ldr r1, [pc, #344] ; (e460 <am_hal_uart_configure+0x1f0>)
|
||
|
|
e306: f851 1023 ldr.w r1, [r1, r3, lsl #2]
|
||
|
|
e30a: 0112 lsls r2, r2, #4
|
||
|
|
e30c: 4291 cmp r1, r2
|
||
|
|
e30e: ea4f 1381 mov.w r3, r1, lsl #6
|
||
|
|
e312: fbb1 f0f2 udiv r0, r1, r2
|
||
|
|
e316: fbb3 f3f2 udiv r3, r3, r2
|
||
|
|
e31a: eba3 1380 sub.w r3, r3, r0, lsl #6
|
||
|
|
e31e: d364 bcc.n e3ea <am_hal_uart_configure+0x17a>
|
||
|
|
e320: 089a lsrs r2, r3, #2
|
||
|
|
e322: 6260 str r0, [r4, #36] ; 0x24
|
||
|
|
e324: eb02 1200 add.w r2, r2, r0, lsl #4
|
||
|
|
e328: 6260 str r0, [r4, #36] ; 0x24
|
||
|
|
e32a: fbb1 f1f2 udiv r1, r1, r2
|
||
|
|
e32e: 62a3 str r3, [r4, #40] ; 0x28
|
||
|
|
e330: 6629 str r1, [r5, #96] ; 0x60
|
||
|
|
e332: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e334: f36f 338e bfc r3, #14, #1
|
||
|
|
e338: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e33a: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e33c: f36f 33cf bfc r3, #15, #1
|
||
|
|
e340: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e342: e9d6 0102 ldrd r0, r1, [r6, #8]
|
||
|
|
e346: 6873 ldr r3, [r6, #4]
|
||
|
|
e348: 6b22 ldr r2, [r4, #48] ; 0x30
|
||
|
|
e34a: 430b orrs r3, r1
|
||
|
|
e34c: 6931 ldr r1, [r6, #16]
|
||
|
|
e34e: 4303 orrs r3, r0
|
||
|
|
e350: 430a orrs r2, r1
|
||
|
|
e352: f043 0310 orr.w r3, r3, #16
|
||
|
|
e356: 6971 ldr r1, [r6, #20]
|
||
|
|
e358: 6322 str r2, [r4, #48] ; 0x30
|
||
|
|
e35a: 6361 str r1, [r4, #52] ; 0x34
|
||
|
|
e35c: 62e3 str r3, [r4, #44] ; 0x2c
|
||
|
|
e35e: f7ff fddf bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e362: 9003 str r0, [sp, #12]
|
||
|
|
e364: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e366: f043 0301 orr.w r3, r3, #1
|
||
|
|
e36a: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e36c: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e36e: f443 7300 orr.w r3, r3, #512 ; 0x200
|
||
|
|
e372: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e374: 8e23 ldrh r3, [r4, #48] ; 0x30
|
||
|
|
e376: f443 7380 orr.w r3, r3, #256 ; 0x100
|
||
|
|
e37a: 8623 strh r3, [r4, #48] ; 0x30
|
||
|
|
e37c: 9803 ldr r0, [sp, #12]
|
||
|
|
e37e: f7ff fdd3 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e382: 682a ldr r2, [r5, #0]
|
||
|
|
e384: 4b33 ldr r3, [pc, #204] ; (e454 <am_hal_uart_configure+0x1e4>)
|
||
|
|
e386: f022 487e bic.w r8, r2, #4261412864 ; 0xfe000000
|
||
|
|
e38a: 4598 cmp r8, r3
|
||
|
|
e38c: d11e bne.n e3cc <am_hal_uart_configure+0x15c>
|
||
|
|
e38e: 69b1 ldr r1, [r6, #24]
|
||
|
|
e390: e9d6 4708 ldrd r4, r7, [r6, #32]
|
||
|
|
e394: b109 cbz r1, e39a <am_hal_uart_configure+0x12a>
|
||
|
|
e396: 69f3 ldr r3, [r6, #28]
|
||
|
|
e398: bb5b cbnz r3, e3f2 <am_hal_uart_configure+0x182>
|
||
|
|
e39a: 6a6b ldr r3, [r5, #36] ; 0x24
|
||
|
|
e39c: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
e3a0: 331c adds r3, #28
|
||
|
|
e3a2: 031b lsls r3, r3, #12
|
||
|
|
e3a4: 2100 movs r1, #0
|
||
|
|
e3a6: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
e3a8: f885 1028 strb.w r1, [r5, #40] ; 0x28
|
||
|
|
e3ac: f022 0220 bic.w r2, r2, #32
|
||
|
|
e3b0: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
e3b2: b10c cbz r4, e3b8 <am_hal_uart_configure+0x148>
|
||
|
|
e3b4: 2f00 cmp r7, #0
|
||
|
|
e3b6: d132 bne.n e41e <am_hal_uart_configure+0x1ae>
|
||
|
|
e3b8: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
e3ba: 2000 movs r0, #0
|
||
|
|
e3bc: f022 0250 bic.w r2, r2, #80 ; 0x50
|
||
|
|
e3c0: f885 0044 strb.w r0, [r5, #68] ; 0x44
|
||
|
|
e3c4: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
e3c6: b004 add sp, #16
|
||
|
|
e3c8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
e3cc: 2000 movs r0, #0
|
||
|
|
e3ce: b004 add sp, #16
|
||
|
|
e3d0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
e3d4: f5b2 2f61 cmp.w r2, #921600 ; 0xe1000
|
||
|
|
e3d8: d985 bls.n e2e6 <am_hal_uart_configure+0x76>
|
||
|
|
e3da: 4822 ldr r0, [pc, #136] ; (e464 <am_hal_uart_configure+0x1f4>)
|
||
|
|
e3dc: e7f3 b.n e3c6 <am_hal_uart_configure+0x156>
|
||
|
|
e3de: 4822 ldr r0, [pc, #136] ; (e468 <am_hal_uart_configure+0x1f8>)
|
||
|
|
e3e0: 2300 movs r3, #0
|
||
|
|
e3e2: 662b str r3, [r5, #96] ; 0x60
|
||
|
|
e3e4: b004 add sp, #16
|
||
|
|
e3e6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
e3ea: 2300 movs r3, #0
|
||
|
|
e3ec: 481d ldr r0, [pc, #116] ; (e464 <am_hal_uart_configure+0x1f4>)
|
||
|
|
e3ee: 662b str r3, [r5, #96] ; 0x60
|
||
|
|
e3f0: e7e9 b.n e3c6 <am_hal_uart_configure+0x156>
|
||
|
|
e3f2: 2201 movs r2, #1
|
||
|
|
e3f4: f885 2028 strb.w r2, [r5, #40] ; 0x28
|
||
|
|
e3f8: f105 002c add.w r0, r5, #44 ; 0x2c
|
||
|
|
e3fc: f000 fb18 bl ea30 <am_hal_queue_init>
|
||
|
|
e400: 682b ldr r3, [r5, #0]
|
||
|
|
e402: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e406: 4543 cmp r3, r8
|
||
|
|
e408: d1e0 bne.n e3cc <am_hal_uart_configure+0x15c>
|
||
|
|
e40a: 6a6b ldr r3, [r5, #36] ; 0x24
|
||
|
|
e40c: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
e410: 331c adds r3, #28
|
||
|
|
e412: 031b lsls r3, r3, #12
|
||
|
|
e414: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
e416: f042 0220 orr.w r2, r2, #32
|
||
|
|
e41a: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
e41c: e7c9 b.n e3b2 <am_hal_uart_configure+0x142>
|
||
|
|
e41e: 2201 movs r2, #1
|
||
|
|
e420: 463b mov r3, r7
|
||
|
|
e422: f885 2044 strb.w r2, [r5, #68] ; 0x44
|
||
|
|
e426: 4621 mov r1, r4
|
||
|
|
e428: f105 0048 add.w r0, r5, #72 ; 0x48
|
||
|
|
e42c: f000 fb00 bl ea30 <am_hal_queue_init>
|
||
|
|
e430: 682b ldr r3, [r5, #0]
|
||
|
|
e432: 4a08 ldr r2, [pc, #32] ; (e454 <am_hal_uart_configure+0x1e4>)
|
||
|
|
e434: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e438: 4293 cmp r3, r2
|
||
|
|
e43a: d1c7 bne.n e3cc <am_hal_uart_configure+0x15c>
|
||
|
|
e43c: 6a6b ldr r3, [r5, #36] ; 0x24
|
||
|
|
e43e: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
e442: 331c adds r3, #28
|
||
|
|
e444: 031b lsls r3, r3, #12
|
||
|
|
e446: 2000 movs r0, #0
|
||
|
|
e448: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
e44a: f042 0250 orr.w r2, r2, #80 ; 0x50
|
||
|
|
e44e: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
e450: e7b9 b.n e3c6 <am_hal_uart_configure+0x156>
|
||
|
|
e452: bf00 nop
|
||
|
|
e454: 01ea9e06 .word 0x01ea9e06
|
||
|
|
e458: 40020000 .word 0x40020000
|
||
|
|
e45c: 0016e360 .word 0x0016e360
|
||
|
|
e460: 0000f068 .word 0x0000f068
|
||
|
|
e464: 08000003 .word 0x08000003
|
||
|
|
e468: 08000002 .word 0x08000002
|
||
|
|
|
||
|
|
0000e46c <am_hal_uart_transfer>:
|
||
|
|
e46c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
||
|
|
e470: ed2d 8b02 vpush {d8}
|
||
|
|
e474: 680d ldr r5, [r1, #0]
|
||
|
|
e476: b091 sub sp, #68 ; 0x44
|
||
|
|
e478: 4604 mov r4, r0
|
||
|
|
e47a: b14d cbz r5, e490 <am_hal_uart_transfer+0x24>
|
||
|
|
e47c: 2d01 cmp r5, #1
|
||
|
|
e47e: f000 8091 beq.w e5a4 <am_hal_uart_transfer+0x138>
|
||
|
|
e482: 2507 movs r5, #7
|
||
|
|
e484: 4628 mov r0, r5
|
||
|
|
e486: b011 add sp, #68 ; 0x44
|
||
|
|
e488: ecbd 8b02 vpop {d8}
|
||
|
|
e48c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
||
|
|
e490: f8d1 900c ldr.w r9, [r1, #12]
|
||
|
|
e494: 684b ldr r3, [r1, #4]
|
||
|
|
e496: 690a ldr r2, [r1, #16]
|
||
|
|
e498: 688e ldr r6, [r1, #8]
|
||
|
|
e49a: 9301 str r3, [sp, #4]
|
||
|
|
e49c: 9203 str r2, [sp, #12]
|
||
|
|
e49e: f1b9 0f00 cmp.w r9, #0
|
||
|
|
e4a2: f000 8113 beq.w e6cc <am_hal_uart_transfer+0x260>
|
||
|
|
e4a6: 2e00 cmp r6, #0
|
||
|
|
e4a8: f000 8179 beq.w e79e <am_hal_uart_transfer+0x332>
|
||
|
|
e4ac: 2800 cmp r0, #0
|
||
|
|
e4ae: f000 8168 beq.w e782 <am_hal_uart_transfer+0x316>
|
||
|
|
e4b2: 46aa mov sl, r5
|
||
|
|
e4b4: 462f mov r7, r5
|
||
|
|
e4b6: 9502 str r5, [sp, #8]
|
||
|
|
e4b8: 4605 mov r5, r0
|
||
|
|
e4ba: 4619 mov r1, r3
|
||
|
|
e4bc: 682a ldr r2, [r5, #0]
|
||
|
|
e4be: 4bb4 ldr r3, [pc, #720] ; (e790 <am_hal_uart_transfer+0x324>)
|
||
|
|
e4c0: f022 427e bic.w r2, r2, #4261412864 ; 0xfe000000
|
||
|
|
e4c4: 429a cmp r2, r3
|
||
|
|
e4c6: d12f bne.n e528 <am_hal_uart_transfer+0xbc>
|
||
|
|
e4c8: f895 2028 ldrb.w r2, [r5, #40] ; 0x28
|
||
|
|
e4cc: 2a00 cmp r2, #0
|
||
|
|
e4ce: d133 bne.n e538 <am_hal_uart_transfer+0xcc>
|
||
|
|
e4d0: 6a68 ldr r0, [r5, #36] ; 0x24
|
||
|
|
e4d2: f500 2080 add.w r0, r0, #262144 ; 0x40000
|
||
|
|
e4d6: 301c adds r0, #28
|
||
|
|
e4d8: 3901 subs r1, #1
|
||
|
|
e4da: 0300 lsls r0, r0, #12
|
||
|
|
e4dc: e005 b.n e4ea <am_hal_uart_transfer+0x7e>
|
||
|
|
e4de: 3201 adds r2, #1
|
||
|
|
e4e0: f811 3f01 ldrb.w r3, [r1, #1]!
|
||
|
|
e4e4: 6003 str r3, [r0, #0]
|
||
|
|
e4e6: 42b2 cmp r2, r6
|
||
|
|
e4e8: d023 beq.n e532 <am_hal_uart_transfer+0xc6>
|
||
|
|
e4ea: 6983 ldr r3, [r0, #24]
|
||
|
|
e4ec: 069c lsls r4, r3, #26
|
||
|
|
e4ee: d5f6 bpl.n e4de <am_hal_uart_transfer+0x72>
|
||
|
|
e4f0: 4417 add r7, r2
|
||
|
|
e4f2: 1ab6 subs r6, r6, r2
|
||
|
|
e4f4: b936 cbnz r6, e504 <am_hal_uart_transfer+0x98>
|
||
|
|
e4f6: 9d02 ldr r5, [sp, #8]
|
||
|
|
e4f8: 9b03 ldr r3, [sp, #12]
|
||
|
|
e4fa: 2b00 cmp r3, #0
|
||
|
|
e4fc: f000 808d beq.w e61a <am_hal_uart_transfer+0x1ae>
|
||
|
|
e500: 601f str r7, [r3, #0]
|
||
|
|
e502: e7bf b.n e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e504: 2010 movs r0, #16
|
||
|
|
e506: f7ff fb0f bl db28 <am_hal_flash_delay>
|
||
|
|
e50a: f1b9 3fff cmp.w r9, #4294967295 ; 0xffffffff
|
||
|
|
e50e: bf18 it ne
|
||
|
|
e510: f10a 0a01 addne.w sl, sl, #1
|
||
|
|
e514: 45d1 cmp r9, sl
|
||
|
|
e516: d9ee bls.n e4f6 <am_hal_uart_transfer+0x8a>
|
||
|
|
e518: 9b01 ldr r3, [sp, #4]
|
||
|
|
e51a: 682a ldr r2, [r5, #0]
|
||
|
|
e51c: 19d9 adds r1, r3, r7
|
||
|
|
e51e: 4b9c ldr r3, [pc, #624] ; (e790 <am_hal_uart_transfer+0x324>)
|
||
|
|
e520: f022 427e bic.w r2, r2, #4261412864 ; 0xfe000000
|
||
|
|
e524: 429a cmp r2, r3
|
||
|
|
e526: d0cf beq.n e4c8 <am_hal_uart_transfer+0x5c>
|
||
|
|
e528: 9b03 ldr r3, [sp, #12]
|
||
|
|
e52a: b103 cbz r3, e52e <am_hal_uart_transfer+0xc2>
|
||
|
|
e52c: 601f str r7, [r3, #0]
|
||
|
|
e52e: 2502 movs r5, #2
|
||
|
|
e530: e7a8 b.n e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e532: 9d02 ldr r5, [sp, #8]
|
||
|
|
e534: 4417 add r7, r2
|
||
|
|
e536: e7df b.n e4f8 <am_hal_uart_transfer+0x8c>
|
||
|
|
e538: e9d5 020d ldrd r0, r2, [r5, #52] ; 0x34
|
||
|
|
e53c: eba2 0b00 sub.w fp, r2, r0
|
||
|
|
e540: 45b3 cmp fp, r6
|
||
|
|
e542: bf28 it cs
|
||
|
|
e544: 46b3 movcs fp, r6
|
||
|
|
e546: f105 042c add.w r4, r5, #44 ; 0x2c
|
||
|
|
e54a: 465a mov r2, fp
|
||
|
|
e54c: 4620 mov r0, r4
|
||
|
|
e54e: f000 fa7b bl ea48 <am_hal_queue_item_add>
|
||
|
|
e552: f8d5 8024 ldr.w r8, [r5, #36] ; 0x24
|
||
|
|
e556: f7ff fce3 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e55a: f508 2880 add.w r8, r8, #262144 ; 0x40000
|
||
|
|
e55e: f108 081c add.w r8, r8, #28
|
||
|
|
e562: ea4f 3808 mov.w r8, r8, lsl #12
|
||
|
|
e566: 9008 str r0, [sp, #32]
|
||
|
|
e568: e00d b.n e586 <am_hal_uart_transfer+0x11a>
|
||
|
|
e56a: f000 faab bl eac4 <am_hal_queue_item_get>
|
||
|
|
e56e: b190 cbz r0, e596 <am_hal_uart_transfer+0x12a>
|
||
|
|
e570: 6a6b ldr r3, [r5, #36] ; 0x24
|
||
|
|
e572: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
e576: 331c adds r3, #28
|
||
|
|
e578: 031b lsls r3, r3, #12
|
||
|
|
e57a: 699a ldr r2, [r3, #24]
|
||
|
|
e57c: 0692 lsls r2, r2, #26
|
||
|
|
e57e: bf5c itt pl
|
||
|
|
e580: f89d 201c ldrbpl.w r2, [sp, #28]
|
||
|
|
e584: 601a strpl r2, [r3, #0]
|
||
|
|
e586: f8d8 3018 ldr.w r3, [r8, #24]
|
||
|
|
e58a: 069b lsls r3, r3, #26
|
||
|
|
e58c: f04f 0201 mov.w r2, #1
|
||
|
|
e590: a907 add r1, sp, #28
|
||
|
|
e592: 4620 mov r0, r4
|
||
|
|
e594: d5e9 bpl.n e56a <am_hal_uart_transfer+0xfe>
|
||
|
|
e596: 9808 ldr r0, [sp, #32]
|
||
|
|
e598: 445f add r7, fp
|
||
|
|
e59a: eba6 060b sub.w r6, r6, fp
|
||
|
|
e59e: f7ff fcc3 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e5a2: e7a7 b.n e4f4 <am_hal_uart_transfer+0x88>
|
||
|
|
e5a4: 68cd ldr r5, [r1, #12]
|
||
|
|
e5a6: 690b ldr r3, [r1, #16]
|
||
|
|
e5a8: 9301 str r3, [sp, #4]
|
||
|
|
e5aa: e9d1 b701 ldrd fp, r7, [r1, #4]
|
||
|
|
e5ae: 2d00 cmp r5, #0
|
||
|
|
e5b0: f000 80b8 beq.w e724 <am_hal_uart_transfer+0x2b8>
|
||
|
|
e5b4: 2f00 cmp r7, #0
|
||
|
|
e5b6: f000 8123 beq.w e800 <am_hal_uart_transfer+0x394>
|
||
|
|
e5ba: 2800 cmp r0, #0
|
||
|
|
e5bc: f000 80ec beq.w e798 <am_hal_uart_transfer+0x32c>
|
||
|
|
e5c0: 6822 ldr r2, [r4, #0]
|
||
|
|
e5c2: f8df a1cc ldr.w sl, [pc, #460] ; e790 <am_hal_uart_transfer+0x324>
|
||
|
|
e5c6: f022 427e bic.w r2, r2, #4261412864 ; 0xfe000000
|
||
|
|
e5ca: f04f 0900 mov.w r9, #0
|
||
|
|
e5ce: f100 0348 add.w r3, r0, #72 ; 0x48
|
||
|
|
e5d2: 4552 cmp r2, sl
|
||
|
|
e5d4: ee08 3a10 vmov s16, r3
|
||
|
|
e5d8: 46c8 mov r8, r9
|
||
|
|
e5da: 465e mov r6, fp
|
||
|
|
e5dc: d134 bne.n e648 <am_hal_uart_transfer+0x1dc>
|
||
|
|
e5de: f894 2044 ldrb.w r2, [r4, #68] ; 0x44
|
||
|
|
e5e2: 2a00 cmp r2, #0
|
||
|
|
e5e4: d138 bne.n e658 <am_hal_uart_transfer+0x1ec>
|
||
|
|
e5e6: 6a61 ldr r1, [r4, #36] ; 0x24
|
||
|
|
e5e8: f501 2180 add.w r1, r1, #262144 ; 0x40000
|
||
|
|
e5ec: 311c adds r1, #28
|
||
|
|
e5ee: 1e73 subs r3, r6, #1
|
||
|
|
e5f0: 0309 lsls r1, r1, #12
|
||
|
|
e5f2: e008 b.n e606 <am_hal_uart_transfer+0x19a>
|
||
|
|
e5f4: 6808 ldr r0, [r1, #0]
|
||
|
|
e5f6: f410 6f70 tst.w r0, #3840 ; 0xf00
|
||
|
|
e5fa: d163 bne.n e6c4 <am_hal_uart_transfer+0x258>
|
||
|
|
e5fc: 3201 adds r2, #1
|
||
|
|
e5fe: 42ba cmp r2, r7
|
||
|
|
e600: f803 0f01 strb.w r0, [r3, #1]!
|
||
|
|
e604: d056 beq.n e6b4 <am_hal_uart_transfer+0x248>
|
||
|
|
e606: 6988 ldr r0, [r1, #24]
|
||
|
|
e608: 06c0 lsls r0, r0, #27
|
||
|
|
e60a: d5f3 bpl.n e5f4 <am_hal_uart_transfer+0x188>
|
||
|
|
e60c: 4490 add r8, r2
|
||
|
|
e60e: 1abf subs r7, r7, r2
|
||
|
|
e610: b957 cbnz r7, e628 <am_hal_uart_transfer+0x1bc>
|
||
|
|
e612: 9b01 ldr r3, [sp, #4]
|
||
|
|
e614: b10b cbz r3, e61a <am_hal_uart_transfer+0x1ae>
|
||
|
|
e616: f8c3 8000 str.w r8, [r3]
|
||
|
|
e61a: 2500 movs r5, #0
|
||
|
|
e61c: 4628 mov r0, r5
|
||
|
|
e61e: b011 add sp, #68 ; 0x44
|
||
|
|
e620: ecbd 8b02 vpop {d8}
|
||
|
|
e624: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
||
|
|
e628: 2010 movs r0, #16
|
||
|
|
e62a: f7ff fa7d bl db28 <am_hal_flash_delay>
|
||
|
|
e62e: 1c6b adds r3, r5, #1
|
||
|
|
e630: bf18 it ne
|
||
|
|
e632: f109 0901 addne.w r9, r9, #1
|
||
|
|
e636: 454d cmp r5, r9
|
||
|
|
e638: d9eb bls.n e612 <am_hal_uart_transfer+0x1a6>
|
||
|
|
e63a: 6822 ldr r2, [r4, #0]
|
||
|
|
e63c: f022 427e bic.w r2, r2, #4261412864 ; 0xfe000000
|
||
|
|
e640: 4552 cmp r2, sl
|
||
|
|
e642: eb0b 0608 add.w r6, fp, r8
|
||
|
|
e646: d0ca beq.n e5de <am_hal_uart_transfer+0x172>
|
||
|
|
e648: 2502 movs r5, #2
|
||
|
|
e64a: 9b01 ldr r3, [sp, #4]
|
||
|
|
e64c: 2b00 cmp r3, #0
|
||
|
|
e64e: f43f af19 beq.w e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e652: f8c3 8000 str.w r8, [r3]
|
||
|
|
e656: e715 b.n e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e658: f7ff fc62 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e65c: 6a62 ldr r2, [r4, #36] ; 0x24
|
||
|
|
e65e: 9007 str r0, [sp, #28]
|
||
|
|
e660: f502 2280 add.w r2, r2, #262144 ; 0x40000
|
||
|
|
e664: 321c adds r2, #28
|
||
|
|
e666: 0310 lsls r0, r2, #12
|
||
|
|
e668: f10d 0c20 add.w ip, sp, #32
|
||
|
|
e66c: 2200 movs r2, #0
|
||
|
|
e66e: 6983 ldr r3, [r0, #24]
|
||
|
|
e670: 06db lsls r3, r3, #27
|
||
|
|
e672: d409 bmi.n e688 <am_hal_uart_transfer+0x21c>
|
||
|
|
e674: 6803 ldr r3, [r0, #0]
|
||
|
|
e676: f413 6f70 tst.w r3, #3840 ; 0xf00
|
||
|
|
e67a: f102 0201 add.w r2, r2, #1
|
||
|
|
e67e: d11b bne.n e6b8 <am_hal_uart_transfer+0x24c>
|
||
|
|
e680: 2a20 cmp r2, #32
|
||
|
|
e682: f80c 3b01 strb.w r3, [ip], #1
|
||
|
|
e686: d1f2 bne.n e66e <am_hal_uart_transfer+0x202>
|
||
|
|
e688: ee18 0a10 vmov r0, s16
|
||
|
|
e68c: a908 add r1, sp, #32
|
||
|
|
e68e: f000 f9db bl ea48 <am_hal_queue_item_add>
|
||
|
|
e692: 2800 cmp r0, #0
|
||
|
|
e694: d077 beq.n e786 <am_hal_uart_transfer+0x31a>
|
||
|
|
e696: 9807 ldr r0, [sp, #28]
|
||
|
|
e698: f7ff fc46 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e69c: 6d22 ldr r2, [r4, #80] ; 0x50
|
||
|
|
e69e: 42ba cmp r2, r7
|
||
|
|
e6a0: bf28 it cs
|
||
|
|
e6a2: 463a movcs r2, r7
|
||
|
|
e6a4: ee18 0a10 vmov r0, s16
|
||
|
|
e6a8: 4631 mov r1, r6
|
||
|
|
e6aa: 4490 add r8, r2
|
||
|
|
e6ac: 1abf subs r7, r7, r2
|
||
|
|
e6ae: f000 fa09 bl eac4 <am_hal_queue_item_get>
|
||
|
|
e6b2: e7ad b.n e610 <am_hal_uart_transfer+0x1a4>
|
||
|
|
e6b4: 4490 add r8, r2
|
||
|
|
e6b6: e7ac b.n e612 <am_hal_uart_transfer+0x1a6>
|
||
|
|
e6b8: 9807 ldr r0, [sp, #28]
|
||
|
|
e6ba: f7ff fc35 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e6be: f04f 6500 mov.w r5, #134217728 ; 0x8000000
|
||
|
|
e6c2: e7c2 b.n e64a <am_hal_uart_transfer+0x1de>
|
||
|
|
e6c4: 4490 add r8, r2
|
||
|
|
e6c6: f04f 6500 mov.w r5, #134217728 ; 0x8000000
|
||
|
|
e6ca: e7be b.n e64a <am_hal_uart_transfer+0x1de>
|
||
|
|
e6cc: 2800 cmp r0, #0
|
||
|
|
e6ce: f43f af2e beq.w e52e <am_hal_uart_transfer+0xc2>
|
||
|
|
e6d2: 6803 ldr r3, [r0, #0]
|
||
|
|
e6d4: 4a2e ldr r2, [pc, #184] ; (e790 <am_hal_uart_transfer+0x324>)
|
||
|
|
e6d6: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e6da: 4293 cmp r3, r2
|
||
|
|
e6dc: f47f af27 bne.w e52e <am_hal_uart_transfer+0xc2>
|
||
|
|
e6e0: 9b03 ldr r3, [sp, #12]
|
||
|
|
e6e2: b10b cbz r3, e6e8 <am_hal_uart_transfer+0x27c>
|
||
|
|
e6e4: f8c3 9000 str.w r9, [r3]
|
||
|
|
e6e8: 2e00 cmp r6, #0
|
||
|
|
e6ea: d096 beq.n e61a <am_hal_uart_transfer+0x1ae>
|
||
|
|
e6ec: f894 5028 ldrb.w r5, [r4, #40] ; 0x28
|
||
|
|
e6f0: 2d00 cmp r5, #0
|
||
|
|
e6f2: d156 bne.n e7a2 <am_hal_uart_transfer+0x336>
|
||
|
|
e6f4: 6a62 ldr r2, [r4, #36] ; 0x24
|
||
|
|
e6f6: 9b01 ldr r3, [sp, #4]
|
||
|
|
e6f8: f502 2280 add.w r2, r2, #262144 ; 0x40000
|
||
|
|
e6fc: 321c adds r2, #28
|
||
|
|
e6fe: 0312 lsls r2, r2, #12
|
||
|
|
e700: 3b01 subs r3, #1
|
||
|
|
e702: e005 b.n e710 <am_hal_uart_transfer+0x2a4>
|
||
|
|
e704: 3501 adds r5, #1
|
||
|
|
e706: f813 1f01 ldrb.w r1, [r3, #1]!
|
||
|
|
e70a: 6011 str r1, [r2, #0]
|
||
|
|
e70c: 42ae cmp r6, r5
|
||
|
|
e70e: d002 beq.n e716 <am_hal_uart_transfer+0x2aa>
|
||
|
|
e710: 6991 ldr r1, [r2, #24]
|
||
|
|
e712: 0689 lsls r1, r1, #26
|
||
|
|
e714: d5f6 bpl.n e704 <am_hal_uart_transfer+0x298>
|
||
|
|
e716: 9b03 ldr r3, [sp, #12]
|
||
|
|
e718: 2b00 cmp r3, #0
|
||
|
|
e71a: f43f af7e beq.w e61a <am_hal_uart_transfer+0x1ae>
|
||
|
|
e71e: 601d str r5, [r3, #0]
|
||
|
|
e720: 2500 movs r5, #0
|
||
|
|
e722: e6af b.n e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e724: 2800 cmp r0, #0
|
||
|
|
e726: f43f af02 beq.w e52e <am_hal_uart_transfer+0xc2>
|
||
|
|
e72a: 6802 ldr r2, [r0, #0]
|
||
|
|
e72c: 4918 ldr r1, [pc, #96] ; (e790 <am_hal_uart_transfer+0x324>)
|
||
|
|
e72e: f022 427e bic.w r2, r2, #4261412864 ; 0xfe000000
|
||
|
|
e732: 428a cmp r2, r1
|
||
|
|
e734: f47f aefb bne.w e52e <am_hal_uart_transfer+0xc2>
|
||
|
|
e738: b103 cbz r3, e73c <am_hal_uart_transfer+0x2d0>
|
||
|
|
e73a: 601d str r5, [r3, #0]
|
||
|
|
e73c: 2f00 cmp r7, #0
|
||
|
|
e73e: f43f af6c beq.w e61a <am_hal_uart_transfer+0x1ae>
|
||
|
|
e742: f894 2044 ldrb.w r2, [r4, #68] ; 0x44
|
||
|
|
e746: 2a00 cmp r2, #0
|
||
|
|
e748: d15c bne.n e804 <am_hal_uart_transfer+0x398>
|
||
|
|
e74a: 6a60 ldr r0, [r4, #36] ; 0x24
|
||
|
|
e74c: f500 2080 add.w r0, r0, #262144 ; 0x40000
|
||
|
|
e750: 301c adds r0, #28
|
||
|
|
e752: 0300 lsls r0, r0, #12
|
||
|
|
e754: f10b 33ff add.w r3, fp, #4294967295 ; 0xffffffff
|
||
|
|
e758: 4614 mov r4, r2
|
||
|
|
e75a: e009 b.n e770 <am_hal_uart_transfer+0x304>
|
||
|
|
e75c: 6801 ldr r1, [r0, #0]
|
||
|
|
e75e: f411 6270 ands.w r2, r1, #3840 ; 0xf00
|
||
|
|
e762: f040 8080 bne.w e866 <am_hal_uart_transfer+0x3fa>
|
||
|
|
e766: 3401 adds r4, #1
|
||
|
|
e768: 42a7 cmp r7, r4
|
||
|
|
e76a: f803 1f01 strb.w r1, [r3, #1]!
|
||
|
|
e76e: d07d beq.n e86c <am_hal_uart_transfer+0x400>
|
||
|
|
e770: 6982 ldr r2, [r0, #24]
|
||
|
|
e772: 06d2 lsls r2, r2, #27
|
||
|
|
e774: d5f2 bpl.n e75c <am_hal_uart_transfer+0x2f0>
|
||
|
|
e776: 9b01 ldr r3, [sp, #4]
|
||
|
|
e778: 2b00 cmp r3, #0
|
||
|
|
e77a: f43f ae83 beq.w e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e77e: 601c str r4, [r3, #0]
|
||
|
|
e780: e680 b.n e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e782: 4607 mov r7, r0
|
||
|
|
e784: e6d0 b.n e528 <am_hal_uart_transfer+0xbc>
|
||
|
|
e786: 9807 ldr r0, [sp, #28]
|
||
|
|
e788: 4d02 ldr r5, [pc, #8] ; (e794 <am_hal_uart_transfer+0x328>)
|
||
|
|
e78a: f7ff fbcd bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e78e: e75c b.n e64a <am_hal_uart_transfer+0x1de>
|
||
|
|
e790: 01ea9e06 .word 0x01ea9e06
|
||
|
|
e794: 08000001 .word 0x08000001
|
||
|
|
e798: 4680 mov r8, r0
|
||
|
|
e79a: 2502 movs r5, #2
|
||
|
|
e79c: e755 b.n e64a <am_hal_uart_transfer+0x1de>
|
||
|
|
e79e: 462f mov r7, r5
|
||
|
|
e7a0: e6aa b.n e4f8 <am_hal_uart_transfer+0x8c>
|
||
|
|
e7a2: e9d4 530d ldrd r5, r3, [r4, #52] ; 0x34
|
||
|
|
e7a6: 1b5d subs r5, r3, r5
|
||
|
|
e7a8: 42b5 cmp r5, r6
|
||
|
|
e7aa: bf28 it cs
|
||
|
|
e7ac: 4635 movcs r5, r6
|
||
|
|
e7ae: f104 072c add.w r7, r4, #44 ; 0x2c
|
||
|
|
e7b2: 9901 ldr r1, [sp, #4]
|
||
|
|
e7b4: 462a mov r2, r5
|
||
|
|
e7b6: 4638 mov r0, r7
|
||
|
|
e7b8: f000 f946 bl ea48 <am_hal_queue_item_add>
|
||
|
|
e7bc: 6a66 ldr r6, [r4, #36] ; 0x24
|
||
|
|
e7be: f7ff fbaf bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e7c2: f506 2680 add.w r6, r6, #262144 ; 0x40000
|
||
|
|
e7c6: 361c adds r6, #28
|
||
|
|
e7c8: 0336 lsls r6, r6, #12
|
||
|
|
e7ca: 9005 str r0, [sp, #20]
|
||
|
|
e7cc: e00d b.n e7ea <am_hal_uart_transfer+0x37e>
|
||
|
|
e7ce: f000 f979 bl eac4 <am_hal_queue_item_get>
|
||
|
|
e7d2: b188 cbz r0, e7f8 <am_hal_uart_transfer+0x38c>
|
||
|
|
e7d4: 6a62 ldr r2, [r4, #36] ; 0x24
|
||
|
|
e7d6: f502 2280 add.w r2, r2, #262144 ; 0x40000
|
||
|
|
e7da: 321c adds r2, #28
|
||
|
|
e7dc: 0312 lsls r2, r2, #12
|
||
|
|
e7de: 6993 ldr r3, [r2, #24]
|
||
|
|
e7e0: 0699 lsls r1, r3, #26
|
||
|
|
e7e2: bf5c itt pl
|
||
|
|
e7e4: f89d 3020 ldrbpl.w r3, [sp, #32]
|
||
|
|
e7e8: 6013 strpl r3, [r2, #0]
|
||
|
|
e7ea: 69b3 ldr r3, [r6, #24]
|
||
|
|
e7ec: 069b lsls r3, r3, #26
|
||
|
|
e7ee: f04f 0201 mov.w r2, #1
|
||
|
|
e7f2: a908 add r1, sp, #32
|
||
|
|
e7f4: 4638 mov r0, r7
|
||
|
|
e7f6: d5ea bpl.n e7ce <am_hal_uart_transfer+0x362>
|
||
|
|
e7f8: 9805 ldr r0, [sp, #20]
|
||
|
|
e7fa: f7ff fb95 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e7fe: e78a b.n e716 <am_hal_uart_transfer+0x2aa>
|
||
|
|
e800: 46b8 mov r8, r7
|
||
|
|
e802: e706 b.n e612 <am_hal_uart_transfer+0x1a6>
|
||
|
|
e804: f7ff fb8c bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e808: 6a62 ldr r2, [r4, #36] ; 0x24
|
||
|
|
e80a: 9006 str r0, [sp, #24]
|
||
|
|
e80c: f502 2280 add.w r2, r2, #262144 ; 0x40000
|
||
|
|
e810: 321c adds r2, #28
|
||
|
|
e812: 0310 lsls r0, r2, #12
|
||
|
|
e814: ae08 add r6, sp, #32
|
||
|
|
e816: 2200 movs r2, #0
|
||
|
|
e818: 6983 ldr r3, [r0, #24]
|
||
|
|
e81a: 06d9 lsls r1, r3, #27
|
||
|
|
e81c: d409 bmi.n e832 <am_hal_uart_transfer+0x3c6>
|
||
|
|
e81e: 6803 ldr r3, [r0, #0]
|
||
|
|
e820: f413 6f70 tst.w r3, #3840 ; 0xf00
|
||
|
|
e824: f102 0201 add.w r2, r2, #1
|
||
|
|
e828: d117 bne.n e85a <am_hal_uart_transfer+0x3ee>
|
||
|
|
e82a: 2a20 cmp r2, #32
|
||
|
|
e82c: f806 3b01 strb.w r3, [r6], #1
|
||
|
|
e830: d1f2 bne.n e818 <am_hal_uart_transfer+0x3ac>
|
||
|
|
e832: f104 0648 add.w r6, r4, #72 ; 0x48
|
||
|
|
e836: a908 add r1, sp, #32
|
||
|
|
e838: 4630 mov r0, r6
|
||
|
|
e83a: f000 f905 bl ea48 <am_hal_queue_item_add>
|
||
|
|
e83e: b1b8 cbz r0, e870 <am_hal_uart_transfer+0x404>
|
||
|
|
e840: 9806 ldr r0, [sp, #24]
|
||
|
|
e842: f7ff fb71 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e846: 6d24 ldr r4, [r4, #80] ; 0x50
|
||
|
|
e848: 42bc cmp r4, r7
|
||
|
|
e84a: bf28 it cs
|
||
|
|
e84c: 463c movcs r4, r7
|
||
|
|
e84e: 4659 mov r1, fp
|
||
|
|
e850: 4630 mov r0, r6
|
||
|
|
e852: 4622 mov r2, r4
|
||
|
|
e854: f000 f936 bl eac4 <am_hal_queue_item_get>
|
||
|
|
e858: e78d b.n e776 <am_hal_uart_transfer+0x30a>
|
||
|
|
e85a: 9806 ldr r0, [sp, #24]
|
||
|
|
e85c: f7ff fb64 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e860: f04f 6500 mov.w r5, #134217728 ; 0x8000000
|
||
|
|
e864: e60e b.n e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e866: f04f 6500 mov.w r5, #134217728 ; 0x8000000
|
||
|
|
e86a: e784 b.n e776 <am_hal_uart_transfer+0x30a>
|
||
|
|
e86c: 4615 mov r5, r2
|
||
|
|
e86e: e782 b.n e776 <am_hal_uart_transfer+0x30a>
|
||
|
|
e870: 9806 ldr r0, [sp, #24]
|
||
|
|
e872: 4d02 ldr r5, [pc, #8] ; (e87c <am_hal_uart_transfer+0x410>)
|
||
|
|
e874: f7ff fb58 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e878: e604 b.n e484 <am_hal_uart_transfer+0x18>
|
||
|
|
e87a: bf00 nop
|
||
|
|
e87c: 08000001 .word 0x08000001
|
||
|
|
|
||
|
|
0000e880 <am_hal_uart_interrupt_service>:
|
||
|
|
e880: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
||
|
|
e884: 4604 mov r4, r0
|
||
|
|
e886: 4847 ldr r0, [pc, #284] ; (e9a4 <am_hal_uart_interrupt_service+0x124>)
|
||
|
|
e888: 6823 ldr r3, [r4, #0]
|
||
|
|
e88a: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e88e: 4283 cmp r3, r0
|
||
|
|
e890: b08a sub sp, #40 ; 0x28
|
||
|
|
e892: d124 bne.n e8de <am_hal_uart_interrupt_service+0x5e>
|
||
|
|
e894: f011 0f50 tst.w r1, #80 ; 0x50
|
||
|
|
e898: 6a67 ldr r7, [r4, #36] ; 0x24
|
||
|
|
e89a: 460d mov r5, r1
|
||
|
|
e89c: 4616 mov r6, r2
|
||
|
|
e89e: d002 beq.n e8a6 <am_hal_uart_interrupt_service+0x26>
|
||
|
|
e8a0: f894 3044 ldrb.w r3, [r4, #68] ; 0x44
|
||
|
|
e8a4: bb63 cbnz r3, e900 <am_hal_uart_interrupt_service+0x80>
|
||
|
|
e8a6: 06a9 lsls r1, r5, #26
|
||
|
|
e8a8: d409 bmi.n e8be <am_hal_uart_interrupt_service+0x3e>
|
||
|
|
e8aa: b126 cbz r6, e8b6 <am_hal_uart_interrupt_service+0x36>
|
||
|
|
e8ac: f894 3028 ldrb.w r3, [r4, #40] ; 0x28
|
||
|
|
e8b0: b15b cbz r3, e8ca <am_hal_uart_interrupt_service+0x4a>
|
||
|
|
e8b2: 6b63 ldr r3, [r4, #52] ; 0x34
|
||
|
|
e8b4: b1bb cbz r3, e8e6 <am_hal_uart_interrupt_service+0x66>
|
||
|
|
e8b6: 2000 movs r0, #0
|
||
|
|
e8b8: b00a add sp, #40 ; 0x28
|
||
|
|
e8ba: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
e8be: f894 3028 ldrb.w r3, [r4, #40] ; 0x28
|
||
|
|
e8c2: 2b00 cmp r3, #0
|
||
|
|
e8c4: d13d bne.n e942 <am_hal_uart_interrupt_service+0xc2>
|
||
|
|
e8c6: 2e00 cmp r6, #0
|
||
|
|
e8c8: d0f5 beq.n e8b6 <am_hal_uart_interrupt_service+0x36>
|
||
|
|
e8ca: f507 2780 add.w r7, r7, #262144 ; 0x40000
|
||
|
|
e8ce: 371c adds r7, #28
|
||
|
|
e8d0: 033f lsls r7, r7, #12
|
||
|
|
e8d2: 69bb ldr r3, [r7, #24]
|
||
|
|
e8d4: 071b lsls r3, r3, #28
|
||
|
|
e8d6: d40e bmi.n e8f6 <am_hal_uart_interrupt_service+0x76>
|
||
|
|
e8d8: 2301 movs r3, #1
|
||
|
|
e8da: 6033 str r3, [r6, #0]
|
||
|
|
e8dc: e7eb b.n e8b6 <am_hal_uart_interrupt_service+0x36>
|
||
|
|
e8de: 2002 movs r0, #2
|
||
|
|
e8e0: b00a add sp, #40 ; 0x28
|
||
|
|
e8e2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
e8e6: f507 2780 add.w r7, r7, #262144 ; 0x40000
|
||
|
|
e8ea: 371c adds r7, #28
|
||
|
|
e8ec: 033f lsls r7, r7, #12
|
||
|
|
e8ee: 69bb ldr r3, [r7, #24]
|
||
|
|
e8f0: 071a lsls r2, r3, #28
|
||
|
|
e8f2: d4e0 bmi.n e8b6 <am_hal_uart_interrupt_service+0x36>
|
||
|
|
e8f4: e7f0 b.n e8d8 <am_hal_uart_interrupt_service+0x58>
|
||
|
|
e8f6: 2000 movs r0, #0
|
||
|
|
e8f8: 6030 str r0, [r6, #0]
|
||
|
|
e8fa: b00a add sp, #40 ; 0x28
|
||
|
|
e8fc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
||
|
|
e900: f7ff fb0e bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e904: 6a61 ldr r1, [r4, #36] ; 0x24
|
||
|
|
e906: 9001 str r0, [sp, #4]
|
||
|
|
e908: f501 2180 add.w r1, r1, #262144 ; 0x40000
|
||
|
|
e90c: 311c adds r1, #28
|
||
|
|
e90e: 0309 lsls r1, r1, #12
|
||
|
|
e910: a802 add r0, sp, #8
|
||
|
|
e912: 2200 movs r2, #0
|
||
|
|
e914: 698b ldr r3, [r1, #24]
|
||
|
|
e916: 06db lsls r3, r3, #27
|
||
|
|
e918: d409 bmi.n e92e <am_hal_uart_interrupt_service+0xae>
|
||
|
|
e91a: 680b ldr r3, [r1, #0]
|
||
|
|
e91c: f413 6f70 tst.w r3, #3840 ; 0xf00
|
||
|
|
e920: f102 0201 add.w r2, r2, #1
|
||
|
|
e924: d132 bne.n e98c <am_hal_uart_interrupt_service+0x10c>
|
||
|
|
e926: 2a20 cmp r2, #32
|
||
|
|
e928: f800 3b01 strb.w r3, [r0], #1
|
||
|
|
e92c: d1f2 bne.n e914 <am_hal_uart_interrupt_service+0x94>
|
||
|
|
e92e: a902 add r1, sp, #8
|
||
|
|
e930: f104 0048 add.w r0, r4, #72 ; 0x48
|
||
|
|
e934: f000 f888 bl ea48 <am_hal_queue_item_add>
|
||
|
|
e938: b370 cbz r0, e998 <am_hal_uart_interrupt_service+0x118>
|
||
|
|
e93a: 9801 ldr r0, [sp, #4]
|
||
|
|
e93c: f7ff faf4 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e940: e7b1 b.n e8a6 <am_hal_uart_interrupt_service+0x26>
|
||
|
|
e942: 6a65 ldr r5, [r4, #36] ; 0x24
|
||
|
|
e944: f7ff faec bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
e948: f505 2580 add.w r5, r5, #262144 ; 0x40000
|
||
|
|
e94c: 351c adds r5, #28
|
||
|
|
e94e: 032d lsls r5, r5, #12
|
||
|
|
e950: 9002 str r0, [sp, #8]
|
||
|
|
e952: f104 082c add.w r8, r4, #44 ; 0x2c
|
||
|
|
e956: e00d b.n e974 <am_hal_uart_interrupt_service+0xf4>
|
||
|
|
e958: f000 f8b4 bl eac4 <am_hal_queue_item_get>
|
||
|
|
e95c: b190 cbz r0, e984 <am_hal_uart_interrupt_service+0x104>
|
||
|
|
e95e: 6a63 ldr r3, [r4, #36] ; 0x24
|
||
|
|
e960: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
e964: 331c adds r3, #28
|
||
|
|
e966: 031b lsls r3, r3, #12
|
||
|
|
e968: 699a ldr r2, [r3, #24]
|
||
|
|
e96a: 0692 lsls r2, r2, #26
|
||
|
|
e96c: bf5c itt pl
|
||
|
|
e96e: f89d 2003 ldrbpl.w r2, [sp, #3]
|
||
|
|
e972: 601a strpl r2, [r3, #0]
|
||
|
|
e974: 69ab ldr r3, [r5, #24]
|
||
|
|
e976: 069b lsls r3, r3, #26
|
||
|
|
e978: f04f 0201 mov.w r2, #1
|
||
|
|
e97c: f10d 0103 add.w r1, sp, #3
|
||
|
|
e980: 4640 mov r0, r8
|
||
|
|
e982: d5e9 bpl.n e958 <am_hal_uart_interrupt_service+0xd8>
|
||
|
|
e984: 9802 ldr r0, [sp, #8]
|
||
|
|
e986: f7ff facf bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e98a: e78e b.n e8aa <am_hal_uart_interrupt_service+0x2a>
|
||
|
|
e98c: 9801 ldr r0, [sp, #4]
|
||
|
|
e98e: f7ff facb bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e992: f04f 6000 mov.w r0, #134217728 ; 0x8000000
|
||
|
|
e996: e78f b.n e8b8 <am_hal_uart_interrupt_service+0x38>
|
||
|
|
e998: 9801 ldr r0, [sp, #4]
|
||
|
|
e99a: f7ff fac5 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
e99e: 4802 ldr r0, [pc, #8] ; (e9a8 <am_hal_uart_interrupt_service+0x128>)
|
||
|
|
e9a0: e78a b.n e8b8 <am_hal_uart_interrupt_service+0x38>
|
||
|
|
e9a2: bf00 nop
|
||
|
|
e9a4: 01ea9e06 .word 0x01ea9e06
|
||
|
|
e9a8: 08000001 .word 0x08000001
|
||
|
|
|
||
|
|
0000e9ac <am_hal_uart_interrupt_enable>:
|
||
|
|
e9ac: 6803 ldr r3, [r0, #0]
|
||
|
|
e9ae: 4a08 ldr r2, [pc, #32] ; (e9d0 <am_hal_uart_interrupt_enable+0x24>)
|
||
|
|
e9b0: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e9b4: 4293 cmp r3, r2
|
||
|
|
e9b6: d109 bne.n e9cc <am_hal_uart_interrupt_enable+0x20>
|
||
|
|
e9b8: 6a43 ldr r3, [r0, #36] ; 0x24
|
||
|
|
e9ba: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
e9be: 331c adds r3, #28
|
||
|
|
e9c0: 031b lsls r3, r3, #12
|
||
|
|
e9c2: 2000 movs r0, #0
|
||
|
|
e9c4: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
e9c6: 4311 orrs r1, r2
|
||
|
|
e9c8: 6399 str r1, [r3, #56] ; 0x38
|
||
|
|
e9ca: 4770 bx lr
|
||
|
|
e9cc: 2002 movs r0, #2
|
||
|
|
e9ce: 4770 bx lr
|
||
|
|
e9d0: 01ea9e06 .word 0x01ea9e06
|
||
|
|
|
||
|
|
0000e9d4 <am_hal_uart_interrupt_clear>:
|
||
|
|
e9d4: 6803 ldr r3, [r0, #0]
|
||
|
|
e9d6: 4a07 ldr r2, [pc, #28] ; (e9f4 <am_hal_uart_interrupt_clear+0x20>)
|
||
|
|
e9d8: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
e9dc: 4293 cmp r3, r2
|
||
|
|
e9de: d107 bne.n e9f0 <am_hal_uart_interrupt_clear+0x1c>
|
||
|
|
e9e0: 6a43 ldr r3, [r0, #36] ; 0x24
|
||
|
|
e9e2: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
e9e6: 331c adds r3, #28
|
||
|
|
e9e8: 031b lsls r3, r3, #12
|
||
|
|
e9ea: 2000 movs r0, #0
|
||
|
|
e9ec: 6459 str r1, [r3, #68] ; 0x44
|
||
|
|
e9ee: 4770 bx lr
|
||
|
|
e9f0: 2002 movs r0, #2
|
||
|
|
e9f2: 4770 bx lr
|
||
|
|
e9f4: 01ea9e06 .word 0x01ea9e06
|
||
|
|
|
||
|
|
0000e9f8 <am_hal_uart_interrupt_status_get>:
|
||
|
|
e9f8: 6803 ldr r3, [r0, #0]
|
||
|
|
e9fa: b410 push {r4}
|
||
|
|
e9fc: 4c0b ldr r4, [pc, #44] ; (ea2c <am_hal_uart_interrupt_status_get+0x34>)
|
||
|
|
e9fe: f023 437e bic.w r3, r3, #4261412864 ; 0xfe000000
|
||
|
|
ea02: 42a3 cmp r3, r4
|
||
|
|
ea04: d10d bne.n ea22 <am_hal_uart_interrupt_status_get+0x2a>
|
||
|
|
ea06: 6a43 ldr r3, [r0, #36] ; 0x24
|
||
|
|
ea08: f503 2380 add.w r3, r3, #262144 ; 0x40000
|
||
|
|
ea0c: 331c adds r3, #28
|
||
|
|
ea0e: 031b lsls r3, r3, #12
|
||
|
|
ea10: b92a cbnz r2, ea1e <am_hal_uart_interrupt_status_get+0x26>
|
||
|
|
ea12: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
ea14: f85d 4b04 ldr.w r4, [sp], #4
|
||
|
|
ea18: 600b str r3, [r1, #0]
|
||
|
|
ea1a: 2000 movs r0, #0
|
||
|
|
ea1c: 4770 bx lr
|
||
|
|
ea1e: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
ea20: e7f8 b.n ea14 <am_hal_uart_interrupt_status_get+0x1c>
|
||
|
|
ea22: 2002 movs r0, #2
|
||
|
|
ea24: f85d 4b04 ldr.w r4, [sp], #4
|
||
|
|
ea28: 4770 bx lr
|
||
|
|
ea2a: bf00 nop
|
||
|
|
ea2c: 01ea9e06 .word 0x01ea9e06
|
||
|
|
|
||
|
|
0000ea30 <am_hal_queue_init>:
|
||
|
|
ea30: b410 push {r4}
|
||
|
|
ea32: 2400 movs r4, #0
|
||
|
|
ea34: e9c0 4400 strd r4, r4, [r0]
|
||
|
|
ea38: 6084 str r4, [r0, #8]
|
||
|
|
ea3a: e9c0 2104 strd r2, r1, [r0, #16]
|
||
|
|
ea3e: f85d 4b04 ldr.w r4, [sp], #4
|
||
|
|
ea42: 60c3 str r3, [r0, #12]
|
||
|
|
ea44: 4770 bx lr
|
||
|
|
ea46: bf00 nop
|
||
|
|
|
||
|
|
0000ea48 <am_hal_queue_item_add>:
|
||
|
|
ea48: b5f0 push {r4, r5, r6, r7, lr}
|
||
|
|
ea4a: 6906 ldr r6, [r0, #16]
|
||
|
|
ea4c: b083 sub sp, #12
|
||
|
|
ea4e: 4604 mov r4, r0
|
||
|
|
ea50: fb06 f602 mul.w r6, r6, r2
|
||
|
|
ea54: 460d mov r5, r1
|
||
|
|
ea56: f7ff fa63 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
ea5a: e9d4 1202 ldrd r1, r2, [r4, #8]
|
||
|
|
ea5e: 1a53 subs r3, r2, r1
|
||
|
|
ea60: 42b3 cmp r3, r6
|
||
|
|
ea62: 9001 str r0, [sp, #4]
|
||
|
|
ea64: d31c bcc.n eaa0 <am_hal_queue_item_add+0x58>
|
||
|
|
ea66: b196 cbz r6, ea8e <am_hal_queue_item_add+0x46>
|
||
|
|
ea68: 6823 ldr r3, [r4, #0]
|
||
|
|
ea6a: b305 cbz r5, eaae <am_hal_queue_item_add+0x66>
|
||
|
|
ea6c: 1e68 subs r0, r5, #1
|
||
|
|
ea6e: 1987 adds r7, r0, r6
|
||
|
|
ea70: 6962 ldr r2, [r4, #20]
|
||
|
|
ea72: f810 1f01 ldrb.w r1, [r0, #1]!
|
||
|
|
ea76: 54d1 strb r1, [r2, r3]
|
||
|
|
ea78: 6823 ldr r3, [r4, #0]
|
||
|
|
ea7a: 68e5 ldr r5, [r4, #12]
|
||
|
|
ea7c: 1c59 adds r1, r3, #1
|
||
|
|
ea7e: 4287 cmp r7, r0
|
||
|
|
ea80: fbb1 f3f5 udiv r3, r1, r5
|
||
|
|
ea84: fb05 1313 mls r3, r5, r3, r1
|
||
|
|
ea88: 6023 str r3, [r4, #0]
|
||
|
|
ea8a: d1f1 bne.n ea70 <am_hal_queue_item_add+0x28>
|
||
|
|
ea8c: 68a1 ldr r1, [r4, #8]
|
||
|
|
ea8e: 9801 ldr r0, [sp, #4]
|
||
|
|
ea90: 440e add r6, r1
|
||
|
|
ea92: 60a6 str r6, [r4, #8]
|
||
|
|
ea94: f7ff fa48 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
ea98: 2401 movs r4, #1
|
||
|
|
ea9a: 4620 mov r0, r4
|
||
|
|
ea9c: b003 add sp, #12
|
||
|
|
ea9e: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
eaa0: 9801 ldr r0, [sp, #4]
|
||
|
|
eaa2: f7ff fa41 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
eaa6: 2400 movs r4, #0
|
||
|
|
eaa8: 4620 mov r0, r4
|
||
|
|
eaaa: b003 add sp, #12
|
||
|
|
eaac: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
eaae: 4628 mov r0, r5
|
||
|
|
eab0: 3001 adds r0, #1
|
||
|
|
eab2: 3301 adds r3, #1
|
||
|
|
eab4: 4286 cmp r6, r0
|
||
|
|
eab6: fbb3 f5f2 udiv r5, r3, r2
|
||
|
|
eaba: fb02 3315 mls r3, r2, r5, r3
|
||
|
|
eabe: d1f7 bne.n eab0 <am_hal_queue_item_add+0x68>
|
||
|
|
eac0: 6023 str r3, [r4, #0]
|
||
|
|
eac2: e7e4 b.n ea8e <am_hal_queue_item_add+0x46>
|
||
|
|
|
||
|
|
0000eac4 <am_hal_queue_item_get>:
|
||
|
|
eac4: b5f0 push {r4, r5, r6, r7, lr}
|
||
|
|
eac6: 6906 ldr r6, [r0, #16]
|
||
|
|
eac8: 4604 mov r4, r0
|
||
|
|
eaca: b083 sub sp, #12
|
||
|
|
eacc: fb06 f602 mul.w r6, r6, r2
|
||
|
|
ead0: 460d mov r5, r1
|
||
|
|
ead2: f7ff fa25 bl df20 <am_hal_interrupt_master_disable>
|
||
|
|
ead6: 68a2 ldr r2, [r4, #8]
|
||
|
|
ead8: 9001 str r0, [sp, #4]
|
||
|
|
eada: 42b2 cmp r2, r6
|
||
|
|
eadc: d31c bcc.n eb18 <am_hal_queue_item_get+0x54>
|
||
|
|
eade: b196 cbz r6, eb06 <am_hal_queue_item_get+0x42>
|
||
|
|
eae0: 6863 ldr r3, [r4, #4]
|
||
|
|
eae2: b305 cbz r5, eb26 <am_hal_queue_item_get+0x62>
|
||
|
|
eae4: 1e68 subs r0, r5, #1
|
||
|
|
eae6: 1987 adds r7, r0, r6
|
||
|
|
eae8: 6962 ldr r2, [r4, #20]
|
||
|
|
eaea: 5cd3 ldrb r3, [r2, r3]
|
||
|
|
eaec: f800 3f01 strb.w r3, [r0, #1]!
|
||
|
|
eaf0: 6863 ldr r3, [r4, #4]
|
||
|
|
eaf2: 68e5 ldr r5, [r4, #12]
|
||
|
|
eaf4: 1c59 adds r1, r3, #1
|
||
|
|
eaf6: 4287 cmp r7, r0
|
||
|
|
eaf8: fbb1 f3f5 udiv r3, r1, r5
|
||
|
|
eafc: fb05 1313 mls r3, r5, r3, r1
|
||
|
|
eb00: 6063 str r3, [r4, #4]
|
||
|
|
eb02: d1f1 bne.n eae8 <am_hal_queue_item_get+0x24>
|
||
|
|
eb04: 68a2 ldr r2, [r4, #8]
|
||
|
|
eb06: 9801 ldr r0, [sp, #4]
|
||
|
|
eb08: 1b92 subs r2, r2, r6
|
||
|
|
eb0a: 60a2 str r2, [r4, #8]
|
||
|
|
eb0c: f7ff fa0c bl df28 <am_hal_interrupt_master_set>
|
||
|
|
eb10: 2401 movs r4, #1
|
||
|
|
eb12: 4620 mov r0, r4
|
||
|
|
eb14: b003 add sp, #12
|
||
|
|
eb16: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
eb18: 9801 ldr r0, [sp, #4]
|
||
|
|
eb1a: f7ff fa05 bl df28 <am_hal_interrupt_master_set>
|
||
|
|
eb1e: 2400 movs r4, #0
|
||
|
|
eb20: 4620 mov r0, r4
|
||
|
|
eb22: b003 add sp, #12
|
||
|
|
eb24: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
eb26: 68e1 ldr r1, [r4, #12]
|
||
|
|
eb28: 4628 mov r0, r5
|
||
|
|
eb2a: 3001 adds r0, #1
|
||
|
|
eb2c: 3301 adds r3, #1
|
||
|
|
eb2e: 42b0 cmp r0, r6
|
||
|
|
eb30: fbb3 f5f1 udiv r5, r3, r1
|
||
|
|
eb34: fb01 3315 mls r3, r1, r5, r3
|
||
|
|
eb38: d1f7 bne.n eb2a <am_hal_queue_item_get+0x66>
|
||
|
|
eb3a: 6063 str r3, [r4, #4]
|
||
|
|
eb3c: e7e3 b.n eb06 <am_hal_queue_item_get+0x42>
|
||
|
|
eb3e: bf00 nop
|
||
|
|
|
||
|
|
0000eb40 <__init_array_end>:
|
||
|
|
eb40: 72410a0a .word 0x72410a0a
|
||
|
|
eb44: 696d6574 .word 0x696d6574
|
||
|
|
eb48: 56532073 .word 0x56532073
|
||
|
|
eb4c: 6f42204c .word 0x6f42204c
|
||
|
|
eb50: 6f6c746f .word 0x6f6c746f
|
||
|
|
eb54: 72656461 .word 0x72656461
|
||
|
|
eb58: 44202d20 .word 0x44202d20
|
||
|
|
eb5c: 47554245 .word 0x47554245
|
||
|
|
eb60: 00000a0a .word 0x00000a0a
|
||
|
|
eb64: 73616870 .word 0x73616870
|
||
|
|
eb68: 63093a65 .word 0x63093a65
|
||
|
|
eb6c: 69666e6f .word 0x69666e6f
|
||
|
|
eb70: 62206d72 .word 0x62206d72
|
||
|
|
eb74: 6c746f6f .word 0x6c746f6f
|
||
|
|
eb78: 6964616f .word 0x6964616f
|
||
|
|
eb7c: 6520676e .word 0x6520676e
|
||
|
|
eb80: 7972746e .word 0x7972746e
|
||
|
|
eb84: 0000000a .word 0x0000000a
|
||
|
|
eb88: 6e657309 .word 0x6e657309
|
||
|
|
eb8c: 676e6964 .word 0x676e6964
|
||
|
|
eb90: 74724120 .word 0x74724120
|
||
|
|
eb94: 73696d65 .word 0x73696d65
|
||
|
|
eb98: 4c565320 .word 0x4c565320
|
||
|
|
eb9c: 72657620 .word 0x72657620
|
||
|
|
eba0: 6e6f6973 .word 0x6e6f6973
|
||
|
|
eba4: 63617020 .word 0x63617020
|
||
|
|
eba8: 0a74656b .word 0x0a74656b
|
||
|
|
ebac: 00000000 .word 0x00000000
|
||
|
|
ebb0: 69617709 .word 0x69617709
|
||
|
|
ebb4: 676e6974 .word 0x676e6974
|
||
|
|
ebb8: 726f6620 .word 0x726f6620
|
||
|
|
ebbc: 6f6f6220 .word 0x6f6f6220
|
||
|
|
ebc0: 616f6c74 .word 0x616f6c74
|
||
|
|
ebc4: 20726564 .word 0x20726564
|
||
|
|
ebc8: 666e6f63 .word 0x666e6f63
|
||
|
|
ebcc: 616d7269 .word 0x616d7269
|
||
|
|
ebd0: 6e6f6974 .word 0x6e6f6974
|
||
|
|
ebd4: 0000000a .word 0x0000000a
|
||
|
|
ebd8: 206f6e09 .word 0x206f6e09
|
||
|
|
ebdc: 666e6f63 .word 0x666e6f63
|
||
|
|
ebe0: 616d7269 .word 0x616d7269
|
||
|
|
ebe4: 6e6f6974 .word 0x6e6f6974
|
||
|
|
ebe8: 63657220 .word 0x63657220
|
||
|
|
ebec: 65766965 .word 0x65766965
|
||
|
|
ebf0: 00000a64 .word 0x00000a64
|
||
|
|
ebf4: 746e6509 .word 0x746e6509
|
||
|
|
ebf8: 6e697265 .word 0x6e697265
|
||
|
|
ebfc: 6f622067 .word 0x6f622067
|
||
|
|
ec00: 6f6c746f .word 0x6f6c746f
|
||
|
|
ec04: 72656461 .word 0x72656461
|
||
|
|
ec08: 00000a0a .word 0x00000a0a
|
||
|
|
ec0c: 4f525245 .word 0x4f525245
|
||
|
|
ec10: 202d2052 .word 0x202d2052
|
||
|
|
ec14: 6f6e7572 .word 0x6f6e7572
|
||
|
|
ec18: 00006666 .word 0x00006666
|
||
|
|
ec1c: 73616870 .word 0x73616870
|
||
|
|
ec20: 64093a65 .word 0x64093a65
|
||
|
|
ec24: 63657465 .word 0x63657465
|
||
|
|
ec28: 61622074 .word 0x61622074
|
||
|
|
ec2c: 72206475 .word 0x72206475
|
||
|
|
ec30: 0a657461 .word 0x0a657461
|
||
|
|
ec34: 00000000 .word 0x00000000
|
||
|
|
ec38: 75616209 .word 0x75616209
|
||
|
|
ec3c: 61722064 .word 0x61722064
|
||
|
|
ec40: 6e206574 .word 0x6e206574
|
||
|
|
ec44: 6420746f .word 0x6420746f
|
||
|
|
ec48: 63657465 .word 0x63657465
|
||
|
|
ec4c: 2e646574 .word 0x2e646574
|
||
|
|
ec50: 7209090a .word 0x7209090a
|
||
|
|
ec54: 6e697369 .word 0x6e697369
|
||
|
|
ec58: 64652067 .word 0x64652067
|
||
|
|
ec5c: 3a736567 .word 0x3a736567
|
||
|
|
ec60: 0a642509 .word 0x0a642509
|
||
|
|
ec64: 69740909 .word 0x69740909
|
||
|
|
ec68: 2064656d .word 0x2064656d
|
||
|
|
ec6c: 3a74756f .word 0x3a74756f
|
||
|
|
ec70: 0a642509 .word 0x0a642509
|
||
|
|
ec74: 0000000a .word 0x0000000a
|
||
|
|
ec78: 74656409 .word 0x74656409
|
||
|
|
ec7c: 65746365 .word 0x65746365
|
||
|
|
ec80: 61762064 .word 0x61762064
|
||
|
|
ec84: 2064696c .word 0x2064696c
|
||
|
|
ec88: 64756162 .word 0x64756162
|
||
|
|
ec8c: 74617220 .word 0x74617220
|
||
|
|
ec90: 25093a65 .word 0x25093a65
|
||
|
|
ec94: 000a0a64 .word 0x000a0a64
|
||
|
|
ec98: 73616870 .word 0x73616870
|
||
|
|
ec9c: 62093a65 .word 0x62093a65
|
||
|
|
eca0: 6c746f6f .word 0x6c746f6f
|
||
|
|
eca4: 0a64616f .word 0x0a64616f
|
||
|
|
eca8: 00000000 .word 0x00000000
|
||
|
|
ecac: 71657209 .word 0x71657209
|
||
|
|
ecb0: 74736575 .word 0x74736575
|
||
|
|
ecb4: 20676e69 .word 0x20676e69
|
||
|
|
ecb8: 72746572 .word 0x72746572
|
||
|
|
ecbc: 6d736e61 .word 0x6d736e61
|
||
|
|
ecc0: 69737369 .word 0x69737369
|
||
|
|
ecc4: 000a6e6f .word 0x000a6e6f
|
||
|
|
ecc8: 71657209 .word 0x71657209
|
||
|
|
eccc: 74736575 .word 0x74736575
|
||
|
|
ecd0: 20676e69 .word 0x20676e69
|
||
|
|
ecd4: 7478656e .word 0x7478656e
|
||
|
|
ecd8: 70706120 .word 0x70706120
|
||
|
|
ecdc: 61726620 .word 0x61726620
|
||
|
|
ece0: 000a656d .word 0x000a656d
|
||
|
|
ece4: 72650909 .word 0x72650909
|
||
|
|
ece8: 20726f72 .word 0x20726f72
|
||
|
|
ecec: 65636572 .word 0x65636572
|
||
|
|
ecf0: 6e697669 .word 0x6e697669
|
||
|
|
ecf4: 61702067 .word 0x61702067
|
||
|
|
ecf8: 74656b63 .word 0x74656b63
|
||
|
|
ecfc: 64252820 .word 0x64252820
|
||
|
|
ed00: 00000a29 .word 0x00000a29
|
||
|
|
ed04: 65720909 .word 0x65720909
|
||
|
|
ed08: 76696563 .word 0x76696563
|
||
|
|
ed0c: 61206465 .word 0x61206465
|
||
|
|
ed10: 7061206e .word 0x7061206e
|
||
|
|
ed14: 72662070 .word 0x72662070
|
||
|
|
ed18: 0a656d61 .word 0x0a656d61
|
||
|
|
ed1c: 00000000 .word 0x00000000
|
||
|
|
ed20: 65720909 .word 0x65720909
|
||
|
|
ed24: 76696563 .word 0x76696563
|
||
|
|
ed28: 64206465 .word 0x64206465
|
||
|
|
ed2c: 20656e6f .word 0x20656e6f
|
||
|
|
ed30: 6e676973 .word 0x6e676973
|
||
|
|
ed34: 0a216c61 .word 0x0a216c61
|
||
|
|
ed38: 0000000a .word 0x0000000a
|
||
|
|
ed3c: 746f6f62 .word 0x746f6f62
|
||
|
|
ed40: 64616f6c .word 0x64616f6c
|
||
|
|
ed44: 72726520 .word 0x72726520
|
||
|
|
ed48: 2d20726f .word 0x2d20726f
|
||
|
|
ed4c: 6b6e7520 .word 0x6b6e7520
|
||
|
|
ed50: 6e776f6e .word 0x6e776f6e
|
||
|
|
ed54: 6d6f6320 .word 0x6d6f6320
|
||
|
|
ed58: 646e616d .word 0x646e616d
|
||
|
|
ed5c: 0000000a .word 0x0000000a
|
||
|
|
ed60: 00000004 .word 0x00000004
|
||
|
|
ed64: 1000023c .word 0x1000023c
|
||
|
|
ed68: 08000800 .word 0x08000800
|
||
|
|
ed6c: 72660909 .word 0x72660909
|
||
|
|
ed70: 5f656d61 .word 0x5f656d61
|
||
|
|
ed74: 72646461 .word 0x72646461
|
||
|
|
ed78: 20737365 .word 0x20737365
|
||
|
|
ed7c: 7830203d .word 0x7830203d
|
||
|
|
ed80: 58383025 .word 0x58383025
|
||
|
|
ed84: 756e202c .word 0x756e202c
|
||
|
|
ed88: 6f775f6d .word 0x6f775f6d
|
||
|
|
ed8c: 20736472 .word 0x20736472
|
||
|
|
ed90: 6425203d .word 0x6425203d
|
||
|
|
ed94: 0000000a .word 0x0000000a
|
||
|
|
ed98: 6f727245 .word 0x6f727245
|
||
|
|
ed9c: 66203a72 .word 0x66203a72
|
||
|
|
eda0: 656d6172 .word 0x656d6172
|
||
|
|
eda4: 63617020 .word 0x63617020
|
||
|
|
eda8: 2074656b .word 0x2074656b
|
||
|
|
edac: 20746f6e .word 0x20746f6e
|
||
|
|
edb0: 65746e69 .word 0x65746e69
|
||
|
|
edb4: 20726567 .word 0x20726567
|
||
|
|
edb8: 746c756d .word 0x746c756d
|
||
|
|
edbc: 656c7069 .word 0x656c7069
|
||
|
|
edc0: 20666f20 .word 0x20666f20
|
||
|
|
edc4: 64726f77 .word 0x64726f77
|
||
|
|
edc8: 34282073 .word 0x34282073
|
||
|
|
edcc: 74796220 .word 0x74796220
|
||
|
|
edd0: 70207365 .word 0x70207365
|
||
|
|
edd4: 77207265 .word 0x77207265
|
||
|
|
edd8: 2964726f .word 0x2964726f
|
||
|
|
eddc: 0000000a .word 0x0000000a
|
||
|
|
ede0: 53414c46 .word 0x53414c46
|
||
|
|
ede4: 414d5f48 .word 0x414d5f48
|
||
|
|
ede8: 455f5353 .word 0x455f5353
|
||
|
|
edec: 45534152 .word 0x45534152
|
||
|
|
edf0: 32336920 .word 0x32336920
|
||
|
|
edf4: 75746552 .word 0x75746552
|
||
|
|
edf8: 6f436e72 .word 0x6f436e72
|
||
|
|
edfc: 3d206564 .word 0x3d206564
|
||
|
|
ee00: 25783020 .word 0x25783020
|
||
|
|
ee04: 0d0a2e78 .word 0x0d0a2e78
|
||
|
|
ee08: 00000000 .word 0x00000000
|
||
|
|
ee0c: 53414c46 .word 0x53414c46
|
||
|
|
ee10: 52575f48 .word 0x52575f48
|
||
|
|
ee14: 20455449 .word 0x20455449
|
||
|
|
ee18: 6f727265 .word 0x6f727265
|
||
|
|
ee1c: 203d2072 .word 0x203d2072
|
||
|
|
ee20: 78257830 .word 0x78257830
|
||
|
|
ee24: 000d0a2e .word 0x000d0a2e
|
||
|
|
ee28: 6d754a0a .word 0x6d754a0a
|
||
|
|
ee2c: 6f742070 .word 0x6f742070
|
||
|
|
ee30: 70704120 .word 0x70704120
|
||
|
|
ee34: 20746120 .word 0x20746120
|
||
|
|
ee38: 30257830 .word 0x30257830
|
||
|
|
ee3c: 0a0a5838 .word 0x0a0a5838
|
||
|
|
ee40: 00000000 .word 0x00000000
|
||
|
|
|
||
|
|
0000ee44 <am_hal_cachectrl_defaults>:
|
||
|
|
ee44: 00000308 ....
|
||
|
|
|
||
|
|
0000ee48 <g_AM_HAL_GPIO_DISABLE>:
|
||
|
|
ee48: 00000003 ....
|
||
|
|
|
||
|
|
0000ee4c <g_AM_HAL_GPIO_INPUT_PULLUP>:
|
||
|
|
ee4c: 00001023 #...
|
||
|
|
|
||
|
|
0000ee50 <g_ui8Bit76Capabilities>:
|
||
|
|
ee50: 02800101 80010180 80800101 80808080 ................
|
||
|
|
ee60: 80808080 80808008 01800180 80808080 ................
|
||
|
|
ee70: 80808080 01800402 01010401 80808080 ................
|
||
|
|
ee80: 00000101 ....
|
||
|
|
|
||
|
|
0000ee84 <g_ui8Inpen>:
|
||
|
|
ee84: 62272323 108703a1 e1005303 55418151 ##'b.....S..Q.AU
|
||
|
|
ee94: 4080c405 4140b101 31a03114 1180f100 ...@..@A.1.1....
|
||
|
|
eea4: 11c12191 304511e5 31300037 40007100 .!....E07.01.q.@
|
||
|
|
eeb4: 00003130 01..
|
||
|
|
|
||
|
|
0000eeb8 <g_ui8NCEtable>:
|
||
|
|
eeb8: 13524232 60221202 21534333 20504030 2BR..."`3CS!0@P
|
||
|
|
eec8: 11514131 ffffffff ffffffff 60514131 1AQ.........1AQ`
|
||
|
|
eed8: 00504030 23534333 60524232 30201000 0@P.3CS#2BR`.. 0
|
||
|
|
eee8: 61504030 01514131 42221202 60231303 0@Pa1AQ..."B..#`
|
||
|
|
eef8: 50201000 41211101 32221202 60331303 .. P..!A.."2..3`
|
||
|
|
ef08: 21514131 22524232 03534333 40201000 1AQ!2BR"3CS... @
|
||
|
|
ef18: 51211101 02524232 13534333 10504030 ..!Q2BR.3CS.0@P.
|
||
|
|
ef28: 60514131 12524232 03534333 40201000 1AQ`2BR.3CS... @
|
||
|
|
ef38: 61211101 52221202 33231303 30201000 ..!a.."R..#3.. 0
|
||
|
|
ef48: 61514131 02524232 53331303 ffffffff 1AQa2BR...3S....
|
||
|
|
ef58: ffffffff 61211101 50201000 61211101 ......!a.. P..!a
|
||
|
|
ef68: 52221202 13534333 61504030 31211101 .."R3CS.0@Pa..!1
|
||
|
|
ef78: 32221202 43231303 .."2..#C
|
||
|
|
|
||
|
|
0000ef80 <g_ui8nCEpins>:
|
||
|
|
ef80: 02070707 00080802 01020202 01010101 ................
|
||
|
|
ef90: 01010101 01010101 01010101 01010101 ................
|
||
|
|
efa0: 01010101 08010101 01010008 01010101 ................
|
||
|
|
efb0: 00000101 ....
|
||
|
|
|
||
|
|
0000efb4 <am_hal_pwrctrl_peripheral_control>:
|
||
|
|
...
|
||
|
|
efc0: 00000001 00000004 00000004 00000002 ................
|
||
|
|
efd0: 00000008 00000008 00000004 00000008 ................
|
||
|
|
efe0: 00000008 00000008 00000008 00000008 ................
|
||
|
|
eff0: 00000010 00000010 00000010 00000020 ............ ...
|
||
|
|
f000: 00000010 00000010 00000040 00000010 ........@.......
|
||
|
|
f010: 00000010 00000080 00000004 00000004 ................
|
||
|
|
f020: 00000100 00000004 00000004 00000200 ................
|
||
|
|
f030: 00000020 00000020 00000400 00000004 ... ...........
|
||
|
|
f040: 00000004 00000800 00000040 00000040 ........@...@...
|
||
|
|
f050: 00001000 00000080 00000080 00002000 ............. ..
|
||
|
|
f060: 00000100 00000100 ........
|
||
|
|
|
||
|
|
0000f068 <CSWTCH.20>:
|
||
|
|
f068: 016e3600 00b71b00 005b8d80 002dc6c0 .6n.......[...-.
|