481 lines
17 KiB
C
481 lines
17 KiB
C
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//*****************************************************************************
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//
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// am_hal_cachectrl.c
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//! @file
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//!
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//! @brief Functions for interfacing with the CACHE controller.
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//!
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//! @addtogroup clkgen3p Clock Generator (CACHE)
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//! @ingroup apollo3phal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Default settings for the cache.
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//
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//*****************************************************************************
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const am_hal_cachectrl_config_t am_hal_cachectrl_defaults =
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{
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.bLRU = 0,
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.eDescript = AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E,
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.eMode = AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA,
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};
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//*****************************************************************************
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//
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// Configure the cache with given and recommended settings, but do not enable.
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//
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//*****************************************************************************
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uint32_t
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am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig)
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{
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//
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// In the case where cache is currently enabled, we need to gracefully
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// bow out of that configuration before reconfiguring. The best way to
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// accomplish that is to shut down the ID bits, leaving the cache enabled.
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// Once the instr and data caches have been disabled, we can safely set
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// any new configuration, including disabling the controller.
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//
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AM_CRITICAL_BEGIN
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CACHECTRL->CACHECFG &=
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~(CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk |
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CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk);
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AM_CRITICAL_END
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CACHECTRL->CACHECFG =
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_VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 0) |
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_VAL2FLD(CACHECTRL_CACHECFG_CACHE_CLKGATE, 1) |
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_VAL2FLD(CACHECTRL_CACHECFG_CACHE_LS, 0) |
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_VAL2FLD(CACHECTRL_CACHECFG_DATA_CLKGATE, 1) |
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_VAL2FLD(CACHECTRL_CACHECFG_ENABLE_MONITOR, 0) |
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_VAL2FLD(CACHECTRL_CACHECFG_LRU, psConfig->bLRU) |
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_VAL2FLD(CACHECTRL_CACHECFG_CONFIG, psConfig->eDescript) |
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((psConfig->eMode << CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos) &
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(CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk |
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CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk));
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return AM_HAL_STATUS_SUCCESS;
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} // am_hal_cachectrl_config()
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//*****************************************************************************
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//
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// Enable the cache.
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//
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//*****************************************************************************
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uint32_t
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am_hal_cachectrl_enable(void)
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{
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//
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// Enable the cache
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//
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CACHECTRL->CACHECFG |= _VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 1);
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return AM_HAL_STATUS_SUCCESS;
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} // am_hal_cachectrl_enable()
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//*****************************************************************************
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//
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// Disable the cache.
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//
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//*****************************************************************************
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uint32_t
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am_hal_cachectrl_disable(void)
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{
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//
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// Shut down as gracefully as possible.
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// Disable the I/D cache enable bits first to allow a little time
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// for any in-flight transactions to hand off to the line buffer.
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// Then clear the enable.
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//
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AM_CRITICAL_BEGIN
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CACHECTRL->CACHECFG &= ~(_VAL2FLD(CACHECTRL_CACHECFG_ICACHE_ENABLE, 1) |
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_VAL2FLD(CACHECTRL_CACHECFG_DCACHE_ENABLE, 1));
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CACHECTRL->CACHECFG &= ~_VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 1);
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AM_CRITICAL_END
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return AM_HAL_STATUS_SUCCESS;
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} // am_hal_cachectrl_disable()
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//*****************************************************************************
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//
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// Control helper functions.
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//
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//*****************************************************************************
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static bool
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set_LPMMODE(uint32_t ui32value)
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{
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uint32_t ui32Val, ui32inst;
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uint32_t *pui32RegAddr;
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if ( ui32value > (CACHECTRL_FLASH0CFG_LPMMODE0_Msk >> CACHECTRL_FLASH0CFG_LPMMODE0_Pos) )
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{
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return false;
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}
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//
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// We need to set all 4 instances.
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//
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for ( ui32inst = 0; ui32inst < 4; ui32inst++ )
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{
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//
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// Compute register address (assumes each reg is 1 word offset).
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//
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pui32RegAddr = (uint32_t*)&CACHECTRL->FLASH0CFG;
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pui32RegAddr += ui32inst;
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AM_CRITICAL_BEGIN
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ui32Val = am_hal_flash_load_ui32(pui32RegAddr);
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ui32Val &= ~(CACHECTRL_FLASH0CFG_LPMMODE0_Msk |
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CACHECTRL_FLASH0CFG_LPMRDWAIT0_Msk);
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ui32Val |= _VAL2FLD(CACHECTRL_FLASH0CFG_LPMMODE0, ui32value) |
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_VAL2FLD(CACHECTRL_FLASH0CFG_LPMRDWAIT0, 0x7);
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am_hal_flash_store_ui32(pui32RegAddr, ui32Val);
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AM_CRITICAL_END
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}
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return true;
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} // set_LPMMODE()
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static bool
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set_SEDELAY(uint32_t ui32value)
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{
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uint32_t ui32Val, ui32inst;
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uint32_t *pui32RegAddr;
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if ( ui32value > (CACHECTRL_FLASH0CFG_SEDELAY0_Msk >> CACHECTRL_FLASH0CFG_SEDELAY0_Pos) )
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{
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return false;
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}
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//
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// We need to set all 4 instances.
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//
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for ( ui32inst = 0; ui32inst < 4; ui32inst++ )
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{
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//
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// Compute register address (assumes each reg is 1 word offset).
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//
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pui32RegAddr = (uint32_t*)&CACHECTRL->FLASH0CFG;
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pui32RegAddr += ui32inst;
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AM_CRITICAL_BEGIN
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ui32Val = am_hal_flash_load_ui32(pui32RegAddr);
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ui32Val &= ~(CACHECTRL_FLASH0CFG_SEDELAY0_Msk |
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CACHECTRL_FLASH0CFG_LPMRDWAIT0_Msk);
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ui32Val |= _VAL2FLD(CACHECTRL_FLASH0CFG_SEDELAY0, ui32value) |
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_VAL2FLD(CACHECTRL_FLASH0CFG_LPMRDWAIT0, 0x7);
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am_hal_flash_store_ui32(pui32RegAddr, ui32Val);
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AM_CRITICAL_END
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}
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return true;
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} // set_SEDELAY()
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static bool
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set_RDWAIT(uint32_t ui32value)
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{
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uint32_t ui32Val, ui32inst;
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uint32_t *pui32RegAddr;
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if ( ui32value > (CACHECTRL_FLASH0CFG_RDWAIT0_Msk >> CACHECTRL_FLASH0CFG_RDWAIT0_Pos) )
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{
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return false;
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}
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//
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// We need to set all 4 instances.
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//
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for ( ui32inst = 0; ui32inst < 4; ui32inst++ )
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{
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//
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// Compute register address (assumes each reg is 1 word offset).
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//
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pui32RegAddr = (uint32_t*)&CACHECTRL->FLASH0CFG;
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pui32RegAddr += ui32inst;
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AM_CRITICAL_BEGIN
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ui32Val = am_hal_flash_load_ui32(pui32RegAddr);
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ui32Val &= ~(CACHECTRL_FLASH0CFG_RDWAIT0_Msk |
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CACHECTRL_FLASH0CFG_LPMRDWAIT0_Msk);
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ui32Val |= _VAL2FLD(CACHECTRL_FLASH0CFG_RDWAIT0, ui32value) |
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_VAL2FLD(CACHECTRL_FLASH0CFG_LPMRDWAIT0, 0x7);
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am_hal_flash_store_ui32(pui32RegAddr, ui32Val);
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AM_CRITICAL_END
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}
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return true;
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} // set_RDWAIT()
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//*****************************************************************************
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//
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// Select the cache configuration type.
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//
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//*****************************************************************************
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uint32_t
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am_hal_cachectrl_control(am_hal_cachectrl_control_e eControl, void *pArgs)
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{
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uint32_t ui32Arg;
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uint32_t ui32SetMask = 0;
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switch ( eControl )
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{
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case AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE:
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ui32SetMask = CACHECTRL_CTRL_INVALIDATE_Msk;
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break;
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case AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET:
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if ( !_FLD2VAL(CACHECTRL_CACHECFG_ENABLE_MONITOR, CACHECTRL->CACHECFG) )
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{
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//
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// The monitor must be enabled for the reset to have any affect.
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//
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return AM_HAL_STATUS_INVALID_OPERATION;
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}
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else
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{
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ui32SetMask = CACHECTRL_CTRL_RESET_STAT_Msk;
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}
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break;
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case AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE:
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ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk |
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CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk;
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break;
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case AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE:
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ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk |
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CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk;
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break;
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case AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE:
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ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk;
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break;
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case AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE:
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ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk;
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break;
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case AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE:
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ui32SetMask = CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk;
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break;
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case AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE:
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ui32SetMask = CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk;
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break;
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case AM_HAL_CACHECTRL_CONTROL_MONITOR_ENABLE:
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ui32SetMask = 0;
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AM_CRITICAL_BEGIN
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CACHECTRL->CACHECFG |= CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
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AM_CRITICAL_END
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break;
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case AM_HAL_CACHECTRL_CONTROL_MONITOR_DISABLE:
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ui32SetMask = 0;
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AM_CRITICAL_BEGIN
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CACHECTRL->CACHECFG &= ~CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk;
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AM_CRITICAL_END
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break;
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case AM_HAL_CACHECTRL_CONTROL_LPMMODE_RESET:
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//
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// Safely set the reset values for LPMMODE, SEDELAY, and RDWAIT.
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//
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if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_NEVER) ||
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!set_SEDELAY(0x7) ||
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!set_RDWAIT(0x3) )
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{
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return AM_HAL_STATUS_FAIL;
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}
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break;
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case AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED:
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//
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// Safely set the as recommended values (from the datasheet)
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// for LPMMODE, SEDELAY, and RDWAIT.
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//
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if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY) ||
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!set_SEDELAY(0x5) ||
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!set_RDWAIT(0x1) )
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{
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return AM_HAL_STATUS_FAIL;
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}
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break;
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case AM_HAL_CACHECTRL_CONTROL_LPMMODE_AGGRESSIVE:
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//
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// Safely set aggressive values for LPMMODE, SEDELAY, and RDWAIT.
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// (For now select recommended values.)
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//
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if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY) ||
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!set_SEDELAY(0x6) ||
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!set_RDWAIT(0x1) )
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{
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return AM_HAL_STATUS_FAIL;
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}
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break;
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case AM_HAL_CACHECTRL_CONTROL_LPMMODE_SET:
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//
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// Safely set LPMMODE, SEDELAY, or RDWAIT.
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// The new value is passed by reference via pArgs. That is, pArgs is
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// assumed to be a pointer to a uint32_t of the new value.
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//
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if ( !pArgs )
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{
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|
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return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
ui32Arg = *(uint32_t*)pArgs;
|
||
|
|
if ( !set_LPMMODE(ui32Arg) )
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_FAIL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case AM_HAL_CACHECTRL_CONTROL_SEDELAY_SET:
|
||
|
|
if ( !pArgs )
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
ui32Arg = *(uint32_t*)pArgs;
|
||
|
|
if ( !set_SEDELAY(ui32Arg) )
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_FAIL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case AM_HAL_CACHECTRL_CONTROL_RDWAIT_SET:
|
||
|
|
if ( !pArgs )
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
ui32Arg = *(uint32_t*)pArgs;
|
||
|
|
if ( !set_RDWAIT(ui32Arg) )
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_FAIL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case AM_HAL_CACHECTRL_CONTROL_NC_CFG:
|
||
|
|
{
|
||
|
|
if ( pArgs == NULL )
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
am_hal_cachectrl_nc_cfg_t *pNcCfg;
|
||
|
|
pNcCfg = (am_hal_cachectrl_nc_cfg_t *)pArgs;
|
||
|
|
#ifndef AM_HAL_DISABLE_API_VALIDATION
|
||
|
|
// Make sure the addresses are valid
|
||
|
|
if ((pNcCfg->ui32StartAddr & ~CACHECTRL_NCR0START_ADDR_Msk) ||
|
||
|
|
(pNcCfg->ui32EndAddr & ~CACHECTRL_NCR0START_ADDR_Msk))
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
#endif // AM_HAL_DISABLE_API_VALIDATION
|
||
|
|
if (pNcCfg->eNCRegion == AM_HAL_CACHECTRL_NCR0)
|
||
|
|
{
|
||
|
|
CACHECTRL->NCR0START = pNcCfg->ui32StartAddr;
|
||
|
|
CACHECTRL->NCR0END = pNcCfg->ui32EndAddr;
|
||
|
|
CACHECTRL->CACHECFG_b.ENABLE_NC0 = pNcCfg->bEnable;
|
||
|
|
}
|
||
|
|
else if (pNcCfg->eNCRegion == AM_HAL_CACHECTRL_NCR1)
|
||
|
|
{
|
||
|
|
CACHECTRL->NCR1START = pNcCfg->ui32StartAddr;
|
||
|
|
CACHECTRL->NCR1END = pNcCfg->ui32EndAddr;
|
||
|
|
CACHECTRL->CACHECFG_b.ENABLE_NC1 = pNcCfg->bEnable;
|
||
|
|
}
|
||
|
|
#ifndef AM_HAL_DISABLE_API_VALIDATION
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
#endif // AM_HAL_DISABLE_API_VALIDATION
|
||
|
|
return AM_HAL_STATUS_SUCCESS;
|
||
|
|
}
|
||
|
|
default:
|
||
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// All fields in the CACHECTRL register are write-only or read-only.
|
||
|
|
// A write to CACHECTRL acts as a mask-set. That is, only the bits
|
||
|
|
// written as '1' have an effect, any bits written as '0' are unaffected.
|
||
|
|
//
|
||
|
|
// Important note - setting of an enable and disable simultanously has
|
||
|
|
// unpredicable results.
|
||
|
|
//
|
||
|
|
if ( ui32SetMask )
|
||
|
|
{
|
||
|
|
CACHECTRL->CTRL = ui32SetMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
return AM_HAL_STATUS_SUCCESS;
|
||
|
|
|
||
|
|
} // am_hal_cachectrl_control()
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Cache controller status function
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
uint32_t
|
||
|
|
am_hal_cachectrl_status_get(am_hal_cachectrl_status_t *psStatus)
|
||
|
|
{
|
||
|
|
uint32_t ui32Status;
|
||
|
|
|
||
|
|
if ( psStatus == NULL )
|
||
|
|
{
|
||
|
|
return AM_HAL_STATUS_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
ui32Status = CACHECTRL->CTRL;
|
||
|
|
|
||
|
|
psStatus->bFlash0SleepMode =
|
||
|
|
_FLD2VAL(CACHECTRL_CTRL_FLASH0_SLM_STATUS, ui32Status);
|
||
|
|
psStatus->bFlash1SleepMode =
|
||
|
|
_FLD2VAL(CACHECTRL_CTRL_FLASH1_SLM_STATUS, ui32Status);
|
||
|
|
psStatus->bCacheReady =
|
||
|
|
_FLD2VAL(CACHECTRL_CTRL_CACHE_READY, ui32Status);
|
||
|
|
|
||
|
|
return AM_HAL_STATUS_SUCCESS;
|
||
|
|
|
||
|
|
} // am_hal_cachectrl_status_get()
|
||
|
|
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// End Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|