159 lines
7.0 KiB
C
159 lines
7.0 KiB
C
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//*****************************************************************************
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//
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//! @file am_devices_mb85rs1mt.h
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//!
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//! @brief Fujitsu 64K SPI FRAM driver.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2020, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// Third party software included in this distribution is subject to the
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// additional license terms as defined in the /docs/licenses directory.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_DEVICES_MB85RS1MT_H
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#define AM_DEVICES_MB85RS1MT_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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// Global definitions for the commands
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//
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//*****************************************************************************
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#define AM_DEVICES_MB85RS1MT_WRITE_ENABLE 0x06
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#define AM_DEVICES_MB85RS1MT_WRITE_DISABLE 0x04
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#define AM_DEVICES_MB85RS1MT_READ_STATUS 0x05
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#define AM_DEVICES_MB85RS1MT_WRITE_STATUS 0x01
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#define AM_DEVICES_MB85RS1MT_READ 0x03
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#define AM_DEVICES_MB85RS1MT_WRITE 0x02
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#define AM_DEVICES_MB85RS1MT_READ_DEVICE_ID 0x9F
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//*****************************************************************************
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//
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// Global definitions for the status register
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//
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//*****************************************************************************
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#define AM_DEVICES_MB85RS1MT_WPEN 0x80 // Write pending status
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#define AM_DEVICES_MB85RS1MT_WEL 0x02 // Write enable latch
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//*****************************************************************************
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//
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// Global definitions for the device id.
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//
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//*****************************************************************************
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#define AM_DEVICES_MB85RS1MT_ID 0x03277F04 //0x047F2703
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//*****************************************************************************
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//
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// Global type definitions.
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//
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//*****************************************************************************
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typedef enum
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{
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AM_DEVICES_MB85RS1MT_STATUS_SUCCESS,
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AM_DEVICES_MB85RS1MT_STATUS_ERROR
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} am_devices_mb85rs1mt_status_t;
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typedef struct
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{
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uint32_t ui32ClockFreq;
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uint32_t *pNBTxnBuf;
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uint32_t ui32NBTxnBufLength;
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} am_devices_mb85rs1mt_config_t;
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#define AM_DEVICES_MB85RS1MT_CMD_WREN AM_DEVICES_MB85RS1MT_WRITE_ENABLE
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#define AM_DEVICES_MB85RS1MT_CMD_WRDI AM_DEVICES_MB85RS1MT_WRITE_DISABLE
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#define AM_DEVICES_MB85RS1MT_MAX_DEVICE_NUM 1
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//*****************************************************************************
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//
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// External function definitions.
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//
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//*****************************************************************************
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extern uint32_t am_devices_mb85rs1mt_init(uint32_t ui32Module, am_devices_mb85rs1mt_config_t *pDevConfig, void **ppHandle, void **ppIomHandle);
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extern uint32_t am_devices_mb85rs1mt_term(void *pHandle);
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extern uint32_t am_devices_mb85rs1mt_read_id(void *pHandle, uint32_t *pDeviceID);
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extern uint32_t am_devices_mb85rs1mt_status_get(void *pHandle, uint32_t *pStatus);
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extern uint32_t am_devices_mb85rs1mt_command_send(void *pHandle, uint32_t ui32Cmd);
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extern uint32_t am_devices_mb85rs1mt_blocking_write(void *pHandle, uint8_t *ui8TxBuffer,
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uint32_t ui32WriteAddress,
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uint32_t ui32NumBytes);
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extern uint32_t am_devices_mb85rs1mt_nonblocking_write(void *pHandle, uint8_t *ui8TxBuffer,
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uint32_t ui32WriteAddress,
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uint32_t ui32NumBytes,
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am_hal_iom_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mb85rs1mt_nonblocking_write_adv(void *pHandle, uint8_t *pui8TxBuffer,
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uint32_t ui32WriteAddress,
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uint32_t ui32NumBytes,
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uint32_t ui32PauseCondition,
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uint32_t ui32StatusSetClr,
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am_hal_iom_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mb85rs1mt_blocking_read(void *pHandle, uint8_t *pui8RxBuffer,
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uint32_t ui32ReadAddress,
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uint32_t ui32NumBytes);
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extern uint32_t am_devices_mb85rs1mt_nonblocking_read(void *pHandle, uint8_t *pui8RxBuffer,
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uint32_t ui32ReadAddress,
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uint32_t ui32NumBytes,
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am_hal_iom_callback_t pfnCallback,
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void *pCallbackCtxt);
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extern uint32_t am_devices_mb85rs1mt_nonblocking_read_hiprio(void *pHandle, uint8_t *pui8RxBuffer,
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uint32_t ui32ReadAddress,
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uint32_t ui32NumBytes,
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am_hal_iom_callback_t pfnCallback,
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void *pCallbackCtxt);
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#ifdef __cplusplus
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}
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#endif
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#endif // AM_DEVICES_MB85RS1MT_H
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