409 lines
15 KiB
ArmAsm
409 lines
15 KiB
ArmAsm
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;******************************************************************************
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;
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;! @file startup_apollo3.s
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;!
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;! @brief Definitions for Apollo3 interrupt handlers, the vector table, and the stack.
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;
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;******************************************************************************
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;******************************************************************************
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;
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; Copyright (c) 2020, Ambiq Micro
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
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; 1. Redistributions of source code must retain the above copyright notice,
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; this list of conditions and the following disclaimer.
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;
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; 3. Neither the name of the copyright holder nor the names of its
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; contributors may be used to endorse or promote products derived from this
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; software without specific prior written permission.
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;
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; Third party software included in this distribution is subject to the
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; additional license terms as defined in the /docs/licenses directory.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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;
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; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
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;
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;******************************************************************************
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;******************************************************************************
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;
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;************************************************************************
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Stack EQU 0x00001000
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;******************************************************************************
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;
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;
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;******************************************************************************
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Heap EQU 0x00000000
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;******************************************************************************
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;
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; Allocate space for the stack.
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;
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;******************************************************************************
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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StackMem
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SPACE Stack
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__initial_sp
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;******************************************************************************
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;
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; Allocate space for the heap.
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;
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;******************************************************************************
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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HeapMem
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SPACE Heap
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__heap_limit
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;******************************************************************************
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;
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; Indicate that the code in this file preserves 8-byte alignment of the stack.
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;
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;******************************************************************************
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PRESERVE8
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;******************************************************************************
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;
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; Place code into the reset code section.
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;
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;******************************************************************************
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AREA RESET, CODE, READONLY
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THUMB
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;******************************************************************************
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;
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; The vector table.
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;
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;******************************************************************************
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;
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; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
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; am_usagefault_isr does not work if am_fault_isr is defined externally.
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; Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
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;
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EXPORT __Vectors
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__Vectors
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DCD StackMem + Stack ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; The MPU fault handler
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DCD BusFault_Handler ; The bus fault handler
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DCD UsageFault_Handler ; The usage fault handler
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DCD SecureFault_Handler ; Secure fault handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall handler
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DCD DebugMon_Handler ; Debug monitor handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; The PendSV handler
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DCD SysTick_Handler ; The SysTick handler
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;
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; Peripheral Interrupts
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;
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DCD am_brownout_isr ; 0: Reserved
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DCD am_watchdog_isr ; 1: Reserved
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DCD am_rtc_isr ; 2: RTC
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DCD am_vcomp_isr ; 3: Voltage Comparator
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DCD am_ioslave_ios_isr ; 4: I/O Slave general
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DCD am_ioslave_acc_isr ; 5: I/O Slave access
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DCD am_iomaster0_isr ; 6: I/O Master 0
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DCD am_iomaster1_isr ; 7: I/O Master 1
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DCD am_iomaster2_isr ; 8: I/O Master 2
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DCD am_iomaster3_isr ; 9: I/O Master 3
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DCD am_iomaster4_isr ; 10: I/O Master 4
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DCD am_iomaster5_isr ; 11: I/O Master 5
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DCD am_ble_isr ; 12: BLEIF
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DCD am_gpio_isr ; 13: GPIO
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DCD am_ctimer_isr ; 14: CTIMER
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DCD am_uart_isr ; 15: UART0
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DCD am_uart1_isr ; 16: UART1
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DCD am_scard_isr ; 17: SCARD
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DCD am_adc_isr ; 18: ADC
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DCD am_pdm0_isr ; 19: PDM
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DCD am_mspi0_isr ; 20: MSPI0
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DCD am_software0_isr ; 21: SOFTWARE0
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DCD am_stimer_isr ; 22: SYSTEM TIMER
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DCD am_stimer_cmpr0_isr ; 23: SYSTEM TIMER COMPARE0
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DCD am_stimer_cmpr1_isr ; 24: SYSTEM TIMER COMPARE1
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DCD am_stimer_cmpr2_isr ; 25: SYSTEM TIMER COMPARE2
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DCD am_stimer_cmpr3_isr ; 26: SYSTEM TIMER COMPARE3
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DCD am_stimer_cmpr4_isr ; 27: SYSTEM TIMER COMPARE4
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DCD am_stimer_cmpr5_isr ; 28: SYSTEM TIMER COMPARE5
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DCD am_stimer_cmpr6_isr ; 29: SYSTEM TIMER COMPARE6
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DCD am_stimer_cmpr7_isr ; 30: SYSTEM TIMER COMPARE7
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DCD am_clkgen_isr ; 31: CLKGEN
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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;******************************************************************************
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;
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; Place code immediately following vector table.
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;
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;******************************************************************************
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;******************************************************************************
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;
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; The Patch table.
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;
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; The patch table should pad the vector table size to a total of 64 entries
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; (16 core + 48 periph) such that code begins at offset 0x100.
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;
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;******************************************************************************
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EXPORT __Patchable
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__Patchable
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DCD 0 ; 32
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DCD 0 ; 33
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DCD 0 ; 34
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DCD 0 ; 35
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DCD 0 ; 36
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DCD 0 ; 37
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DCD 0 ; 38
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DCD 0 ; 39
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DCD 0 ; 40
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DCD 0 ; 41
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DCD 0 ; 42
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DCD 0 ; 43
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DCD 0 ; 44
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DCD 0 ; 45
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DCD 0 ; 46
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DCD 0 ; 47
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;******************************************************************************
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;
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; This is the code that gets called when the processor first starts execution
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; following a reset event.
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;
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;******************************************************************************
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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;
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; Enable the FPU.
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;
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MOVW R0, #0xED88
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MOVT R0, #0xE000
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LDR R1, [R0]
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ORR R1, #0x00F00000
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STR R1, [R0]
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DSB
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ISB
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;
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; Branch to main.
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;
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LDR R0, =__main
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BX R0
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ENDP
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;******************************************************************************
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;
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; Weak Exception Handlers.
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;
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;******************************************************************************
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SecureFault_Handler\
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PROC
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EXPORT SecureFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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am_default_isr\
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PROC
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EXPORT am_brownout_isr [WEAK]
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EXPORT am_watchdog_isr [WEAK]
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EXPORT am_rtc_isr [WEAK]
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EXPORT am_vcomp_isr [WEAK]
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EXPORT am_ioslave_ios_isr [WEAK]
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EXPORT am_ioslave_acc_isr [WEAK]
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EXPORT am_iomaster0_isr [WEAK]
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EXPORT am_iomaster1_isr [WEAK]
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EXPORT am_iomaster2_isr [WEAK]
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EXPORT am_iomaster3_isr [WEAK]
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EXPORT am_iomaster4_isr [WEAK]
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EXPORT am_iomaster5_isr [WEAK]
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EXPORT am_ble_isr [WEAK]
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EXPORT am_gpio_isr [WEAK]
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EXPORT am_ctimer_isr [WEAK]
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EXPORT am_uart_isr [WEAK]
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EXPORT am_uart0_isr [WEAK]
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EXPORT am_uart1_isr [WEAK]
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EXPORT am_scard_isr [WEAK]
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EXPORT am_adc_isr [WEAK]
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EXPORT am_pdm0_isr [WEAK]
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EXPORT am_mspi0_isr [WEAK]
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EXPORT am_software0_isr [WEAK]
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EXPORT am_stimer_isr [WEAK]
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EXPORT am_stimer_cmpr0_isr [WEAK]
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EXPORT am_stimer_cmpr1_isr [WEAK]
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EXPORT am_stimer_cmpr2_isr [WEAK]
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EXPORT am_stimer_cmpr3_isr [WEAK]
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EXPORT am_stimer_cmpr4_isr [WEAK]
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EXPORT am_stimer_cmpr5_isr [WEAK]
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EXPORT am_stimer_cmpr6_isr [WEAK]
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EXPORT am_stimer_cmpr7_isr [WEAK]
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EXPORT am_clkgen_isr [WEAK]
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am_brownout_isr
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am_watchdog_isr
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am_rtc_isr
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am_vcomp_isr
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am_ioslave_ios_isr
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am_ioslave_acc_isr
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am_iomaster0_isr
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am_iomaster1_isr
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am_iomaster2_isr
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am_iomaster3_isr
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am_iomaster4_isr
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am_iomaster5_isr
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am_ble_isr
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am_gpio_isr
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am_ctimer_isr
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am_uart_isr
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am_uart0_isr
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am_uart1_isr
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am_scard_isr
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am_adc_isr
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am_pdm0_isr
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am_mspi0_isr
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am_software0_isr
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am_stimer_isr
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am_stimer_cmpr0_isr
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am_stimer_cmpr1_isr
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am_stimer_cmpr2_isr
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am_stimer_cmpr3_isr
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am_stimer_cmpr4_isr
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am_stimer_cmpr5_isr
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am_stimer_cmpr6_isr
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am_stimer_cmpr7_isr
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am_clkgen_isr
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; all device interrupts go here unless the weak label is over
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; ridden in the linker hard spin so the debugger will know it
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; was an unhandled interrupt request a come-from-buffer or
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; instruction trace hardware would sure be nice if you get here
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B .
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ENDP
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;******************************************************************************
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;
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; Align the end of the section.
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;
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;******************************************************************************
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ALIGN
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;******************************************************************************
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;
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; Initialization of the heap and stack.
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;
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;******************************************************************************
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AREA |.text|, CODE, READONLY
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||
|
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|
||
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;******************************************************************************
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||
|
|
;
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||
|
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; User Initial Stack & Heap.
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||
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;
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;******************************************************************************
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IF :DEF: __MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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|
LDR R0, =HeapMem
|
||
|
|
LDR R1, =(StackMem + Stack)
|
||
|
|
LDR R2, =(HeapMem + Heap)
|
||
|
|
LDR R3, =StackMem
|
||
|
|
BX LR
|
||
|
|
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
;******************************************************************************
|
||
|
|
;
|
||
|
|
; Align the end of the section.
|
||
|
|
;
|
||
|
|
;******************************************************************************
|
||
|
|
ALIGN
|
||
|
|
|
||
|
|
;******************************************************************************
|
||
|
|
;
|
||
|
|
; All Done
|
||
|
|
;
|
||
|
|
;******************************************************************************
|
||
|
|
END
|
||
|
|
|
||
|
|
|