b1b6f294f2
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure 😩
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
624 lines
18 KiB
C#
624 lines
18 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitAluHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Add(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Add(n, m);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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EmitAddsCCheck(context, n, res);
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EmitAddsVCheck(context, n, m, res);
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}
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EmitAluStore(context, res);
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}
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public static void Adc(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Add(n, m);
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Operand carry = GetFlag(PState.CFlag);
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res = context.Add(res, carry);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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EmitAdcsCCheck(context, n, res);
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EmitAddsVCheck(context, n, m, res);
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}
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EmitAluStore(context, res);
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}
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public static void And(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res = context.BitwiseAnd(n, m);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitAluStore(context, res);
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}
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public static void Bfc(ArmEmitterContext context)
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{
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OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
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Operand d = GetIntA32(context, op.Rd);
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Operand res = context.BitwiseAnd(d, Const(~op.DestMask));
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SetIntA32(context, op.Rd, res);
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}
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public static void Bfi(ArmEmitterContext context)
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{
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OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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Operand d = GetIntA32(context, op.Rd);
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Operand part = context.BitwiseAnd(n, Const(op.SourceMask));
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if (op.Lsb != 0)
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{
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part = context.ShiftLeft(part, Const(op.Lsb));
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}
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Operand res = context.BitwiseAnd(d, Const(~op.DestMask));
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res = context.BitwiseOr(res, context.BitwiseAnd(part, Const(op.DestMask)));
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SetIntA32(context, op.Rd, res);
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}
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public static void Bic(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res = context.BitwiseAnd(n, context.BitwiseNot(m));
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitAluStore(context, res);
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}
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public static void Clz(ArmEmitterContext context)
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{
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.CountLeadingZeros(m);
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EmitAluStore(context, res);
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}
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public static void Cmp(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Subtract(n, m);
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EmitNZFlagsCheck(context, res);
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EmitSubsCCheck(context, n, res);
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EmitSubsVCheck(context, n, m, res);
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}
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public static void Cmn(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Add(n, m);
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EmitNZFlagsCheck(context, res);
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EmitAddsCCheck(context, n, res);
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EmitAddsVCheck(context, n, m, res);
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}
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public static void Eor(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res = context.BitwiseExclusiveOr(n, m);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitAluStore(context, res);
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}
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public static void Mov(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand m = GetAluM(context);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, m);
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}
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EmitAluStore(context, m);
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}
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public static void Movt(ArmEmitterContext context)
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{
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OpCode32AluImm16 op = (OpCode32AluImm16)context.CurrOp;
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Operand d = GetIntA32(context, op.Rd);
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Operand imm = Const(op.Immediate << 16); // Immeditate value as top halfword.
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Operand res = context.BitwiseAnd(d, Const(0x0000ffff));
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res = context.BitwiseOr(res, imm);
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EmitAluStore(context, res);
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}
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public static void Mul(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res = context.Multiply(n, m);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitAluStore(context, res);
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}
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public static void Mvn(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand m = GetAluM(context);
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Operand res = context.BitwiseNot(m);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitAluStore(context, res);
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}
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public static void Orr(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res = context.BitwiseOr(n, m);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitAluStore(context, res);
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}
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public static void Pkh(ArmEmitterContext context)
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{
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OpCode32AluRsImm op = (OpCode32AluRsImm)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res;
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bool tbform = op.ShiftType == ShiftType.Asr;
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if (tbform)
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{
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res = context.BitwiseOr(context.BitwiseAnd(n, Const(0xFFFF0000)), context.BitwiseAnd(m, Const(0xFFFF)));
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}
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else
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{
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res = context.BitwiseOr(context.BitwiseAnd(m, Const(0xFFFF0000)), context.BitwiseAnd(n, Const(0xFFFF)));
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}
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EmitAluStore(context, res);
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}
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public static void Rbit(ArmEmitterContext context)
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{
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Operand m = GetAluM(context);
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Operand res = EmitReverseBits32Op(context, m);
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EmitAluStore(context, res);
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}
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public static void Rev(ArmEmitterContext context)
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{
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Operand m = GetAluM(context);
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Operand res = context.ByteSwap(m);
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EmitAluStore(context, res);
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}
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public static void Rev16(ArmEmitterContext context)
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{
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Operand m = GetAluM(context);
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Operand res = EmitReverseBytes16_32Op(context, m);
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EmitAluStore(context, res);
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}
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public static void Revsh(ArmEmitterContext context)
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{
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Operand m = GetAluM(context);
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Operand res = EmitReverseBytes16_32Op(context, m);
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EmitAluStore(context, context.SignExtend16(OperandType.I32, res));
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}
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public static void Rsc(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Subtract(m, n);
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Operand borrow = context.BitwiseExclusiveOr(GetFlag(PState.CFlag), Const(1));
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res = context.Subtract(res, borrow);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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EmitSbcsCCheck(context, m, n);
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EmitSubsVCheck(context, m, n, res);
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}
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EmitAluStore(context, res);
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}
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public static void Rsb(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Subtract(m, n);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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EmitSubsCCheck(context, m, res);
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EmitSubsVCheck(context, m, n, res);
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}
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EmitAluStore(context, res);
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}
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public static void Sbc(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Subtract(n, m);
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Operand borrow = context.BitwiseExclusiveOr(GetFlag(PState.CFlag), Const(1));
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res = context.Subtract(res, borrow);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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EmitSbcsCCheck(context, n, m);
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EmitSubsVCheck(context, n, m, res);
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}
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EmitAluStore(context, res);
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}
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public static void Sbfx(ArmEmitterContext context)
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{
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OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
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var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.
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Operand n = GetIntA32(context, op.Rn);
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Operand res = context.ShiftRightSI(context.ShiftLeft(n, Const(31 - msb)), Const(31 - op.Msb));
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SetIntA32(context, op.Rd, res);
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}
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public static void Sdiv(ArmEmitterContext context)
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{
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EmitDiv(context, false);
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}
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public static void Sub(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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Operand n = GetAluN(context);
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Operand m = GetAluM(context, setCarry: false);
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Operand res = context.Subtract(n, m);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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EmitSubsCCheck(context, n, res);
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EmitSubsVCheck(context, n, m, res);
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}
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EmitAluStore(context, res);
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}
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public static void Sxtb(ArmEmitterContext context)
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{
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EmitSignExtend(context, true, 8);
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}
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public static void Sxtb16(ArmEmitterContext context)
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{
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EmitExtend16(context, true);
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}
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public static void Sxth(ArmEmitterContext context)
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{
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EmitSignExtend(context, true, 16);
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}
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public static void Teq(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res = context.BitwiseExclusiveOr(n, m);
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EmitNZFlagsCheck(context, res);
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}
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public static void Tst(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand res = context.BitwiseAnd(n, m);
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EmitNZFlagsCheck(context, res);
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}
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public static void Ubfx(ArmEmitterContext context)
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{
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OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
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var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.
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Operand n = GetIntA32(context, op.Rn);
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Operand res = context.ShiftRightUI(context.ShiftLeft(n, Const(31 - msb)), Const(31 - op.Msb));
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SetIntA32(context, op.Rd, res);
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}
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public static void Udiv(ArmEmitterContext context)
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{
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EmitDiv(context, true);
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}
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public static void Uxtb(ArmEmitterContext context)
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{
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EmitSignExtend(context, false, 8);
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}
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public static void Uxtb16(ArmEmitterContext context)
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{
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EmitExtend16(context, false);
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}
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public static void Uxth(ArmEmitterContext context)
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{
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EmitSignExtend(context, false, 16);
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}
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private static void EmitSignExtend(ArmEmitterContext context, bool signed, int bits)
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{
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IOpCode32AluUx op = (IOpCode32AluUx)context.CurrOp;
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Operand m = GetAluM(context);
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Operand res;
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if (op.RotateBits == 0)
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{
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res = m;
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}
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else
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{
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Operand rotate = Const(op.RotateBits);
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res = context.RotateRight(m, rotate);
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}
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switch (bits)
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{
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case 8:
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res = (signed) ? context.SignExtend8(OperandType.I32, res) : context.ZeroExtend8(OperandType.I32, res);
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break;
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case 16:
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res = (signed) ? context.SignExtend16(OperandType.I32, res) : context.ZeroExtend16(OperandType.I32, res);
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break;
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}
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if (op.Add)
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{
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res = context.Add(res, GetAluN(context));
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}
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|
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EmitAluStore(context, res);
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}
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private static void EmitExtend16(ArmEmitterContext context, bool signed)
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|
{
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IOpCode32AluUx op = (IOpCode32AluUx)context.CurrOp;
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|
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|
Operand m = GetAluM(context);
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Operand res;
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|
|
|
if (op.RotateBits == 0)
|
|
{
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|
res = m;
|
|
}
|
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else
|
|
{
|
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Operand rotate = Const(op.RotateBits);
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res = context.RotateRight(m, rotate);
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|
}
|
|
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Operand low16, high16;
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if (signed)
|
|
{
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|
low16 = context.SignExtend8(OperandType.I32, res);
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high16 = context.SignExtend8(OperandType.I32, context.ShiftRightUI(res, Const(16)));
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}
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else
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|
{
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low16 = context.ZeroExtend8(OperandType.I32, res);
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high16 = context.ZeroExtend8(OperandType.I32, context.ShiftRightUI(res, Const(16)));
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|
}
|
|
|
|
if (op.Add)
|
|
{
|
|
Operand n = GetAluN(context);
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|
Operand lowAdd, highAdd;
|
|
if (signed)
|
|
{
|
|
lowAdd = context.SignExtend16(OperandType.I32, n);
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|
highAdd = context.SignExtend16(OperandType.I32, context.ShiftRightUI(n, Const(16)));
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|
}
|
|
else
|
|
{
|
|
lowAdd = context.ZeroExtend16(OperandType.I32, n);
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|
highAdd = context.ZeroExtend16(OperandType.I32, context.ShiftRightUI(n, Const(16)));
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|
}
|
|
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|
low16 = context.Add(low16, lowAdd);
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|
high16 = context.Add(high16, highAdd);
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|
}
|
|
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|
res = context.BitwiseOr(
|
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context.ZeroExtend16(OperandType.I32, low16),
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context.ShiftLeft(context.ZeroExtend16(OperandType.I32, high16), Const(16)));
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|
|
|
EmitAluStore(context, res);
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|
}
|
|
|
|
public static void EmitDiv(ArmEmitterContext context, bool unsigned)
|
|
{
|
|
Operand n = GetAluN(context);
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|
Operand m = GetAluM(context);
|
|
Operand zero = Const(m.Type, 0);
|
|
|
|
Operand divisorIsZero = context.ICompareEqual(m, zero);
|
|
|
|
Operand lblBadDiv = Label();
|
|
Operand lblEnd = Label();
|
|
|
|
context.BranchIfTrue(lblBadDiv, divisorIsZero);
|
|
|
|
if (!unsigned)
|
|
{
|
|
// ARM64 behaviour: If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
|
|
// TODO: tests to ensure A32 works the same
|
|
|
|
Operand intMin = Const(int.MinValue);
|
|
Operand minus1 = Const(-1);
|
|
|
|
Operand nIsIntMin = context.ICompareEqual(n, intMin);
|
|
Operand mIsMinus1 = context.ICompareEqual(m, minus1);
|
|
|
|
Operand lblGoodDiv = Label();
|
|
|
|
context.BranchIfFalse(lblGoodDiv, context.BitwiseAnd(nIsIntMin, mIsMinus1));
|
|
|
|
EmitAluStore(context, intMin);
|
|
|
|
context.Branch(lblEnd);
|
|
|
|
context.MarkLabel(lblGoodDiv);
|
|
}
|
|
|
|
Operand res = unsigned
|
|
? context.DivideUI(n, m)
|
|
: context.Divide(n, m);
|
|
|
|
EmitAluStore(context, res);
|
|
|
|
context.Branch(lblEnd);
|
|
|
|
context.MarkLabel(lblBadDiv);
|
|
|
|
EmitAluStore(context, zero);
|
|
|
|
context.MarkLabel(lblEnd);
|
|
}
|
|
|
|
private static void EmitAluStore(ArmEmitterContext context, Operand value)
|
|
{
|
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
|
EmitGenericAluStoreA32(context, op.Rd, op.SetFlags, value);
|
|
}
|
|
}
|
|
} |