ryujinx/ARMeilleure/IntermediateRepresentation
Wunk 17620d18db
ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147)
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection

Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.

* ARMeilleure: Add initial support for EVEX instruction encoding

Does not implement rounding, or exception controls.

* ARMeilleure: Add `X86Vpternlogd`

Accelerates the vector-`Not` instruction.

* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}

* ARMeilleure: Add check for `XCR0` flags

Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.

* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting

* ARMeilleure: Move XCR0 procedure to GetXcr0Eax

* ARMeilleure: Add `XCR0` to `FeatureInfo` structure

* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly

Avoids an additional allocation

* ARMeilleure: Formatting fixes

* ARMeilleure: Fix EVEX encoding src2 register index

> Just like in VEX prefix, vvvv is provided in inverted form.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`

Passes unit tests, verified instruction utilization

* ARMeilleure: Fix EVEX register operand designations

Operand 2 was being sourced improperly.

EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm

This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`

* ARMeilleure: PTC version bump

* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail

* ARMeilleure: Update EVEX encoding comment capitalization
2023-03-20 16:09:24 -03:00
..
BasicBlock.cs Use new ArgumentNullException and ObjectDisposedException throw-helper API (#4163) 2022-12-27 20:27:11 +01:00
BasicBlockFrequency.cs Implement block placement (#1549) 2020-09-19 20:00:24 -03:00
Comparison.cs Improve branch operations (#1442) 2020-08-05 08:52:33 +10:00
IIntrusiveListNode.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
Instruction.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
Intrinsic.cs ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147) 2023-03-20 16:09:24 -03:00
IntrusiveList.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
MemoryOperand.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
Multiplier.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
Operand.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
OperandKind.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
OperandType.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
Operation.cs Optimize HybridAllocator (#2637) 2021-09-29 01:38:37 +02:00
PhiOperation.cs Make structs readonly when applicable (#4002) 2022-12-05 14:47:39 +01:00
Register.cs Make structs readonly when applicable (#4002) 2022-12-05 14:47:39 +01:00
RegisterType.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00