9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
107 lines
5.4 KiB
C#
107 lines
5.4 KiB
C#
#define CcmpImm
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("CcmpImm")] // Tested: second half of 2018.
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public sealed class CpuTestCcmpImm : CpuTest
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{
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#if CcmpImm
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private const int RndCnt = 2;
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private const int RndCntImm = 2;
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private const int RndCntNzcv = 2;
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[Test, Pairwise, Description("CCMN <Xn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmn_64bit([Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0xBA400800; // CCMN X0, #0, #0, EQ
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Opcode |= ((Rn & 31) << 5);
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("CCMN <Wn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmn_32bit([Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0x3A400800; // CCMN W0, #0, #0, EQ
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Opcode |= ((Rn & 31) << 5);
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("CCMP <Xn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmp_64bit([Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0xFA400800; // CCMP X0, #0, #0, EQ
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Opcode |= ((Rn & 31) << 5);
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("CCMP <Wn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmp_32bit([Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0x7A400800; // CCMP W0, #0, #0, EQ
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Opcode |= ((Rn & 31) << 5);
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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