9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
135 lines
6.1 KiB
C#
135 lines
6.1 KiB
C#
#define Bfm
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Bfm")] // Tested: second half of 2018.
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public sealed class CpuTestBfm : CpuTest
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{
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#if Bfm
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private const int RndCnt = 2;
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private const int RndCntImmr = 2;
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private const int RndCntImms = 2;
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[Test, Pairwise, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")]
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public void Bfm_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Random(RndCnt)] ulong _Xd,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
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{
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uint Opcode = 0xB3400000; // BFM X0, X0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("BFM <Wd>, <Wn>, #<immr>, #<imms>")]
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public void Bfm_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Random(RndCnt)] uint _Wd,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
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{
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uint Opcode = 0x33000000; // BFM W0, W0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SBFM <Xd>, <Xn>, #<immr>, #<imms>")]
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public void Sbfm_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
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{
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uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SBFM <Wd>, <Wn>, #<immr>, #<imms>")]
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public void Sbfm_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
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{
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uint Opcode = 0x13000000; // SBFM W0, W0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("UBFM <Xd>, <Xn>, #<immr>, #<imms>")]
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public void Ubfm_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
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{
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uint Opcode = 0xD3400000; // UBFM X0, X0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("UBFM <Wd>, <Wn>, #<immr>, #<imms>")]
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public void Ubfm_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
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{
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uint Opcode = 0x53000000; // UBFM W0, W0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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