56 lines
2.0 KiB
C#
56 lines
2.0 KiB
C#
using System;
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namespace ARMeilleure.Decoders
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{
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abstract class OpCode32SimdBase : OpCode32, IOpCode32Simd
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{
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public int Vd { get; protected set; }
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public int Vm { get; protected set; }
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public int Size { get; protected set; }
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// Helpers to index doublewords within quad words. Essentially, looping over the vector starts at quadword Q and index Fx or Ix within it,
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// depending on instruction type.
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//
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// Qx: The quadword register that the target vector is contained in.
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// Ix: The starting index of the target vector within the quadword, with size treated as integer.
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// Fx: The starting index of the target vector within the quadword, with size treated as floating point. (16 or 32)
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public int Qd => GetQuadwordIndex(Vd);
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public int Id => GetQuadwordSubindex(Vd) << (3 - Size);
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public int Fd => GetQuadwordSubindex(Vd) << (1 - (Size & 1)); // When the top bit is truncated, 1 is fp16 which is an optional extension in ARMv8.2. We always assume 64.
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public int Qm => GetQuadwordIndex(Vm);
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public int Im => GetQuadwordSubindex(Vm) << (3 - Size);
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public int Fm => GetQuadwordSubindex(Vm) << (1 - (Size & 1));
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protected int GetQuadwordIndex(int index)
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{
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switch (RegisterSize)
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{
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case RegisterSize.Simd128:
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case RegisterSize.Simd64:
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return index >> 1;
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}
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throw new InvalidOperationException();
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}
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protected int GetQuadwordSubindex(int index)
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{
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switch (RegisterSize)
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{
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case RegisterSize.Simd128:
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return 0;
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case RegisterSize.Simd64:
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return index & 1;
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}
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throw new InvalidOperationException();
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}
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protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
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{
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IsThumb = isThumb;
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}
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}
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}
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