9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
193 lines
7.5 KiB
C#
193 lines
7.5 KiB
C#
#define Alu
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Alu")] // Tested: second half of 2018.
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public sealed class CpuTestAlu : CpuTest
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{
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#if Alu
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private const int RndCnt = 2;
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[Test, Pairwise, Description("CLS <Xd>, <Xn>")]
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public void Cls_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
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{
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uint Opcode = 0xDAC01400; // CLS X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("CLS <Wd>, <Wn>")]
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public void Cls_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
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{
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uint Opcode = 0x5AC01400; // CLS W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("CLZ <Xd>, <Xn>")]
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public void Clz_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
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{
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uint Opcode = 0xDAC01000; // CLZ X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("CLZ <Wd>, <Wn>")]
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public void Clz_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
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{
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uint Opcode = 0x5AC01000; // CLZ W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("RBIT <Xd>, <Xn>")]
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public void Rbit_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
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{
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uint Opcode = 0xDAC00000; // RBIT X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("RBIT <Wd>, <Wn>")]
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public void Rbit_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
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{
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uint Opcode = 0x5AC00000; // RBIT W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("REV16 <Xd>, <Xn>")]
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public void Rev16_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
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{
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uint Opcode = 0xDAC00400; // REV16 X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("REV16 <Wd>, <Wn>")]
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public void Rev16_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
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{
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uint Opcode = 0x5AC00400; // REV16 W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("REV32 <Xd>, <Xn>")]
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public void Rev32_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
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{
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uint Opcode = 0xDAC00800; // REV32 X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("REV <Wd>, <Wn>")]
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public void Rev32_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
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{
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uint Opcode = 0x5AC00800; // REV W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("REV64 <Xd>, <Xn>")]
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public void Rev64_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
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{
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uint Opcode = 0xDAC00C00; // REV64 X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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