790 lines
31 KiB
C#
790 lines
31 KiB
C#
using ARMeilleure.CodeGen.RegisterAllocators;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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using static ARMeilleure.IntermediateRepresentation.Operation.Factory;
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namespace ARMeilleure.CodeGen.X86
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{
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class PreAllocator
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{
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public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out int maxCallArgs)
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{
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maxCallArgs = -1;
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Span<Operation> buffer = default;
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CallConvName callConv = CallingConvention.GetCurrentCallConv();
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Operand[] preservedArgs = new Operand[CallingConvention.GetArgumentsOnRegsCount()];
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for (BasicBlock block = cctx.Cfg.Blocks.First; block != null; block = block.ListNext)
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{
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Operation nextNode;
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for (Operation node = block.Operations.First; node != default; node = nextNode)
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{
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nextNode = node.ListNext;
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if (node.Instruction == Instruction.Phi)
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{
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continue;
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}
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InsertConstantRegCopies(block.Operations, node);
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InsertDestructiveRegCopies(block.Operations, node);
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InsertConstrainedRegCopies(block.Operations, node);
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switch (node.Instruction)
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{
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case Instruction.Call:
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// Get the maximum number of arguments used on a call.
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// On windows, when a struct is returned from the call,
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// we also need to pass the pointer where the struct
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// should be written on the first argument.
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int argsCount = node.SourcesCount - 1;
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if (node.Destination != default && node.Destination.Type == OperandType.V128)
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{
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argsCount++;
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}
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if (maxCallArgs < argsCount)
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{
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maxCallArgs = argsCount;
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}
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// Copy values to registers expected by the function
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// being called, as mandated by the ABI.
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if (callConv == CallConvName.Windows)
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{
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PreAllocatorWindows.InsertCallCopies(block.Operations, stackAlloc, node);
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}
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else /* if (callConv == CallConvName.SystemV) */
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{
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PreAllocatorSystemV.InsertCallCopies(block.Operations, node);
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}
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break;
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case Instruction.ConvertToFPUI:
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GenerateConvertToFPUI(block.Operations, node);
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break;
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case Instruction.LoadArgument:
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if (callConv == CallConvName.Windows)
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{
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nextNode = PreAllocatorWindows.InsertLoadArgumentCopy(cctx, ref buffer, block.Operations, preservedArgs, node);
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}
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else /* if (callConv == CallConvName.SystemV) */
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{
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nextNode = PreAllocatorSystemV.InsertLoadArgumentCopy(cctx, ref buffer, block.Operations, preservedArgs, node);
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}
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break;
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case Instruction.Negate:
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if (!node.GetSource(0).Type.IsInteger())
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{
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GenerateNegate(block.Operations, node);
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}
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break;
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case Instruction.Return:
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if (callConv == CallConvName.Windows)
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{
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PreAllocatorWindows.InsertReturnCopy(cctx, block.Operations, preservedArgs, node);
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}
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else /* if (callConv == CallConvName.SystemV) */
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{
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PreAllocatorSystemV.InsertReturnCopy(block.Operations, node);
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}
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break;
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case Instruction.Tailcall:
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if (callConv == CallConvName.Windows)
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{
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PreAllocatorWindows.InsertTailcallCopies(block.Operations, stackAlloc, node);
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}
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else
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{
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PreAllocatorSystemV.InsertTailcallCopies(block.Operations, stackAlloc, node);
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}
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break;
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case Instruction.VectorInsert8:
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if (!HardwareCapabilities.SupportsSse41)
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{
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GenerateVectorInsert8(block.Operations, node);
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}
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break;
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case Instruction.Extended:
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if (node.Intrinsic == Intrinsic.X86Mxcsrmb || node.Intrinsic == Intrinsic.X86Mxcsrub)
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{
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int stackOffset = stackAlloc.Allocate(OperandType.I32);
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node.SetSources(new Operand[] { Const(stackOffset), node.GetSource(0) });
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}
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break;
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}
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}
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}
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}
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protected static void InsertConstantRegCopies(IntrusiveList<Operation> nodes, Operation node)
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{
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if (node.SourcesCount == 0 || IsXmmIntrinsic(node))
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{
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return;
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}
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Instruction inst = node.Instruction;
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Operand src1 = node.GetSource(0);
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Operand src2;
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if (src1.Kind == OperandKind.Constant)
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{
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if (!src1.Type.IsInteger())
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{
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// Handle non-integer types (FP32, FP64 and V128).
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// For instructions without an immediate operand, we do the following:
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// - Insert a copy with the constant value (as integer) to a GPR.
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// - Insert a copy from the GPR to a XMM register.
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// - Replace the constant use with the XMM register.
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src1 = AddXmmCopy(nodes, node, src1);
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node.SetSource(0, src1);
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}
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else if (!HasConstSrc1(inst))
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{
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// Handle integer types.
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// Most ALU instructions accepts a 32-bits immediate on the second operand.
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// We need to ensure the following:
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// - If the constant is on operand 1, we need to move it.
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// -- But first, we try to swap operand 1 and 2 if the instruction is commutative.
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// -- Doing so may allow us to encode the constant as operand 2 and avoid a copy.
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// - If the constant is on operand 2, we check if the instruction supports it,
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// if not, we also add a copy. 64-bits constants are usually not supported.
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if (IsCommutative(node))
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{
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src2 = node.GetSource(1);
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Operand temp = src1;
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src1 = src2;
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src2 = temp;
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node.SetSource(0, src1);
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node.SetSource(1, src2);
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}
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if (src1.Kind == OperandKind.Constant)
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{
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src1 = AddCopy(nodes, node, src1);
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node.SetSource(0, src1);
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}
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}
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}
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if (node.SourcesCount < 2)
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{
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return;
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}
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src2 = node.GetSource(1);
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if (src2.Kind == OperandKind.Constant)
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{
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if (!src2.Type.IsInteger())
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{
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src2 = AddXmmCopy(nodes, node, src2);
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node.SetSource(1, src2);
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}
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else if (!HasConstSrc2(inst) || CodeGenCommon.IsLongConst(src2))
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{
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src2 = AddCopy(nodes, node, src2);
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node.SetSource(1, src2);
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}
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}
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}
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protected static void InsertConstrainedRegCopies(IntrusiveList<Operation> nodes, Operation node)
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{
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Operand dest = node.Destination;
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switch (node.Instruction)
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{
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case Instruction.CompareAndSwap:
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case Instruction.CompareAndSwap16:
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case Instruction.CompareAndSwap8:
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{
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OperandType type = node.GetSource(1).Type;
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if (type == OperandType.V128)
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{
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// Handle the many restrictions of the compare and exchange (16 bytes) instruction:
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// - The expected value should be in RDX:RAX.
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// - The new value to be written should be in RCX:RBX.
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// - The value at the memory location is loaded to RDX:RAX.
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void SplitOperand(Operand source, Operand lr, Operand hr)
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{
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nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0)));
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nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1)));
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}
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Operand rax = Gpr(X86Register.Rax, OperandType.I64);
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Operand rbx = Gpr(X86Register.Rbx, OperandType.I64);
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Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
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Operand rdx = Gpr(X86Register.Rdx, OperandType.I64);
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SplitOperand(node.GetSource(1), rax, rdx);
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SplitOperand(node.GetSource(2), rbx, rcx);
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Operation operation = node;
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node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax));
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nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1)));
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operation.SetDestinations(new Operand[] { rdx, rax });
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operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx });
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}
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else
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{
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// Handle the many restrictions of the compare and exchange (32/64) instruction:
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// - The expected value should be in (E/R)AX.
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// - The value at the memory location is loaded to (E/R)AX.
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Operand expected = node.GetSource(1);
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Operand newValue = node.GetSource(2);
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Operand rax = Gpr(X86Register.Rax, expected.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected));
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// We need to store the new value into a temp, since it may
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// be a constant, and this instruction does not support immediate operands.
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Operand temp = Local(newValue.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue));
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node.SetSources(new Operand[] { node.GetSource(0), rax, temp });
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
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node.Destination = rax;
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}
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break;
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}
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case Instruction.Divide:
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case Instruction.DivideUI:
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{
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// Handle the many restrictions of the division instructions:
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// - The dividend is always in RDX:RAX.
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// - The result is always in RAX.
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// - Additionally it also writes the remainder in RDX.
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if (dest.Type.IsInteger())
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{
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Operand src1 = node.GetSource(0);
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Operand rax = Gpr(X86Register.Rax, src1.Type);
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Operand rdx = Gpr(X86Register.Rdx, src1.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
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nodes.AddBefore(node, Operation(Instruction.Clobber, rdx));
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
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node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) });
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node.Destination = rax;
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}
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break;
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}
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case Instruction.Extended:
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{
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bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
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node.Intrinsic == Intrinsic.X86Blendvps ||
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node.Intrinsic == Intrinsic.X86Pblendvb;
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// BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
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// SHA256RNDS2 always has an implied XMM0 as a last operand.
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if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2)
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{
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Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128);
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nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2)));
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node.SetSource(2, xmm0);
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}
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break;
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}
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case Instruction.Multiply64HighSI:
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case Instruction.Multiply64HighUI:
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{
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// Handle the many restrictions of the i64 * i64 = i128 multiply instructions:
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// - The multiplicand is always in RAX.
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// - The lower 64-bits of the result is always in RAX.
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// - The higher 64-bits of the result is always in RDX.
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Operand src1 = node.GetSource(0);
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Operand rax = Gpr(X86Register.Rax, src1.Type);
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Operand rdx = Gpr(X86Register.Rdx, src1.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
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node.SetSource(0, rax);
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx));
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node.SetDestinations(new Operand[] { rdx, rax });
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break;
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}
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case Instruction.RotateRight:
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case Instruction.ShiftLeft:
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case Instruction.ShiftRightSI:
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case Instruction.ShiftRightUI:
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{
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// The shift register is always implied to be CL (low 8-bits of RCX or ECX).
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if (node.GetSource(1).Kind == OperandKind.LocalVariable)
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{
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Operand rcx = Gpr(X86Register.Rcx, OperandType.I32);
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nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1)));
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node.SetSource(1, rcx);
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}
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break;
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}
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}
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}
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protected static void InsertDestructiveRegCopies(IntrusiveList<Operation> nodes, Operation node)
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{
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if (node.Destination == default || node.SourcesCount == 0)
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{
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return;
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}
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Instruction inst = node.Instruction;
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Operand dest = node.Destination;
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Operand src1 = node.GetSource(0);
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// The multiply instruction (that maps to IMUL) is somewhat special, it has
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// a three operand form where the second source is a immediate value.
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bool threeOperandForm = inst == Instruction.Multiply && node.GetSource(1).Kind == OperandKind.Constant;
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if (IsSameOperandDestSrc1(node) && src1.Kind == OperandKind.LocalVariable && !threeOperandForm)
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{
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bool useNewLocal = false;
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for (int srcIndex = 1; srcIndex < node.SourcesCount; srcIndex++)
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{
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if (node.GetSource(srcIndex) == dest)
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{
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useNewLocal = true;
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break;
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}
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}
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if (useNewLocal)
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{
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// Dest is being used as some source already, we need to use a new
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// local to store the temporary value, otherwise the value on dest
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// local would be overwritten.
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Operand temp = Local(dest.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, temp, src1));
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node.SetSource(0, temp);
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, temp));
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node.Destination = temp;
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}
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else
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{
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nodes.AddBefore(node, Operation(Instruction.Copy, dest, src1));
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node.SetSource(0, dest);
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}
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}
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else if (inst == Instruction.ConditionalSelect)
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{
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Operand src2 = node.GetSource(1);
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Operand src3 = node.GetSource(2);
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if (src1 == dest || src2 == dest)
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{
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Operand temp = Local(dest.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, temp, src3));
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node.SetSource(2, temp);
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, temp));
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node.Destination = temp;
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}
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else
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{
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nodes.AddBefore(node, Operation(Instruction.Copy, dest, src3));
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node.SetSource(2, dest);
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}
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}
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}
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private static void GenerateConvertToFPUI(IntrusiveList<Operation> nodes, Operation node)
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{
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// Unsigned integer to FP conversions are not supported on X86.
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// We need to turn them into signed integer to FP conversions, and
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// adjust the final result.
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Operand dest = node.Destination;
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Operand source = node.GetSource(0);
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Debug.Assert(source.Type.IsInteger(), $"Invalid source type \"{source.Type}\".");
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Operation currentNode = node;
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if (source.Type == OperandType.I32)
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{
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// For 32-bits integers, we can just zero-extend to 64-bits,
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// and then use the 64-bits signed conversion instructions.
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Operand zex = Local(OperandType.I64);
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node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source));
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node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex));
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}
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else /* if (source.Type == OperandType.I64) */
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{
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// For 64-bits integers, we need to do the following:
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// - Ensure that the integer has the most significant bit clear.
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// -- This can be done by shifting the value right by 1, that is, dividing by 2.
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// -- The least significant bit is lost in this case though.
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// - We can then convert the shifted value with a signed integer instruction.
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// - The result still needs to be corrected after that.
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// -- First, we need to multiply the result by 2, as we divided it by 2 before.
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// --- This can be done efficiently by adding the result to itself.
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// -- Then, we need to add the least significant bit that was shifted out.
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// --- We can convert the least significant bit to float, and add it to the result.
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Operand lsb = Local(OperandType.I64);
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Operand half = Local(OperandType.I64);
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Operand lsbF = Local(dest.Type);
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node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source));
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node = nodes.AddAfter(node, Operation(Instruction.Copy, half, source));
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node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L)));
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node = nodes.AddAfter(node, Operation(Instruction.ShiftRightUI, half, half, Const(1)));
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node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, lsbF, lsb));
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node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, half));
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node = nodes.AddAfter(node, Operation(Instruction.Add, dest, dest, dest));
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nodes.AddAfter(node, Operation(Instruction.Add, dest, dest, lsbF));
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}
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Delete(nodes, currentNode);
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}
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private static void GenerateNegate(IntrusiveList<Operation> nodes, Operation node)
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{
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// There's no SSE FP negate instruction, so we need to transform that into
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// a XOR of the value to be negated with a mask with the highest bit set.
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// This also produces -0 for a negation of the value 0.
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Operand dest = node.Destination;
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Operand source = node.GetSource(0);
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Debug.Assert(dest.Type == OperandType.FP32 ||
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dest.Type == OperandType.FP64, $"Invalid destination type \"{dest.Type}\".");
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Operation currentNode = node;
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Operand res = Local(dest.Type);
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node = nodes.AddAfter(node, Operation(Instruction.VectorOne, res));
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if (dest.Type == OperandType.FP32)
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{
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node = nodes.AddAfter(node, Operation(Intrinsic.X86Pslld, res, res, Const(31)));
|
|
}
|
|
else /* if (dest.Type == OperandType.FP64) */
|
|
{
|
|
node = nodes.AddAfter(node, Operation(Intrinsic.X86Psllq, res, res, Const(63)));
|
|
}
|
|
|
|
node = nodes.AddAfter(node, Operation(Intrinsic.X86Xorps, res, res, source));
|
|
|
|
nodes.AddAfter(node, Operation(Instruction.Copy, dest, res));
|
|
|
|
Delete(nodes, currentNode);
|
|
}
|
|
|
|
private static void GenerateVectorInsert8(IntrusiveList<Operation> nodes, Operation node)
|
|
{
|
|
// Handle vector insertion, when SSE 4.1 is not supported.
|
|
Operand dest = node.Destination;
|
|
Operand src1 = node.GetSource(0); // Vector
|
|
Operand src2 = node.GetSource(1); // Value
|
|
Operand src3 = node.GetSource(2); // Index
|
|
|
|
Debug.Assert(src3.Kind == OperandKind.Constant);
|
|
|
|
byte index = src3.AsByte();
|
|
|
|
Debug.Assert(index < 16);
|
|
|
|
Operation currentNode = node;
|
|
|
|
Operand temp1 = Local(OperandType.I32);
|
|
Operand temp2 = Local(OperandType.I32);
|
|
|
|
node = nodes.AddAfter(node, Operation(Instruction.Copy, temp2, src2));
|
|
|
|
Operation vextOp = Operation(Instruction.VectorExtract16, temp1, src1, Const(index >> 1));
|
|
|
|
node = nodes.AddAfter(node, vextOp);
|
|
|
|
if ((index & 1) != 0)
|
|
{
|
|
node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp1, temp1));
|
|
node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8)));
|
|
node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
|
|
}
|
|
else
|
|
{
|
|
node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp2, temp2));
|
|
node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00)));
|
|
node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
|
|
}
|
|
|
|
Operation vinsOp = Operation(Instruction.VectorInsert16, dest, src1, temp1, Const(index >> 1));
|
|
|
|
nodes.AddAfter(node, vinsOp);
|
|
|
|
Delete(nodes, currentNode);
|
|
}
|
|
|
|
protected static Operand AddXmmCopy(IntrusiveList<Operation> nodes, Operation node, Operand source)
|
|
{
|
|
Operand temp = Local(source.Type);
|
|
Operand intConst = AddCopy(nodes, node, GetIntConst(source));
|
|
|
|
Operation copyOp = Operation(Instruction.VectorCreateScalar, temp, intConst);
|
|
|
|
nodes.AddBefore(node, copyOp);
|
|
|
|
return temp;
|
|
}
|
|
|
|
protected static Operand AddCopy(IntrusiveList<Operation> nodes, Operation node, Operand source)
|
|
{
|
|
Operand temp = Local(source.Type);
|
|
|
|
Operation copyOp = Operation(Instruction.Copy, temp, source);
|
|
|
|
nodes.AddBefore(node, copyOp);
|
|
|
|
return temp;
|
|
}
|
|
|
|
private static Operand GetIntConst(Operand value)
|
|
{
|
|
if (value.Type == OperandType.FP32)
|
|
{
|
|
return Const(value.AsInt32());
|
|
}
|
|
else if (value.Type == OperandType.FP64)
|
|
{
|
|
return Const(value.AsInt64());
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
protected static void Delete(IntrusiveList<Operation> nodes, Operation node)
|
|
{
|
|
node.Destination = default;
|
|
|
|
for (int index = 0; index < node.SourcesCount; index++)
|
|
{
|
|
node.SetSource(index, default);
|
|
}
|
|
|
|
nodes.Remove(node);
|
|
}
|
|
|
|
protected static Operand Gpr(X86Register register, OperandType type)
|
|
{
|
|
return Register((int)register, RegisterType.Integer, type);
|
|
}
|
|
|
|
protected static Operand Xmm(X86Register register, OperandType type)
|
|
{
|
|
return Register((int)register, RegisterType.Vector, type);
|
|
}
|
|
|
|
private static bool IsSameOperandDestSrc1(Operation operation)
|
|
{
|
|
switch (operation.Instruction)
|
|
{
|
|
case Instruction.Add:
|
|
return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger();
|
|
case Instruction.Multiply:
|
|
case Instruction.Subtract:
|
|
return !HardwareCapabilities.SupportsVexEncoding || operation.Destination.Type.IsInteger();
|
|
|
|
case Instruction.BitwiseAnd:
|
|
case Instruction.BitwiseExclusiveOr:
|
|
case Instruction.BitwiseNot:
|
|
case Instruction.BitwiseOr:
|
|
case Instruction.ByteSwap:
|
|
case Instruction.Negate:
|
|
case Instruction.RotateRight:
|
|
case Instruction.ShiftLeft:
|
|
case Instruction.ShiftRightSI:
|
|
case Instruction.ShiftRightUI:
|
|
return true;
|
|
|
|
case Instruction.Divide:
|
|
return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger();
|
|
|
|
case Instruction.VectorInsert:
|
|
case Instruction.VectorInsert16:
|
|
case Instruction.VectorInsert8:
|
|
return !HardwareCapabilities.SupportsVexEncoding;
|
|
|
|
case Instruction.Extended:
|
|
return IsIntrinsicSameOperandDestSrc1(operation);
|
|
}
|
|
|
|
return IsVexSameOperandDestSrc1(operation);
|
|
}
|
|
|
|
private static bool IsIntrinsicSameOperandDestSrc1(Operation operation)
|
|
{
|
|
IntrinsicInfo info = IntrinsicTable.GetInfo(operation.Intrinsic);
|
|
|
|
return info.Type == IntrinsicType.Crc32 || info.Type == IntrinsicType.Fma || IsVexSameOperandDestSrc1(operation);
|
|
}
|
|
|
|
private static bool IsVexSameOperandDestSrc1(Operation operation)
|
|
{
|
|
if (IsIntrinsic(operation.Instruction))
|
|
{
|
|
IntrinsicInfo info = IntrinsicTable.GetInfo(operation.Intrinsic);
|
|
|
|
bool hasVex = HardwareCapabilities.SupportsVexEncoding && Assembler.SupportsVexPrefix(info.Inst);
|
|
|
|
bool isUnary = operation.SourcesCount < 2;
|
|
|
|
bool hasVecDest = operation.Destination != default && operation.Destination.Type == OperandType.V128;
|
|
|
|
return !hasVex && !isUnary && hasVecDest;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
private static bool HasConstSrc1(Instruction inst)
|
|
{
|
|
switch (inst)
|
|
{
|
|
case Instruction.Copy:
|
|
case Instruction.LoadArgument:
|
|
case Instruction.Spill:
|
|
case Instruction.SpillArg:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
private static bool HasConstSrc2(Instruction inst)
|
|
{
|
|
switch (inst)
|
|
{
|
|
case Instruction.Add:
|
|
case Instruction.BitwiseAnd:
|
|
case Instruction.BitwiseExclusiveOr:
|
|
case Instruction.BitwiseOr:
|
|
case Instruction.BranchIf:
|
|
case Instruction.Compare:
|
|
case Instruction.Multiply:
|
|
case Instruction.RotateRight:
|
|
case Instruction.ShiftLeft:
|
|
case Instruction.ShiftRightSI:
|
|
case Instruction.ShiftRightUI:
|
|
case Instruction.Store:
|
|
case Instruction.Store16:
|
|
case Instruction.Store8:
|
|
case Instruction.Subtract:
|
|
case Instruction.VectorExtract:
|
|
case Instruction.VectorExtract16:
|
|
case Instruction.VectorExtract8:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
private static bool IsCommutative(Operation operation)
|
|
{
|
|
switch (operation.Instruction)
|
|
{
|
|
case Instruction.Add:
|
|
case Instruction.BitwiseAnd:
|
|
case Instruction.BitwiseExclusiveOr:
|
|
case Instruction.BitwiseOr:
|
|
case Instruction.Multiply:
|
|
return true;
|
|
|
|
case Instruction.BranchIf:
|
|
case Instruction.Compare:
|
|
{
|
|
Operand comp = operation.GetSource(2);
|
|
|
|
Debug.Assert(comp.Kind == OperandKind.Constant);
|
|
|
|
var compType = (Comparison)comp.AsInt32();
|
|
|
|
return compType == Comparison.Equal || compType == Comparison.NotEqual;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
private static bool IsIntrinsic(Instruction inst)
|
|
{
|
|
return inst == Instruction.Extended;
|
|
}
|
|
|
|
private static bool IsXmmIntrinsic(Operation operation)
|
|
{
|
|
if (operation.Instruction != Instruction.Extended)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
IntrinsicInfo info = IntrinsicTable.GetInfo(operation.Intrinsic);
|
|
|
|
return info.Type != IntrinsicType.Crc32;
|
|
}
|
|
}
|
|
} |