68e15c1a74
* Begin work on A32 SIMD Intrinsics * More instructions, some cleanup. * Intrinsics for Move instructions (zip etc) These pass the existing tests. * Intrinsics for some of Cvt While doing this I noticed that the conversion for int/fp was incorrect in the slow path. I'll fix this in the original repo. * Intrinsics for more Arithmetic instructions. * Intrinsics for Vext * Fix VEXT Intrinsic for double words. * Use InsertPs to move scalar values. * Cleanup, fix VPADD.f32 and VMIN signed integer. * Cleanup, add SSE2 support for scalar insert. Works similarly to the IR scalar insert, but obviously this one works directly on V128. * Minor cleanup. * Enable intrinsic for FP64 to integer conversion. * Address feedback apart from splitting out intrinsic float abs Also: bad VREV encodings as undefined rather than throwing in translation. * Move float abs to helper, fix bug with cvt * Rename opc2 & 3 to match A32 docs, use ArgumentOutOfRangeException appropriately. * Get name of variable at compilation rather than string literal. * Use correct double sign mask.
1022 lines
36 KiB
C#
1022 lines
36 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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using Func1I = Func<Operand, Operand>;
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using Func2I = Func<Operand, Operand, Operand>;
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using Func3I = Func<Operand, Operand, Operand, Operand>;
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static class InstEmitSimdHelper32
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{
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public static (int, int) GetQuadwordAndSubindex(int index, RegisterSize size)
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{
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switch (size)
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{
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case RegisterSize.Simd128:
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return (index >> 1, 0);
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case RegisterSize.Simd64:
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case RegisterSize.Int64:
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return (index >> 1, index & 1);
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case RegisterSize.Int32:
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return (index >> 2, index & 3);
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}
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throw new ArgumentException("Unrecognized Vector Register Size.");
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}
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public static Operand ExtractScalar(ArmEmitterContext context, OperandType type, int reg)
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{
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Debug.Assert(type != OperandType.V128);
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if (type == OperandType.FP64 || type == OperandType.I64)
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{
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// From dreg.
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return context.VectorExtract(type, GetVecA32(reg >> 1), reg & 1);
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}
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else
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{
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// From sreg.
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return context.VectorExtract(type, GetVecA32(reg >> 2), reg & 3);
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}
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}
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public static void InsertScalar(ArmEmitterContext context, int reg, Operand value)
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{
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Debug.Assert(value.Type != OperandType.V128);
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Operand vec, insert;
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if (value.Type == OperandType.FP64 || value.Type == OperandType.I64)
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{
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// From dreg.
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vec = GetVecA32(reg >> 1);
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insert = context.VectorInsert(vec, value, reg & 1);
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}
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else
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{
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// From sreg.
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vec = GetVecA32(reg >> 2);
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insert = context.VectorInsert(vec, value, reg & 3);
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}
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context.Copy(vec, insert);
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}
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public static void EmitVectorImmUnaryOp32(ArmEmitterContext context, Func1I emit)
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{
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IOpCode32SimdImm op = (IOpCode32SimdImm)context.CurrOp;
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Operand imm = Const(op.Immediate);
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int elems = op.Elems;
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(int index, int subIndex) = GetQuadwordAndSubindex(op.Vd, op.RegisterSize);
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Operand vec = GetVecA32(index);
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Operand res = vec;
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for (int item = 0; item < elems; item++)
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{
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res = EmitVectorInsert(context, res, emit(imm), item + subIndex * elems, op.Size);
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}
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context.Copy(vec, res);
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}
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public static void EmitScalarUnaryOpF32(ArmEmitterContext context, Func1I emit)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(m));
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}
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public static void EmitScalarBinaryOpF32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand n = ExtractScalar(context, type, op.Vn);
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(n, m));
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}
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public static void EmitScalarBinaryOpI32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.I64 : OperandType.I32;
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if (op.Size < 2)
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{
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throw new NotSupportedException("Cannot perform a scalar SIMD operation on integers smaller than 32 bits.");
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}
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Operand n = ExtractScalar(context, type, op.Vn);
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(n, m));
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}
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public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Func3I emit)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand a = ExtractScalar(context, type, op.Vd);
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Operand n = ExtractScalar(context, type, op.Vn);
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(a, n, m));
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}
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public static void EmitVectorUnaryOpF32(ArmEmitterContext context, Func1I emit)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> sizeF + 2;
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand me = context.VectorExtract(type, GetVecA32(op.Qm), op.Fm + index);
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res = context.VectorInsert(res, emit(me), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorBinaryOpF32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> (sizeF + 2);
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
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Operand me = context.VectorExtract(type, GetVecA32(op.Qm), op.Fm + index);
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res = context.VectorInsert(res, emit(ne, me), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorTernaryOpF32(ArmEmitterContext context, Func3I emit)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> sizeF + 2;
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand de = context.VectorExtract(type, GetVecA32(op.Qd), op.Fd + index);
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Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
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Operand me = context.VectorExtract(type, GetVecA32(op.Qm), op.Fm + index);
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res = context.VectorInsert(res, emit(de, ne, me), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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// Integer
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public static void EmitVectorUnaryOpI32(ArmEmitterContext context, Func1I emit, bool signed)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(me), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorBinaryOpI32(ArmEmitterContext context, Func2I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(ne, me), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorTernaryOpI32(ArmEmitterContext context, Func3I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed);
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(de, ne, me), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorUnaryOpSx32(ArmEmitterContext context, Func1I emit)
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{
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EmitVectorUnaryOpI32(context, emit, true);
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}
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public static void EmitVectorBinaryOpSx32(ArmEmitterContext context, Func2I emit)
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{
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EmitVectorBinaryOpI32(context, emit, true);
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}
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public static void EmitVectorTernaryOpSx32(ArmEmitterContext context, Func3I emit)
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{
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EmitVectorTernaryOpI32(context, emit, true);
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}
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public static void EmitVectorUnaryOpZx32(ArmEmitterContext context, Func1I emit)
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{
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EmitVectorUnaryOpI32(context, emit, false);
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}
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public static void EmitVectorBinaryOpZx32(ArmEmitterContext context, Func2I emit)
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{
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EmitVectorBinaryOpI32(context, emit, false);
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}
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public static void EmitVectorTernaryOpZx32(ArmEmitterContext context, Func3I emit)
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{
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EmitVectorTernaryOpI32(context, emit, false);
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}
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// Vector by scalar
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public static void EmitVectorByScalarOpF32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> sizeF + 2;
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Operand m = ExtractScalar(context, type, op.Vm);
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
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res = context.VectorInsert(res, emit(ne, m), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorByScalarOpI32(ArmEmitterContext context, Func2I emit, bool signed)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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Operand m = EmitVectorExtract32(context, op.Vm >> (4 - op.Size), op.Vm & ((1 << (4 - op.Size)) - 1), op.Size, signed);
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(ne, m), op.In + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorsByScalarOpF32(ArmEmitterContext context, Func3I emit)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> sizeF + 2;
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Operand m = ExtractScalar(context, type, op.Vm);
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand de = context.VectorExtract(type, GetVecA32(op.Qd), op.Fd + index);
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Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
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res = context.VectorInsert(res, emit(de, ne, m), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorsByScalarOpI32(ArmEmitterContext context, Func3I emit, bool signed)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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Operand m = EmitVectorExtract32(context, op.Vm >> (4 - op.Size), op.Vm & ((1 << (4 - op.Size)) - 1), op.Size, signed);
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed);
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(de, ne, m), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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// Pairwise
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public static void EmitVectorPairwiseOpF32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> (sizeF + 2);
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int pairs = elems >> 1;
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Operand res = GetVecA32(op.Qd);
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Operand mvec = GetVecA32(op.Qm);
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Operand nvec = GetVecA32(op.Qn);
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for (int index = 0; index < pairs; index++)
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{
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int pairIndex = index << 1;
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Operand n1 = context.VectorExtract(type, nvec, op.Fn + pairIndex);
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Operand n2 = context.VectorExtract(type, nvec, op.Fn + pairIndex + 1);
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res = context.VectorInsert(res, emit(n1, n2), op.Fd + index);
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Operand m1 = context.VectorExtract(type, mvec, op.Fm + pairIndex);
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Operand m2 = context.VectorExtract(type, mvec, op.Fm + pairIndex + 1);
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res = context.VectorInsert(res, emit(m1, m2), op.Fd + index + pairs);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorPairwiseOpI32(ArmEmitterContext context, Func2I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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int elems = op.GetBytesCount() >> op.Size;
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int pairs = elems >> 1;
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < pairs; index++)
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{
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int pairIndex = index << 1;
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Operand n1 = EmitVectorExtract32(context, op.Qn, op.In + pairIndex, op.Size, signed);
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Operand n2 = EmitVectorExtract32(context, op.Qn, op.In + pairIndex + 1, op.Size, signed);
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Operand m1 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex, op.Size, signed);
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Operand m2 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex + 1, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(n1, n2), op.Id + index, op.Size);
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res = EmitVectorInsert(context, res, emit(m1, m2), op.Id + index + pairs, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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// Narrow
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public static void EmitVectorUnaryNarrowOp32(ArmEmitterContext context, Func1I emit)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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int elems = 8 >> op.Size; // Size contains the target element size. (for when it becomes a doubleword)
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Operand res = GetVecA32(op.Qd);
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int id = (op.Vd & 1) << (3 - op.Size); // Target doubleword base.
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for (int index = 0; index < elems; index++)
|
|
{
|
|
Operand m = EmitVectorExtract32(context, op.Qm, index, op.Size + 1, false);
|
|
|
|
res = EmitVectorInsert(context, res, emit(m), id + index, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVecA32(op.Qd), res);
|
|
}
|
|
|
|
// Intrinsic Helpers
|
|
|
|
public static Operand EmitMoveDoubleWordToSide(ArmEmitterContext context, Operand input, int originalV, int targetV)
|
|
{
|
|
Debug.Assert(input.Type == OperandType.V128);
|
|
|
|
int originalSide = originalV & 1;
|
|
int targetSide = targetV & 1;
|
|
|
|
if (originalSide == targetSide)
|
|
{
|
|
return input;
|
|
}
|
|
|
|
if (targetSide == 1)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Movlhps, input, input); // Low to high.
|
|
}
|
|
else
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Movhlps, input, input); // High to low.
|
|
}
|
|
}
|
|
|
|
public static Operand EmitDoubleWordInsert(ArmEmitterContext context, Operand target, Operand value, int targetV)
|
|
{
|
|
Debug.Assert(target.Type == OperandType.V128 && value.Type == OperandType.V128);
|
|
|
|
int targetSide = targetV & 1;
|
|
int shuffleMask = 2;
|
|
|
|
if (targetSide == 1)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Shufpd, target, value, Const(shuffleMask));
|
|
}
|
|
else
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Shufpd, value, target, Const(shuffleMask));
|
|
}
|
|
}
|
|
|
|
public static Operand EmitScalarInsert(ArmEmitterContext context, Operand target, Operand value, int reg, bool doubleWidth)
|
|
{
|
|
Debug.Assert(target.Type == OperandType.V128 && value.Type == OperandType.V128);
|
|
|
|
// Insert from index 0 in value to index in target.
|
|
int index = reg & (doubleWidth ? 1 : 3);
|
|
|
|
if (doubleWidth)
|
|
{
|
|
if (index == 1)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Movlhps, target, value); // Low to high.
|
|
}
|
|
else
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Shufpd, value, target, Const(2)); // Low to low, keep high from original.
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (Optimizations.UseSse41)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Insertps, target, value, Const(index << 4));
|
|
}
|
|
else
|
|
{
|
|
target = EmitSwapScalar(context, target, index, doubleWidth); // Swap value to replace into element 0.
|
|
target = context.AddIntrinsic(Intrinsic.X86Movss, target, value); // Move the value into element 0 of the vector.
|
|
return EmitSwapScalar(context, target, index, doubleWidth); // Swap new value back to the correct index.
|
|
}
|
|
}
|
|
}
|
|
|
|
public static Operand EmitSwapScalar(ArmEmitterContext context, Operand target, int reg, bool doubleWidth)
|
|
{
|
|
// Index into 0, 0 into index. This swap happens at the start of an A32 scalar op if required.
|
|
int index = reg & (doubleWidth ? 1 : 3);
|
|
if (index == 0) return target;
|
|
|
|
if (doubleWidth)
|
|
{
|
|
int shuffleMask = 1; // Swap top and bottom. (b0 = 1, b1 = 0)
|
|
return context.AddIntrinsic(Intrinsic.X86Shufpd, target, target, Const(shuffleMask));
|
|
}
|
|
else
|
|
{
|
|
int shuffleMask = (3 << 6) | (2 << 4) | (1 << 2) | index; // Swap index and 0. (others remain)
|
|
shuffleMask &= ~(3 << (index * 2));
|
|
|
|
return context.AddIntrinsic(Intrinsic.X86Shufps, target, target, Const(shuffleMask));
|
|
}
|
|
}
|
|
|
|
// Vector Operand Templates
|
|
|
|
public static void EmitVectorUnaryOpSimd32(ArmEmitterContext context, Func1I vectorFunc)
|
|
{
|
|
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
|
|
|
Operand m = GetVecA32(op.Qm);
|
|
Operand d = GetVecA32(op.Qd);
|
|
|
|
if (!op.Q) // Register swap: move relevant doubleword to destination side.
|
|
{
|
|
m = EmitMoveDoubleWordToSide(context, m, op.Vm, op.Vd);
|
|
}
|
|
|
|
Operand res = vectorFunc(m);
|
|
|
|
if (!op.Q) // Register insert.
|
|
{
|
|
res = EmitDoubleWordInsert(context, d, res, op.Vd);
|
|
}
|
|
|
|
context.Copy(d, res);
|
|
}
|
|
|
|
public static void EmitVectorUnaryOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
|
|
{
|
|
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
|
|
|
Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
|
|
|
|
EmitVectorUnaryOpSimd32(context, (m) => context.AddIntrinsic(inst, m));
|
|
}
|
|
|
|
public static void EmitVectorBinaryOpSimd32(ArmEmitterContext context, Func2I vectorFunc, int side = -1)
|
|
{
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|
|
|
Operand n = GetVecA32(op.Qn);
|
|
Operand m = GetVecA32(op.Qm);
|
|
Operand d = GetVecA32(op.Qd);
|
|
|
|
if (side == -1)
|
|
{
|
|
side = op.Vd;
|
|
}
|
|
|
|
if (!op.Q) // Register swap: move relevant doubleword to destination side.
|
|
{
|
|
n = EmitMoveDoubleWordToSide(context, n, op.Vn, side);
|
|
m = EmitMoveDoubleWordToSide(context, m, op.Vm, side);
|
|
}
|
|
|
|
Operand res = vectorFunc(n, m);
|
|
|
|
if (!op.Q) // Register insert.
|
|
{
|
|
if (side != op.Vd)
|
|
{
|
|
res = EmitMoveDoubleWordToSide(context, res, side, op.Vd);
|
|
}
|
|
res = EmitDoubleWordInsert(context, d, res, op.Vd);
|
|
}
|
|
|
|
context.Copy(d, res);
|
|
}
|
|
|
|
public static void EmitVectorBinaryOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
|
|
{
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|
|
|
Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
|
|
EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m));
|
|
}
|
|
|
|
public static void EmitVectorTernaryOpSimd32(ArmEmitterContext context, Func3I vectorFunc)
|
|
{
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|
|
|
Operand n = GetVecA32(op.Qn);
|
|
Operand m = GetVecA32(op.Qm);
|
|
Operand d = GetVecA32(op.Qd);
|
|
Operand initialD = d;
|
|
|
|
if (!op.Q) // Register swap: move relevant doubleword to destination side.
|
|
{
|
|
n = EmitMoveDoubleWordToSide(context, n, op.Vn, op.Vd);
|
|
m = EmitMoveDoubleWordToSide(context, m, op.Vm, op.Vd);
|
|
}
|
|
|
|
Operand res = vectorFunc(d, n, m);
|
|
|
|
if (!op.Q) // Register insert.
|
|
{
|
|
res = EmitDoubleWordInsert(context, initialD, res, op.Vd);
|
|
}
|
|
|
|
context.Copy(initialD, res);
|
|
}
|
|
|
|
public static void EmitVectorTernaryOpF32(ArmEmitterContext context, Intrinsic inst32pt1, Intrinsic inst64pt1, Intrinsic inst32pt2, Intrinsic inst64pt2)
|
|
{
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|
|
|
Intrinsic inst1 = (op.Size & 1) != 0 ? inst64pt1 : inst32pt1;
|
|
Intrinsic inst2 = (op.Size & 1) != 0 ? inst64pt2 : inst32pt2;
|
|
|
|
EmitVectorTernaryOpSimd32(context, (d, n, m) =>
|
|
{
|
|
Operand res = context.AddIntrinsic(inst1, n, m);
|
|
return res = context.AddIntrinsic(inst2, d, res);
|
|
});
|
|
}
|
|
|
|
public static void EmitScalarUnaryOpSimd32(ArmEmitterContext context, Func1I scalarFunc)
|
|
{
|
|
OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
|
|
|
|
bool doubleSize = (op.Size & 1) != 0;
|
|
int shift = doubleSize ? 1 : 2;
|
|
Operand m = GetVecA32(op.Vm >> shift);
|
|
Operand d = GetVecA32(op.Vd >> shift);
|
|
|
|
m = EmitSwapScalar(context, m, op.Vm, doubleSize);
|
|
|
|
Operand res = scalarFunc(m);
|
|
|
|
// Insert scalar into vector.
|
|
res = EmitScalarInsert(context, d, res, op.Vd, doubleSize);
|
|
|
|
context.Copy(d, res);
|
|
}
|
|
|
|
public static void EmitScalarUnaryOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
|
|
{
|
|
OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
|
|
|
|
Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
|
|
|
|
EmitScalarUnaryOpSimd32(context, (m) => (inst == 0) ? m : context.AddIntrinsic(inst, m));
|
|
}
|
|
|
|
public static void EmitScalarBinaryOpSimd32(ArmEmitterContext context, Func2I scalarFunc)
|
|
{
|
|
OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
|
|
|
|
bool doubleSize = (op.Size & 1) != 0;
|
|
int shift = doubleSize ? 1 : 2;
|
|
Operand n = GetVecA32(op.Vn >> shift);
|
|
Operand m = GetVecA32(op.Vm >> shift);
|
|
Operand d = GetVecA32(op.Vd >> shift);
|
|
|
|
n = EmitSwapScalar(context, n, op.Vn, doubleSize);
|
|
m = EmitSwapScalar(context, m, op.Vm, doubleSize);
|
|
|
|
Operand res = scalarFunc(n, m);
|
|
|
|
// Insert scalar into vector.
|
|
res = EmitScalarInsert(context, d, res, op.Vd, doubleSize);
|
|
|
|
context.Copy(d, res);
|
|
}
|
|
|
|
public static void EmitScalarBinaryOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
|
|
{
|
|
OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
|
|
|
|
Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
|
|
|
|
EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m));
|
|
}
|
|
|
|
public static void EmitScalarTernaryOpSimd32(ArmEmitterContext context, Func3I scalarFunc)
|
|
{
|
|
OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
|
|
|
|
bool doubleSize = (op.Size & 1) != 0;
|
|
int shift = doubleSize ? 1 : 2;
|
|
Operand n = GetVecA32(op.Vn >> shift);
|
|
Operand m = GetVecA32(op.Vm >> shift);
|
|
Operand d = GetVecA32(op.Vd >> shift);
|
|
Operand initialD = d;
|
|
|
|
n = EmitSwapScalar(context, n, op.Vn, doubleSize);
|
|
m = EmitSwapScalar(context, m, op.Vm, doubleSize);
|
|
d = EmitSwapScalar(context, d, op.Vd, doubleSize);
|
|
|
|
Operand res = scalarFunc(d, n, m);
|
|
|
|
// Insert scalar into vector.
|
|
res = EmitScalarInsert(context, initialD, res, op.Vd, doubleSize);
|
|
|
|
context.Copy(initialD, res);
|
|
}
|
|
|
|
public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Intrinsic inst32pt1, Intrinsic inst64pt1, Intrinsic inst32pt2, Intrinsic inst64pt2)
|
|
{
|
|
OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
|
|
|
|
bool doubleSize = (op.Size & 1) != 0;
|
|
int shift = doubleSize ? 1 : 2;
|
|
Intrinsic inst1 = doubleSize ? inst64pt1 : inst32pt1;
|
|
Intrinsic inst2 = doubleSize ? inst64pt2 : inst32pt2;
|
|
|
|
EmitScalarTernaryOpSimd32(context, (d, n, m) =>
|
|
{
|
|
Operand res = context.AddIntrinsic(inst1, n, m);
|
|
return context.AddIntrinsic(inst2, d, res);
|
|
});
|
|
}
|
|
|
|
// By Scalar
|
|
|
|
public static void EmitVectorByScalarOpSimd32(ArmEmitterContext context, Func2I vectorFunc)
|
|
{
|
|
OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
|
|
|
|
Operand n = GetVecA32(op.Qn);
|
|
Operand d = GetVecA32(op.Qd);
|
|
|
|
int index = op.Vm & 3;
|
|
int dupeMask = (index << 6) | (index << 4) | (index << 2) | index;
|
|
Operand m = GetVecA32(op.Vm >> 2);
|
|
m = context.AddIntrinsic(Intrinsic.X86Shufps, m, m, Const(dupeMask));
|
|
|
|
if (!op.Q) // Register swap: move relevant doubleword to destination side.
|
|
{
|
|
n = EmitMoveDoubleWordToSide(context, n, op.Vn, op.Vd);
|
|
}
|
|
|
|
Operand res = vectorFunc(n, m);
|
|
|
|
if (!op.Q) // Register insert.
|
|
{
|
|
res = EmitDoubleWordInsert(context, d, res, op.Vd);
|
|
}
|
|
|
|
context.Copy(d, res);
|
|
}
|
|
|
|
public static void EmitVectorByScalarOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
|
|
{
|
|
OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
|
|
|
|
Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
|
|
EmitVectorByScalarOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m));
|
|
}
|
|
|
|
public static void EmitVectorsByScalarOpSimd32(ArmEmitterContext context, Func3I vectorFunc)
|
|
{
|
|
OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
|
|
|
|
Operand n = GetVecA32(op.Qn);
|
|
Operand d = GetVecA32(op.Qd);
|
|
Operand initialD = d;
|
|
|
|
int index = op.Vm & 3;
|
|
int dupeMask = (index << 6) | (index << 4) | (index << 2) | index;
|
|
Operand m = GetVecA32(op.Vm >> 2);
|
|
m = context.AddIntrinsic(Intrinsic.X86Shufps, m, m, Const(dupeMask));
|
|
|
|
if (!op.Q) // Register swap: move relevant doubleword to destination side.
|
|
{
|
|
n = EmitMoveDoubleWordToSide(context, n, op.Vn, op.Vd);
|
|
}
|
|
|
|
Operand res = vectorFunc(d, n, m);
|
|
|
|
if (!op.Q) // Register insert.
|
|
{
|
|
res = EmitDoubleWordInsert(context, initialD, res, op.Vd);
|
|
}
|
|
|
|
context.Copy(initialD, res);
|
|
}
|
|
|
|
public static void EmitVectorsByScalarOpF32(ArmEmitterContext context, Intrinsic inst32pt1, Intrinsic inst64pt1, Intrinsic inst32pt2, Intrinsic inst64pt2)
|
|
{
|
|
OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
|
|
|
|
Intrinsic inst1 = (op.Size & 1) != 0 ? inst64pt1 : inst32pt1;
|
|
Intrinsic inst2 = (op.Size & 1) != 0 ? inst64pt2 : inst32pt2;
|
|
|
|
EmitVectorsByScalarOpSimd32(context, (d, n, m) =>
|
|
{
|
|
Operand res = context.AddIntrinsic(inst1, n, m);
|
|
return res = context.AddIntrinsic(inst2, d, res);
|
|
});
|
|
}
|
|
|
|
// Pairwise
|
|
|
|
public static void EmitSse2VectorPairwiseOpF32(ArmEmitterContext context, Intrinsic inst32)
|
|
{
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|
|
|
EmitVectorBinaryOpSimd32(context, (n, m) =>
|
|
{
|
|
Operand unpck = context.AddIntrinsic(Intrinsic.X86Unpcklps, n, m);
|
|
|
|
Operand part0 = unpck;
|
|
Operand part1 = context.AddIntrinsic(Intrinsic.X86Movhlps, unpck, unpck);
|
|
|
|
return context.AddIntrinsic(inst32, part0, part1);
|
|
}, 0);
|
|
}
|
|
|
|
public static void EmitSsse3VectorPairwiseOp32(ArmEmitterContext context, Intrinsic[] inst)
|
|
{
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|
|
|
EmitVectorBinaryOpSimd32(context, (n, m) =>
|
|
{
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
Operand zeroEvenMask = X86GetElements(context, ZeroMask, EvenMasks[op.Size]);
|
|
Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks[op.Size]);
|
|
|
|
Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n
|
|
|
|
Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
|
|
Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n
|
|
|
|
return context.AddIntrinsic(inst[op.Size], left, right);
|
|
}
|
|
else if (op.Size < 3)
|
|
{
|
|
Operand oddEvenMask = X86GetElements(context, OddMasks[op.Size], EvenMasks[op.Size]);
|
|
|
|
Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n
|
|
Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m
|
|
|
|
Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
|
|
Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM);
|
|
|
|
return context.AddIntrinsic(inst[op.Size], left, right);
|
|
}
|
|
else
|
|
{
|
|
Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
|
|
Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m);
|
|
|
|
return context.AddIntrinsic(inst[3], left, right);
|
|
}
|
|
}, 0);
|
|
}
|
|
|
|
// Generic Functions
|
|
|
|
public static Operand EmitSoftFloatCallDefaultFpscr(
|
|
ArmEmitterContext context,
|
|
_F32_F32_Bool f32,
|
|
_F64_F64_Bool f64,
|
|
params Operand[] callArgs)
|
|
{
|
|
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
|
|
|
|
Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
|
|
|
|
Array.Resize(ref callArgs, callArgs.Length + 1);
|
|
callArgs[callArgs.Length - 1] = Const(1);
|
|
|
|
return context.Call(dlg, callArgs);
|
|
}
|
|
|
|
public static Operand EmitSoftFloatCallDefaultFpscr(
|
|
ArmEmitterContext context,
|
|
_F32_F32_F32_Bool f32,
|
|
_F64_F64_F64_Bool f64,
|
|
params Operand[] callArgs)
|
|
{
|
|
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
|
|
|
|
Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
|
|
|
|
Array.Resize(ref callArgs, callArgs.Length + 1);
|
|
callArgs[callArgs.Length - 1] = Const(1);
|
|
|
|
return context.Call(dlg, callArgs);
|
|
}
|
|
|
|
public static Operand EmitSoftFloatCallDefaultFpscr(
|
|
ArmEmitterContext context,
|
|
_F32_F32_F32_F32_Bool f32,
|
|
_F64_F64_F64_F64_Bool f64,
|
|
params Operand[] callArgs)
|
|
{
|
|
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
|
|
|
|
Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
|
|
|
|
Array.Resize(ref callArgs, callArgs.Length + 1);
|
|
callArgs[callArgs.Length - 1] = Const(1);
|
|
|
|
return context.Call(dlg, callArgs);
|
|
}
|
|
|
|
public static Operand EmitVectorExtractSx32(ArmEmitterContext context, int reg, int index, int size)
|
|
{
|
|
return EmitVectorExtract32(context, reg, index, size, true);
|
|
}
|
|
|
|
public static Operand EmitVectorExtractZx32(ArmEmitterContext context, int reg, int index, int size)
|
|
{
|
|
return EmitVectorExtract32(context, reg, index, size, false);
|
|
}
|
|
|
|
public static Operand EmitVectorExtract32(ArmEmitterContext context, int reg, int index, int size, bool signed)
|
|
{
|
|
ThrowIfInvalid(index, size);
|
|
|
|
Operand res = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0:
|
|
res = context.VectorExtract8(GetVec(reg), index);
|
|
break;
|
|
|
|
case 1:
|
|
res = context.VectorExtract16(GetVec(reg), index);
|
|
break;
|
|
|
|
case 2:
|
|
res = context.VectorExtract(OperandType.I32, GetVec(reg), index);
|
|
break;
|
|
|
|
case 3:
|
|
res = context.VectorExtract(OperandType.I64, GetVec(reg), index);
|
|
break;
|
|
}
|
|
|
|
if (signed)
|
|
{
|
|
switch (size)
|
|
{
|
|
case 0: res = context.SignExtend8(OperandType.I32, res); break;
|
|
case 1: res = context.SignExtend16(OperandType.I32, res); break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (size)
|
|
{
|
|
case 0: res = context.ZeroExtend8(OperandType.I32, res); break;
|
|
case 1: res = context.ZeroExtend16(OperandType.I32, res); break;
|
|
}
|
|
}
|
|
|
|
return res;
|
|
}
|
|
}
|
|
}
|