LDj3SNuD
74da8785a5
Sse optimized the 32-bit Vector & Scalar integer-to-fp conversion instructions (signed & unsigned); added the related Gp & V_Fixed Tests (signed & unsigned). ( #662 )
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* Update CpuTestSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdShImm.cs
* Update InstEmitSimdCvt.cs
* Update OpCodeTable.cs
* Update InstEmitSimdCvt.cs
2019-04-20 23:07:35 -03:00
LDj3SNuD
233fc95e1e
Sse optimized the Vector & Scalar fp-to-integer conversion instructions (unsigned); improved the related Tests. ( #656 )
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* Update InstEmitSimdCvt.cs
* Update CpuTestSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdShImm.cs
* Update InstEmitSimdCvt.cs
2019-04-12 13:14:16 -03:00
LDj3SNuD
febc2ad6f4
Sse optimized all the fp to integer conversion instructions (signed) with Tests (signed & unsigned). ( #655 )
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* Update CpuTestSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdShImm.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdMove.cs
* Update InstEmitSimdCmp.cs
* Update VectorHelper.cs
* Update InstEmitSimdHelper.cs
* Update OpCodeTable.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdHelper.cs
* Update InstEmitSimdMove.cs
2019-04-03 09:21:22 -03:00
LDj3SNuD
1bef70c068
Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. ( #614 )
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* Update CountLeadingZeros().
* Remove obsolete Tests.
* Follow-up.
* Follow-up.
* Follow-up.
* Add Mla_V, Mls_V & Mul_V Tests.
* Update PackageReferences.
* Remove EmitLd/Stvectmp2().
* Remove Dup. Nits.
* Remove EmitLd/Stvectmp2() & Dup; nits.
* Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn().
* Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits.
* Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt..
Remove Tmp stuff; remove Dup.
Nits.
* Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt..
Remove EmitLd/Stvectmp2(), remove Dup.
Nits.
* Nits.
* Nits.
* Nit.
* Add "Part" opt.. Nit.
* Nit.
* Nit.
* Add Cmhi_V & Cmhs_V Sse opt..
2019-03-13 19:23:52 +11:00
LDj3SNuD
0f5b6dfbe8
Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl. for Fcmeq/ge/gt/le/lt_S/V (Reg & Zero), Faddp_S/V, Fmaxp_V, Fminp_V Inst.; add Sse Opt. for Shll_V, S/Ushll_V Inst.; improve Sse Opt. for Xtn_V Inst.. Add Tests. ( #543 )
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* Update Optimizations.cs
* Update InstEmitSimdShift.cs
* Update InstEmitSimdHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdMove.cs
* Update SoftFloat.cs
* Update InstEmitSimdCmp.cs
* Update CpuTestSimdShImm.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Nit.
* Update SoftFloat.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdHelper.cs
* Update CpuTestSimd.cs
* Explicit some implicit casts.
* Simplify some powers; nits.
* Update OpCodeTable.cs
* Update InstEmitSimdArithmetic.cs
* Update CpuTestSimdReg.cs
* Update InstEmitSimdArithmetic.cs
2018-12-26 15:11:36 -02:00
LDj3SNuD
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. ( #489 )
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* Update SoftFloat.cs
* Update SoftFallback.cs
* Update InstEmitSimdShift.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdArithmetic.cs
* Update CryptoHelper.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuThreadState.cs
* Update OpCodeTable.cs
* Add files via upload
* Nit.
* Remove unused using. Nit.
* Remove unused using. FZ update.
* Nit.
* Remove unused using.
2018-11-01 01:22:09 -03:00
Alex Barney
9cb57fb4bb
Adjust naming conventions for Ryujinx and ChocolArm64 projects ( #484 )
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* Change naming convention for Ryujinx project
* Change naming convention for ChocolArm64 project
* Fix NaN
* Remove unneeded this. from Ryujinx project
* Adjust naming from new PRs
* Name changes based on feedback
* How did this get removed?
* Rebasing fix
* Change FP enum case
* Remove prefix from ChocolArm64 classes - Part 1
* Remove prefix from ChocolArm64 classes - Part 2
* Fix alignment from last commit's renaming
* Rename namespaces
* Rename stragglers
* Fix alignment
* Rename OpCode class
* Missed a few
* Adjust alignment
2018-10-30 22:43:02 -03:00
LDj3SNuD
c7387be0d2
Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. ( #409 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update CpuTestSimdShImm.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdIns.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-09-17 01:54:05 -03:00
LDj3SNuD
a0c78f7920
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. ( #407 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update AOpCodeSimdShImm.cs
* Update ABitUtils.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdShImm.cs
* Create CpuTestSimdRegElem.cs
* Address PR feedback.
* Nit.
* Nit.
2018-09-08 14:24:29 -03:00
