3 Commits

Author	SHA1	Message	Date
LDj3SNuD	262b5b8054	Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) ... * Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs	2018-04-12 11:52:00 -03:00
LDj3SNuD	f09a0082bf	Review of cpu tests and creation of a class for mixed cpu tests. (#35) ... * Update CpuTest.cs * Update CpuTestAlu.cs * Update CpuTestScalar.cs * Update CpuTestSimdMove.cs * Create CpuTestMisc.cs * Update CpuTest.cs * Update CpuTestScalar.cs * Update CpuTest.cs * Update CpuTestAlu.cs * Update CpuTestMisc.cs * Update CpuTestScalar.cs	2018-02-23 09:29:20 -03:00
Merry	1039797c30	Implement Zip1, Zip2 (#25)	2018-02-20 07:41:55 -03:00