Improve accuracy of reciprocal step instructions (#2305)
* Improve accuracy of reciprocal step instructions * Fix small mistake on RECPE rounding, nits, PTC version bump
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gdkchan
GitHub
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3fd6b55f04
commit
fb65f392d1
@ -1477,7 +1477,7 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rcpss, GetVec(op.Rn)), scalar: true);
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Operand res = EmitSse41Round32Exp8OpF(context, context.AddIntrinsic(Intrinsic.X86Rcpss, GetVec(op.Rn)), scalar: true);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
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}
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@ -1498,7 +1498,7 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rcpps, GetVec(op.Rn)), scalar: false);
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Operand res = EmitSse41Round32Exp8OpF(context, context.AddIntrinsic(Intrinsic.X86Rcpps, GetVec(op.Rn)), scalar: false);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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@ -1518,19 +1518,23 @@ namespace ARMeilleure.Instructions
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public static void Frecps_S(ArmEmitterContext context) // Fused.
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Operand mask = X86GetScalar(context, 2f);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulss, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulss, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Subss, mask, res);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, mask, scalar: true, sizeF);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
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}
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@ -1538,9 +1542,10 @@ namespace ARMeilleure.Instructions
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{
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Operand mask = X86GetScalar(context, 2d);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulsd, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulsd, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Subsd, mask, res);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, mask, scalar: true, sizeF);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper64(res));
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}
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@ -1556,17 +1561,21 @@ namespace ARMeilleure.Instructions
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public static void Frecps_V(ArmEmitterContext context) // Fused.
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Operand mask = X86GetAllElements(context, 2f);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulps, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulps, n, m);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, mask, scalar: false, sizeF);
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res = context.AddIntrinsic(Intrinsic.X86Subps, mask, res);
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@ -1581,7 +1590,8 @@ namespace ARMeilleure.Instructions
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{
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Operand mask = X86GetAllElements(context, 2d);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulpd, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulpd, n, m);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, mask, scalar: false, sizeF);
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res = context.AddIntrinsic(Intrinsic.X86Subpd, mask, res);
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@ -1821,7 +1831,7 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rsqrtss, GetVec(op.Rn)), scalar: true);
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Operand res = EmitSse41Round32Exp8OpF(context, context.AddIntrinsic(Intrinsic.X86Rsqrtss, GetVec(op.Rn)), scalar: true);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
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}
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@ -1842,7 +1852,7 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rsqrtps, GetVec(op.Rn)), scalar: false);
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Operand res = EmitSse41Round32Exp8OpF(context, context.AddIntrinsic(Intrinsic.X86Rsqrtps, GetVec(op.Rn)), scalar: false);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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@ -1862,21 +1872,26 @@ namespace ARMeilleure.Instructions
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public static void Frsqrts_S(ArmEmitterContext context) // Fused.
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Operand maskHalf = X86GetScalar(context, 0.5f);
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Operand maskThree = X86GetScalar(context, 3f);
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Operand maskOneHalf = X86GetScalar(context, 1.5f);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulss, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulss, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Subss, maskThree, res);
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res = context.AddIntrinsic(Intrinsic.X86Mulss, maskHalf, res);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: true, sizeF);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
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}
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@ -1884,11 +1899,13 @@ namespace ARMeilleure.Instructions
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{
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Operand maskHalf = X86GetScalar(context, 0.5d);
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Operand maskThree = X86GetScalar(context, 3d);
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Operand maskOneHalf = X86GetScalar(context, 1.5d);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulsd, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulsd, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Subsd, maskThree, res);
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res = context.AddIntrinsic(Intrinsic.X86Mulsd, maskHalf, res);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: true, sizeF);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper64(res));
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}
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@ -1904,21 +1921,26 @@ namespace ARMeilleure.Instructions
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public static void Frsqrts_V(ArmEmitterContext context) // Fused.
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Operand maskHalf = X86GetAllElements(context, 0.5f);
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Operand maskThree = X86GetAllElements(context, 3f);
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Operand maskOneHalf = X86GetAllElements(context, 1.5f);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulps, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulps, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Subps, maskThree, res);
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res = context.AddIntrinsic(Intrinsic.X86Mulps, maskHalf, res);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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@ -1931,11 +1953,13 @@ namespace ARMeilleure.Instructions
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{
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Operand maskHalf = X86GetAllElements(context, 0.5d);
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Operand maskThree = X86GetAllElements(context, 3d);
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Operand maskOneHalf = X86GetAllElements(context, 1.5d);
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulpd, GetVec(op.Rn), GetVec(op.Rm));
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Operand res = context.AddIntrinsic(Intrinsic.X86Mulpd, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Subpd, maskThree, res);
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res = context.AddIntrinsic(Intrinsic.X86Mulpd, maskHalf, res);
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res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF);
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context.Copy(GetVec(op.Rd), res);
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}
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@ -3566,7 +3590,7 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), res);
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}
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private static Operand EmitSse41FP32RoundExp8(ArmEmitterContext context, Operand value, bool scalar)
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private static Operand EmitSse41Round32Exp8OpF(ArmEmitterContext context, Operand value, bool scalar)
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{
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Operand roundMask;
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Operand truncMask;
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@ -3587,7 +3611,7 @@ namespace ARMeilleure.Instructions
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Operand oValue = value;
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Operand masked = context.AddIntrinsic(Intrinsic.X86Pand, value, expMask);
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Operand isNaNInf = context.AddIntrinsic(Intrinsic.X86Pcmpeqw, masked, expMask);
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Operand isNaNInf = context.AddIntrinsic(Intrinsic.X86Pcmpeqd, masked, expMask);
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value = context.AddIntrinsic(Intrinsic.X86Paddw, value, roundMask);
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value = context.AddIntrinsic(Intrinsic.X86Pand, value, truncMask);
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@ -3595,6 +3619,51 @@ namespace ARMeilleure.Instructions
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return context.AddIntrinsic(Intrinsic.X86Blendvps, value, oValue, isNaNInf);
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}
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private static Operand EmitSse41RecipStepSelectOpF(
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ArmEmitterContext context,
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Operand n,
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Operand m,
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Operand res,
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Operand mask,
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bool scalar,
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int sizeF)
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{
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Intrinsic cmpOp;
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Intrinsic shlOp;
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Intrinsic blendOp;
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Operand zero = context.VectorZero();
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Operand expMask;
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if (sizeF == 0)
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{
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cmpOp = Intrinsic.X86Pcmpeqd;
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shlOp = Intrinsic.X86Pslld;
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blendOp = Intrinsic.X86Blendvps;
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expMask = scalar ? X86GetScalar(context, 0x7F800000 << 1) : X86GetAllElements(context, 0x7F800000 << 1);
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}
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else /* if (sizeF == 1) */
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{
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cmpOp = Intrinsic.X86Pcmpeqq;
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shlOp = Intrinsic.X86Psllq;
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blendOp = Intrinsic.X86Blendvpd;
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expMask = scalar ? X86GetScalar(context, 0x7FF0000000000000L << 1) : X86GetAllElements(context, 0x7FF0000000000000L << 1);
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}
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n = context.AddIntrinsic(shlOp, n, Const(1));
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m = context.AddIntrinsic(shlOp, m, Const(1));
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Operand nZero = context.AddIntrinsic(cmpOp, n, zero);
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Operand mZero = context.AddIntrinsic(cmpOp, m, zero);
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Operand nInf = context.AddIntrinsic(cmpOp, n, expMask);
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Operand mInf = context.AddIntrinsic(cmpOp, m, expMask);
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Operand nmZero = context.AddIntrinsic(Intrinsic.X86Por, nZero, mZero);
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Operand nmInf = context.AddIntrinsic(Intrinsic.X86Por, nInf, mInf);
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Operand nmZeroInf = context.AddIntrinsic(Intrinsic.X86Pand, nmZero, nmInf);
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return context.AddIntrinsic(blendOp, res, mask, nmZeroInf);
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}
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public static void EmitSse2VectorIsNaNOpF(
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ArmEmitterContext context,
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Operand opF,
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@ -28,7 +28,7 @@ namespace ARMeilleure.Translation.PTC
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const uint InternalVersion = 2282; //! To be incremented manually for each change to the ARMeilleure project.
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private const uint InternalVersion = 2305; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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