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.NET Core 3.0 is here! (#784)

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* .NET Core 3.0 is here!

* Remove IMemoryManager.cs and its references.

* Add T Math/F.FusedMultiplyAdd(T, T, T). Nits.

* Nit.

* Update appveyor.yml

* Revert "Resolve Visual Studio build issues"

This reverts commit 1772128ce0.

* Update SvcTable.cs
This commit is contained in:
LDj3SNuD 2019-10-31 19:09:03 +01:00 committed by Ac_K
parent 35443bac5a
commit eee639d6ba
208 changed files with 138 additions and 27346 deletions
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3
ARMeilleure/ARMeilleure.csproj
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@ -1,9 +1,8 @@
<Project Sdk="Microsoft.NET.Sdk"> <Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup> <PropertyGroup>
<TargetFramework>netcoreapp2.1</TargetFramework> <TargetFramework>netcoreapp3.0</TargetFramework>
<RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers> <RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
<LangVersion>latest</LangVersion>
</PropertyGroup> </PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|AnyCPU'"> <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|AnyCPU'">

10
ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
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@ -1033,14 +1033,13 @@ namespace ARMeilleure.Instructions
} }
} }
public static void Fnmadd_S(ArmEmitterContext context) public static void Fnmadd_S(ArmEmitterContext context) // Fused.
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
OperandType type = sizeF != 0 ? OperandType.FP64 OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
: OperandType.FP32;
Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0); Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
Operand me = context.VectorExtract(type, GetVec(op.Rm), 0); Operand me = context.VectorExtract(type, GetVec(op.Rm), 0);
@ -1051,14 +1050,13 @@ namespace ARMeilleure.Instructions
context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0)); context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
} }
public static void Fnmsub_S(ArmEmitterContext context) public static void Fnmsub_S(ArmEmitterContext context) // Fused.
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
OperandType type = sizeF != 0 ? OperandType.FP64 OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
: OperandType.FP32;
Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0); Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
Operand me = context.VectorExtract(type, GetVec(op.Rm), 0); Operand me = context.VectorExtract(type, GetVec(op.Rm), 0);

30
ARMeilleure/Instructions/SoftFloat.cs
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@ -1073,10 +1073,7 @@ namespace ARMeilleure.Instructions
} }
else else
{ {
// TODO: When available, use: T MathF.FusedMultiplyAdd(T, T, T); result = MathF.FusedMultiplyAdd(value1, value2, valueA);
// https://github.com/dotnet/corefx/issues/31903
result = valueA + (value1 * value2);
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result)) if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
{ {
@ -1256,10 +1253,7 @@ namespace ARMeilleure.Instructions
} }
else else
{ {
// TODO: When available, use: T MathF.FusedMultiplyAdd(T, T, T); result = MathF.FusedMultiplyAdd(value1, value2, 2f);
// https://github.com/dotnet/corefx/issues/31903
result = 2f + (value1 * value2);
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result)) if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
{ {
@ -1388,10 +1382,7 @@ namespace ARMeilleure.Instructions
} }
else else
{ {
// TODO: When available, use: T MathF.FusedMultiplyAdd(T, T, T); result = MathF.FusedMultiplyAdd(value1, value2, 3f) / 2f;
// https://github.com/dotnet/corefx/issues/31903
result = (3f + (value1 * value2)) / 2f;
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result)) if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
{ {
@ -2142,10 +2133,7 @@ namespace ARMeilleure.Instructions
} }
else else
{ {
// TODO: When available, use: T Math.FusedMultiplyAdd(T, T, T); result = Math.FusedMultiplyAdd(value1, value2, valueA);
// https://github.com/dotnet/corefx/issues/31903
result = valueA + (value1 * value2);
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result)) if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
{ {
@ -2323,10 +2311,7 @@ namespace ARMeilleure.Instructions
} }
else else
{ {
// TODO: When available, use: T Math.FusedMultiplyAdd(T, T, T); result = Math.FusedMultiplyAdd(value1, value2, 2d);
// https://github.com/dotnet/corefx/issues/31903
result = 2d + (value1 * value2);
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result)) if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
{ {
@ -2455,10 +2440,7 @@ namespace ARMeilleure.Instructions
} }
else else
{ {
// TODO: When available, use: T Math.FusedMultiplyAdd(T, T, T); result = Math.FusedMultiplyAdd(value1, value2, 3d) / 2d;
// https://github.com/dotnet/corefx/issues/31903
result = (3d + (value1 * value2)) / 2d;
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result)) if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
{ {

40
ARMeilleure/Memory/IMemoryManager.cs
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@ -1,40 +0,0 @@
using ARMeilleure.State;
using System;
namespace ARMeilleure.Memory
{
public interface IMemoryManager : IMemory, IDisposable
{
void Map(long va, long pa, long size);
void Unmap(long position, long size);
bool IsMapped(long position);
long GetPhysicalAddress(long virtualAddress);
bool IsRegionModified(long position, long size);
bool TryGetHostAddress(long position, long size, out IntPtr ptr);
bool IsValidPosition(long position);
bool AtomicCompareExchangeInt32(long position, int expected, int desired);
int AtomicIncrementInt32(long position);
int AtomicDecrementInt32(long position);
byte[] ReadBytes(long position, long size);
void ReadBytes(long position, byte[] data, int startIndex, int size);
void WriteVector128(long position, V128 value);
void WriteBytes(long position, byte[] data);
void WriteBytes(long position, byte[] data, int startIndex, int size);
void CopyBytes(long src, long dst, long size);
}
}

8
ARMeilleure/Memory/MemoryHelper.cs
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@ -7,7 +7,7 @@ namespace ARMeilleure.Memory
{ {
public static class MemoryHelper public static class MemoryHelper
{ {
public static void FillWithZeros(IMemoryManager memory, long position, int size) public static void FillWithZeros(MemoryManager memory, long position, int size)
{ {
int size8 = size & ~(8 - 1); int size8 = size & ~(8 - 1);
@ -22,7 +22,7 @@ namespace ARMeilleure.Memory
} }
} }
public unsafe static T Read<T>(IMemoryManager memory, long position) where T : struct public unsafe static T Read<T>(MemoryManager memory, long position) where T : struct
{ {
long size = Marshal.SizeOf<T>(); long size = Marshal.SizeOf<T>();
@ -34,7 +34,7 @@ namespace ARMeilleure.Memory
} }
} }
public unsafe static void Write<T>(IMemoryManager memory, long position, T value) where T : struct public unsafe static void Write<T>(MemoryManager memory, long position, T value) where T : struct
{ {
long size = Marshal.SizeOf<T>(); long size = Marshal.SizeOf<T>();
@ -48,7 +48,7 @@ namespace ARMeilleure.Memory
memory.WriteBytes(position, data); memory.WriteBytes(position, data);
} }
public static string ReadAsciiString(IMemoryManager memory, long position, long maxSize = -1) public static string ReadAsciiString(MemoryManager memory, long position, long maxSize = -1)
{ {
using (MemoryStream ms = new MemoryStream()) using (MemoryStream ms = new MemoryStream())
{ {

2
ARMeilleure/Memory/MemoryManager.cs
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@ -7,7 +7,7 @@ using static ARMeilleure.Memory.MemoryManagement;
namespace ARMeilleure.Memory namespace ARMeilleure.Memory
{ {
public unsafe class MemoryManager : IMemoryManager public unsafe class MemoryManager
{ {
public const int PageBits = 12; public const int PageBits = 12;
public const int PageSize = 1 << PageBits; public const int PageSize = 1 << PageBits;

2
ARMeilleure/State/ExecutionContext.cs
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@ -3,7 +3,7 @@ using System.Diagnostics;
namespace ARMeilleure.State namespace ARMeilleure.State
{ {
public class ExecutionContext : IExecutionContext public class ExecutionContext
{ {
private const int MinCountForCheck = 40000; private const int MinCountForCheck = 40000;

37
ARMeilleure/State/IExecutionContext.cs
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@ -1,37 +0,0 @@
using System;
namespace ARMeilleure.State
{
public interface IExecutionContext : IDisposable
{
uint CtrEl0 { get; }
uint DczidEl0 { get; }
ulong CntfrqEl0 { get; set; }
ulong CntpctEl0 { get; }
long TpidrEl0 { get; set; }
long Tpidr { get; set; }
FPCR Fpcr { get; set; }
FPSR Fpsr { get; set; }
bool IsAarch32 { get; set; }
bool Running { get; set; }
event EventHandler<EventArgs> Interrupt;
event EventHandler<InstExceptionEventArgs> Break;
event EventHandler<InstExceptionEventArgs> SupervisorCall;
event EventHandler<InstUndefinedEventArgs> Undefined;
ulong GetX(int index);
void SetX(int index, ulong value);
V128 GetV(int index);
bool GetPstateFlag(PState flag);
void RequestInterrupt();
}
}

9
ARMeilleure/Translation/ITranslator.cs
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@ -1,9 +0,0 @@
using ARMeilleure.State;
namespace ARMeilleure.Translation
{
public interface ITranslator
{
void Execute(IExecutionContext context, ulong address);
}
}

6
ARMeilleure/Translation/Translator.cs
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@ -12,7 +12,7 @@ using static ARMeilleure.IntermediateRepresentation.OperandHelper;
namespace ARMeilleure.Translation namespace ARMeilleure.Translation
{ {
public class Translator : ITranslator public class Translator
{ {
private const ulong CallFlag = InstEmitFlowHelper.CallFlag; private const ulong CallFlag = InstEmitFlowHelper.CallFlag;
@ -54,10 +54,8 @@ namespace ARMeilleure.Translation
} }
} }
public void Execute(IExecutionContext ctx, ulong address) public void Execute(State.ExecutionContext context, ulong address)
{ {
State.ExecutionContext context = (State.ExecutionContext)ctx;
if (Interlocked.Increment(ref _threadCount) == 1) if (Interlocked.Increment(ref _threadCount) == 1)
{ {
Thread backgroundTranslatorThread = new Thread(TranslateQueuedSubs); Thread backgroundTranslatorThread = new Thread(TranslateQueuedSubs);

39
ChocolArm64/ChocolArm64.csproj
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@ -1,39 +0,0 @@
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<TargetFramework>netcoreapp2.1</TargetFramework>
<RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
<Configurations>Debug;Release;Profile Debug;Profile Release</Configurations>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|AnyCPU'">
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Profile Debug|AnyCPU'">
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
<DefineConstants>TRACE;USE_PROFILING</DefineConstants>
<Optimize>false</Optimize>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|AnyCPU'">
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Profile Release|AnyCPU'">
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
<DefineConstants>TRACE;USE_PROFILING</DefineConstants>
<Optimize>true</Optimize>
</PropertyGroup>
<ItemGroup>
<PackageReference Include="Mono.Posix.NETStandard" Version="1.0.0" />
<PackageReference Include="System.Runtime.Intrinsics.Experimental" Version="4.5.0-rc1" />
</ItemGroup>
<ItemGroup>
<ProjectReference Include="..\Ryujinx.Profiler\Ryujinx.Profiler.csproj" />
<ProjectReference Include="..\ARMeilleure\ARMeilleure.csproj" />
</ItemGroup>
</Project>

59
ChocolArm64/Decoders/BitUtils.cs
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@ -1,59 +0,0 @@
namespace ChocolArm64.Decoders
{
static class BitUtils
{
public static int HighestBitSet32(int value)
{
for (int bit = 31; bit >= 0; bit--)
{
if (((value >> bit) & 1) != 0)
{
return bit;
}
}
return -1;
}
private static readonly sbyte[] HbsNibbleTbl = { -1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
public static int HighestBitSetNibble(int value) => HbsNibbleTbl[value & 0b1111];
public static long Replicate(long bits, int size)
{
long output = 0;
for (int bit = 0; bit < 64; bit += size)
{
output |= bits << bit;
}
return output;
}
public static long FillWithOnes(int bits)
{
return bits == 64 ? -1L : (1L << bits) - 1;
}
public static int RotateRight(int bits, int shift, int size)
{
return (int)RotateRight((uint)bits, shift, size);
}
public static uint RotateRight(uint bits, int shift, int size)
{
return (bits >> shift) | (bits << (size - shift));
}
public static long RotateRight(long bits, int shift, int size)
{
return (long)RotateRight((ulong)bits, shift, size);
}
public static ulong RotateRight(ulong bits, int shift, int size)
{
return (bits >> shift) | (bits << (size - shift));
}
}
}

99
ChocolArm64/Decoders/Block.cs
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@ -1,99 +0,0 @@
using System;
using System.Collections.Generic;
namespace ChocolArm64.Decoders
{
class Block
{
public ulong Address { get; set; }
public ulong EndAddress { get; set; }
public Block Next { get; set; }
public Block Branch { get; set; }
public List<OpCode64> OpCodes { get; private set; }
public Block()
{
OpCodes = new List<OpCode64>();
}
public Block(ulong address) : this()
{
Address = address;
}
public void Split(Block rightBlock)
{
int splitIndex = BinarySearch(OpCodes, rightBlock.Address);
if ((ulong)OpCodes[splitIndex].Position < rightBlock.Address)
{
splitIndex++;
}
int splitCount = OpCodes.Count - splitIndex;
if (splitCount <= 0)
{
throw new ArgumentException("Can't split at right block address.");
}
rightBlock.EndAddress = EndAddress;
rightBlock.Next = Next;
rightBlock.Branch = Branch;
rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount));
EndAddress = rightBlock.Address;
Next = rightBlock;
Branch = null;
OpCodes.RemoveRange(splitIndex, splitCount);
}
private static int BinarySearch(List<OpCode64> opCodes, ulong address)
{
int left = 0;
int middle = 0;
int right = opCodes.Count - 1;
while (left <= right)
{
int size = right - left;
middle = left + (size >> 1);
OpCode64 opCode = opCodes[middle];
if (address == (ulong)opCode.Position)
{
break;
}
if (address < (ulong)opCode.Position)
{
right = middle - 1;
}
else
{
left = middle + 1;
}
}
return middle;
}
public OpCode64 GetLastOp()
{
if (OpCodes.Count > 0)
{
return OpCodes[OpCodes.Count - 1];
}
return null;
}
}
}

32
ChocolArm64/Decoders/Condition.cs
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@ -1,32 +0,0 @@
namespace ChocolArm64.Decoders
{
enum Condition
{
Eq = 0,
Ne = 1,
GeUn = 2,
LtUn = 3,
Mi = 4,
Pl = 5,
Vs = 6,
Vc = 7,
GtUn = 8,
LeUn = 9,
Ge = 10,
Lt = 11,
Gt = 12,
Le = 13,
Al = 14,
Nv = 15
}
static class ConditionExtensions
{
public static Condition Invert(this Condition cond)
{
// Bit 0 of all conditions is basically a negation bit, so
// inverting this bit has the effect of inverting the condition.
return (Condition)((int)cond ^ 1);
}
}
}

10
ChocolArm64/Decoders/DataOp.cs
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@ -1,10 +0,0 @@
namespace ChocolArm64.Decoders
{
enum DataOp
{
Adr = 0,
Arithmetic = 1,
Logical = 2,
BitField = 3
}
}

379
ChocolArm64/Decoders/Decoder.cs
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@ -1,379 +0,0 @@
using ChocolArm64.Instructions;
using ChocolArm64.Memory;
using ChocolArm64.State;
using System;
using System.Collections.Concurrent;
using System.Collections.Generic;
using System.Reflection.Emit;
namespace ChocolArm64.Decoders
{
static class Decoder
{
private delegate object OpActivator(Inst inst, long position, int opCode);
private static ConcurrentDictionary<Type, OpActivator> _opActivators;
static Decoder()
{
_opActivators = new ConcurrentDictionary<Type, OpActivator>();
}
public static Block[] DecodeBasicBlock(MemoryManager memory, ulong address, ExecutionMode mode)
{
Block block = new Block(address);
FillBlock(memory, mode, block, ulong.MaxValue);
OpCode64 lastOp = block.GetLastOp();
if (IsBranch(lastOp) && !IsCall(lastOp) && lastOp is IOpCodeBImm op)
{
// It's possible that the branch on this block lands on the middle of the block.
// This is more common on tight loops. In this case, we can improve the codegen
// a bit by changing the CFG and either making the branch point to the same block
// (which indicates that the block is a loop that jumps back to the start), and the
// other possible case is a jump somewhere on the middle of the block, which is
// also a loop, but in this case we need to split the block in half.
if ((ulong)op.Imm == address)
{
block.Branch = block;
}
else if ((ulong)op.Imm > address &&
(ulong)op.Imm < block.EndAddress)
{
Block rightBlock = new Block((ulong)op.Imm);
block.Split(rightBlock);
return new Block[] { block, rightBlock };
}
}
return new Block[] { block };
}
public static Block[] DecodeSubroutine(MemoryManager memory, ulong address, ExecutionMode mode)
{
List<Block> blocks = new List<Block>();
Queue<Block> workQueue = new Queue<Block>();
Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
Block GetBlock(ulong blkAddress)
{
if (!visited.TryGetValue(blkAddress, out Block block))
{
block = new Block(blkAddress);
workQueue.Enqueue(block);
visited.Add(blkAddress, block);
}
return block;
}
GetBlock(address);
while (workQueue.TryDequeue(out Block currBlock))
{
// Check if the current block is inside another block.
if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
{
Block nBlock = blocks[nBlkIndex];
if (nBlock.Address == currBlock.Address)
{
throw new InvalidOperationException("Found duplicate block address on the list.");
}
nBlock.Split(currBlock);
blocks.Insert(nBlkIndex + 1, currBlock);
continue;
}
// If we have a block after the current one, set the limit address.
ulong limitAddress = ulong.MaxValue;
if (nBlkIndex != blocks.Count)
{
Block nBlock = blocks[nBlkIndex];
int nextIndex = nBlkIndex + 1;
if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
{
limitAddress = blocks[nextIndex].Address;
}
else if (nBlock.Address > currBlock.Address)
{
limitAddress = blocks[nBlkIndex].Address;
}
}
FillBlock(memory, mode, currBlock, limitAddress);
if (currBlock.OpCodes.Count != 0)
{
// Set child blocks. "Branch" is the block the branch instruction
// points to (when taken), "Next" is the block at the next address,
// executed when the branch is not taken. For Unconditional Branches
// (except BL/BLR that are sub calls) or end of executable, Next is null.
OpCode64 lastOp = currBlock.GetLastOp();
bool isCall = IsCall(lastOp);
if (lastOp is IOpCodeBImm op && !isCall)
{
currBlock.Branch = GetBlock((ulong)op.Imm);
}
if (!IsUnconditionalBranch(lastOp) || isCall)
{
currBlock.Next = GetBlock(currBlock.EndAddress);
}
}
// Insert the new block on the list (sorted by address).
if (blocks.Count != 0)
{
Block nBlock = blocks[nBlkIndex];
blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
}
else
{
blocks.Add(currBlock);
}
}
return blocks.ToArray();
}
private static bool BinarySearch(List<Block> blocks, ulong address, out int index)
{
index = 0;
int left = 0;
int right = blocks.Count - 1;
while (left <= right)
{
int size = right - left;
int middle = left + (size >> 1);
Block block = blocks[middle];
index = middle;
if (address >= block.Address && address < block.EndAddress)
{
return true;
}
if (address < block.Address)
{
right = middle - 1;
}
else
{
left = middle + 1;
}
}
return false;
}
private static void FillBlock(
MemoryManager memory,
ExecutionMode mode,
Block block,
ulong limitAddress)
{
ulong address = block.Address;
OpCode64 opCode;
do
{
if (address >= limitAddress)
{
break;
}
opCode = DecodeOpCode(memory, address, mode);
block.OpCodes.Add(opCode);
address += (ulong)opCode.OpCodeSizeInBytes;
}
while (!(IsBranch(opCode) || IsException(opCode)));
block.EndAddress = address;
}
private static bool IsBranch(OpCode64 opCode)
{
return opCode is OpCodeBImm64 ||
opCode is OpCodeBReg64 || IsAarch32Branch(opCode);
}
private static bool IsUnconditionalBranch(OpCode64 opCode)
{
return opCode is OpCodeBImmAl64 ||
opCode is OpCodeBReg64 || IsAarch32UnconditionalBranch(opCode);
}
private static bool IsAarch32UnconditionalBranch(OpCode64 opCode)
{
if (!(opCode is OpCode32 op))
{
return false;
}
// Note: On ARM32, most instructions have conditional execution,
// so there's no "Always" (unconditional) branch like on ARM64.
// We need to check if the condition is "Always" instead.
return IsAarch32Branch(op) && op.Cond >= Condition.Al;
}
private static bool IsAarch32Branch(OpCode64 opCode)
{
// Note: On ARM32, most ALU operations can write to R15 (PC),
// so we must consider such operations as a branch in potential as well.
if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
{
return true;
}
// Same thing for memory operations. We have the cases where PC is a target
// register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
// a write back to PC (wback == true && Rn == 15), however the later may
// be "undefined" depending on the CPU, so compilers should not produce that.
if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
{
int rt, rn;
bool wBack, isLoad;
if (opCode is IOpCode32Mem opMem)
{
rt = opMem.Rt;
rn = opMem.Rn;
wBack = opMem.WBack;
isLoad = opMem.IsLoad;
// For the dual load, we also need to take into account the
// case were Rt2 == 15 (PC).
if (rt == 14 && opMem.Emitter == InstEmit32.Ldrd)
{
rt = RegisterAlias.Aarch32Pc;
}
}
else if (opCode is IOpCode32MemMult opMemMult)
{
const int pcMask = 1 << RegisterAlias.Aarch32Pc;
rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
rn = opMemMult.Rn;
wBack = opMemMult.PostOffset != 0;
isLoad = opMemMult.IsLoad;
}
else
{
throw new NotImplementedException($"The type \"{opCode.GetType().Name}\" is not implemented on the decoder.");
}
if ((rt == RegisterAlias.Aarch32Pc && isLoad) ||
(rn == RegisterAlias.Aarch32Pc && wBack))
{
return true;
}
}
// Explicit branch instructions.
return opCode is IOpCode32BImm ||
opCode is IOpCode32BReg;
}
private static bool IsCall(OpCode64 opCode)
{
// TODO (CQ): ARM32 support.
return opCode.Emitter == InstEmit.Bl ||
opCode.Emitter == InstEmit.Blr;
}
private static bool IsException(OpCode64 opCode)
{
return opCode.Emitter == InstEmit.Brk ||
opCode.Emitter == InstEmit.Svc ||
opCode.Emitter == InstEmit.Und;
}
public static OpCode64 DecodeOpCode(MemoryManager memory, ulong address, ExecutionMode mode)
{
int opCode = memory.ReadInt32((long)address);
Inst inst;
if (mode == ExecutionMode.Aarch64)
{
inst = OpCodeTable.GetInstA64(opCode);
}
else
{
if (mode == ExecutionMode.Aarch32Arm)
{
inst = OpCodeTable.GetInstA32(opCode);
}
else /* if (mode == ExecutionMode.Aarch32Thumb) */
{
inst = OpCodeTable.GetInstT32(opCode);
}
}
OpCode64 decodedOpCode = new OpCode64(Inst.Undefined, (long)address, opCode);
if (inst.Type != null)
{
decodedOpCode = MakeOpCode(inst.Type, inst, (long)address, opCode);
}
return decodedOpCode;
}
private static OpCode64 MakeOpCode(Type type, Inst inst, long position, int opCode)
{
if (type == null)
{
throw new ArgumentNullException(nameof(type));
}
OpActivator createInstance = _opActivators.GetOrAdd(type, CacheOpActivator);
return (OpCode64)createInstance(inst, position, opCode);
}
private static OpActivator CacheOpActivator(Type type)
{
Type[] argTypes = new Type[] { typeof(Inst), typeof(long), typeof(int) };
DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
ILGenerator generator = mthd.GetILGenerator();
generator.Emit(OpCodes.Ldarg_0);
generator.Emit(OpCodes.Ldarg_1);
generator.Emit(OpCodes.Ldarg_2);
generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
generator.Emit(OpCodes.Ret);
return (OpActivator)mthd.CreateDelegate(typeof(OpActivator));
}
}
}

112
ChocolArm64/Decoders/DecoderHelper.cs
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@ -1,112 +0,0 @@
using System;
namespace ChocolArm64.Decoders
{
static class DecoderHelper
{
public struct BitMask
{
public long WMask;
public long TMask;
public int Pos;
public int Shift;
public bool IsUndefined;
public static BitMask Invalid => new BitMask { IsUndefined = true };
}
public static BitMask DecodeBitMask(int opCode, bool immediate)
{
int immS = (opCode >> 10) & 0x3f;
int immR = (opCode >> 16) & 0x3f;
int n = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1;
int length = BitUtils.HighestBitSet32((~immS & 0x3f) | (n << 6));
if (length < 1 || (sf == 0 && n != 0))
{
return BitMask.Invalid;
}
int size = 1 << length;
int levels = size - 1;
int s = immS & levels;
int r = immR & levels;
if (immediate && s == levels)
{
return BitMask.Invalid;
}
long wMask = BitUtils.FillWithOnes(s + 1);
long tMask = BitUtils.FillWithOnes(((s - r) & levels) + 1);
if (r > 0)
{
wMask = BitUtils.RotateRight(wMask, r, size);
wMask &= BitUtils.FillWithOnes(size);
}
return new BitMask()
{
WMask = BitUtils.Replicate(wMask, size),
TMask = BitUtils.Replicate(tMask, size),
Pos = immS,
Shift = immR
};
}
public static long DecodeImm8Float(long imm, int size)
{
int e = 0, f = 0;
switch (size)
{
case 0: e = 8; f = 23; break;
case 1: e = 11; f = 52; break;
default: throw new ArgumentOutOfRangeException(nameof(size));
}
long value = (imm & 0x3f) << f - 4;
long eBit = (imm >> 6) & 1;
long sBit = (imm >> 7) & 1;
if (eBit != 0)
{
value |= (1L << e - 3) - 1 << f + 2;
}
value |= (eBit ^ 1) << f + e - 1;
value |= sBit << f + e;
return value;
}
public static long DecodeImm24_2(int opCode)
{
return ((long)opCode << 40) >> 38;
}
public static long DecodeImm26_2(int opCode)
{
return ((long)opCode << 38) >> 36;
}
public static long DecodeImmS19_2(int opCode)
{
return (((long)opCode << 40) >> 43) & ~3;
}
public static long DecodeImmS14_2(int opCode)
{
return (((long)opCode << 45) >> 48) & ~3;
}
}
}

9
ChocolArm64/Decoders/IOpCode32.cs
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@ -1,9 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCode32 : IOpCode64
{
Condition Cond { get; }
uint GetPc();
}
}

10
ChocolArm64/Decoders/IOpCode32Alu.cs
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@ -1,10 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCode32Alu : IOpCode32
{
int Rd { get; }
int Rn { get; }
bool SetFlags { get; }
}
}

4
ChocolArm64/Decoders/IOpCode32BImm.cs
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@ -1,4 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCode32BImm : IOpCode32, IOpCodeBImm { }
}

7
ChocolArm64/Decoders/IOpCode32BReg.cs
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@ -1,7 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCode32BReg : IOpCode32
{
int Rm { get; }
}
}

12
ChocolArm64/Decoders/IOpCode32Mem.cs
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@ -1,12 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCode32Mem : IOpCode32
{
int Rt { get; }
int Rn { get; }
bool WBack { get; }
bool IsLoad { get; }
}
}

13
ChocolArm64/Decoders/IOpCode32MemMult.cs
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@ -1,13 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCode32MemMult : IOpCode32
{
int Rn { get; }
int RegisterMask { get; }
int PostOffset { get; }
bool IsLoad { get; }
}
}

13
ChocolArm64/Decoders/IOpCode64.cs
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@ -1,13 +0,0 @@
using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders
{
interface IOpCode64
{
long Position { get; }
InstEmitter Emitter { get; }
RegisterSize RegisterSize { get; }
}
}

10
ChocolArm64/Decoders/IOpCodeAlu64.cs
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@ -1,10 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeAlu64 : IOpCode64
{
int Rd { get; }
int Rn { get; }
DataOp DataOp { get; }
}
}

7
ChocolArm64/Decoders/IOpCodeAluImm64.cs
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@ -1,7 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeAluImm64 : IOpCodeAlu64
{
long Imm { get; }
}
}

10
ChocolArm64/Decoders/IOpCodeAluRs64.cs
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@ -1,10 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeAluRs64 : IOpCodeAlu64
{
int Shift { get; }
int Rm { get; }
ShiftType ShiftType { get; }
}
}

10
ChocolArm64/Decoders/IOpCodeAluRx64.cs
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@ -1,10 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeAluRx64 : IOpCodeAlu64
{
int Shift { get; }
int Rm { get; }
IntType IntType { get; }
}
}

7
ChocolArm64/Decoders/IOpCodeBImm.cs
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@ -1,7 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeBImm : IOpCode64
{
long Imm { get; }
}
}

7
ChocolArm64/Decoders/IOpCodeCond64.cs
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@ -1,7 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeCond64 : IOpCode64
{
Condition Cond { get; }
}
}

11
ChocolArm64/Decoders/IOpCodeLit64.cs
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@ -1,11 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeLit64 : IOpCode64
{
int Rt { get; }
long Imm { get; }
int Size { get; }
bool Signed { get; }
bool Prefetch { get; }
}
}

7
ChocolArm64/Decoders/IOpCodeSimd64.cs
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@ -1,7 +0,0 @@
namespace ChocolArm64.Decoders
{
interface IOpCodeSimd64 : IOpCode64
{
int Size { get; }
}
}

14
ChocolArm64/Decoders/IntType.cs
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@ -1,14 +0,0 @@
namespace ChocolArm64.Decoders
{
enum IntType
{
UInt8 = 0,
UInt16 = 1,
UInt32 = 2,
UInt64 = 3,
Int8 = 4,
Int16 = 5,
Int32 = 6,
Int64 = 7
}
}

24
ChocolArm64/Decoders/OpCode32.cs
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@ -1,24 +0,0 @@
using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders
{
class OpCode32 : OpCode64
{
public Condition Cond { get; protected set; }
public OpCode32(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
RegisterSize = RegisterSize.Int32;
Cond = (Condition)((uint)opCode >> 28);
}
public uint GetPc()
{
// Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
// the PC actually points 2 instructions ahead.
return (uint)Position + (uint)OpCodeSizeInBytes * 2;
}
}
}

20
ChocolArm64/Decoders/OpCode32Alu.cs
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@ -1,20 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32Alu : OpCode32, IOpCode32Alu
{
public int Rd { get; private set; }
public int Rn { get; private set; }
public bool SetFlags { get; private set; }
public OpCode32Alu(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rd = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf;
SetFlags = ((opCode >> 20) & 1) != 0;
}
}
}

21
ChocolArm64/Decoders/OpCode32AluImm.cs
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@ -1,21 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32AluImm : OpCode32Alu
{
public int Imm { get; private set; }
public bool IsRotated { get; private set; }
public OpCode32AluImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int value = (opCode >> 0) & 0xff;
int shift = (opCode >> 8) & 0xf;
Imm = BitUtils.RotateRight(value, shift * 2, 32);
IsRotated = shift != 0;
}
}
}

20
ChocolArm64/Decoders/OpCode32AluRsImm.cs
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@ -1,20 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32AluRsImm : OpCode32Alu
{
public int Rm { get; private set; }
public int Imm { get; private set; }
public ShiftType ShiftType { get; private set; }
public OpCode32AluRsImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rm = (opCode >> 0) & 0xf;
Imm = (opCode >> 7) & 0x1f;
ShiftType = (ShiftType)((opCode >> 5) & 3);
}
}
}

29
ChocolArm64/Decoders/OpCode32BImm.cs
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@ -1,29 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32BImm : OpCode32, IOpCode32BImm
{
public long Imm { get; private set; }
public OpCode32BImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
uint pc = GetPc();
// When the condition is never, the instruction is BLX to Thumb mode.
if (Cond != Condition.Nv)
{
pc &= ~3u;
}
Imm = pc + DecoderHelper.DecodeImm24_2(opCode);
if (Cond == Condition.Nv)
{
long H = (opCode >> 23) & 2;
Imm |= H;
}
}
}
}

14
ChocolArm64/Decoders/OpCode32BReg.cs
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@ -1,14 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32BReg : OpCode32, IOpCode32BReg
{
public int Rm { get; private set; }
public OpCode32BReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rm = opCode & 0xf;
}
}
}

37
ChocolArm64/Decoders/OpCode32Mem.cs
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@ -1,37 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32Mem : OpCode32, IOpCode32Mem
{
public int Rt { get; private set; }
public int Rn { get; private set; }
public int Imm { get; protected set; }
public bool Index { get; private set; }
public bool Add { get; private set; }
public bool WBack { get; private set; }
public bool Unprivileged { get; private set; }
public bool IsLoad { get; private set; }
public OpCode32Mem(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf;
bool isLoad = (opCode & (1 << 20)) != 0;
bool w = (opCode & (1 << 21)) != 0;
bool u = (opCode & (1 << 23)) != 0;
bool p = (opCode & (1 << 24)) != 0;
Index = p;
Add = u;
WBack = !p || w;
Unprivileged = !p && w;
IsLoad = isLoad || inst.Emitter == InstEmit32.Ldrd;
}
}
}

12
ChocolArm64/Decoders/OpCode32MemImm.cs
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@ -1,12 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32MemImm : OpCode32Mem
{
public OpCode32MemImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = opCode & 0xfff;
}
}
}

15
ChocolArm64/Decoders/OpCode32MemImm8.cs
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@ -1,15 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32MemImm8 : OpCode32Mem
{
public OpCode32MemImm8(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int imm4L = (opCode >> 0) & 0xf;
int imm4H = (opCode >> 8) & 0xf;
Imm = imm4L | (imm4H << 4);
}
}
}

57
ChocolArm64/Decoders/OpCode32MemMult.cs
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@ -1,57 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCode32MemMult : OpCode32, IOpCode32MemMult
{
public int Rn { get; private set; }
public int RegisterMask { get; private set; }
public int Offset { get; private set; }
public int PostOffset { get; private set; }
public bool IsLoad { get; private set; }
public OpCode32MemMult(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rn = (opCode >> 16) & 0xf;
bool isLoad = (opCode & (1 << 20)) != 0;
bool w = (opCode & (1 << 21)) != 0;
bool u = (opCode & (1 << 23)) != 0;
bool p = (opCode & (1 << 24)) != 0;
RegisterMask = opCode & 0xffff;
int regsSize = 0;
for (int index = 0; index < 16; index++)
{
regsSize += (RegisterMask >> index) & 1;
}
regsSize *= 4;
if (!u)
{
Offset -= regsSize;
}
if (u == p)
{
Offset += 4;
}
if (w)
{
PostOffset = u ? regsSize : -regsSize;
}
else
{
PostOffset = 0;
}
IsLoad = isLoad;
}
}
}

40
ChocolArm64/Decoders/OpCode64.cs
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@ -1,40 +0,0 @@
using ChocolArm64.Instructions;
using ChocolArm64.State;
using System;
namespace ChocolArm64.Decoders
{
class OpCode64 : IOpCode64
{
public long Position { get; private set; }
public int RawOpCode { get; private set; }
public int OpCodeSizeInBytes { get; protected set; } = 4;
public InstEmitter Emitter { get; protected set; }
public RegisterSize RegisterSize { get; protected set; }
public OpCode64(Inst inst, long position, int opCode)
{
Position = position;
RawOpCode = opCode;
RegisterSize = RegisterSize.Int64;
Emitter = inst.Emitter;
}
public int GetBitsCount()
{
switch (RegisterSize)
{
case RegisterSize.Int32: return 32;
case RegisterSize.Int64: return 64;
case RegisterSize.Simd64: return 64;
case RegisterSize.Simd128: return 128;
}
throw new InvalidOperationException();
}
}
}

18
ChocolArm64/Decoders/OpCodeAdr64.cs
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@ -1,18 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeAdr64 : OpCode64
{
public int Rd { get; private set; }
public long Imm { get; private set; }
public OpCodeAdr64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rd = opCode & 0x1f;
Imm = DecoderHelper.DecodeImmS19_2(opCode);
Imm |= ((long)opCode >> 29) & 3;
}
}
}

23
ChocolArm64/Decoders/OpCodeAlu64.cs
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@ -1,23 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeAlu64 : OpCode64, IOpCodeAlu64
{
public int Rd { get; protected set; }
public int Rn { get; private set; }
public DataOp DataOp { get; private set; }
public OpCodeAlu64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
DataOp = (DataOp)((opCode >> 24) & 0x3);
RegisterSize = (opCode >> 31) != 0
? State.RegisterSize.Int64
: State.RegisterSize.Int32;
}
}
}

39
ChocolArm64/Decoders/OpCodeAluImm64.cs
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@ -1,39 +0,0 @@
using ChocolArm64.Instructions;
using System;
namespace ChocolArm64.Decoders
{
class OpCodeAluImm64 : OpCodeAlu64, IOpCodeAluImm64
{
public long Imm { get; private set; }
public OpCodeAluImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
if (DataOp == DataOp.Arithmetic)
{
Imm = (opCode >> 10) & 0xfff;
int shift = (opCode >> 22) & 3;
Imm <<= shift * 12;
}
else if (DataOp == DataOp.Logical)
{
var bm = DecoderHelper.DecodeBitMask(opCode, true);
if (bm.IsUndefined)
{
Emitter = InstEmit.Und;
return;
}
Imm = bm.WMask;
}
else
{
throw new ArgumentException(nameof(opCode));
}
}
}
}

29
ChocolArm64/Decoders/OpCodeAluRs64.cs
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@ -1,29 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeAluRs64 : OpCodeAlu64, IOpCodeAluRs64
{
public int Shift { get; private set; }
public int Rm { get; private set; }
public ShiftType ShiftType { get; private set; }
public OpCodeAluRs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int shift = (opCode >> 10) & 0x3f;
if (shift >= GetBitsCount())
{
Emitter = InstEmit.Und;
return;
}
Shift = shift;
Rm = (opCode >> 16) & 0x1f;
ShiftType = (ShiftType)((opCode >> 22) & 0x3);
}
}
}

19
ChocolArm64/Decoders/OpCodeAluRx64.cs
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@ -1,19 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeAluRx64 : OpCodeAlu64, IOpCodeAluRx64
{
public int Shift { get; private set; }
public int Rm { get; private set; }
public IntType IntType { get; private set; }
public OpCodeAluRx64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Shift = (opCode >> 10) & 0x7;
IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f;
}
}
}

11
ChocolArm64/Decoders/OpCodeBImm64.cs
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@ -1,11 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBImm64 : OpCode64, IOpCodeBImm
{
public long Imm { get; protected set; }
public OpCodeBImm64(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

12
ChocolArm64/Decoders/OpCodeBImmAl64.cs
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@ -1,12 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBImmAl64 : OpCodeBImm64
{
public OpCodeBImmAl64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = position + DecoderHelper.DecodeImm26_2(opCode);
}
}
}

20
ChocolArm64/Decoders/OpCodeBImmCmp64.cs
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@ -1,20 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBImmCmp64 : OpCodeBImm64
{
public int Rt { get; private set; }
public OpCodeBImmCmp64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = opCode & 0x1f;
Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
RegisterSize = (opCode >> 31) != 0
? State.RegisterSize.Int64
: State.RegisterSize.Int32;
}
}
}

25
ChocolArm64/Decoders/OpCodeBImmCond64.cs
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@ -1,25 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBImmCond64 : OpCodeBImm64, IOpCodeCond64
{
public Condition Cond { get; private set; }
public OpCodeBImmCond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int o0 = (opCode >> 4) & 1;
if (o0 != 0)
{
Emitter = InstEmit.Und;
return;
}
Cond = (Condition)(opCode & 0xf);
Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
}
}
}

20
ChocolArm64/Decoders/OpCodeBImmTest64.cs
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@ -1,20 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBImmTest64 : OpCodeBImm64
{
public int Rt { get; private set; }
public int Pos { get; private set; }
public OpCodeBImmTest64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = opCode & 0x1f;
Imm = position + DecoderHelper.DecodeImmS14_2(opCode);
Pos = (opCode >> 19) & 0x1f;
Pos |= (opCode >> 26) & 0x20;
}
}
}

24
ChocolArm64/Decoders/OpCodeBReg64.cs
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@ -1,24 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBReg64 : OpCode64
{
public int Rn { get; private set; }
public OpCodeBReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int op4 = (opCode >> 0) & 0x1f;
int op2 = (opCode >> 16) & 0x1f;
if (op2 != 0b11111 || op4 != 0b00000)
{
Emitter = InstEmit.Und;
return;
}
Rn = (opCode >> 5) & 0x1f;
}
}
}

29
ChocolArm64/Decoders/OpCodeBfm64.cs
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@ -1,29 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBfm64 : OpCodeAlu64
{
public long WMask { get; private set; }
public long TMask { get; private set; }
public int Pos { get; private set; }
public int Shift { get; private set; }
public OpCodeBfm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
var bm = DecoderHelper.DecodeBitMask(opCode, false);
if (bm.IsUndefined)
{
Emitter = InstEmit.Und;
return;
}
WMask = bm.WMask;
TMask = bm.TMask;
Pos = bm.Pos;
Shift = bm.Shift;
}
}
}

31
ChocolArm64/Decoders/OpCodeCcmp64.cs
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@ -1,31 +0,0 @@
using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders
{
class OpCodeCcmp64 : OpCodeAlu64, IOpCodeCond64
{
public int Nzcv { get; private set; }
protected int RmImm;
public Condition Cond { get; private set; }
public OpCodeCcmp64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int o3 = (opCode >> 4) & 1;
if (o3 != 0)
{
Emitter = InstEmit.Und;
return;
}
Nzcv = (opCode >> 0) & 0xf;
Cond = (Condition)((opCode >> 12) & 0xf);
RmImm = (opCode >> 16) & 0x1f;
Rd = RegisterAlias.Zr;
}
}
}

11
ChocolArm64/Decoders/OpCodeCcmpImm64.cs
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@ -1,11 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeCcmpImm64 : OpCodeCcmp64, IOpCodeAluImm64
{
public long Imm => RmImm;
public OpCodeCcmpImm64(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

15
ChocolArm64/Decoders/OpCodeCcmpReg64.cs
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@ -1,15 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeCcmpReg64 : OpCodeCcmp64, IOpCodeAluRs64
{
public int Rm => RmImm;
public int Shift => 0;
public ShiftType ShiftType => ShiftType.Lsl;
public OpCodeCcmpReg64(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

17
ChocolArm64/Decoders/OpCodeCsel64.cs
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@ -1,17 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeCsel64 : OpCodeAlu64, IOpCodeCond64
{
public int Rm { get; private set; }
public Condition Cond { get; private set; }
public OpCodeCsel64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rm = (opCode >> 16) & 0x1f;
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
}

14
ChocolArm64/Decoders/OpCodeException64.cs
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@ -1,14 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeException64 : OpCode64
{
public int Id { get; private set; }
public OpCodeException64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Id = (opCode >> 5) & 0xffff;
}
}
}

19
ChocolArm64/Decoders/OpCodeMem64.cs
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@ -1,19 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMem64 : OpCode64
{
public int Rt { get; protected set; }
public int Rn { get; protected set; }
public int Size { get; protected set; }
public bool Extend64 { get; protected set; }
public OpCodeMem64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
Size = (opCode >> 30) & 0x3;
}
}
}

16
ChocolArm64/Decoders/OpCodeMemEx64.cs
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@ -1,16 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMemEx64 : OpCodeMem64
{
public int Rt2 { get; private set; }
public int Rs { get; private set; }
public OpCodeMemEx64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt2 = (opCode >> 10) & 0x1f;
Rs = (opCode >> 16) & 0x1f;
}
}
}

53
ChocolArm64/Decoders/OpCodeMemImm64.cs
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@ -1,53 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMemImm64 : OpCodeMem64
{
public long Imm { get; protected set; }
public bool WBack { get; protected set; }
public bool PostIdx { get; protected set; }
protected bool Unscaled { get; private set; }
private enum MemOp
{
Unscaled = 0,
PostIndexed = 1,
Unprivileged = 2,
PreIndexed = 3,
Unsigned
}
public OpCodeMemImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Extend64 = ((opCode >> 22) & 3) == 2;
WBack = ((opCode >> 24) & 1) == 0;
// The type is not valid for the Unsigned Immediate 12-bits encoding,
// because the bits 11:10 are used for the larger Immediate offset.
MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned;
PostIdx = type == MemOp.PostIndexed;
Unscaled = type == MemOp.Unscaled ||
type == MemOp.Unprivileged;
// Unscaled and Unprivileged doesn't write back,
// but they do use the 9-bits Signed Immediate.
if (Unscaled)
{
WBack = false;
}
if (WBack || Unscaled)
{
// 9-bits Signed Immediate.
Imm = (opCode << 11) >> 23;
}
else
{
// 12-bits Unsigned Immediate.
Imm = ((opCode >> 10) & 0xfff) << Size;
}
}
}
}

28
ChocolArm64/Decoders/OpCodeMemLit64.cs
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@ -1,28 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMemLit64 : OpCode64, IOpCodeLit64
{
public int Rt { get; private set; }
public long Imm { get; private set; }
public int Size { get; private set; }
public bool Signed { get; private set; }
public bool Prefetch { get; private set; }
public OpCodeMemLit64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = opCode & 0x1f;
Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
switch ((opCode >> 30) & 3)
{
case 0: Size = 2; Signed = false; Prefetch = false; break;
case 1: Size = 3; Signed = false; Prefetch = false; break;
case 2: Size = 2; Signed = true; Prefetch = false; break;
case 3: Size = 0; Signed = false; Prefetch = true; break;
}
}
}
}

25
ChocolArm64/Decoders/OpCodeMemPair64.cs
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@ -1,25 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMemPair64 : OpCodeMemImm64
{
public int Rt2 { get; private set; }
public OpCodeMemPair64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt2 = (opCode >> 10) & 0x1f;
WBack = ((opCode >> 23) & 0x1) != 0;
PostIdx = ((opCode >> 23) & 0x3) == 1;
Extend64 = ((opCode >> 30) & 0x3) == 1;
Size = ((opCode >> 31) & 0x1) | 2;
DecodeImm(opCode);
}
protected void DecodeImm(int opCode)
{
Imm = ((long)(opCode >> 15) << 57) >> (57 - Size);
}
}
}

20
ChocolArm64/Decoders/OpCodeMemReg64.cs
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@ -1,20 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMemReg64 : OpCodeMem64
{
public bool Shift { get; private set; }
public int Rm { get; private set; }
public IntType IntType { get; private set; }
public OpCodeMemReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Shift = ((opCode >> 12) & 0x1) != 0;
IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f;
Extend64 = ((opCode >> 22) & 0x3) == 2;
}
}
}

35
ChocolArm64/Decoders/OpCodeMov64.cs
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@ -1,35 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMov64 : OpCode64
{
public int Rd { get; private set; }
public long Imm { get; private set; }
public int Pos { get; private set; }
public OpCodeMov64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int p1 = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1;
if (sf == 0 && p1 != 0)
{
Emitter = InstEmit.Und;
return;
}
Rd = (opCode >> 0) & 0x1f;
Imm = (opCode >> 5) & 0xffff;
Pos = (opCode >> 21) & 0x3;
Pos <<= 4;
Imm <<= Pos;
RegisterSize = (opCode >> 31) != 0
? State.RegisterSize.Int64
: State.RegisterSize.Int32;
}
}
}

16
ChocolArm64/Decoders/OpCodeMul64.cs
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@ -1,16 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeMul64 : OpCodeAlu64
{
public int Rm { get; private set; }
public int Ra { get; private set; }
public OpCodeMul64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Ra = (opCode >> 10) & 0x1f;
Rm = (opCode >> 16) & 0x1f;
}
}
}

25
ChocolArm64/Decoders/OpCodeSimd64.cs
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@ -1,25 +0,0 @@
using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders
{
class OpCodeSimd64 : OpCode64, IOpCodeSimd64
{
public int Rd { get; private set; }
public int Rn { get; private set; }
public int Opc { get; private set; }
public int Size { get; protected set; }
public OpCodeSimd64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
Opc = (opCode >> 15) & 0x3;
Size = (opCode >> 22) & 0x3;
RegisterSize = ((opCode >> 30) & 1) != 0
? RegisterSize.Simd128
: RegisterSize.Simd64;
}
}
}

21
ChocolArm64/Decoders/OpCodeSimdCvt64.cs
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@ -1,21 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdCvt64 : OpCodeSimd64
{
public int FBits { get; private set; }
public OpCodeSimdCvt64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int scale = (opCode >> 10) & 0x3f;
int sf = (opCode >> 31) & 0x1;
FBits = 64 - scale;
RegisterSize = sf != 0
? State.RegisterSize.Int64
: State.RegisterSize.Int32;
}
}
}

14
ChocolArm64/Decoders/OpCodeSimdExt64.cs
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@ -1,14 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdExt64 : OpCodeSimdReg64
{
public int Imm4 { get; private set; }
public OpCodeSimdExt64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm4 = (opCode >> 11) & 0xf;
}
}
}

17
ChocolArm64/Decoders/OpCodeSimdFcond64.cs
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@ -1,17 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdFcond64 : OpCodeSimdReg64, IOpCodeCond64
{
public int Nzcv { get; private set; }
public Condition Cond { get; private set; }
public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Nzcv = (opCode >> 0) & 0xf;
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
}

33
ChocolArm64/Decoders/OpCodeSimdFmov64.cs
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@ -1,33 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdFmov64 : OpCode64, IOpCodeSimd64
{
public int Rd { get; private set; }
public long Imm { get; private set; }
public int Size { get; private set; }
public OpCodeSimdFmov64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int imm5 = (opCode >> 5) & 0x1f;
int type = (opCode >> 22) & 0x3;
if (imm5 != 0b00000 || type > 1)
{
Emitter = InstEmit.Und;
return;
}
Size = type;
long imm;
Rd = (opCode >> 0) & 0x1f;
imm = (opCode >> 13) & 0xff;
Imm = DecoderHelper.DecodeImm8Float(imm, type);
}
}
}

100
ChocolArm64/Decoders/OpCodeSimdImm64.cs
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@ -1,100 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdImm64 : OpCode64, IOpCodeSimd64
{
public int Rd { get; private set; }
public long Imm { get; private set; }
public int Size { get; private set; }
public OpCodeSimdImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rd = opCode & 0x1f;
int cMode = (opCode >> 12) & 0xf;
int op = (opCode >> 29) & 0x1;
int modeLow = cMode & 1;
int modeHigh = cMode >> 1;
long imm;
imm = ((uint)opCode >> 5) & 0x1f;
imm |= ((uint)opCode >> 11) & 0xe0;
if (modeHigh == 0b111)
{
Size = modeLow != 0 ? op : 3;
switch (op | (modeLow << 1))
{
case 0:
// 64-bits Immediate.
// Transform abcd efgh into abcd efgh abcd efgh ...
imm = (long)((ulong)imm * 0x0101010101010101);
break;
case 1:
// 64-bits Immediate.
// Transform abcd efgh into aaaa aaaa bbbb bbbb ...
imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4;
imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2;
imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1;
imm = (long)((ulong)imm * 0x8040201008040201);
imm = (long)((ulong)imm & 0x8080808080808080);
imm |= imm >> 4;
imm |= imm >> 2;
imm |= imm >> 1;
break;
case 2:
case 3:
// Floating point Immediate.
imm = DecoderHelper.DecodeImm8Float(imm, Size);
break;
}
}
else if ((modeHigh & 0b110) == 0b100)
{
// 16-bits shifted Immediate.
Size = 1; imm <<= (modeHigh & 1) << 3;
}
else if ((modeHigh & 0b100) == 0b000)
{
// 32-bits shifted Immediate.
Size = 2; imm <<= modeHigh << 3;
}
else if ((modeHigh & 0b111) == 0b110)
{
// 32-bits shifted Immediate (fill with ones).
Size = 2; imm = ShlOnes(imm, 8 << modeLow);
}
else
{
// 8 bits without shift.
Size = 0;
}
Imm = imm;
RegisterSize = ((opCode >> 30) & 1) != 0
? State.RegisterSize.Simd128
: State.RegisterSize.Simd64;
}
private static long ShlOnes(long value, int shift)
{
if (shift != 0)
{
return value << shift | (long)(ulong.MaxValue >> (64 - shift));
}
else
{
return value;
}
}
}
}

36
ChocolArm64/Decoders/OpCodeSimdIns64.cs
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@ -1,36 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdIns64 : OpCodeSimd64
{
public int SrcIndex { get; private set; }
public int DstIndex { get; private set; }
public OpCodeSimdIns64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int imm4 = (opCode >> 11) & 0xf;
int imm5 = (opCode >> 16) & 0x1f;
if (imm5 == 0b10000)
{
Emitter = InstEmit.Und;
return;
}
Size = imm5 & -imm5;
switch (Size)
{
case 1: Size = 0; break;
case 2: Size = 1; break;
case 4: Size = 2; break;
case 8: Size = 3; break;
}
SrcIndex = imm4 >> Size;
DstIndex = imm5 >> (Size + 1);
}
}
}

19
ChocolArm64/Decoders/OpCodeSimdMemImm64.cs
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@ -1,19 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdMemImm64 : OpCodeMemImm64, IOpCodeSimd64
{
public OpCodeSimdMemImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Size |= (opCode >> 21) & 4;
if (!WBack && !Unscaled && Size >= 4)
{
Imm <<= 4;
}
Extend64 = false;
}
}
}

31
ChocolArm64/Decoders/OpCodeSimdMemLit64.cs
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@ -1,31 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdMemLit64 : OpCode64, IOpCodeSimd64, IOpCodeLit64
{
public int Rt { get; private set; }
public long Imm { get; private set; }
public int Size { get; private set; }
public bool Signed => false;
public bool Prefetch => false;
public OpCodeSimdMemLit64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int opc = (opCode >> 30) & 3;
if (opc == 3)
{
Emitter = InstEmit.Und;
return;
}
Rt = opCode & 0x1f;
Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
Size = opc + 2;
}
}
}

48
ChocolArm64/Decoders/OpCodeSimdMemMs64.cs
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@ -1,48 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdMemMs64 : OpCodeMemReg64, IOpCodeSimd64
{
public int Reps { get; private set; }
public int SElems { get; private set; }
public int Elems { get; private set; }
public bool WBack { get; private set; }
public OpCodeSimdMemMs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
switch ((opCode >> 12) & 0xf)
{
case 0b0000: Reps = 1; SElems = 4; break;
case 0b0010: Reps = 4; SElems = 1; break;
case 0b0100: Reps = 1; SElems = 3; break;
case 0b0110: Reps = 3; SElems = 1; break;
case 0b0111: Reps = 1; SElems = 1; break;
case 0b1000: Reps = 1; SElems = 2; break;
case 0b1010: Reps = 2; SElems = 1; break;
default: inst = Inst.Undefined; return;
}
Size = (opCode >> 10) & 3;
WBack = ((opCode >> 23) & 1) != 0;
bool q = ((opCode >> 30) & 1) != 0;
if (!q && Size == 3 && SElems != 1)
{
inst = Inst.Undefined;
return;
}
Extend64 = false;
RegisterSize = q
? State.RegisterSize.Simd128
: State.RegisterSize.Simd64;
Elems = (GetBitsCount() >> 3) >> Size;
}
}
}

16
ChocolArm64/Decoders/OpCodeSimdMemPair64.cs
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@ -1,16 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdMemPair64 : OpCodeMemPair64, IOpCodeSimd64
{
public OpCodeSimdMemPair64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Size = ((opCode >> 30) & 3) + 2;
Extend64 = false;
DecodeImm(opCode);
}
}
}

14
ChocolArm64/Decoders/OpCodeSimdMemReg64.cs
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@ -1,14 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdMemReg64 : OpCodeMemReg64, IOpCodeSimd64
{
public OpCodeSimdMemReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Size |= (opCode >> 21) & 4;
Extend64 = false;
}
}
}

97
ChocolArm64/Decoders/OpCodeSimdMemSs64.cs
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@ -1,97 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdMemSs64 : OpCodeMemReg64, IOpCodeSimd64
{
public int SElems { get; private set; }
public int Index { get; private set; }
public bool Replicate { get; private set; }
public bool WBack { get; private set; }
public OpCodeSimdMemSs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int size = (opCode >> 10) & 3;
int s = (opCode >> 12) & 1;
int sElems = (opCode >> 12) & 2;
int scale = (opCode >> 14) & 3;
int l = (opCode >> 22) & 1;
int q = (opCode >> 30) & 1;
sElems |= (opCode >> 21) & 1;
sElems++;
int index = (q << 3) | (s << 2) | size;
switch (scale)
{
case 1:
{
if ((size & 1) != 0)
{
inst = Inst.Undefined;
return;
}
index >>= 1;
break;
}
case 2:
{
if ((size & 2) != 0 ||
((size & 1) != 0 && s != 0))
{
inst = Inst.Undefined;
return;
}
if ((size & 1) != 0)
{
index >>= 3;
scale = 3;
}
else
{
index >>= 2;
}
break;
}
case 3:
{
if (l == 0 || s != 0)
{
inst = Inst.Undefined;
return;
}
scale = size;
Replicate = true;
break;
}
}
Index = index;
SElems = sElems;
Size = scale;
Extend64 = false;
WBack = ((opCode >> 23) & 1) != 0;
RegisterSize = q != 0
? State.RegisterSize.Simd128
: State.RegisterSize.Simd64;
}
}
}

18
ChocolArm64/Decoders/OpCodeSimdReg64.cs
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@ -1,18 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdReg64 : OpCodeSimd64
{
public bool Bit3 { get; private set; }
public int Ra { get; private set; }
public int Rm { get; protected set; }
public OpCodeSimdReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Bit3 = ((opCode >> 3) & 0x1) != 0;
Ra = (opCode >> 10) & 0x1f;
Rm = (opCode >> 16) & 0x1f;
}
}
}

31
ChocolArm64/Decoders/OpCodeSimdRegElem64.cs
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using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdRegElem64 : OpCodeSimdReg64
{
public int Index { get; private set; }
public OpCodeSimdRegElem64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
switch (Size)
{
case 1:
Index = (opCode >> 20) & 3 |
(opCode >> 9) & 4;
Rm &= 0xf;
break;
case 2:
Index = (opCode >> 21) & 1 |
(opCode >> 10) & 2;
break;
default: Emitter = InstEmit.Und; return;
}
}
}
}

33
ChocolArm64/Decoders/OpCodeSimdRegElemF64.cs
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@ -1,33 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdRegElemF64 : OpCodeSimdReg64
{
public int Index { get; private set; }
public OpCodeSimdRegElemF64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
switch ((opCode >> 21) & 3) // sz:L
{
case 0: // H:0
Index = (opCode >> 10) & 2; // 0, 2
break;
case 1: // H:1
Index = (opCode >> 10) & 2;
Index++; // 1, 3
break;
case 2: // H
Index = (opCode >> 11) & 1; // 0, 1
break;
default: Emitter = InstEmit.Und; return;
}
}
}
}

16
ChocolArm64/Decoders/OpCodeSimdShImm64.cs
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@ -1,16 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdShImm64 : OpCodeSimd64
{
public int Imm { get; private set; }
public OpCodeSimdShImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = (opCode >> 16) & 0x7f;
Size = BitUtils.HighestBitSetNibble(Imm >> 3);
}
}
}

12
ChocolArm64/Decoders/OpCodeSimdTbl64.cs
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@ -1,12 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdTbl64 : OpCodeSimdReg64
{
public OpCodeSimdTbl64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Size = ((opCode >> 13) & 3) + 1;
}
}
}

24
ChocolArm64/Decoders/OpCodeSystem64.cs
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@ -1,24 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSystem64 : OpCode64
{
public int Rt { get; private set; }
public int Op2 { get; private set; }
public int CRm { get; private set; }
public int CRn { get; private set; }
public int Op1 { get; private set; }
public int Op0 { get; private set; }
public OpCodeSystem64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = (opCode >> 0) & 0x1f;
Op2 = (opCode >> 5) & 0x7;
CRm = (opCode >> 8) & 0xf;
CRn = (opCode >> 12) & 0xf;
Op1 = (opCode >> 16) & 0x7;
Op0 = ((opCode >> 19) & 0x1) | 2;
}
}
}

14
ChocolArm64/Decoders/OpCodeT16.cs
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@ -1,14 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeT16 : OpCode32
{
public OpCodeT16(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Cond = Condition.Al;
OpCodeSizeInBytes = 2;
}
}
}

22
ChocolArm64/Decoders/OpCodeT16AluImm8.cs
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@ -1,22 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeT16AluImm8 : OpCodeT16, IOpCode32Alu
{
private int _rdn;
public int Rd => _rdn;
public int Rn => _rdn;
public bool SetFlags => false;
public int Imm { get; private set; }
public OpCodeT16AluImm8(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = (opCode >> 0) & 0xff;
_rdn = (opCode >> 8) & 0x7;
}
}
}

14
ChocolArm64/Decoders/OpCodeT16BReg.cs
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@ -1,14 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeT16BReg : OpCodeT16, IOpCode32BReg
{
public int Rm { get; private set; }
public OpCodeT16BReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rm = (opCode >> 3) & 0xf;
}
}
}

10
ChocolArm64/Decoders/ShiftType.cs
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@ -1,10 +0,0 @@
namespace ChocolArm64.Decoders
{
enum ShiftType
{
Lsl = 0,
Lsr = 1,
Asr = 2,
Ror = 3
}
}

14
ChocolArm64/Events/CpuTraceEventArgs.cs
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@ -1,14 +0,0 @@
using System;
namespace ChocolArm64.Events
{
public class CpuTraceEventArgs : EventArgs
{
public long Position { get; private set; }
public CpuTraceEventArgs(long position)
{
Position = position;
}
}
}

16
ChocolArm64/Events/InstExceptionEventArgs.cs
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@ -1,16 +0,0 @@
using System;
namespace ChocolArm64.Events
{
public class InstExceptionEventArgs : EventArgs
{
public long Position { get; private set; }
public int Id { get; private set; }
public InstExceptionEventArgs(long position, int id)
{
Position = position;
Id = id;
}
}
}

16
ChocolArm64/Events/InstUndefinedEventArgs.cs
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@ -1,16 +0,0 @@
using System;
namespace ChocolArm64.Events
{
public class InstUndefinedEventArgs : EventArgs
{
public long Position { get; private set; }
public int RawOpCode { get; private set; }
public InstUndefinedEventArgs(long position, int rawOpCode)
{
Position = position;
RawOpCode = rawOpCode;
}
}
}

331
ChocolArm64/Instructions/CryptoHelper.cs
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@ -1,331 +0,0 @@
// https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf
using System;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.X86;
namespace ChocolArm64.Instructions
{
static class CryptoHelper
{
#region "LookUp Tables"
private static readonly byte[] _sBox = new byte[]
{
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
};
private static readonly byte[] _invSBox = new byte[]
{
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
};
private static readonly byte[] _gfMul02 = new byte[]
{
0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e,
0x60, 0x62, 0x64, 0x66, 0x68, 0x6a, 0x6c, 0x6e, 0x70, 0x72, 0x74, 0x76, 0x78, 0x7a, 0x7c, 0x7e,
0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9c, 0x9e,
0xa0, 0xa2, 0xa4, 0xa6, 0xa8, 0xaa, 0xac, 0xae, 0xb0, 0xb2, 0xb4, 0xb6, 0xb8, 0xba, 0xbc, 0xbe,
0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce, 0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
0xe0, 0xe2, 0xe4, 0xe6, 0xe8, 0xea, 0xec, 0xee, 0xf0, 0xf2, 0xf4, 0xf6, 0xf8, 0xfa, 0xfc, 0xfe,
0x1b, 0x19, 0x1f, 0x1d, 0x13, 0x11, 0x17, 0x15, 0x0b, 0x09, 0x0f, 0x0d, 0x03, 0x01, 0x07, 0x05,
0x3b, 0x39, 0x3f, 0x3d, 0x33, 0x31, 0x37, 0x35, 0x2b, 0x29, 0x2f, 0x2d, 0x23, 0x21, 0x27, 0x25,
0x5b, 0x59, 0x5f, 0x5d, 0x53, 0x51, 0x57, 0x55, 0x4b, 0x49, 0x4f, 0x4d, 0x43, 0x41, 0x47, 0x45,
0x7b, 0x79, 0x7f, 0x7d, 0x73, 0x71, 0x77, 0x75, 0x6b, 0x69, 0x6f, 0x6d, 0x63, 0x61, 0x67, 0x65,
0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, 0x83, 0x81, 0x87, 0x85,
0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5,
0xdb, 0xd9, 0xdf, 0xdd, 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5,
0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5
};
private static readonly byte[] _gfMul03 = new byte[]
{
0x00, 0x03, 0x06, 0x05, 0x0c, 0x0f, 0x0a, 0x09, 0x18, 0x1b, 0x1e, 0x1d, 0x14, 0x17, 0x12, 0x11,
0x30, 0x33, 0x36, 0x35, 0x3c, 0x3f, 0x3a, 0x39, 0x28, 0x2b, 0x2e, 0x2d, 0x24, 0x27, 0x22, 0x21,
0x60, 0x63, 0x66, 0x65, 0x6c, 0x6f, 0x6a, 0x69, 0x78, 0x7b, 0x7e, 0x7d, 0x74, 0x77, 0x72, 0x71,
0x50, 0x53, 0x56, 0x55, 0x5c, 0x5f, 0x5a, 0x59, 0x48, 0x4b, 0x4e, 0x4d, 0x44, 0x47, 0x42, 0x41,
0xc0, 0xc3, 0xc6, 0xc5, 0xcc, 0xcf, 0xca, 0xc9, 0xd8, 0xdb, 0xde, 0xdd, 0xd4, 0xd7, 0xd2, 0xd1,
0xf0, 0xf3, 0xf6, 0xf5, 0xfc, 0xff, 0xfa, 0xf9, 0xe8, 0xeb, 0xee, 0xed, 0xe4, 0xe7, 0xe2, 0xe1,
0xa0, 0xa3, 0xa6, 0xa5, 0xac, 0xaf, 0xaa, 0xa9, 0xb8, 0xbb, 0xbe, 0xbd, 0xb4, 0xb7, 0xb2, 0xb1,
0x90, 0x93, 0x96, 0x95, 0x9c, 0x9f, 0x9a, 0x99, 0x88, 0x8b, 0x8e, 0x8d, 0x84, 0x87, 0x82, 0x81,
0x9b, 0x98, 0x9d, 0x9e, 0x97, 0x94, 0x91, 0x92, 0x83, 0x80, 0x85, 0x86, 0x8f, 0x8c, 0x89, 0x8a,
0xab, 0xa8, 0xad, 0xae, 0xa7, 0xa4, 0xa1, 0xa2, 0xb3, 0xb0, 0xb5, 0xb6, 0xbf, 0xbc, 0xb9, 0xba,
0xfb, 0xf8, 0xfd, 0xfe, 0xf7, 0xf4, 0xf1, 0xf2, 0xe3, 0xe0, 0xe5, 0xe6, 0xef, 0xec, 0xe9, 0xea,
0xcb, 0xc8, 0xcd, 0xce, 0xc7, 0xc4, 0xc1, 0xc2, 0xd3, 0xd0, 0xd5, 0xd6, 0xdf, 0xdc, 0xd9, 0xda,
0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, 0x4f, 0x4c, 0x49, 0x4a,
0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a,
0x3b, 0x38, 0x3d, 0x3e, 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a,
0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a
};
private static readonly byte[] _gfMul09 = new byte[]
{
0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
0x90, 0x99, 0x82, 0x8b, 0xb4, 0xbd, 0xa6, 0xaf, 0xd8, 0xd1, 0xca, 0xc3, 0xfc, 0xf5, 0xee, 0xe7,
0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
0xab, 0xa2, 0xb9, 0xb0, 0x8f, 0x86, 0x9d, 0x94, 0xe3, 0xea, 0xf1, 0xf8, 0xc7, 0xce, 0xd5, 0xdc,
0x76, 0x7f, 0x64, 0x6d, 0x52, 0x5b, 0x40, 0x49, 0x3e, 0x37, 0x2c, 0x25, 0x1a, 0x13, 0x08, 0x01,
0xe6, 0xef, 0xf4, 0xfd, 0xc2, 0xcb, 0xd0, 0xd9, 0xae, 0xa7, 0xbc, 0xb5, 0x8a, 0x83, 0x98, 0x91,
0x4d, 0x44, 0x5f, 0x56, 0x69, 0x60, 0x7b, 0x72, 0x05, 0x0c, 0x17, 0x1e, 0x21, 0x28, 0x33, 0x3a,
0xdd, 0xd4, 0xcf, 0xc6, 0xf9, 0xf0, 0xeb, 0xe2, 0x95, 0x9c, 0x87, 0x8e, 0xb1, 0xb8, 0xa3, 0xaa,
0xec, 0xe5, 0xfe, 0xf7, 0xc8, 0xc1, 0xda, 0xd3, 0xa4, 0xad, 0xb6, 0xbf, 0x80, 0x89, 0x92, 0x9b,
0x7c, 0x75, 0x6e, 0x67, 0x58, 0x51, 0x4a, 0x43, 0x34, 0x3d, 0x26, 0x2f, 0x10, 0x19, 0x02, 0x0b,
0xd7, 0xde, 0xc5, 0xcc, 0xf3, 0xfa, 0xe1, 0xe8, 0x9f, 0x96, 0x8d, 0x84, 0xbb, 0xb2, 0xa9, 0xa0,
0x47, 0x4e, 0x55, 0x5c, 0x63, 0x6a, 0x71, 0x78, 0x0f, 0x06, 0x1d, 0x14, 0x2b, 0x22, 0x39, 0x30,
0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, 0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed,
0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d,
0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e, 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6,
0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46
};
private static readonly byte[] _gfMul0B = new byte[]
{
0x00, 0x0b, 0x16, 0x1d, 0x2c, 0x27, 0x3a, 0x31, 0x58, 0x53, 0x4e, 0x45, 0x74, 0x7f, 0x62, 0x69,
0xb0, 0xbb, 0xa6, 0xad, 0x9c, 0x97, 0x8a, 0x81, 0xe8, 0xe3, 0xfe, 0xf5, 0xc4, 0xcf, 0xd2, 0xd9,
0x7b, 0x70, 0x6d, 0x66, 0x57, 0x5c, 0x41, 0x4a, 0x23, 0x28, 0x35, 0x3e, 0x0f, 0x04, 0x19, 0x12,
0xcb, 0xc0, 0xdd, 0xd6, 0xe7, 0xec, 0xf1, 0xfa, 0x93, 0x98, 0x85, 0x8e, 0xbf, 0xb4, 0xa9, 0xa2,
0xf6, 0xfd, 0xe0, 0xeb, 0xda, 0xd1, 0xcc, 0xc7, 0xae, 0xa5, 0xb8, 0xb3, 0x82, 0x89, 0x94, 0x9f,
0x46, 0x4d, 0x50, 0x5b, 0x6a, 0x61, 0x7c, 0x77, 0x1e, 0x15, 0x08, 0x03, 0x32, 0x39, 0x24, 0x2f,
0x8d, 0x86, 0x9b, 0x90, 0xa1, 0xaa, 0xb7, 0xbc, 0xd5, 0xde, 0xc3, 0xc8, 0xf9, 0xf2, 0xef, 0xe4,
0x3d, 0x36, 0x2b, 0x20, 0x11, 0x1a, 0x07, 0x0c, 0x65, 0x6e, 0x73, 0x78, 0x49, 0x42, 0x5f, 0x54,
0xf7, 0xfc, 0xe1, 0xea, 0xdb, 0xd0, 0xcd, 0xc6, 0xaf, 0xa4, 0xb9, 0xb2, 0x83, 0x88, 0x95, 0x9e,
0x47, 0x4c, 0x51, 0x5a, 0x6b, 0x60, 0x7d, 0x76, 0x1f, 0x14, 0x09, 0x02, 0x33, 0x38, 0x25, 0x2e,
0x8c, 0x87, 0x9a, 0x91, 0xa0, 0xab, 0xb6, 0xbd, 0xd4, 0xdf, 0xc2, 0xc9, 0xf8, 0xf3, 0xee, 0xe5,
0x3c, 0x37, 0x2a, 0x21, 0x10, 0x1b, 0x06, 0x0d, 0x64, 0x6f, 0x72, 0x79, 0x48, 0x43, 0x5e, 0x55,
0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, 0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68,
0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8,
0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b, 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13,
0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3
};
private static readonly byte[] _gfMul0D = new byte[]
{
0x00, 0x0d, 0x1a, 0x17, 0x34, 0x39, 0x2e, 0x23, 0x68, 0x65, 0x72, 0x7f, 0x5c, 0x51, 0x46, 0x4b,
0xd0, 0xdd, 0xca, 0xc7, 0xe4, 0xe9, 0xfe, 0xf3, 0xb8, 0xb5, 0xa2, 0xaf, 0x8c, 0x81, 0x96, 0x9b,
0xbb, 0xb6, 0xa1, 0xac, 0x8f, 0x82, 0x95, 0x98, 0xd3, 0xde, 0xc9, 0xc4, 0xe7, 0xea, 0xfd, 0xf0,
0x6b, 0x66, 0x71, 0x7c, 0x5f, 0x52, 0x45, 0x48, 0x03, 0x0e, 0x19, 0x14, 0x37, 0x3a, 0x2d, 0x20,
0x6d, 0x60, 0x77, 0x7a, 0x59, 0x54, 0x43, 0x4e, 0x05, 0x08, 0x1f, 0x12, 0x31, 0x3c, 0x2b, 0x26,
0xbd, 0xb0, 0xa7, 0xaa, 0x89, 0x84, 0x93, 0x9e, 0xd5, 0xd8, 0xcf, 0xc2, 0xe1, 0xec, 0xfb, 0xf6,
0xd6, 0xdb, 0xcc, 0xc1, 0xe2, 0xef, 0xf8, 0xf5, 0xbe, 0xb3, 0xa4, 0xa9, 0x8a, 0x87, 0x90, 0x9d,
0x06, 0x0b, 0x1c, 0x11, 0x32, 0x3f, 0x28, 0x25, 0x6e, 0x63, 0x74, 0x79, 0x5a, 0x57, 0x40, 0x4d,
0xda, 0xd7, 0xc0, 0xcd, 0xee, 0xe3, 0xf4, 0xf9, 0xb2, 0xbf, 0xa8, 0xa5, 0x86, 0x8b, 0x9c, 0x91,
0x0a, 0x07, 0x10, 0x1d, 0x3e, 0x33, 0x24, 0x29, 0x62, 0x6f, 0x78, 0x75, 0x56, 0x5b, 0x4c, 0x41,
0x61, 0x6c, 0x7b, 0x76, 0x55, 0x58, 0x4f, 0x42, 0x09, 0x04, 0x13, 0x1e, 0x3d, 0x30, 0x27, 0x2a,
0xb1, 0xbc, 0xab, 0xa6, 0x85, 0x88, 0x9f, 0x92, 0xd9, 0xd4, 0xc3, 0xce, 0xed, 0xe0, 0xf7, 0xfa,
0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, 0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc,
0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c,
0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f, 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47,
0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97
};
private static readonly byte[] _gfMul0E = new byte[]
{
0x00, 0x0e, 0x1c, 0x12, 0x38, 0x36, 0x24, 0x2a, 0x70, 0x7e, 0x6c, 0x62, 0x48, 0x46, 0x54, 0x5a,
0xe0, 0xee, 0xfc, 0xf2, 0xd8, 0xd6, 0xc4, 0xca, 0x90, 0x9e, 0x8c, 0x82, 0xa8, 0xa6, 0xb4, 0xba,
0xdb, 0xd5, 0xc7, 0xc9, 0xe3, 0xed, 0xff, 0xf1, 0xab, 0xa5, 0xb7, 0xb9, 0x93, 0x9d, 0x8f, 0x81,
0x3b, 0x35, 0x27, 0x29, 0x03, 0x0d, 0x1f, 0x11, 0x4b, 0x45, 0x57, 0x59, 0x73, 0x7d, 0x6f, 0x61,
0xad, 0xa3, 0xb1, 0xbf, 0x95, 0x9b, 0x89, 0x87, 0xdd, 0xd3, 0xc1, 0xcf, 0xe5, 0xeb, 0xf9, 0xf7,
0x4d, 0x43, 0x51, 0x5f, 0x75, 0x7b, 0x69, 0x67, 0x3d, 0x33, 0x21, 0x2f, 0x05, 0x0b, 0x19, 0x17,
0x76, 0x78, 0x6a, 0x64, 0x4e, 0x40, 0x52, 0x5c, 0x06, 0x08, 0x1a, 0x14, 0x3e, 0x30, 0x22, 0x2c,
0x96, 0x98, 0x8a, 0x84, 0xae, 0xa0, 0xb2, 0xbc, 0xe6, 0xe8, 0xfa, 0xf4, 0xde, 0xd0, 0xc2, 0xcc,
0x41, 0x4f, 0x5d, 0x53, 0x79, 0x77, 0x65, 0x6b, 0x31, 0x3f, 0x2d, 0x23, 0x09, 0x07, 0x15, 0x1b,
0xa1, 0xaf, 0xbd, 0xb3, 0x99, 0x97, 0x85, 0x8b, 0xd1, 0xdf, 0xcd, 0xc3, 0xe9, 0xe7, 0xf5, 0xfb,
0x9a, 0x94, 0x86, 0x88, 0xa2, 0xac, 0xbe, 0xb0, 0xea, 0xe4, 0xf6, 0xf8, 0xd2, 0xdc, 0xce, 0xc0,
0x7a, 0x74, 0x66, 0x68, 0x42, 0x4c, 0x5e, 0x50, 0x0a, 0x04, 0x16, 0x18, 0x32, 0x3c, 0x2e, 0x20,
0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, 0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6,
0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56,
0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d, 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d,
0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d
};
private static readonly byte[] _srPerm = new byte[]
{
0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3
};
private static readonly byte[] _isrPerm = new byte[]
{
0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11
};
#endregion
public static Vector128<float> AesInvMixColumns(Vector128<float> op)
{
byte[] inState = new byte[16];
byte[] outState = new byte[16];
FromVectorToByteArray(op, inState);
for (int columns = 0; columns <= 3; columns++)
{
int idx = columns << 2;
byte row0 = inState[idx + 0]; // A, E, I, M: [row0, col0-col3]
byte row1 = inState[idx + 1]; // B, F, J, N: [row1, col0-col3]
byte row2 = inState[idx + 2]; // C, G, K, O: [row2, col0-col3]
byte row3 = inState[idx + 3]; // D, H, L, P: [row3, col0-col3]
outState[idx + 0] = (byte)((uint)_gfMul0E[row0] ^ _gfMul0B[row1] ^ _gfMul0D[row2] ^ _gfMul09[row3]);
outState[idx + 1] = (byte)((uint)_gfMul09[row0] ^ _gfMul0E[row1] ^ _gfMul0B[row2] ^ _gfMul0D[row3]);
outState[idx + 2] = (byte)((uint)_gfMul0D[row0] ^ _gfMul09[row1] ^ _gfMul0E[row2] ^ _gfMul0B[row3]);
outState[idx + 3] = (byte)((uint)_gfMul0B[row0] ^ _gfMul0D[row1] ^ _gfMul09[row2] ^ _gfMul0E[row3]);
}
FromByteArrayToVector(outState, ref op);
return op;
}
public static Vector128<float> AesInvShiftRows(Vector128<float> op)
{
byte[] inState = new byte[16];
byte[] outState = new byte[16];
FromVectorToByteArray(op, inState);
for (int idx = 0; idx <= 15; idx++)
{
outState[_isrPerm[idx]] = inState[idx];
}
FromByteArrayToVector(outState, ref op);
return op;
}
public static Vector128<float> AesInvSubBytes(Vector128<float> op)
{
byte[] inState = new byte[16];
byte[] outState = new byte[16];
FromVectorToByteArray(op, inState);
for (int idx = 0; idx <= 15; idx++)
{
outState[idx] = _invSBox[inState[idx]];
}
FromByteArrayToVector(outState, ref op);
return op;
}
public static Vector128<float> AesMixColumns(Vector128<float> op)
{
byte[] inState = new byte[16];
byte[] outState = new byte[16];
FromVectorToByteArray(op, inState);
for (int columns = 0; columns <= 3; columns++)
{
int idx = columns << 2;
byte row0 = inState[idx + 0]; // A, E, I, M: [row0, col0-col3]
byte row1 = inState[idx + 1]; // B, F, J, N: [row1, col0-col3]
byte row2 = inState[idx + 2]; // C, G, K, O: [row2, col0-col3]
byte row3 = inState[idx + 3]; // D, H, L, P: [row3, col0-col3]
outState[idx + 0] = (byte)((uint)_gfMul02[row0] ^ _gfMul03[row1] ^ row2 ^ row3);
outState[idx + 1] = (byte)((uint)row0 ^ _gfMul02[row1] ^ _gfMul03[row2] ^ row3);
outState[idx + 2] = (byte)((uint)row0 ^ row1 ^ _gfMul02[row2] ^ _gfMul03[row3]);
outState[idx + 3] = (byte)((uint)_gfMul03[row0] ^ row1 ^ row2 ^ _gfMul02[row3]);
}
FromByteArrayToVector(outState, ref op);
return op;
}
public static Vector128<float> AesShiftRows(Vector128<float> op)
{
byte[] inState = new byte[16];
byte[] outState = new byte[16];
FromVectorToByteArray(op, inState);
for (int idx = 0; idx <= 15; idx++)
{
outState[_srPerm[idx]] = inState[idx];
}
FromByteArrayToVector(outState, ref op);
return op;
}
public static Vector128<float> AesSubBytes(Vector128<float> op)
{
byte[] inState = new byte[16];
byte[] outState = new byte[16];
FromVectorToByteArray(op, inState);
for (int idx = 0; idx <= 15; idx++)
{
outState[idx] = _sBox[inState[idx]];
}
FromByteArrayToVector(outState, ref op);
return op;
}
private unsafe static void FromVectorToByteArray(Vector128<float> op, byte[] state)
{
if (!Sse2.IsSupported)
{
throw new PlatformNotSupportedException();
}
fixed (byte* ptr = &state[0])
{
Sse2.Store(ptr, Sse.StaticCast<float, byte>(op));
}
}
private unsafe static void FromByteArrayToVector(byte[] state, ref Vector128<float> op)
{
if (!Sse2.IsSupported)
{
throw new PlatformNotSupportedException();
}
fixed (byte* ptr = &state[0])
{
op = Sse.StaticCast<byte, float>(Sse2.LoadVector128(ptr));
}
}
}
}

18
ChocolArm64/Instructions/Inst.cs
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@ -1,18 +0,0 @@
using System;
namespace ChocolArm64.Instructions
{
struct Inst
{
public InstEmitter Emitter { get; }
public Type Type { get; }
public static Inst Undefined => new Inst(InstEmit.Und, null);
public Inst(InstEmitter emitter, Type type)
{
Emitter = emitter;
Type = type;
}
}
}

146
ChocolArm64/Instructions/InstEmit32Helper.cs
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@ -1,146 +0,0 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;
using System.Reflection.Emit;
namespace ChocolArm64.Instructions
{
static class InstEmit32Helper
{
public static bool IsThumb(OpCode64 op)
{
return op is OpCodeT16;
}
public static void EmitLoadFromRegister(ILEmitterCtx context, int register)
{
if (register == RegisterAlias.Aarch32Pc)
{
OpCode32 op = (OpCode32)context.CurrOp;
context.EmitLdc_I4((int)op.GetPc());
}
else
{
context.EmitLdint(GetRegisterAlias(context.Mode, register));
}
}
public static void EmitStoreToRegister(ILEmitterCtx context, int register)
{
if (register == RegisterAlias.Aarch32Pc)
{
context.EmitStoreContext();
EmitBxWritePc(context);
}
else
{
context.EmitStint(GetRegisterAlias(context.Mode, register));
}
}
public static void EmitBxWritePc(ILEmitterCtx context)
{
context.Emit(OpCodes.Dup);
context.EmitLdc_I4(1);
context.Emit(OpCodes.And);
context.Emit(OpCodes.Dup);
context.EmitStflg((int)PState.TBit);
ILLabel lblArmMode = new ILLabel();
ILLabel lblEnd = new ILLabel();
context.Emit(OpCodes.Brtrue_S, lblArmMode);
context.EmitLdc_I4(~1);
context.Emit(OpCodes.Br_S, lblEnd);
context.MarkLabel(lblArmMode);
context.EmitLdc_I4(~3);
context.MarkLabel(lblEnd);
context.Emit(OpCodes.And);
context.Emit(OpCodes.Conv_U8);
context.Emit(OpCodes.Ret);
}
public static int GetRegisterAlias(Aarch32Mode mode, int register)
{
//Only registers >= 8 are banked, with registers in the range [8, 12] being
//banked for the FIQ mode, and registers 13 and 14 being banked for all modes.
if ((uint)register < 8)
{
return register;
}
return GetBankedRegisterAlias(mode, register);
}
public static int GetBankedRegisterAlias(Aarch32Mode mode, int register)
{
switch (register)
{
case 8: return mode == Aarch32Mode.Fiq
? RegisterAlias.R8Fiq
: RegisterAlias.R8Usr;
case 9: return mode == Aarch32Mode.Fiq
? RegisterAlias.R9Fiq
: RegisterAlias.R9Usr;
case 10: return mode == Aarch32Mode.Fiq
? RegisterAlias.R10Fiq
: RegisterAlias.R10Usr;
case 11: return mode == Aarch32Mode.Fiq
? RegisterAlias.R11Fiq
: RegisterAlias.R11Usr;
case 12: return mode == Aarch32Mode.Fiq
? RegisterAlias.R12Fiq
: RegisterAlias.R12Usr;
case 13:
switch (mode)
{
case Aarch32Mode.User:
case Aarch32Mode.System: return RegisterAlias.SpUsr;
case Aarch32Mode.Fiq: return RegisterAlias.SpFiq;
case Aarch32Mode.Irq: return RegisterAlias.SpIrq;
case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc;
case Aarch32Mode.Abort: return RegisterAlias.SpAbt;
case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp;
case Aarch32Mode.Undefined: return RegisterAlias.SpUnd;
default: throw new ArgumentException(nameof(mode));
}
case 14:
switch (mode)
{
case Aarch32Mode.User:
case Aarch32Mode.Hypervisor:
case Aarch32Mode.System: return RegisterAlias.LrUsr;
case Aarch32Mode.Fiq: return RegisterAlias.LrFiq;
case Aarch32Mode.Irq: return RegisterAlias.LrIrq;
case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc;
case Aarch32Mode.Abort: return RegisterAlias.LrAbt;
case Aarch32Mode.Undefined: return RegisterAlias.LrUnd;
default: throw new ArgumentException(nameof(mode));
}
default: throw new ArgumentOutOfRangeException(nameof(register));
}
}
}
}

422
ChocolArm64/Instructions/InstEmitAlu.cs
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@ -1,422 +0,0 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;
using System.Reflection;
using System.Reflection.Emit;
using System.Runtime.Intrinsics.X86;
using static ChocolArm64.Instructions.InstEmitAluHelper;
namespace ChocolArm64.Instructions
{
static partial class InstEmit
{
public static void Adc(ILEmitterCtx context) => EmitAdc(context, false);
public static void Adcs(ILEmitterCtx context) => EmitAdc(context, true);
private static void EmitAdc(ILEmitterCtx context, bool setFlags)
{
EmitAluLoadOpers(context);
context.Emit(OpCodes.Add);
context.EmitLdflg((int)PState.CBit);
Type[] mthdTypes = new Type[] { typeof(bool) };
MethodInfo mthdInfo = typeof(Convert).GetMethod(nameof(Convert.ToInt32), mthdTypes);
context.EmitCall(mthdInfo);
if (context.CurrOp.RegisterSize != RegisterSize.Int32)
{
context.Emit(OpCodes.Conv_U8);
}
context.Emit(OpCodes.Add);
if (setFlags)
{
context.EmitZnFlagCheck();
EmitAdcsCCheck(context);
EmitAddsVCheck(context);
}
EmitAluStore(context);
}
public static void Add(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Add);
public static void Adds(ILEmitterCtx context)
{
context.TryOptMarkCondWithoutCmp();
EmitAluLoadOpers(context);
context.Emit(OpCodes.Add);
context.EmitZnFlagCheck();
EmitAddsCCheck(context);
EmitAddsVCheck(context);
EmitAluStoreS(context);
}
public static void And(ILEmitterCtx context) => EmitAluOp(context, OpCodes.And);
public static void Ands(ILEmitterCtx context)
{
EmitAluLoadOpers(context);
context.Emit(OpCodes.And);
EmitZeroCvFlags(context);
context.EmitZnFlagCheck();
EmitAluStoreS(context);
}
public static void Asrv(ILEmitterCtx context) => EmitAluOpShift(context, OpCodes.Shr);
public static void Bic(ILEmitterCtx context) => EmitBic(context, false);
public static void Bics(ILEmitterCtx context) => EmitBic(context, true);
private static void EmitBic(ILEmitterCtx context, bool setFlags)
{
EmitAluLoadOpers(context);
context.Emit(OpCodes.Not);
context.Emit(OpCodes.And);
if (setFlags)
{
EmitZeroCvFlags(context);
context.EmitZnFlagCheck();
}
EmitAluStore(context, setFlags);
}
public static void Cls(ILEmitterCtx context)
{
OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn);
context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64);
SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingSigns));
context.EmitStintzr(op.Rd);
}
public static void Clz(ILEmitterCtx context)
{
OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn);
if (Lzcnt.IsSupported)
{
Type tValue = op.RegisterSize == RegisterSize.Int32 ? typeof(uint) : typeof(ulong);
context.EmitCall(typeof(Lzcnt).GetMethod(nameof(Lzcnt.LeadingZeroCount), new Type[] { tValue }));
}
else
{
context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64);
SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingZeros));
}
context.EmitStintzr(op.Rd);
}
public static void Eon(ILEmitterCtx context)
{
EmitAluLoadOpers(context);
context.Emit(OpCodes.Not);
context.Emit(OpCodes.Xor);
EmitAluStore(context);
}
public static void Eor(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Xor);
public static void Extr(ILEmitterCtx context)
{
// TODO: Ensure that the Shift is valid for the Is64Bits.
OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp;
context.EmitLdintzr(op.Rm);
if (op.Shift > 0)
{
context.EmitLdc_I4(op.Shift);
context.Emit(OpCodes.Shr_Un);
context.EmitLdintzr(op.Rn);
context.EmitLdc_I4(op.GetBitsCount() - op.Shift);
context.Emit(OpCodes.Shl);
context.Emit(OpCodes.Or);
}
EmitAluStore(context);
}
public static void Lslv(ILEmitterCtx context) => EmitAluOpShift(context, OpCodes.Shl);
public static void Lsrv(ILEmitterCtx context) => EmitAluOpShift(context, OpCodes.Shr_Un);
public static void Sbc(ILEmitterCtx context) => EmitSbc(context, false);
public static void Sbcs(ILEmitterCtx context) => EmitSbc(context, true);
private static void EmitSbc(ILEmitterCtx context, bool setFlags)
{
EmitAluLoadOpers(context);
context.Emit(OpCodes.Sub);
context.EmitLdflg((int)PState.CBit);
Type[] mthdTypes = new Type[] { typeof(bool) };
MethodInfo mthdInfo = typeof(Convert).GetMethod(nameof(Convert.ToInt32), mthdTypes);
context.EmitCall(mthdInfo);
context.EmitLdc_I4(1);
context.Emit(OpCodes.Xor);
if (context.CurrOp.RegisterSize != RegisterSize.Int32)
{
context.Emit(OpCodes.Conv_U8);
}
context.Emit(OpCodes.Sub);
if (setFlags)
{
context.EmitZnFlagCheck();
EmitSbcsCCheck(context);
EmitSubsVCheck(context);
}
EmitAluStore(context);
}
public static void Sub(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Sub);
public static void Subs(ILEmitterCtx context)
{
context.TryOptMarkCondWithoutCmp();
EmitAluLoadOpers(context);
context.Emit(OpCodes.Sub);
context.EmitZnFlagCheck();
EmitSubsCCheck(context);
EmitSubsVCheck(context);
EmitAluStoreS(context);
}
public static void Orn(ILEmitterCtx context)
{
EmitAluLoadOpers(context);
context.Emit(OpCodes.Not);
context.Emit(OpCodes.Or);
EmitAluStore(context);
}
public static void Orr(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Or);
public static void Rbit(ILEmitterCtx context) => EmitFallback32_64(context,
nameof(SoftFallback.ReverseBits32),
nameof(SoftFallback.ReverseBits64));
public static void Rev16(ILEmitterCtx context) => EmitFallback32_64(context,
nameof(SoftFallback.ReverseBytes16_32),
nameof(SoftFallback.ReverseBytes16_64));
public static void Rev32(ILEmitterCtx context) => EmitFallback32_64(context,
nameof(SoftFallback.ReverseBytes32_32),
nameof(SoftFallback.ReverseBytes32_64));
private static void EmitFallback32_64(ILEmitterCtx context, string name32, string name64)
{
OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn);
if (op.RegisterSize == RegisterSize.Int32)
{
SoftFallback.EmitCall(context, name32);
}
else
{
SoftFallback.EmitCall(context, name64);
}
context.EmitStintzr(op.Rd);
}
public static void Rev64(ILEmitterCtx context)
{
OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn);
SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBytes64));
context.EmitStintzr(op.Rd);
}
public static void Rorv(ILEmitterCtx context)
{
EmitAluLoadRn(context);
EmitAluLoadShift(context);
context.Emit(OpCodes.Shr_Un);
EmitAluLoadRn(context);
context.EmitLdc_I4(context.CurrOp.GetBitsCount());
EmitAluLoadShift(context);
context.Emit(OpCodes.Sub);
context.Emit(OpCodes.Shl);
context.Emit(OpCodes.Or);
EmitAluStore(context);
}
public static void Sdiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div);
public static void Udiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div_Un);
private static void EmitDiv(ILEmitterCtx context, OpCode ilOp)
{
// If Rm == 0, Rd = 0 (division by zero).
context.EmitLdc_I(0);
EmitAluLoadRm(context);
context.EmitLdc_I(0);
ILLabel badDiv = new ILLabel();
context.Emit(OpCodes.Beq_S, badDiv);
context.Emit(OpCodes.Pop);
if (ilOp == OpCodes.Div)
{
// If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
long intMin = 1L << (context.CurrOp.GetBitsCount() - 1);
context.EmitLdc_I(intMin);
EmitAluLoadRn(context);
context.EmitLdc_I(intMin);
context.Emit(OpCodes.Ceq);
EmitAluLoadRm(context);
context.EmitLdc_I(-1);
context.Emit(OpCodes.Ceq);
context.Emit(OpCodes.And);
context.Emit(OpCodes.Brtrue_S, badDiv);
context.Emit(OpCodes.Pop);
}
EmitAluLoadRn(context);
EmitAluLoadRm(context);
context.Emit(ilOp);
context.MarkLabel(badDiv);
EmitAluStore(context);
}
private static void EmitAluOp(ILEmitterCtx context, OpCode ilOp)
{
EmitAluLoadOpers(context);
context.Emit(ilOp);
EmitAluStore(context);
}
private static void EmitAluOpShift(ILEmitterCtx context, OpCode ilOp)
{
EmitAluLoadRn(context);
EmitAluLoadShift(context);
context.Emit(ilOp);
EmitAluStore(context);
}
private static void EmitAluLoadShift(ILEmitterCtx context)
{
EmitAluLoadRm(context);
context.EmitLdc_I(context.CurrOp.GetBitsCount() - 1);
context.Emit(OpCodes.And);
// Note: Only 32-bits shift values are valid, so when the value is 64-bits
// we need to cast it to a 32-bits integer. This is fine because we
// AND the value and only keep the lower 5 or 6 bits anyway -- it
// could very well fit on a byte.
if (context.CurrOp.RegisterSize != RegisterSize.Int32)
{
context.Emit(OpCodes.Conv_I4);
}
}
private static void EmitZeroCvFlags(ILEmitterCtx context)
{
context.EmitLdc_I4(0);
context.EmitStflg((int)PState.VBit);
context.EmitLdc_I4(0);
context.EmitStflg((int)PState.CBit);
}
public static void EmitAluStore(ILEmitterCtx context) => EmitAluStore(context, false);
public static void EmitAluStoreS(ILEmitterCtx context) => EmitAluStore(context, true);
public static void EmitAluStore(ILEmitterCtx context, bool setFlags)
{
IOpCodeAlu64 op = (IOpCodeAlu64)context.CurrOp;
if (setFlags || op is IOpCodeAluRs64)
{
context.EmitStintzr(op.Rd);
}
else
{
context.EmitStint(op.Rd);
}
}
}
}

142
ChocolArm64/Instructions/InstEmitAlu32.cs
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@ -1,142 +0,0 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System.Reflection.Emit;
using static ChocolArm64.Instructions.InstEmit32Helper;
using static ChocolArm64.Instructions.InstEmitAluHelper;
namespace ChocolArm64.Instructions
{
static partial class InstEmit32
{
public static void Add(ILEmitterCtx context)
{
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
EmitAluLoadOpers(context, setCarry: false);
context.Emit(OpCodes.Add);
if (op.SetFlags)
{
context.EmitZnFlagCheck();
EmitAddsCCheck(context);
EmitAddsVCheck(context);
}
EmitAluStore(context);
}
public static void Cmp(ILEmitterCtx context)
{
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
EmitAluLoadOpers(context, setCarry: false);
context.Emit(OpCodes.Sub);
context.EmitZnFlagCheck();
EmitSubsCCheck(context);
EmitSubsVCheck(context);
context.Emit(OpCodes.Pop);
}
public static void Mov(ILEmitterCtx context)
{
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
EmitAluLoadOper2(context);
if (op.SetFlags)
{
context.EmitZnFlagCheck();
}
EmitAluStore(context);
}
public static void Sub(ILEmitterCtx context)
{
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
EmitAluLoadOpers(context, setCarry: false);
context.Emit(OpCodes.Sub);
if (op.SetFlags)
{
context.EmitZnFlagCheck();
EmitSubsCCheck(context);
EmitSubsVCheck(context);
}
EmitAluStore(context);
}
private static void EmitAluStore(ILEmitterCtx context)
{
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
if (op.Rd == RegisterAlias.Aarch32Pc)
{
if (op.SetFlags)
{
// TODO: Load SPSR etc.
context.EmitLdflg((int)PState.TBit);
ILLabel lblThumb = new ILLabel();
ILLabel lblEnd = new ILLabel();
context.Emit(OpCodes.Brtrue_S, lblThumb);
context.EmitLdc_I4(~3);
context.Emit(OpCodes.Br_S, lblEnd);
context.MarkLabel(lblThumb);
context.EmitLdc_I4(~1);
context.MarkLabel(lblEnd);
context.Emit(OpCodes.And);
context.Emit(OpCodes.Conv_U8);
context.Emit(OpCodes.Ret);
}
else
{
EmitAluWritePc(context);
}
}
else
{
context.EmitStint(GetRegisterAlias(context.Mode, op.Rd));
}
}
private static void EmitAluWritePc(ILEmitterCtx context)
{
context.EmitStoreContext();
if (IsThumb(context.CurrOp))
{
context.EmitLdc_I4(~1);
context.Emit(OpCodes.And);
context.Emit(OpCodes.Conv_U8);
context.Emit(OpCodes.Ret);
}
else
{
EmitBxWritePc(context);
}
}
}
}

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