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Implement VORN (register) Arm32 instruction (#2396)

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gdkchan 2021-06-23 18:21:23 -03:00 committed by GitHub
parent 49edf14a3e
commit ab9d4b862d
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4 changed files with 30 additions and 9 deletions
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1
ARMeilleure/Decoders/OpCodeTable.cs
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@ -907,6 +907,7 @@ namespace ARMeilleure.Decoders
SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla, InstEmit32.Vnmla_S, OpCode32SimdRegS.Create); SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla, InstEmit32.Vnmla_S, OpCode32SimdRegS.Create);
SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, OpCode32SimdRegS.Create); SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, OpCode32SimdRegS.Create);
SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, OpCode32SimdRegS.Create); SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, OpCode32SimdRegS.Create);
SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn, InstEmit32.Vorn_I, OpCode32SimdBinary.Create);
SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, OpCode32SimdBinary.Create); SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, OpCode32SimdBinary.Create);
SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, OpCode32SimdImm.Create); SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, OpCode32SimdImm.Create);
SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, OpCode32SimdReg.Create); SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, OpCode32SimdReg.Create);

18
ARMeilleure/Instructions/InstEmitSimdLogical32.cs
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@ -115,6 +115,24 @@ namespace ARMeilleure.Instructions
} }
} }
public static void Vorn_I(ArmEmitterContext context)
{
if (Optimizations.UseSse2)
{
Operand mask = context.VectorOne();
EmitVectorBinaryOpSimd32(context, (n, m) =>
{
m = context.AddIntrinsic(Intrinsic.X86Pandn, m, mask);
return context.AddIntrinsic(Intrinsic.X86Por, n, m);
});
}
else
{
EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, context.BitwiseNot(op2)));
}
}
public static void Vorr_I(ArmEmitterContext context) public static void Vorr_I(ArmEmitterContext context)
{ {
if (Optimizations.UseSse2) if (Optimizations.UseSse2)

1
ARMeilleure/Instructions/InstName.cs
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@ -605,6 +605,7 @@ namespace ARMeilleure.Instructions
Vnmul, Vnmul,
Vnmla, Vnmla,
Vnmls, Vnmls,
Vorn,
Vorr, Vorr,
Vpadd, Vpadd,
Vpmax, Vpmax,

5
Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
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@ -22,7 +22,7 @@ namespace Ryujinx.Tests.Cpu
#endregion #endregion
#region "ValueSource (Opcodes)" #region "ValueSource (Opcodes)"
private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_() private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_()
{ {
return new uint[] return new uint[]
{ {
@ -31,6 +31,7 @@ namespace Ryujinx.Tests.Cpu
0xf3200110u, // VBIT D0, D0, D0 0xf3200110u, // VBIT D0, D0, D0
0xf3100110u, // VBSL D0, D0, D0 0xf3100110u, // VBSL D0, D0, D0
0xf2000110u, // VAND D0, D0, D0 0xf2000110u, // VAND D0, D0, D0
0xf2300110u, // VORN D0, D0, D0
0xf2200110u, // VORR D0, D0, D0 0xf2200110u, // VORR D0, D0, D0
0xf3000110u // VEOR D0, D0, D0 0xf3000110u // VEOR D0, D0, D0
}; };
@ -51,7 +52,7 @@ namespace Ryujinx.Tests.Cpu
private const int RndCnt = 2; private const int RndCnt = 2;
[Test, Pairwise] [Test, Pairwise]
public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_")] uint opcode, public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_")] uint opcode,
[Range(0u, 5u)] uint rd, [Range(0u, 5u)] uint rd,
[Range(0u, 5u)] uint rn, [Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm, [Range(0u, 5u)] uint rm,