vance/ryujinx
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204)

Browse Source 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Update Instructions.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs
This commit is contained in:
LDj3SNuD 2018-06-30 17:40:41 +02:00 committed by gdkchan
parent edfd4bc860
commit 53934e8872
7 changed files with 945 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ChocolArm64/AOpCodeTable.cs
View File

@ -352,6 +352,10 @@ namespace ChocolArm64
SetA64("0x1011100x100000000010xxxxxxxxxx", AInstEmit.Rev32_V, typeof(AOpCodeSimd));
SetA64("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Rsubhn_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Saba_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
@ -390,6 +394,8 @@ namespace ChocolArm64
SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", AInstEmit.Trn2_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Uaba_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Uabal_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));

117
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View File

@ -22,19 +22,6 @@ namespace ChocolArm64.Instruction
EmitVectorUnaryOpSx(Context, () => EmitAbs(Context));
}
private static void EmitAbs(AILEmitterCtx Context)
{
AILLabel LblTrue = new AILLabel();
Context.Emit(OpCodes.Dup);
Context.Emit(OpCodes.Ldc_I4_0);
Context.Emit(OpCodes.Bge_S, LblTrue);
Context.Emit(OpCodes.Neg);
Context.MarkLabel(LblTrue);
}
public static void Add_S(AILEmitterCtx Context)
{
EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
@ -179,6 +166,19 @@ namespace ChocolArm64.Instruction
}
}
private static void EmitAbs(AILEmitterCtx Context)
{
AILLabel LblTrue = new AILLabel();
Context.Emit(OpCodes.Dup);
Context.Emit(OpCodes.Ldc_I4_0);
Context.Emit(OpCodes.Bge_S, LblTrue);
Context.Emit(OpCodes.Neg);
Context.MarkLabel(LblTrue);
}
private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -188,6 +188,8 @@ namespace ChocolArm64.Instruction
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
long RoundConst = 1L << (ESize - 1);
for (int Index = 0; Index < Elems; Index++)
{
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
@ -197,7 +199,7 @@ namespace ChocolArm64.Instruction
if (Round)
{
Context.EmitLdc_I8(1L << (ESize - 1));
Context.EmitLdc_I8(RoundConst);
Context.Emit(OpCodes.Add);
}
@ -220,11 +222,11 @@ namespace ChocolArm64.Instruction
int Elems = (!Scalar ? 8 >> Op.Size : 1);
int ESize = 8 << Op.Size;
int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
int TMaxValue = (SignedDst ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
int TMinValue = (SignedDst ? -((1 << (ESize - 1))) : 0);
int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
Context.EmitLdc_I8(0L);
Context.EmitSttmp();
@ -1107,6 +1109,46 @@ namespace ChocolArm64.Instruction
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: true);
}
public static void Saba_V(AILEmitterCtx Context)
{
EmitVectorTernaryOpSx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
Context.Emit(OpCodes.Add);
});
}
public static void Sabal_V(AILEmitterCtx Context)
{
EmitVectorWidenRnRmTernaryOpSx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
Context.Emit(OpCodes.Add);
});
}
public static void Sabd_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpSx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
});
}
public static void Sabdl_V(AILEmitterCtx Context)
{
EmitVectorWidenRnRmBinaryOpSx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
});
}
public static void Saddw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
@ -1186,23 +1228,44 @@ namespace ChocolArm64.Instruction
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: false);
}
public static void Uaba_V(AILEmitterCtx Context)
{
EmitVectorTernaryOpZx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
Context.Emit(OpCodes.Add);
});
}
public static void Uabal_V(AILEmitterCtx Context)
{
EmitVectorWidenRnRmTernaryOpZx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
Context.Emit(OpCodes.Add);
});
}
public static void Uabd_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpZx(Context, () => EmitAbd(Context));
EmitVectorBinaryOpZx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
});
}
public static void Uabdl_V(AILEmitterCtx Context)
{
EmitVectorWidenRnRmBinaryOpZx(Context, () => EmitAbd(Context));
}
private static void EmitAbd(AILEmitterCtx Context)
{
Context.Emit(OpCodes.Sub);
Type[] Types = new Type[] { typeof(long) };
Context.EmitCall(typeof(Math).GetMethod(nameof(Math.Abs), Types));
EmitVectorWidenRnRmBinaryOpZx(Context, () =>
{
Context.Emit(OpCodes.Sub);
EmitAbs(Context);
});
}
public static void Uaddl_V(AILEmitterCtx Context)

5
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View File

@ -483,6 +483,11 @@ namespace ChocolArm64.Instruction
EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
}
public static void EmitVectorTernaryOpSx(AILEmitterCtx Context, Action Emit)
{
EmitVectorOp(Context, Emit, OperFlags.RdRnRm, true);
}
public static void EmitVectorUnaryOpZx(AILEmitterCtx Context, Action Emit)
{
EmitVectorOp(Context, Emit, OperFlags.Rn, false);

30
Ryujinx.Tests/Cpu/CpuTest.cs
View File

@ -113,20 +113,20 @@ namespace Ryujinx.Tests.Cpu
return GetThreadState();
}
protected static Vector128<float> MakeVectorE0(double A0)
protected static Vector128<float> MakeVectorE0(double E0)
{
return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(A0)));
return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(E0)));
}
protected static Vector128<float> MakeVectorE0E1(double A0, double A1)
protected static Vector128<float> MakeVectorE0E1(double E0, double E1)
{
return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(A1),
BitConverter.DoubleToInt64Bits(A0)));
return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1),
BitConverter.DoubleToInt64Bits(E0)));
}
protected static Vector128<float> MakeVectorE1(double A1)
protected static Vector128<float> MakeVectorE1(double E1)
{
return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(A1), 0));
return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1), 0));
}
protected static double VectorExtractDouble(Vector128<float> Vector, byte Index)
@ -136,29 +136,29 @@ namespace Ryujinx.Tests.Cpu
return BitConverter.Int64BitsToDouble(Value);
}
protected static Vector128<float> MakeVectorE0(ulong A0)
protected static Vector128<float> MakeVectorE0(ulong E0)
{
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A0));
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, E0));
}
protected static Vector128<float> MakeVectorE0E1(ulong A0, ulong A1)
protected static Vector128<float> MakeVectorE0E1(ulong E0, ulong E1)
{
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(A1, A0));
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, E0));
}
protected static Vector128<float> MakeVectorE1(ulong A1)
protected static Vector128<float> MakeVectorE1(ulong E1)
{
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(A1, 0));
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, 0));
}
protected static ulong GetVectorE0(Vector128<float> Vector)
{
return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), 0);
return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)0);
}
protected static ulong GetVectorE1(Vector128<float> Vector)
{
return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), 1);
return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)1);
}
}
}

18
Ryujinx.Tests/Cpu/CpuTestSimd.cs
View File

@ -834,8 +834,8 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_X0);
ulong _E0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_E0);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
@ -845,7 +845,7 @@ namespace Ryujinx.Tests.Cpu
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
@ -910,8 +910,8 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_X0);
ulong _E0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_E0);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
@ -921,7 +921,7 @@ namespace Ryujinx.Tests.Cpu
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
@ -986,8 +986,8 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_X0);
ulong _E0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_E0);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
@ -997,7 +997,7 @@ namespace Ryujinx.Tests.Cpu
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));

476
Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
View File

@ -176,8 +176,8 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_X0);
ulong _E0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_E0);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
@ -190,7 +190,7 @@ namespace Ryujinx.Tests.Cpu
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
@ -1157,8 +1157,8 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_X0);
ulong _E0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_E0);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
@ -1171,7 +1171,7 @@ namespace Ryujinx.Tests.Cpu
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
@ -1216,8 +1216,8 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_X0);
ulong _E0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_E0);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
@ -1230,7 +1230,233 @@ namespace Ryujinx.Tests.Cpu
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Saba_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E227C20; // SABA V0.8B, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z, TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
SimdFp.Saba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
});
}
[Test, Pairwise, Description("SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Saba_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong _Z1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x4E227C20; // SABA V0.16B, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z0));
AArch64.Vpart(0, 1, new Bits(_Z1));
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 0, new Bits(B0));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Saba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Pairwise, Description("SABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Sabal_V_8B8H_4H4S_2S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong _Z1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E225020; // SABAL V0.8H, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
Vector128<float> V1 = MakeVectorE0(A0);
Vector128<float> V2 = MakeVectorE0(B0);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z0));
AArch64.Vpart(0, 1, new Bits(_Z1));
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(2, 0, new Bits(B0));
SimdFp.Sabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Pairwise, Description("SABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Sabal_V_16B8H_8H4S_4S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong _Z1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x4E225020; // SABAL2 V0.8H, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
Vector128<float> V1 = MakeVectorE1(A1);
Vector128<float> V2 = MakeVectorE1(B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z0));
AArch64.Vpart(0, 1, new Bits(_Z1));
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Sabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Sabd_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E227420; // SABD V0.8B, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
SimdFp.Sabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
});
}
[Test, Pairwise, Description("SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Sabd_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x4E227420; // SABD V0.16B, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 0, new Bits(B0));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Sabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("SABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Sabdl_V_8B8H_4H4S_2S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E227020; // SABDL V0.8H, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0(A0);
Vector128<float> V2 = MakeVectorE0(B0);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(2, 0, new Bits(B0));
SimdFp.Sabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("SABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Sabdl_V_16B8H_8H4S_4S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x4E227020; // SABDL2 V0.8H, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE1(A1);
Vector128<float> V2 = MakeVectorE1(B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Sabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
@ -1351,8 +1577,8 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_X0);
ulong _E0 = TestContext.CurrentContext.Random.NextULong();
Vector128<float> V0 = MakeVectorE0(_E0);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
@ -1365,7 +1591,233 @@ namespace Ryujinx.Tests.Cpu
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uaba_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E227C20; // UABA V0.8B, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z, TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
SimdFp.Uaba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
});
}
[Test, Pairwise, Description("UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uaba_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong _Z1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x6E227C20; // UABA V0.16B, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z0));
AArch64.Vpart(0, 1, new Bits(_Z1));
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 0, new Bits(B0));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Uaba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Pairwise, Description("UABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Uabal_V_8B8H_4H4S_2S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong _Z1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E225020; // UABAL V0.8H, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
Vector128<float> V1 = MakeVectorE0(A0);
Vector128<float> V2 = MakeVectorE0(B0);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z0));
AArch64.Vpart(0, 1, new Bits(_Z1));
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(2, 0, new Bits(B0));
SimdFp.Uabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Pairwise, Description("UABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Uabal_V_16B8H_8H4S_4S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong _Z0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong _Z1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x6E225020; // UABAL2 V0.8H, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
Vector128<float> V1 = MakeVectorE1(A1);
Vector128<float> V2 = MakeVectorE1(B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(0, 0, new Bits(_Z0));
AArch64.Vpart(0, 1, new Bits(_Z1));
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Uabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uabd_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E227420; // UABD V0.8B, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
SimdFp.Uabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
});
}
[Test, Pairwise, Description("UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uabd_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x6E227420; // UABD V0.16B, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 0, new Bits(B0));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Uabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("UABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Uabdl_V_8B8H_4H4S_2S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B0,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E227020; // UABDL V0.8H, V1.8B, V2.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE0(A0);
Vector128<float> V2 = MakeVectorE0(B0);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(2, 0, new Bits(B0));
SimdFp.Uabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("UABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
public void Uabdl_V_16B8H_8H4S_4S2D([ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
[ValueSource("_8B4H2S_")] [Random(1)] ulong B1,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
{
uint Opcode = 0x6E227020; // UABDL2 V0.8H, V1.16B, V2.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
TestContext.CurrentContext.Random.NextULong());
Vector128<float> V1 = MakeVectorE1(A1);
Vector128<float> V2 = MakeVectorE1(B1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
AArch64.Vpart(1, 1, new Bits(A1));
AArch64.Vpart(2, 1, new Bits(B1));
SimdFp.Uabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}

356
Ryujinx.Tests/Cpu/Tester/Instructions.cs
View File

@ -4074,6 +4074,184 @@ namespace Ryujinx.Tests.Cpu.Tester
Vpart(d, part, result);
}
// saba_advsimd.html
public static void Saba_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool ac = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (ac == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(datasize, d) : Zeros(datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0);
Elem(result, e, esize, Elem(result, e, esize) + absdiff);
}
V(d, result);
}
// sabal_advsimd.html
public static void Sabal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool op = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (op == false);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0);
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff);
}
V(d, result);
}
// sabd_advsimd.html
public static void Sabd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool ac = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (ac == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(datasize, d) : Zeros(datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0);
Elem(result, e, esize, Elem(result, e, esize) + absdiff);
}
V(d, result);
}
// sabdl_advsimd.html
public static void Sabdl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool op = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (op == false);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0);
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff);
}
V(d, result);
}
// sub_advsimd.html#SUB_asisdsame_only
public static void Sub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
@ -4217,6 +4395,184 @@ namespace Ryujinx.Tests.Cpu.Tester
Vpart(d, part, result);
}
// uaba_advsimd.html
public static void Uaba_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool ac = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (ac == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(datasize, d) : Zeros(datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0);
Elem(result, e, esize, Elem(result, e, esize) + absdiff);
}
V(d, result);
}
// uabal_advsimd.html
public static void Uabal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool op = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (op == false);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0);
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff);
}
V(d, result);
}
// uabd_advsimd.html
public static void Uabd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool ac = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (ac == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(datasize, d) : Zeros(datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0);
Elem(result, e, esize, Elem(result, e, esize) + absdiff);
}
V(d, result);
}
// uabdl_advsimd.html
public static void Uabdl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool op = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool unsigned = (U == true);
bool accumulate = (op == false);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
Bits absdiff;
Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize));
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0);
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff);
}
V(d, result);
}
#endregion
}
}